Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3874	1			T6	97		T7	14		T9	6
values[1]	3794	1			T6	97		T25	20		T44	51
values[2]	3659	1			T6	212		T25	22		T111	14
values[3]	3152	1			T5	20		T25	20		T240	6
values[4]	4118	1			T6	308		T14	12		T177	8
values[5]	4114	1			T10	18		T25	21		T45	12
values[6]	3056	1			T25	22		T132	2		T114	4
values[7]	3100	1			T12	18		T25	49		T44	55

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3625	1			T5	20		T25	22		T44	26
values[1]	3826	1			T6	165		T10	18		T177	8
values[2]	3350	1			T6	84		T44	71		T49	8
values[3]	2911	1			T6	27		T9	6		T25	87
values[4]	4204	1			T114	4		T47	20		T34	22
values[5]	3361	1			T6	179		T13	24		T25	62
values[6]	3763	1			T6	156		T14	12		T25	20
values[7]	3827	1			T6	103		T7	14		T12	18

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28130

1

T5

20

T6

709

T7

14

auto[1]

737

1

T6

5

T13

2

T25

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	466	1			T205	19		T31	26		T176	20
auto[0]	values[0]	values[1]	366	1			T31	27		T217	22		T274	12
auto[0]	values[0]	values[2]	334	1			T20	20		T275	24		T85	20
auto[0]	values[0]	values[3]	438	1			T9	6		T25	45		T226	18
auto[0]	values[0]	values[4]	841	1			T216	10		T31	20		T199	20
auto[0]	values[0]	values[5]	675	1			T6	97		T13	22		T25	20
auto[0]	values[0]	values[6]	239	1			T276	8		T277	20		T278	8
auto[0]	values[0]	values[7]	418	1			T7	14		T25	21		T44	63
auto[0]	values[1]	values[0]	659	1			T32	27		T199	138		T241	20
auto[0]	values[1]	values[1]	452	1			T6	57		T115	10		T21	20
auto[0]	values[1]	values[2]	321	1			T6	20		T44	51		T268	2
auto[0]	values[1]	values[3]	335	1			T264	6		T70	22		T31	106
auto[0]	values[1]	values[4]	611	1			T205	164		T31	39		T213	20
auto[0]	values[1]	values[5]	196	1			T20	42		T199	20		T82	20
auto[0]	values[1]	values[6]	520	1			T25	19		T46	20		T34	18
auto[0]	values[1]	values[7]	617	1			T6	20		T46	20		T31	96
auto[0]	values[2]	values[0]	665	1			T25	22		T31	89		T210	89
auto[0]	values[2]	values[1]	525	1			T6	106		T21	21		T31	39
auto[0]	values[2]	values[2]	374	1			T6	20		T205	87		T242	2
auto[0]	values[2]	values[3]	451	1			T111	14		T146	16		T220	58
auto[0]	values[2]	values[4]	344	1			T47	18		T34	20		T22	20
auto[0]	values[2]	values[5]	352	1			T20	24		T176	20		T279	14
auto[0]	values[2]	values[6]	454	1			T145	10		T205	25		T58	23
auto[0]	values[2]	values[7]	417	1			T6	82		T47	19		T34	23
auto[0]	values[3]	values[0]	318	1			T5	20		T44	26		T102	16
auto[0]	values[3]	values[1]	250	1			T240	6		T243	20		T171	20
auto[0]	values[3]	values[2]	476	1			T205	40		T210	51		T215	20
auto[0]	values[3]	values[3]	131	1			T25	20		T50	19		T85	19
auto[0]	values[3]	values[4]	468	1			T31	19		T32	45		T247	2
auto[0]	values[3]	values[5]	395	1			T46	20		T205	104		T31	20
auto[0]	values[3]	values[6]	546	1			T69	2		T20	20		T31	18
auto[0]	values[3]	values[7]	493	1			T46	20		T48	2		T32	30
auto[0]	values[4]	values[0]	498	1			T46	27		T246	10		T82	53
auto[0]	values[4]	values[1]	492	1			T177	8		T44	24		T22	23
auto[0]	values[4]	values[2]	495	1			T6	43		T49	6		T50	20
auto[0]	values[4]	values[3]	459	1			T6	27		T47	19		T62	10
auto[0]	values[4]	values[4]	518	1			T199	144		T219	10		T82	23
auto[0]	values[4]	values[5]	490	1			T6	82		T251	2		T31	20
auto[0]	values[4]	values[6]	585	1			T6	155		T14	12		T22	22
auto[0]	values[4]	values[7]	461	1			T46	21		T22	26		T280	2
auto[0]	values[5]	values[0]	400	1			T31	20		T85	160		T60	21
auto[0]	values[5]	values[1]	629	1			T10	18		T197	16		T31	23
auto[0]	values[5]	values[2]	502	1			T50	14		T66	10		T20	20
auto[0]	values[5]	values[3]	445	1			T220	18		T190	20		T244	21
auto[0]	values[5]	values[4]	539	1			T220	33		T241	22		T192	10
auto[0]	values[5]	values[5]	472	1			T25	18		T50	19		T21	31
auto[0]	values[5]	values[6]	458	1			T45	12		T44	61		T102	24
auto[0]	values[5]	values[7]	554	1			T250	36		T47	20		T227	14
auto[0]	values[6]	values[0]	123	1			T215	19		T60	45		T281	20
auto[0]	values[6]	values[1]	712	1			T205	103		T282	2		T210	54
auto[0]	values[6]	values[2]	302	1			T85	93		T191	19		T60	22
auto[0]	values[6]	values[3]	267	1			T25	22		T46	18		T190	17
auto[0]	values[6]	values[4]	502	1			T114	4		T22	20		T243	52
auto[0]	values[6]	values[5]	467	1			T132	2		T199	111		T267	2
auto[0]	values[6]	values[6]	361	1			T283	18		T221	22		T82	34
auto[0]	values[6]	values[7]	225	1			T34	24		T205	53		T22	21
auto[0]	values[7]	values[0]	400	1			T85	40		T225	55		T191	37
auto[0]	values[7]	values[1]	299	1			T46	23		T31	20		T220	20
auto[0]	values[7]	values[2]	442	1			T44	20		T199	72		T232	86
auto[0]	values[7]	values[3]	292	1			T21	20		T239	30		T82	34
auto[0]	values[7]	values[4]	294	1			T31	20		T284	12		T201	22
auto[0]	values[7]	values[5]	251	1			T25	21		T22	20		T199	42
auto[0]	values[7]	values[6]	511	1			T44	35		T51	47		T205	60
auto[0]	values[7]	values[7]	538	1			T12	18		T25	26		T212	18
auto[1]	values[0]	values[0]	15	1			T205	1		T31	2		T85	2
auto[1]	values[0]	values[1]	10	1			T201	5		T245	1		T285	3
auto[1]	values[0]	values[2]	14	1			T20	1		T223	6		T263	1
auto[1]	values[0]	values[3]	11	1			T190	3		T206	3		T198	2
auto[1]	values[0]	values[4]	17	1			T243	1		T60	2		T286	3
auto[1]	values[0]	values[5]	6	1			T13	2		T210	1		T287	1
auto[1]	values[0]	values[6]	6	1			T286	2		T209	2		T288	1
auto[1]	values[0]	values[7]	18	1			T25	1		T215	5		T254	1
auto[1]	values[1]	values[0]	16	1			T32	1		T199	3		T241	1
auto[1]	values[1]	values[1]	8	1			T239	2		T223	2		T198	1
auto[1]	values[1]	values[2]	2	1			T289	2		-	-		-	-
auto[1]	values[1]	values[3]	12	1			T31	3		T32	1		T290	6
auto[1]	values[1]	values[4]	9	1			T31	1		T291	1		T198	1
auto[1]	values[1]	values[5]	2	1			T20	2		-	-		-	-
auto[1]	values[1]	values[6]	17	1			T25	1		T34	2		T31	2
auto[1]	values[1]	values[7]	17	1			T31	2		T85	1		T225	1
auto[1]	values[2]	values[0]	4	1			T31	1		T208	2		T214	1
auto[1]	values[2]	values[1]	12	1			T6	2		T31	2		T220	1
auto[1]	values[2]	values[2]	13	1			T6	1		T292	2		T237	2
auto[1]	values[2]	values[3]	13	1			T220	3		T60	1		T249	1
auto[1]	values[2]	values[4]	10	1			T47	2		T34	2		T190	1
auto[1]	values[2]	values[5]	7	1			T20	1		T293	1		T294	2
auto[1]	values[2]	values[6]	10	1			T205	3		T58	1		T60	1
auto[1]	values[2]	values[7]	8	1			T6	1		T47	1		T34	1
auto[1]	values[3]	values[0]	12	1			T102	4		T82	2		T58	1
auto[1]	values[3]	values[1]	6	1			T295	1		T296	1		T207	1
auto[1]	values[3]	values[2]	13	1			T210	1		T171	1		T214	1
auto[1]	values[3]	values[3]	3	1			T50	1		T85	1		T297	1
auto[1]	values[3]	values[4]	8	1			T31	1		T210	2		T60	2
auto[1]	values[3]	values[5]	9	1			T205	2		T262	3		T287	1
auto[1]	values[3]	values[6]	17	1			T31	2		T210	2		T261	2
auto[1]	values[3]	values[7]	7	1			T48	2		T243	1		T225	1
auto[1]	values[4]	values[0]	16	1			T46	1		T60	5		T173	1
auto[1]	values[4]	values[1]	13	1			T44	2		T22	2		T31	1
auto[1]	values[4]	values[2]	26	1			T49	2		T31	3		T190	1
auto[1]	values[4]	values[3]	14	1			T47	1		T199	2		T298	2
auto[1]	values[4]	values[4]	17	1			T199	4		T281	2		T198	3
auto[1]	values[4]	values[5]	8	1			T85	1		T296	1		T299	2
auto[1]	values[4]	values[6]	9	1			T6	1		T213	2		T201	3
auto[1]	values[4]	values[7]	17	1			T280	2		T243	3		T171	1
auto[1]	values[5]	values[0]	12	1			T85	4		T60	1		T237	1
auto[1]	values[5]	values[1]	19	1			T281	1		T300	4		T255	4
auto[1]	values[5]	values[2]	22	1			T50	6		T20	1		T200	1
auto[1]	values[5]	values[3]	14	1			T220	2		T244	4		T237	1
auto[1]	values[5]	values[4]	11	1			T220	2		T249	1		T291	3
auto[1]	values[5]	values[5]	17	1			T25	3		T50	1		T215	2
auto[1]	values[5]	values[6]	5	1			T205	1		T190	3		T301	1
auto[1]	values[5]	values[7]	15	1			T34	3		T241	1		T191	2
auto[1]	values[6]	values[0]	2	1			T215	1		T302	1		-	-
auto[1]	values[6]	values[1]	27	1			T205	2		T210	3		T270	4
auto[1]	values[6]	values[2]	9	1			T85	2		T191	1		T173	2
auto[1]	values[6]	values[3]	21	1			T46	2		T190	3		T303	2
auto[1]	values[6]	values[4]	13	1			T243	1		T201	1		T244	3
auto[1]	values[6]	values[5]	11	1			T199	1		T81	4		T223	2
auto[1]	values[6]	values[6]	8	1			T82	4		T237	1		T304	2
auto[1]	values[6]	values[7]	6	1			T34	2		T22	1		T266	1
auto[1]	values[7]	values[0]	19	1			T85	2		T191	3		T171	3
auto[1]	values[7]	values[1]	6	1			T191	2		T171	1		T291	2
auto[1]	values[7]	values[2]	5	1			T281	2		T304	1		T305	2
auto[1]	values[7]	values[3]	5	1			T239	3		T299	1		T306	1
auto[1]	values[7]	values[4]	2	1			T171	2		-	-		-	-
auto[1]	values[7]	values[5]	3	1			T22	1		T209	2		-	-
auto[1]	values[7]	values[6]	17	1			T51	1		T205	1		T31	2
auto[1]	values[7]	values[7]	16	1			T25	2		T178	6		T58	1