Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	894	1			T15	18		T17	17		T18	4
all_values[1]	894	1			T15	18		T17	17		T18	4
all_values[2]	894	1			T15	18		T17	17		T18	4
all_values[3]	894	1			T15	18		T17	17		T18	4
all_values[4]	894	1			T15	18		T17	17		T18	4
all_values[5]	894	1			T15	18		T17	17		T18	4
all_values[6]	894	1			T15	18		T17	17		T18	4
all_values[7]	894	1			T15	18		T17	17		T18	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3729

1

T15

71

T17

68

T18

20

auto[1]

3423

1

T15

73

T17

68

T18

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2805

1

T15

58

T17

50

T18

8

auto[1]

4347

1

T15

86

T17

86

T18

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4058

1

T15

80

T17

73

T18

17

auto[1]

3094

1

T15

64

T17

63

T18

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	158	1			T15	5		T17	3		T34	3
all_values[0]	auto[0]	auto[0]	auto[1]	103	1			T15	3		T17	2		T18	1
all_values[0]	auto[0]	auto[1]	auto[0]	146	1			T15	1		T17	2		T34	2
all_values[0]	auto[0]	auto[1]	auto[1]	92	1			T15	2		T17	2		T21	1
all_values[0]	auto[1]	auto[0]	auto[1]	224	1			T15	6		T17	6		T18	1
all_values[0]	auto[1]	auto[1]	auto[1]	171	1			T15	1		T17	2		T18	2
all_values[1]	auto[0]	auto[0]	auto[0]	186	1			T15	2		T17	4		T34	3
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T17	1		T18	2		T34	2
all_values[1]	auto[0]	auto[1]	auto[0]	169	1			T15	3		T17	4		T34	1
all_values[1]	auto[0]	auto[1]	auto[1]	99	1			T15	1		T17	2		T18	1
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T15	4		T17	3		T34	1
all_values[1]	auto[1]	auto[1]	auto[1]	169	1			T15	8		T17	3		T18	1
all_values[2]	auto[0]	auto[0]	auto[0]	188	1			T15	1		T17	2		T34	2
all_values[2]	auto[0]	auto[0]	auto[1]	85	1			T15	2		T18	1		T21	2
all_values[2]	auto[0]	auto[1]	auto[0]	138	1			T15	4		T17	3		T21	4
all_values[2]	auto[0]	auto[1]	auto[1]	100	1			T15	4		T17	3		T18	1
all_values[2]	auto[1]	auto[0]	auto[1]	198	1			T15	6		T17	3		T18	1
all_values[2]	auto[1]	auto[1]	auto[1]	185	1			T15	1		T17	6		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	166	1			T15	3		T17	5		T34	2
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T21	4		T30	1		T31	2
all_values[3]	auto[0]	auto[1]	auto[0]	149	1			T15	3		T17	5		T20	1
all_values[3]	auto[0]	auto[1]	auto[1]	92	1			T15	2		T17	1		T18	1
all_values[3]	auto[1]	auto[0]	auto[1]	226	1			T15	8		T17	2		T18	2
all_values[3]	auto[1]	auto[1]	auto[1]	176	1			T15	2		T17	4		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	164	1			T15	3		T17	1		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	96	1			T15	2		T17	4		T18	1
all_values[4]	auto[0]	auto[1]	auto[0]	169	1			T15	2		T17	1		T34	1
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T15	2		T21	1		T176	2
all_values[4]	auto[1]	auto[0]	auto[1]	218	1			T15	2		T17	7		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	179	1			T15	7		T17	4		T34	2
all_values[5]	auto[0]	auto[0]	auto[0]	253	1			T15	5		T17	4		T18	3
all_values[5]	auto[0]	auto[1]	auto[0]	238	1			T15	7		T17	8		T34	1
all_values[5]	auto[1]	auto[0]	auto[1]	214	1			T15	5		T17	2		T18	1
all_values[5]	auto[1]	auto[1]	auto[1]	189	1			T15	1		T17	3		T20	1
all_values[6]	auto[0]	auto[0]	auto[0]	178	1			T15	4		T17	2		T18	3
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T15	2		T34	1		T21	1
all_values[6]	auto[0]	auto[1]	auto[0]	164	1			T15	3		T17	2		T21	8
all_values[6]	auto[0]	auto[1]	auto[1]	106	1			T15	1		T17	2		T34	1
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T15	2		T17	6		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	198	1			T15	6		T17	5		T19	1
all_values[7]	auto[0]	auto[0]	auto[0]	168	1			T15	2		T17	3		T20	3
all_values[7]	auto[0]	auto[0]	auto[1]	86	1			T15	1		T17	3		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	171	1			T15	10		T17	1		T18	1
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T17	3		T18	1		T34	2
all_values[7]	auto[1]	auto[0]	auto[1]	214	1			T15	3		T17	5		T34	2
all_values[7]	auto[1]	auto[1]	auto[1]	169	1			T15	2		T17	2		T18	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal