Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1689

1

T3

11

T4

17

T8

9

auto[1]

1724

1

T3

14

T4

15

T8

12

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1710

1

T11

3

T25

15

T26

4

auto[1]

1703

1

T3

25

T4

32

T8

21

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2753

1

T3

25

T4

32

T8

21

auto[1]

660

1

T11

2

T25

8

T28

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	687	1			T3	4		T4	7		T8	4
valid[1]	657	1			T3	6		T4	6		T8	4
valid[2]	705	1			T3	6		T4	6		T8	4
valid[3]	694	1			T3	5		T4	6		T8	6
valid[4]	670	1			T3	4		T4	7		T8	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	119	1			T25	1		T28	1		T18	2
auto[0]	auto[0]	valid[0]	auto[1]	169	1			T3	1		T4	2		T8	1
auto[0]	auto[0]	valid[1]	auto[0]	102	1			T25	1		T40	1		T54	1
auto[0]	auto[0]	valid[1]	auto[1]	181	1			T3	1		T4	5		T8	3
auto[0]	auto[0]	valid[2]	auto[0]	112	1			T26	2		T28	1		T17	1
auto[0]	auto[0]	valid[2]	auto[1]	156	1			T3	3		T4	4		T8	1
auto[0]	auto[0]	valid[3]	auto[0]	101	1			T28	1		T18	1		T52	3
auto[0]	auto[0]	valid[3]	auto[1]	164	1			T3	3		T4	2		T8	2
auto[0]	auto[0]	valid[4]	auto[0]	77	1			T11	1		T28	3		T17	1
auto[0]	auto[0]	valid[4]	auto[1]	170	1			T3	3		T4	4		T8	2
auto[0]	auto[1]	valid[0]	auto[0]	105	1			T25	1		T28	2		T52	1
auto[0]	auto[1]	valid[0]	auto[1]	157	1			T3	3		T4	5		T8	3
auto[0]	auto[1]	valid[1]	auto[0]	109	1			T18	1		T46	1		T34	1
auto[0]	auto[1]	valid[1]	auto[1]	151	1			T3	5		T4	1		T8	1
auto[0]	auto[1]	valid[2]	auto[0]	104	1			T28	1		T17	1		T46	2
auto[0]	auto[1]	valid[2]	auto[1]	191	1			T3	3		T4	2		T8	3
auto[0]	auto[1]	valid[3]	auto[0]	111	1			T25	1		T28	1		T17	2
auto[0]	auto[1]	valid[3]	auto[1]	190	1			T3	2		T4	4		T8	4
auto[0]	auto[1]	valid[4]	auto[0]	110	1			T25	3		T26	2		T28	2
auto[0]	auto[1]	valid[4]	auto[1]	174	1			T3	1		T4	3		T8	1
auto[1]	auto[0]	valid[0]	auto[0]	54	1			T25	2		T52	1		T46	1
auto[1]	auto[0]	valid[1]	auto[0]	62	1			T25	1		T46	2		T34	2
auto[1]	auto[0]	valid[2]	auto[0]	60	1			T25	1		T17	1		T52	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T25	1		T28	1		T18	2
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T11	2		T25	2		T28	1
auto[1]	auto[1]	valid[0]	auto[0]	83	1			T28	1		T17	1		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	52	1			T18	1		T34	1		T56	3
auto[1]	auto[1]	valid[2]	auto[0]	82	1			T25	1		T28	1		T17	1
auto[1]	auto[1]	valid[3]	auto[0]	52	1			T17	1		T52	2		T46	1
auto[1]	auto[1]	valid[4]	auto[0]	53	1			T54	2		T46	1		T92	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal