Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44597

1

T11

12

T25

310

T26

157

auto[1]

17505

1

T3

232

T4

422

T8

431

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45553

1

T3

232

T4

422

T8

431

auto[1]

16549

1

T11

9

T25

115

T26

76

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31868	1			T3	122		T4	210		T8	224
others[1]	5299	1			T3	22		T4	40		T8	35
others[2]	5248	1			T3	19		T4	31		T8	37
others[3]	5908	1			T3	20		T4	43		T8	43
interest[1]	3572	1			T3	14		T4	22		T8	22
interest[4]	20868	1			T3	79		T4	132		T8	153
interest[64]	10207	1			T3	35		T4	76		T8	70

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14344	1			T11	2		T25	109		T26	34
auto[0]	auto[0]	others[1]	2375	1			T25	7		T26	11		T28	30
auto[0]	auto[0]	others[2]	2383	1			T25	13		T26	5		T28	31
auto[0]	auto[0]	others[3]	2662	1			T25	21		T26	8		T28	30
auto[0]	auto[0]	interest[1]	1623	1			T25	13		T26	9		T28	16
auto[0]	auto[0]	interest[4]	9340	1			T11	2		T25	68		T26	26
auto[0]	auto[0]	interest[64]	4661	1			T11	1		T25	32		T26	14
auto[0]	auto[1]	others[0]	9141	1			T3	122		T4	210		T8	224
auto[0]	auto[1]	others[1]	1523	1			T3	22		T4	40		T8	35
auto[0]	auto[1]	others[2]	1422	1			T3	19		T4	31		T8	37
auto[0]	auto[1]	others[3]	1591	1			T3	20		T4	43		T8	43
auto[0]	auto[1]	interest[1]	971	1			T3	14		T4	22		T8	22
auto[0]	auto[1]	interest[4]	6038	1			T3	79		T4	132		T8	153
auto[0]	auto[1]	interest[64]	2857	1			T3	35		T4	76		T8	70
auto[1]	auto[0]	others[0]	8383	1			T11	4		T25	64		T26	34
auto[1]	auto[0]	others[1]	1401	1			T25	5		T26	6		T28	16
auto[1]	auto[0]	others[2]	1443	1			T11	1		T25	10		T26	11
auto[1]	auto[0]	others[3]	1655	1			T11	1		T25	15		T26	5
auto[1]	auto[0]	interest[1]	978	1			T11	1		T25	8		T26	3
auto[1]	auto[0]	interest[4]	5490	1			T11	3		T25	45		T26	23
auto[1]	auto[0]	interest[64]	2689	1			T11	2		T25	13		T26	17

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal