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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
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T1040 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.436288913 Jul 02 09:54:39 AM PDT 24 Jul 02 09:54:41 AM PDT 24 14619588 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1959855418 Jul 02 09:54:31 AM PDT 24 Jul 02 09:54:33 AM PDT 24 89051018 ps
T164 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.15548846 Jul 02 09:54:39 AM PDT 24 Jul 02 09:54:44 AM PDT 24 356081572 ps
T1041 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.463187571 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:41 AM PDT 24 23384627 ps
T1042 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2677990557 Jul 02 09:54:49 AM PDT 24 Jul 02 09:54:51 AM PDT 24 20885626 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2534230106 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:42 AM PDT 24 572377350 ps
T1044 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4118829646 Jul 02 09:54:57 AM PDT 24 Jul 02 09:54:59 AM PDT 24 29525055 ps
T110 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2904451626 Jul 02 09:54:31 AM PDT 24 Jul 02 09:54:36 AM PDT 24 841843093 ps
T108 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1490731848 Jul 02 09:54:22 AM PDT 24 Jul 02 09:54:29 AM PDT 24 288606724 ps
T130 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3697250343 Jul 02 09:54:42 AM PDT 24 Jul 02 09:54:47 AM PDT 24 100415532 ps
T129 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2318682960 Jul 02 09:54:32 AM PDT 24 Jul 02 09:54:38 AM PDT 24 113206673 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.481545170 Jul 02 09:54:30 AM PDT 24 Jul 02 09:54:54 AM PDT 24 1455590935 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2524288822 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:36 AM PDT 24 39717688 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3550524542 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:40 AM PDT 24 137187713 ps
T120 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.163355845 Jul 02 09:54:43 AM PDT 24 Jul 02 09:54:46 AM PDT 24 108552911 ps
T1048 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1597160045 Jul 02 09:54:38 AM PDT 24 Jul 02 09:54:45 AM PDT 24 36756267 ps
T131 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.890813096 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:40 AM PDT 24 216833709 ps
T121 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2056128350 Jul 02 09:54:55 AM PDT 24 Jul 02 09:55:00 AM PDT 24 876090634 ps
T165 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.795771788 Jul 02 09:54:50 AM PDT 24 Jul 02 09:54:53 AM PDT 24 151073694 ps
T1049 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.703853589 Jul 02 09:54:41 AM PDT 24 Jul 02 09:54:42 AM PDT 24 12633953 ps
T166 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4107828723 Jul 02 09:54:59 AM PDT 24 Jul 02 09:55:03 AM PDT 24 411596396 ps
T1050 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3769020524 Jul 02 09:55:07 AM PDT 24 Jul 02 09:55:08 AM PDT 24 44728988 ps
T109 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2770488456 Jul 02 09:54:37 AM PDT 24 Jul 02 09:54:52 AM PDT 24 201170235 ps
T126 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2291311824 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:39 AM PDT 24 71327434 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.996180530 Jul 02 09:54:24 AM PDT 24 Jul 02 09:54:29 AM PDT 24 101801910 ps
T142 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.766363887 Jul 02 09:54:24 AM PDT 24 Jul 02 09:54:30 AM PDT 24 104787645 ps
T1052 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1475650569 Jul 02 09:54:52 AM PDT 24 Jul 02 09:54:54 AM PDT 24 17413778 ps
T181 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2042931337 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:53 AM PDT 24 582567037 ps
T167 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2528314802 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:36 AM PDT 24 74295022 ps
T1053 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1568310791 Jul 02 09:55:14 AM PDT 24 Jul 02 09:55:17 AM PDT 24 10952920 ps
T123 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3932309707 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:41 AM PDT 24 47814335 ps
T1054 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.875597361 Jul 02 09:54:27 AM PDT 24 Jul 02 09:54:43 AM PDT 24 608470448 ps
T1055 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2986130735 Jul 02 09:54:31 AM PDT 24 Jul 02 09:54:33 AM PDT 24 43616333 ps
T1056 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3169379256 Jul 02 09:54:41 AM PDT 24 Jul 02 09:54:42 AM PDT 24 21963884 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.202848102 Jul 02 09:54:27 AM PDT 24 Jul 02 09:54:32 AM PDT 24 392578591 ps
T143 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3351977059 Jul 02 09:54:31 AM PDT 24 Jul 02 09:54:57 AM PDT 24 2329728319 ps
T168 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3481809872 Jul 02 09:54:25 AM PDT 24 Jul 02 09:54:30 AM PDT 24 231533906 ps
T1058 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3954006548 Jul 02 09:54:48 AM PDT 24 Jul 02 09:54:50 AM PDT 24 17848625 ps
T187 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2179327236 Jul 02 09:54:27 AM PDT 24 Jul 02 09:54:42 AM PDT 24 206089171 ps
T1059 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2840471827 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:40 AM PDT 24 57096572 ps
T1060 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2002713223 Jul 02 09:54:49 AM PDT 24 Jul 02 09:54:52 AM PDT 24 26464815 ps
T1061 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1773092449 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:42 AM PDT 24 626094870 ps
T122 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2859178437 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:38 AM PDT 24 45503430 ps
T184 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4137896210 Jul 02 09:54:21 AM PDT 24 Jul 02 09:54:47 AM PDT 24 1056242743 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2905683411 Jul 02 09:54:52 AM PDT 24 Jul 02 09:54:54 AM PDT 24 39246181 ps
T1063 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3637402084 Jul 02 09:55:04 AM PDT 24 Jul 02 09:55:06 AM PDT 24 13734967 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3091560806 Jul 02 09:54:20 AM PDT 24 Jul 02 09:54:22 AM PDT 24 34212540 ps
T144 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2985480571 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:39 AM PDT 24 28629892 ps
T1065 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2967357935 Jul 02 09:54:51 AM PDT 24 Jul 02 09:54:53 AM PDT 24 59440060 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3342206971 Jul 02 09:54:55 AM PDT 24 Jul 02 09:55:04 AM PDT 24 382372003 ps
T1067 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.60213950 Jul 02 09:54:36 AM PDT 24 Jul 02 09:54:40 AM PDT 24 76536662 ps
T1068 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.28928927 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:41 AM PDT 24 886685971 ps
T1069 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3256377439 Jul 02 09:54:37 AM PDT 24 Jul 02 09:54:41 AM PDT 24 101555965 ps
T117 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3108270532 Jul 02 09:54:41 AM PDT 24 Jul 02 09:54:44 AM PDT 24 29562257 ps
T1070 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4289672728 Jul 02 09:54:45 AM PDT 24 Jul 02 09:54:48 AM PDT 24 199153708 ps
T188 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.276523040 Jul 02 09:54:48 AM PDT 24 Jul 02 09:55:03 AM PDT 24 396402089 ps
T1071 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.851047281 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:37 AM PDT 24 199397375 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.60525750 Jul 02 09:54:31 AM PDT 24 Jul 02 09:54:33 AM PDT 24 135266143 ps
T118 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2660599620 Jul 02 09:54:29 AM PDT 24 Jul 02 09:54:34 AM PDT 24 159179236 ps
T1073 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2394931280 Jul 02 09:54:32 AM PDT 24 Jul 02 09:54:36 AM PDT 24 26424450 ps
T1074 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.36001397 Jul 02 09:55:01 AM PDT 24 Jul 02 09:55:11 AM PDT 24 2237287929 ps
T90 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.493013285 Jul 02 09:54:32 AM PDT 24 Jul 02 09:54:34 AM PDT 24 23943373 ps
T1075 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3246478558 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:39 AM PDT 24 38819524 ps
T1076 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3854815003 Jul 02 09:54:39 AM PDT 24 Jul 02 09:54:41 AM PDT 24 54711596 ps
T1077 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3121975100 Jul 02 09:54:46 AM PDT 24 Jul 02 09:54:48 AM PDT 24 16470540 ps
T1078 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3153454457 Jul 02 09:54:53 AM PDT 24 Jul 02 09:54:56 AM PDT 24 26571285 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1080609625 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:39 AM PDT 24 46724689 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3731318808 Jul 02 09:54:20 AM PDT 24 Jul 02 09:54:24 AM PDT 24 172948200 ps
T1081 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3622257546 Jul 02 09:54:41 AM PDT 24 Jul 02 09:54:47 AM PDT 24 24780200 ps
T1082 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2749664791 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 12800561 ps
T1083 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3806543873 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:39 AM PDT 24 428060134 ps
T1084 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4096737022 Jul 02 09:54:50 AM PDT 24 Jul 02 09:54:55 AM PDT 24 238260645 ps
T182 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2142046012 Jul 02 09:54:47 AM PDT 24 Jul 02 09:55:11 AM PDT 24 5103317089 ps
T1085 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3447485392 Jul 02 09:54:31 AM PDT 24 Jul 02 09:54:32 AM PDT 24 28998596 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2655366113 Jul 02 09:54:27 AM PDT 24 Jul 02 09:54:52 AM PDT 24 1295357907 ps
T127 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.414633893 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:39 AM PDT 24 24580341 ps
T1087 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1632793210 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:39 AM PDT 24 377149569 ps
T1088 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4232920472 Jul 02 09:54:57 AM PDT 24 Jul 02 09:55:01 AM PDT 24 439537844 ps
T1089 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.345188771 Jul 02 09:54:54 AM PDT 24 Jul 02 09:54:56 AM PDT 24 21605462 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4188709357 Jul 02 09:54:29 AM PDT 24 Jul 02 09:54:31 AM PDT 24 20426967 ps
T1091 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3688157699 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:39 AM PDT 24 600226927 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3059565053 Jul 02 09:54:22 AM PDT 24 Jul 02 09:54:26 AM PDT 24 14878470 ps
T1093 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3616056441 Jul 02 09:54:41 AM PDT 24 Jul 02 09:54:42 AM PDT 24 36819745 ps
T1094 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1104758735 Jul 02 09:54:42 AM PDT 24 Jul 02 09:54:47 AM PDT 24 531925004 ps
T119 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1682266407 Jul 02 09:54:24 AM PDT 24 Jul 02 09:54:32 AM PDT 24 245469842 ps
T1095 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.674056215 Jul 02 09:54:25 AM PDT 24 Jul 02 09:54:43 AM PDT 24 3651575911 ps
T1096 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2410749138 Jul 02 09:54:36 AM PDT 24 Jul 02 09:54:40 AM PDT 24 15350353 ps
T1097 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1295565142 Jul 02 09:54:26 AM PDT 24 Jul 02 09:54:32 AM PDT 24 492783914 ps
T1098 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2360775225 Jul 02 09:54:23 AM PDT 24 Jul 02 09:54:30 AM PDT 24 347894435 ps
T1099 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.572550261 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:37 AM PDT 24 11964493 ps
T186 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1512338043 Jul 02 09:54:31 AM PDT 24 Jul 02 09:54:56 AM PDT 24 1995270736 ps
T124 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3192256278 Jul 02 09:54:56 AM PDT 24 Jul 02 09:55:01 AM PDT 24 375185339 ps
T1100 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1767562509 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:44 AM PDT 24 322651458 ps
T1101 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4287973996 Jul 02 09:54:50 AM PDT 24 Jul 02 09:54:52 AM PDT 24 10832289 ps
T91 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2622905411 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:41 AM PDT 24 24572989 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1282058921 Jul 02 09:54:27 AM PDT 24 Jul 02 09:54:32 AM PDT 24 88860893 ps
T1103 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3941392635 Jul 02 09:54:51 AM PDT 24 Jul 02 09:54:53 AM PDT 24 10908962 ps
T1104 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2800045456 Jul 02 09:54:53 AM PDT 24 Jul 02 09:54:56 AM PDT 24 287296256 ps
T1105 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1417511363 Jul 02 09:54:35 AM PDT 24 Jul 02 09:55:01 AM PDT 24 1088403666 ps
T1106 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2158853359 Jul 02 09:54:48 AM PDT 24 Jul 02 09:54:51 AM PDT 24 86307820 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4277672844 Jul 02 09:54:21 AM PDT 24 Jul 02 09:54:25 AM PDT 24 134392836 ps
T1108 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4276210963 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:37 AM PDT 24 135418558 ps
T1109 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3014035980 Jul 02 09:54:28 AM PDT 24 Jul 02 09:55:11 AM PDT 24 2703837179 ps
T185 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.504100449 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:59 AM PDT 24 2008999649 ps
T1110 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1002701563 Jul 02 09:54:36 AM PDT 24 Jul 02 09:54:47 AM PDT 24 1435532286 ps
T125 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1353972398 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:41 AM PDT 24 145307657 ps
T1111 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4082516078 Jul 02 09:54:20 AM PDT 24 Jul 02 09:54:22 AM PDT 24 20628967 ps
T128 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1679515469 Jul 02 09:54:40 AM PDT 24 Jul 02 09:54:46 AM PDT 24 3302212219 ps
T183 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3280105160 Jul 02 09:54:47 AM PDT 24 Jul 02 09:55:10 AM PDT 24 4169575217 ps
T1112 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1893954287 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:40 AM PDT 24 45815878 ps
T1113 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1018839109 Jul 02 09:54:45 AM PDT 24 Jul 02 09:54:47 AM PDT 24 38943344 ps
T1114 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2878196336 Jul 02 09:54:49 AM PDT 24 Jul 02 09:54:54 AM PDT 24 1396069407 ps
T1115 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.143552968 Jul 02 09:54:58 AM PDT 24 Jul 02 09:55:04 AM PDT 24 1036123170 ps
T1116 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3770938877 Jul 02 09:54:35 AM PDT 24 Jul 02 09:54:45 AM PDT 24 1810811099 ps
T1117 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.999082975 Jul 02 09:54:44 AM PDT 24 Jul 02 09:54:47 AM PDT 24 25124757 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2694121620 Jul 02 09:54:27 AM PDT 24 Jul 02 09:54:32 AM PDT 24 175140846 ps
T1119 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1752986083 Jul 02 09:54:23 AM PDT 24 Jul 02 09:54:27 AM PDT 24 11981389 ps
T1120 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2617852631 Jul 02 09:54:30 AM PDT 24 Jul 02 09:54:33 AM PDT 24 29292022 ps
T1121 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4258099716 Jul 02 09:54:37 AM PDT 24 Jul 02 09:54:40 AM PDT 24 17423697 ps
T1122 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.600156709 Jul 02 09:54:51 AM PDT 24 Jul 02 09:54:54 AM PDT 24 46564874 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4071253764 Jul 02 09:54:21 AM PDT 24 Jul 02 09:54:24 AM PDT 24 11439522 ps
T1124 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2747589161 Jul 02 09:55:03 AM PDT 24 Jul 02 09:55:05 AM PDT 24 39587909 ps
T1125 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.684131101 Jul 02 09:54:40 AM PDT 24 Jul 02 09:54:45 AM PDT 24 1345631146 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2758656726 Jul 02 09:54:23 AM PDT 24 Jul 02 09:54:42 AM PDT 24 572897677 ps
T1127 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1947940167 Jul 02 09:54:42 AM PDT 24 Jul 02 09:54:46 AM PDT 24 93349649 ps
T1128 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.279412042 Jul 02 09:54:21 AM PDT 24 Jul 02 09:54:28 AM PDT 24 401801301 ps
T1129 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2496216854 Jul 02 09:54:52 AM PDT 24 Jul 02 09:54:53 AM PDT 24 11910566 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1325406650 Jul 02 09:54:45 AM PDT 24 Jul 02 09:54:58 AM PDT 24 57157196 ps
T1131 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.723544187 Jul 02 09:54:46 AM PDT 24 Jul 02 09:54:48 AM PDT 24 110897878 ps
T1132 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1155749690 Jul 02 09:54:27 AM PDT 24 Jul 02 09:54:32 AM PDT 24 367651612 ps
T1133 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1718542919 Jul 02 09:54:42 AM PDT 24 Jul 02 09:54:46 AM PDT 24 253782945 ps
T1134 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3272855875 Jul 02 09:54:27 AM PDT 24 Jul 02 09:54:30 AM PDT 24 31948650 ps
T180 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2383887813 Jul 02 09:54:23 AM PDT 24 Jul 02 09:54:31 AM PDT 24 169545768 ps
T1135 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.588056449 Jul 02 09:54:32 AM PDT 24 Jul 02 09:54:37 AM PDT 24 30218483 ps
T1136 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.764507828 Jul 02 09:54:48 AM PDT 24 Jul 02 09:54:51 AM PDT 24 16181111 ps
T1137 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2595753015 Jul 02 09:55:03 AM PDT 24 Jul 02 09:55:11 AM PDT 24 336437950 ps
T1138 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1340025274 Jul 02 09:55:03 AM PDT 24 Jul 02 09:55:05 AM PDT 24 174139491 ps
T1139 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3880963923 Jul 02 09:54:45 AM PDT 24 Jul 02 09:54:47 AM PDT 24 14989753 ps
T1140 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.747305883 Jul 02 09:54:50 AM PDT 24 Jul 02 09:54:54 AM PDT 24 209771098 ps
T1141 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1879495042 Jul 02 09:54:26 AM PDT 24 Jul 02 09:54:30 AM PDT 24 22241640 ps
T1142 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.149960141 Jul 02 09:54:32 AM PDT 24 Jul 02 09:54:34 AM PDT 24 56853254 ps
T1143 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2159174199 Jul 02 09:54:22 AM PDT 24 Jul 02 09:54:28 AM PDT 24 287533098 ps
T1144 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1442841492 Jul 02 09:54:43 AM PDT 24 Jul 02 09:54:46 AM PDT 24 304913128 ps
T1145 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3985668848 Jul 02 09:54:32 AM PDT 24 Jul 02 09:54:39 AM PDT 24 179193509 ps
T1146 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.106837511 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:37 AM PDT 24 12896198 ps
T1147 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1300920298 Jul 02 09:54:32 AM PDT 24 Jul 02 09:54:38 AM PDT 24 531820180 ps
T1148 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.108114902 Jul 02 09:54:34 AM PDT 24 Jul 02 09:54:39 AM PDT 24 103056461 ps
T1149 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2947343246 Jul 02 09:55:01 AM PDT 24 Jul 02 09:55:02 AM PDT 24 31976382 ps
T1150 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.808843656 Jul 02 09:54:38 AM PDT 24 Jul 02 09:54:40 AM PDT 24 51206417 ps
T189 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3807596416 Jul 02 09:54:33 AM PDT 24 Jul 02 09:54:41 AM PDT 24 406231066 ps

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2389781122
Short name T6
Test name
Test status
Simulation time 14280069397 ps
CPU time 106.95 seconds
Started Jul 02 09:52:01 AM PDT 24
Finished Jul 02 09:53:51 AM PDT 24
Peak memory 270416 kb
Host smart-c7fff53a-9bf5-40ea-979e-2baa5e7de429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389781122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2389781122
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4174652879
Short name T25
Test name
Test status
Simulation time 288478761439 ps
CPU time 673.29 seconds
Started Jul 02 09:51:23 AM PDT 24
Finished Jul 02 10:02:44 AM PDT 24
Peak memory 269660 kb
Host smart-4932a068-b797-4600-844e-ba9454da0cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174652879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4174652879
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3868389680
Short name T31
Test name
Test status
Simulation time 356474371842 ps
CPU time 588.81 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 10:02:01 AM PDT 24
Peak memory 284588 kb
Host smart-e1b637d7-c426-4502-85f5-c1603561abee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868389680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3868389680
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_upload.2956357284
Short name T14
Test name
Test status
Simulation time 3163031862 ps
CPU time 11.98 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 225644 kb
Host smart-19432690-fa6b-48d6-9b5e-34a642e68664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956357284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2956357284
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3020806361
Short name T138
Test name
Test status
Simulation time 83475382 ps
CPU time 2.27 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:38 AM PDT 24
Peak memory 215584 kb
Host smart-5e9157d8-9885-44c5-af94-b8c059f95fb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020806361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
020806361
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2867674053
Short name T34
Test name
Test status
Simulation time 5583719609 ps
CPU time 121.07 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:52:55 AM PDT 24
Peak memory 269064 kb
Host smart-806bb4ec-d38b-4d91-a1fd-b76ab31568a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867674053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2867674053
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1815775136
Short name T74
Test name
Test status
Simulation time 15484583 ps
CPU time 0.72 seconds
Started Jul 02 09:50:27 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 217068 kb
Host smart-3d86c1ad-6cf4-4d6d-beca-7345d000a85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815775136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1815775136
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.203234002
Short name T58
Test name
Test status
Simulation time 212481494275 ps
CPU time 545.72 seconds
Started Jul 02 09:51:24 AM PDT 24
Finished Jul 02 10:00:31 AM PDT 24
Peak memory 283224 kb
Host smart-3e0b1fed-df01-4b8d-948a-8234605562f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203234002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.203234002
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1490731848
Short name T108
Test name
Test status
Simulation time 288606724 ps
CPU time 3.63 seconds
Started Jul 02 09:54:22 AM PDT 24
Finished Jul 02 09:54:29 AM PDT 24
Peak memory 215684 kb
Host smart-ee8669d8-896e-4648-ae52-2ce999e3cfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490731848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
490731848
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2176250651
Short name T18
Test name
Test status
Simulation time 12593444050 ps
CPU time 90.88 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:53:59 AM PDT 24
Peak memory 267720 kb
Host smart-658731c2-e316-402b-a742-e7baeb54b530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176250651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2176250651
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3754037022
Short name T75
Test name
Test status
Simulation time 114333824 ps
CPU time 1.15 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 236404 kb
Host smart-04b7238c-22d2-44b2-9fee-8feed177e000
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754037022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3754037022
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.774095092
Short name T171
Test name
Test status
Simulation time 293918747041 ps
CPU time 1276.83 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 10:13:21 AM PDT 24
Peak memory 283216 kb
Host smart-f6968c00-9c1c-4af4-934c-b991c3e7612c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774095092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.774095092
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3195977243
Short name T60
Test name
Test status
Simulation time 559943466148 ps
CPU time 1125.12 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 10:10:12 AM PDT 24
Peak memory 275044 kb
Host smart-17b0cd81-dd05-4f88-bbb4-fb5d47a61e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195977243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3195977243
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3546994117
Short name T158
Test name
Test status
Simulation time 383253823 ps
CPU time 3.84 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 221808 kb
Host smart-227d8f94-e3ac-4646-919b-a3c36dc1589a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3546994117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3546994117
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1840073664
Short name T57
Test name
Test status
Simulation time 187581834741 ps
CPU time 327.22 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:57:38 AM PDT 24
Peak memory 273376 kb
Host smart-9cbbefdf-74ef-4036-bc97-693385c075ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840073664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1840073664
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2184932901
Short name T190
Test name
Test status
Simulation time 5080742528 ps
CPU time 83.09 seconds
Started Jul 02 09:52:11 AM PDT 24
Finished Jul 02 09:53:37 AM PDT 24
Peak memory 264752 kb
Host smart-d2716aac-545c-4e91-848b-da5c930446ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184932901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2184932901
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4137896210
Short name T184
Test name
Test status
Simulation time 1056242743 ps
CPU time 23.11 seconds
Started Jul 02 09:54:21 AM PDT 24
Finished Jul 02 09:54:47 AM PDT 24
Peak memory 215928 kb
Host smart-dc31846e-ba31-4e0b-bf24-9d300ce9a6a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137896210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4137896210
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3894839962
Short name T209
Test name
Test status
Simulation time 211947859087 ps
CPU time 617.02 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 10:02:52 AM PDT 24
Peak memory 283260 kb
Host smart-35a44211-bd3a-426f-8808-ce348131bd02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894839962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3894839962
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1643691318
Short name T20
Test name
Test status
Simulation time 3907570577 ps
CPU time 81.55 seconds
Started Jul 02 09:51:30 AM PDT 24
Finished Jul 02 09:52:54 AM PDT 24
Peak memory 266328 kb
Host smart-4500c96f-5c77-4f51-912e-9ebedaab10dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643691318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1643691318
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2866539912
Short name T552
Test name
Test status
Simulation time 109413741 ps
CPU time 0.99 seconds
Started Jul 02 09:50:22 AM PDT 24
Finished Jul 02 09:50:31 AM PDT 24
Peak memory 218860 kb
Host smart-e4812115-94ab-41e7-9ef1-cb78399ebaf7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866539912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2866539912
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1877809961
Short name T52
Test name
Test status
Simulation time 17007420083 ps
CPU time 125.25 seconds
Started Jul 02 09:51:22 AM PDT 24
Finished Jul 02 09:53:29 AM PDT 24
Peak memory 250428 kb
Host smart-106d77ee-824a-4d70-a3e0-9a614f7a1e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877809961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1877809961
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.229240906
Short name T245
Test name
Test status
Simulation time 25227243234 ps
CPU time 54.47 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:51:18 AM PDT 24
Peak memory 255976 kb
Host smart-356b9e16-6753-44d1-aacf-aaf9916e3355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229240906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
229240906
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2978518254
Short name T380
Test name
Test status
Simulation time 49300204 ps
CPU time 0.72 seconds
Started Jul 02 09:50:30 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 206424 kb
Host smart-d852ef33-c361-4b9e-9857-bc825d3504ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978518254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
978518254
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4057758374
Short name T304
Test name
Test status
Simulation time 52522599941 ps
CPU time 377.67 seconds
Started Jul 02 09:50:53 AM PDT 24
Finished Jul 02 09:57:12 AM PDT 24
Peak memory 250328 kb
Host smart-07132b78-0136-43db-89a6-80c82a0fc39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057758374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4057758374
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.384780208
Short name T287
Test name
Test status
Simulation time 94862828788 ps
CPU time 433.64 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:57:47 AM PDT 24
Peak memory 265668 kb
Host smart-252f4194-13a6-40e1-b6e5-fca2e0b7aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384780208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.384780208
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3432337094
Short name T241
Test name
Test status
Simulation time 227346645319 ps
CPU time 366.49 seconds
Started Jul 02 09:51:02 AM PDT 24
Finished Jul 02 09:57:11 AM PDT 24
Peak memory 253776 kb
Host smart-d75d9aa6-4dec-478e-9c2b-d1c13c5b5ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432337094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3432337094
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2670914975
Short name T205
Test name
Test status
Simulation time 47234534639 ps
CPU time 81.03 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:53:04 AM PDT 24
Peak memory 257428 kb
Host smart-a6851ec7-5a2e-4db9-9d70-01134925c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670914975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2670914975
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.430119382
Short name T307
Test name
Test status
Simulation time 4563622169 ps
CPU time 62.37 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:53:03 AM PDT 24
Peak memory 233892 kb
Host smart-b9a18df1-cf3d-4af6-a550-c18bab6ddb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430119382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.430119382
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2383887813
Short name T180
Test name
Test status
Simulation time 169545768 ps
CPU time 4.61 seconds
Started Jul 02 09:54:23 AM PDT 24
Finished Jul 02 09:54:31 AM PDT 24
Peak memory 215820 kb
Host smart-6e17af92-2843-4537-a2e7-fb36ec6b5e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383887813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
383887813
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.640461072
Short name T4
Test name
Test status
Simulation time 2505005111 ps
CPU time 11.25 seconds
Started Jul 02 09:50:15 AM PDT 24
Finished Jul 02 09:50:35 AM PDT 24
Peak memory 217492 kb
Host smart-b39e7529-ec92-4f73-b43b-17ae2149bcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640461072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.640461072
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2219254495
Short name T199
Test name
Test status
Simulation time 21386014981 ps
CPU time 94.17 seconds
Started Jul 02 09:52:01 AM PDT 24
Finished Jul 02 09:53:38 AM PDT 24
Peak memory 266032 kb
Host smart-ced8f28f-fad6-452b-a52c-b02e9a247c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219254495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2219254495
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2142046012
Short name T182
Test name
Test status
Simulation time 5103317089 ps
CPU time 22.36 seconds
Started Jul 02 09:54:47 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 215704 kb
Host smart-f3aa0cfd-5d33-48c2-8d2c-8f4eae3ff967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142046012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2142046012
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1512338043
Short name T186
Test name
Test status
Simulation time 1995270736 ps
CPU time 14.93 seconds
Started Jul 02 09:54:31 AM PDT 24
Finished Jul 02 09:54:56 AM PDT 24
Peak memory 216232 kb
Host smart-93cfab6d-aa4a-424d-880b-9e735163f2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512338043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1512338043
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3382654473
Short name T299
Test name
Test status
Simulation time 11212676764 ps
CPU time 67.91 seconds
Started Jul 02 09:51:27 AM PDT 24
Finished Jul 02 09:52:37 AM PDT 24
Peak memory 252836 kb
Host smart-b6d7f05d-afc2-4989-977d-cbb1fad85078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382654473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3382654473
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4250520593
Short name T331
Test name
Test status
Simulation time 32826044687 ps
CPU time 325.18 seconds
Started Jul 02 09:51:49 AM PDT 24
Finished Jul 02 09:57:16 AM PDT 24
Peak memory 254968 kb
Host smart-a45d1432-8533-4345-a685-6e799433995d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250520593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4250520593
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.191313413
Short name T99
Test name
Test status
Simulation time 358918824 ps
CPU time 9.11 seconds
Started Jul 02 09:52:41 AM PDT 24
Finished Jul 02 09:52:50 AM PDT 24
Peak memory 242004 kb
Host smart-68f69d1c-3171-4532-9eb8-c42e82b7ab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191313413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.191313413
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1380827754
Short name T832
Test name
Test status
Simulation time 49808462793 ps
CPU time 454.56 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:57:56 AM PDT 24
Peak memory 262732 kb
Host smart-33008017-2383-4ee8-93d6-d93b8d2be749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380827754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1380827754
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3120948718
Short name T297
Test name
Test status
Simulation time 11201377138 ps
CPU time 60.6 seconds
Started Jul 02 09:51:13 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 254928 kb
Host smart-9c0c6769-c86f-4255-bc43-1b5b2220afaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120948718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3120948718
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.191546813
Short name T316
Test name
Test status
Simulation time 237453732 ps
CPU time 6.83 seconds
Started Jul 02 09:51:40 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 233784 kb
Host smart-090af9bb-69c4-450a-b2eb-4f552a7ce9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191546813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.191546813
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1682266407
Short name T119
Test name
Test status
Simulation time 245469842 ps
CPU time 3.8 seconds
Started Jul 02 09:54:24 AM PDT 24
Finished Jul 02 09:54:32 AM PDT 24
Peak memory 215708 kb
Host smart-924c54c6-4ad2-4f87-9895-06f89cdc21c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682266407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
682266407
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.4085502122
Short name T293
Test name
Test status
Simulation time 43174458313 ps
CPU time 276.85 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 258440 kb
Host smart-a7ed749b-ea11-4d8b-8685-d187f98576f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085502122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.4085502122
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1166631032
Short name T289
Test name
Test status
Simulation time 4346105657 ps
CPU time 9.14 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 241916 kb
Host smart-92d4cc36-9f57-46c3-9f31-6fbd0cca9d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166631032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1166631032
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3784075259
Short name T39
Test name
Test status
Simulation time 121258442598 ps
CPU time 221.05 seconds
Started Jul 02 09:50:55 AM PDT 24
Finished Jul 02 09:54:37 AM PDT 24
Peak memory 258372 kb
Host smart-b45f6ad3-97e7-41e6-a90a-7e8ed70196a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784075259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3784075259
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3115300633
Short name T217
Test name
Test status
Simulation time 4117566549 ps
CPU time 7.33 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 233844 kb
Host smart-d91c143e-580b-44a1-b1b1-5b0bf3e9364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115300633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3115300633
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2070325750
Short name T1021
Test name
Test status
Simulation time 13245597812 ps
CPU time 69.31 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:52:19 AM PDT 24
Peak memory 253376 kb
Host smart-963e4875-e02d-4c02-aea7-baec212925da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070325750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2070325750
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3841433830
Short name T330
Test name
Test status
Simulation time 9401609521 ps
CPU time 47.37 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:56 AM PDT 24
Peak memory 217520 kb
Host smart-dfc066c9-03cd-4f0b-bdb0-93997ef3e9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841433830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3841433830
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1668141559
Short name T902
Test name
Test status
Simulation time 1290259163 ps
CPU time 9.18 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 238588 kb
Host smart-92e05eaf-0309-4d15-bcf4-ea9220dfe585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668141559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1668141559
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2300226414
Short name T302
Test name
Test status
Simulation time 5606156109 ps
CPU time 42.72 seconds
Started Jul 02 09:52:11 AM PDT 24
Finished Jul 02 09:52:57 AM PDT 24
Peak memory 250300 kb
Host smart-68ea7b32-c37a-4d29-a4b2-e8f973c063a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300226414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2300226414
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3364390967
Short name T5
Test name
Test status
Simulation time 26449258081 ps
CPU time 79.63 seconds
Started Jul 02 09:51:52 AM PDT 24
Finished Jul 02 09:53:13 AM PDT 24
Peak memory 241724 kb
Host smart-83af985d-da20-4265-9d5d-70087ba781f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364390967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3364390967
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2210806314
Short name T88
Test name
Test status
Simulation time 21849863 ps
CPU time 1.37 seconds
Started Jul 02 09:54:24 AM PDT 24
Finished Jul 02 09:54:29 AM PDT 24
Peak memory 207192 kb
Host smart-9314d7eb-2d74-47bc-8584-f05ae74d9b68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210806314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2210806314
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1300920298
Short name T1147
Test name
Test status
Simulation time 531820180 ps
CPU time 3.69 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:38 AM PDT 24
Peak memory 215712 kb
Host smart-99007dbf-b30a-447c-bf49-d1f3f4a6ef33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300920298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1300920298
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3808388309
Short name T133
Test name
Test status
Simulation time 1067516856 ps
CPU time 8.62 seconds
Started Jul 02 09:54:22 AM PDT 24
Finished Jul 02 09:54:33 AM PDT 24
Peak memory 216556 kb
Host smart-531bc7ae-5e9f-4f1e-8a1b-e4d0cf390e6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808388309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3808388309
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3351977059
Short name T143
Test name
Test status
Simulation time 2329728319 ps
CPU time 26.11 seconds
Started Jul 02 09:54:31 AM PDT 24
Finished Jul 02 09:54:57 AM PDT 24
Peak memory 207440 kb
Host smart-b54ec8ea-f53d-4324-a5f8-73eabd007d11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351977059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3351977059
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4082516078
Short name T1111
Test name
Test status
Simulation time 20628967 ps
CPU time 0.98 seconds
Started Jul 02 09:54:20 AM PDT 24
Finished Jul 02 09:54:22 AM PDT 24
Peak memory 207024 kb
Host smart-bb8cab84-70fe-4f6a-9914-5f3f03ebe710
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082516078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4082516078
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2360775225
Short name T1098
Test name
Test status
Simulation time 347894435 ps
CPU time 3.61 seconds
Started Jul 02 09:54:23 AM PDT 24
Finished Jul 02 09:54:30 AM PDT 24
Peak memory 216972 kb
Host smart-3b51ff7e-8b4b-4a16-9eee-941384d18e74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360775225 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2360775225
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.766363887
Short name T142
Test name
Test status
Simulation time 104787645 ps
CPU time 2.63 seconds
Started Jul 02 09:54:24 AM PDT 24
Finished Jul 02 09:54:30 AM PDT 24
Peak memory 215552 kb
Host smart-79361f1b-3186-4d0e-bc59-ec4e4cffdb6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766363887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.766363887
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3059565053
Short name T1092
Test name
Test status
Simulation time 14878470 ps
CPU time 0.7 seconds
Started Jul 02 09:54:22 AM PDT 24
Finished Jul 02 09:54:26 AM PDT 24
Peak memory 204148 kb
Host smart-557df84d-db52-4710-abb4-5ec17c06c98b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059565053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
059565053
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3091560806
Short name T1064
Test name
Test status
Simulation time 34212540 ps
CPU time 1.15 seconds
Started Jul 02 09:54:20 AM PDT 24
Finished Jul 02 09:54:22 AM PDT 24
Peak memory 215532 kb
Host smart-4d949d3a-5a98-406f-b241-346e9e270536
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091560806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3091560806
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3447485392
Short name T1085
Test name
Test status
Simulation time 28998596 ps
CPU time 0.72 seconds
Started Jul 02 09:54:31 AM PDT 24
Finished Jul 02 09:54:32 AM PDT 24
Peak memory 203920 kb
Host smart-8735ef44-644d-4851-bb93-3cc0d080475a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447485392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3447485392
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.279412042
Short name T1128
Test name
Test status
Simulation time 401801301 ps
CPU time 4.26 seconds
Started Jul 02 09:54:21 AM PDT 24
Finished Jul 02 09:54:28 AM PDT 24
Peak memory 215592 kb
Host smart-ca2997c7-ff7f-44c0-a2ff-68befbb440ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279412042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.279412042
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2032860945
Short name T135
Test name
Test status
Simulation time 2317445854 ps
CPU time 24.35 seconds
Started Jul 02 09:54:21 AM PDT 24
Finished Jul 02 09:54:48 AM PDT 24
Peak memory 215656 kb
Host smart-6e79b8f2-e160-4da4-9de2-2f8cd2e305a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032860945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2032860945
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4194839947
Short name T163
Test name
Test status
Simulation time 1804530412 ps
CPU time 26.54 seconds
Started Jul 02 09:54:21 AM PDT 24
Finished Jul 02 09:54:50 AM PDT 24
Peak memory 207308 kb
Host smart-226d0925-0bc3-4af9-91ea-699df60a7b88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194839947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4194839947
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3481809872
Short name T168
Test name
Test status
Simulation time 231533906 ps
CPU time 1.88 seconds
Started Jul 02 09:54:25 AM PDT 24
Finished Jul 02 09:54:30 AM PDT 24
Peak memory 215612 kb
Host smart-b6de1a6c-afc4-471d-a24d-92b8a51ef2f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481809872 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3481809872
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3731318808
Short name T1080
Test name
Test status
Simulation time 172948200 ps
CPU time 1.55 seconds
Started Jul 02 09:54:20 AM PDT 24
Finished Jul 02 09:54:24 AM PDT 24
Peak memory 207280 kb
Host smart-720a4a28-0880-41fc-9b43-490731c5510d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731318808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
731318808
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4277672844
Short name T1107
Test name
Test status
Simulation time 134392836 ps
CPU time 0.71 seconds
Started Jul 02 09:54:21 AM PDT 24
Finished Jul 02 09:54:25 AM PDT 24
Peak memory 204032 kb
Host smart-f2bbcb6a-af5b-4a8f-9292-8ba72cbb07f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277672844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
277672844
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2159174199
Short name T1143
Test name
Test status
Simulation time 287533098 ps
CPU time 2.29 seconds
Started Jul 02 09:54:22 AM PDT 24
Finished Jul 02 09:54:28 AM PDT 24
Peak memory 215572 kb
Host smart-8f10800f-f309-4364-a2bc-c6c376f96c3d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159174199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2159174199
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4071253764
Short name T1123
Test name
Test status
Simulation time 11439522 ps
CPU time 0.71 seconds
Started Jul 02 09:54:21 AM PDT 24
Finished Jul 02 09:54:24 AM PDT 24
Peak memory 203876 kb
Host smart-d909bf40-452f-49ad-83d6-8e9bfccead6b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071253764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4071253764
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1295565142
Short name T1097
Test name
Test status
Simulation time 492783914 ps
CPU time 2.89 seconds
Started Jul 02 09:54:26 AM PDT 24
Finished Jul 02 09:54:32 AM PDT 24
Peak memory 215492 kb
Host smart-c7fa5a72-9b3e-4848-a435-cce54aecf7bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295565142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1295565142
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2758656726
Short name T1126
Test name
Test status
Simulation time 572897677 ps
CPU time 15.14 seconds
Started Jul 02 09:54:23 AM PDT 24
Finished Jul 02 09:54:42 AM PDT 24
Peak memory 215528 kb
Host smart-e3e35ce0-9199-4869-aa27-a700887ff6a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758656726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2758656726
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2840471827
Short name T1059
Test name
Test status
Simulation time 57096572 ps
CPU time 1.82 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 216644 kb
Host smart-0595a72d-406b-4f94-abb7-92c03f18a4c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840471827 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2840471827
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.60213950
Short name T1067
Test name
Test status
Simulation time 76536662 ps
CPU time 1.29 seconds
Started Jul 02 09:54:36 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 207296 kb
Host smart-470b324f-ccc7-4fcc-940c-9d64c084a783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60213950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.60213950
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1903487978
Short name T1034
Test name
Test status
Simulation time 208671077 ps
CPU time 0.79 seconds
Started Jul 02 09:54:47 AM PDT 24
Finished Jul 02 09:54:49 AM PDT 24
Peak memory 204088 kb
Host smart-00321e77-b473-44c2-a057-27ddbd26effe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903487978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1903487978
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4096737022
Short name T1084
Test name
Test status
Simulation time 238260645 ps
CPU time 3.57 seconds
Started Jul 02 09:54:50 AM PDT 24
Finished Jul 02 09:54:55 AM PDT 24
Peak memory 215492 kb
Host smart-fccc0877-13ed-46d8-b289-1e705617e9c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096737022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4096737022
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.414633893
Short name T127
Test name
Test status
Simulation time 24580341 ps
CPU time 1.6 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 215784 kb
Host smart-8f496649-97fd-4fb4-b105-133c540d96ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414633893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.414633893
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3807596416
Short name T189
Test name
Test status
Simulation time 406231066 ps
CPU time 6.76 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 215604 kb
Host smart-0fd9e9e5-5719-4cdc-9b66-35a24a31c74c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807596416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3807596416
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4289672728
Short name T1070
Test name
Test status
Simulation time 199153708 ps
CPU time 1.62 seconds
Started Jul 02 09:54:45 AM PDT 24
Finished Jul 02 09:54:48 AM PDT 24
Peak memory 215616 kb
Host smart-bb6d2338-a286-4df5-bb37-80ee94edd6ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289672728 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4289672728
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4276210963
Short name T1108
Test name
Test status
Simulation time 135418558 ps
CPU time 1.34 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:37 AM PDT 24
Peak memory 207392 kb
Host smart-8b34f8b8-3bc7-4d91-8bfc-b3da01076def
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276210963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4276210963
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2158853359
Short name T1106
Test name
Test status
Simulation time 86307820 ps
CPU time 0.76 seconds
Started Jul 02 09:54:48 AM PDT 24
Finished Jul 02 09:54:51 AM PDT 24
Peak memory 204036 kb
Host smart-e1c4f580-4c2d-4909-9b2e-bfadea198312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158853359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2158853359
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2800045456
Short name T1104
Test name
Test status
Simulation time 287296256 ps
CPU time 1.84 seconds
Started Jul 02 09:54:53 AM PDT 24
Finished Jul 02 09:54:56 AM PDT 24
Peak memory 207528 kb
Host smart-253f4cf6-ca7b-48e1-9bf9-b1db42117bb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800045456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2800045456
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3688157699
Short name T1091
Test name
Test status
Simulation time 600226927 ps
CPU time 3.69 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 218008 kb
Host smart-efce5952-e891-4ceb-97ad-2549c1e1c108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688157699 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3688157699
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.588056449
Short name T1135
Test name
Test status
Simulation time 30218483 ps
CPU time 2.19 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:37 AM PDT 24
Peak memory 215772 kb
Host smart-6268231c-3fe4-4e85-b8e7-8fd9dac91bd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588056449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.588056449
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1325406650
Short name T1130
Test name
Test status
Simulation time 57157196 ps
CPU time 0.73 seconds
Started Jul 02 09:54:45 AM PDT 24
Finished Jul 02 09:54:58 AM PDT 24
Peak memory 204072 kb
Host smart-220fb8b5-241d-4984-9f51-a013716a5999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325406650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1325406650
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.15548846
Short name T164
Test name
Test status
Simulation time 356081572 ps
CPU time 3.81 seconds
Started Jul 02 09:54:39 AM PDT 24
Finished Jul 02 09:54:44 AM PDT 24
Peak memory 215508 kb
Host smart-c01fc52c-4e6d-4702-8095-92838e6e884d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15548846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sp
i_device_same_csr_outstanding.15548846
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.747305883
Short name T1140
Test name
Test status
Simulation time 209771098 ps
CPU time 2.9 seconds
Started Jul 02 09:54:50 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 216824 kb
Host smart-ce94d85c-e070-4d59-9ec6-d65c2de021be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747305883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.747305883
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2042931337
Short name T181
Test name
Test status
Simulation time 582567037 ps
CPU time 18.1 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:53 AM PDT 24
Peak memory 215544 kb
Host smart-9d5d6fa1-365e-4b22-938d-94fb447deeb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042931337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2042931337
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.890813096
Short name T131
Test name
Test status
Simulation time 216833709 ps
CPU time 3.78 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 217388 kb
Host smart-08628f06-d386-4f4c-af60-6dfaaee4ef17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890813096 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.890813096
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3342206971
Short name T1066
Test name
Test status
Simulation time 382372003 ps
CPU time 2.62 seconds
Started Jul 02 09:54:55 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 215744 kb
Host smart-93ea5e36-5701-4ece-a788-8f47ffda4b6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342206971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3342206971
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.40529283
Short name T1038
Test name
Test status
Simulation time 11282240 ps
CPU time 0.73 seconds
Started Jul 02 09:54:37 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 204080 kb
Host smart-d2b525ae-6892-49b8-960e-f26912938dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40529283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.40529283
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1893954287
Short name T1112
Test name
Test status
Simulation time 45815878 ps
CPU time 2.89 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 215564 kb
Host smart-ad490c75-be91-4166-890c-17e0f7b60d8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893954287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1893954287
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.163355845
Short name T120
Test name
Test status
Simulation time 108552911 ps
CPU time 1.99 seconds
Started Jul 02 09:54:43 AM PDT 24
Finished Jul 02 09:54:46 AM PDT 24
Peak memory 215772 kb
Host smart-3ad19d75-50c7-472d-bfed-ca3d06e3b35e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163355845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.163355845
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3280105160
Short name T183
Test name
Test status
Simulation time 4169575217 ps
CPU time 20.93 seconds
Started Jul 02 09:54:47 AM PDT 24
Finished Jul 02 09:55:10 AM PDT 24
Peak memory 216768 kb
Host smart-b409aaa5-4e7f-4d75-858d-2fd0724792f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280105160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3280105160
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3153454457
Short name T1078
Test name
Test status
Simulation time 26571285 ps
CPU time 1.67 seconds
Started Jul 02 09:54:53 AM PDT 24
Finished Jul 02 09:54:56 AM PDT 24
Peak memory 215864 kb
Host smart-b64c1633-7b34-4fad-9c43-27f071f45702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153454457 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3153454457
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2407464429
Short name T134
Test name
Test status
Simulation time 497380388 ps
CPU time 1.98 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 215592 kb
Host smart-3dd9adfe-e9a2-4744-b576-1a71a66c3486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407464429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2407464429
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.851047281
Short name T1071
Test name
Test status
Simulation time 199397375 ps
CPU time 0.74 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:37 AM PDT 24
Peak memory 204040 kb
Host smart-2b251150-cd72-4bf5-8cdd-f7da38728964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851047281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.851047281
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1442841492
Short name T1144
Test name
Test status
Simulation time 304913128 ps
CPU time 1.96 seconds
Started Jul 02 09:54:43 AM PDT 24
Finished Jul 02 09:54:46 AM PDT 24
Peak memory 215500 kb
Host smart-9a40d627-bb68-4c9b-8fb0-18300b00cb96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442841492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1442841492
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2674083238
Short name T104
Test name
Test status
Simulation time 174599224 ps
CPU time 2.6 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:37 AM PDT 24
Peak memory 215896 kb
Host smart-1624f690-c7e8-4a0d-a3a7-6940b719615c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674083238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2674083238
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2770488456
Short name T109
Test name
Test status
Simulation time 201170235 ps
CPU time 12.4 seconds
Started Jul 02 09:54:37 AM PDT 24
Finished Jul 02 09:54:52 AM PDT 24
Peak memory 217012 kb
Host smart-250e1d8d-422e-46d1-b3f4-b4fac3943468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770488456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2770488456
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2904451626
Short name T110
Test name
Test status
Simulation time 841843093 ps
CPU time 3.63 seconds
Started Jul 02 09:54:31 AM PDT 24
Finished Jul 02 09:54:36 AM PDT 24
Peak memory 218036 kb
Host smart-ca1c37f9-1f33-4e16-b2ee-1d39a6962bc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904451626 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2904451626
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3246478558
Short name T1075
Test name
Test status
Simulation time 38819524 ps
CPU time 1.25 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 207388 kb
Host smart-4f12e138-e4ba-4518-90ba-2783715edb03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246478558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3246478558
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2905683411
Short name T1062
Test name
Test status
Simulation time 39246181 ps
CPU time 0.76 seconds
Started Jul 02 09:54:52 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 204360 kb
Host smart-7ac23f42-84c8-4535-b8cc-606fed86db83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905683411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2905683411
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2534230106
Short name T1043
Test name
Test status
Simulation time 572377350 ps
CPU time 3.57 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:42 AM PDT 24
Peak memory 215372 kb
Host smart-ee3b6cf9-efed-4d80-a475-ddc6b285bda2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534230106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2534230106
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3108270532
Short name T117
Test name
Test status
Simulation time 29562257 ps
CPU time 1.83 seconds
Started Jul 02 09:54:41 AM PDT 24
Finished Jul 02 09:54:44 AM PDT 24
Peak memory 215900 kb
Host smart-b5708824-cc34-4bbf-9ca8-23cfdc7860b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108270532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3108270532
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3770938877
Short name T1116
Test name
Test status
Simulation time 1810811099 ps
CPU time 7.31 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:45 AM PDT 24
Peak memory 215560 kb
Host smart-67ac07ce-b96f-4e48-8ba3-d56c8d318ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770938877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3770938877
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.723544187
Short name T1131
Test name
Test status
Simulation time 110897878 ps
CPU time 1.73 seconds
Started Jul 02 09:54:46 AM PDT 24
Finished Jul 02 09:54:48 AM PDT 24
Peak memory 216644 kb
Host smart-2821a45d-ffab-4e88-83d7-be2bdb191e4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723544187 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.723544187
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3550524542
Short name T1047
Test name
Test status
Simulation time 137187713 ps
CPU time 1.41 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 207260 kb
Host smart-1f4f66ce-1c8d-4013-9e8f-4cb1f1952d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550524542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3550524542
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3622257546
Short name T1081
Test name
Test status
Simulation time 24780200 ps
CPU time 0.72 seconds
Started Jul 02 09:54:41 AM PDT 24
Finished Jul 02 09:54:47 AM PDT 24
Peak memory 204064 kb
Host smart-0f44506d-1ea5-455b-a472-cca7e11024e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622257546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3622257546
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1104758735
Short name T1094
Test name
Test status
Simulation time 531925004 ps
CPU time 3.92 seconds
Started Jul 02 09:54:42 AM PDT 24
Finished Jul 02 09:54:47 AM PDT 24
Peak memory 215576 kb
Host smart-93444bf7-67c7-4540-9ec2-50b0af7a775a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104758735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1104758735
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2056128350
Short name T121
Test name
Test status
Simulation time 876090634 ps
CPU time 3.83 seconds
Started Jul 02 09:54:55 AM PDT 24
Finished Jul 02 09:55:00 AM PDT 24
Peak memory 215788 kb
Host smart-6e0faf64-56d1-46b8-a2dc-e7f19e7b8aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056128350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2056128350
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.504100449
Short name T185
Test name
Test status
Simulation time 2008999649 ps
CPU time 21.42 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 217000 kb
Host smart-0b12b5cd-c840-4bbd-8d81-49091af99f55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504100449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.504100449
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3697250343
Short name T130
Test name
Test status
Simulation time 100415532 ps
CPU time 3.42 seconds
Started Jul 02 09:54:42 AM PDT 24
Finished Jul 02 09:54:47 AM PDT 24
Peak memory 217216 kb
Host smart-a6cc5e4a-2d2e-4810-8e2f-d3ec10c9f55b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697250343 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3697250343
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2002713223
Short name T1060
Test name
Test status
Simulation time 26464815 ps
CPU time 1.25 seconds
Started Jul 02 09:54:49 AM PDT 24
Finished Jul 02 09:54:52 AM PDT 24
Peak memory 215504 kb
Host smart-0c2760b6-452c-4914-8744-ddfa42deeec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002713223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2002713223
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2967357935
Short name T1065
Test name
Test status
Simulation time 59440060 ps
CPU time 0.75 seconds
Started Jul 02 09:54:51 AM PDT 24
Finished Jul 02 09:54:53 AM PDT 24
Peak memory 204312 kb
Host smart-ed3dcd47-7e18-4573-88fd-486db713ff87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967357935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2967357935
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4232920472
Short name T1088
Test name
Test status
Simulation time 439537844 ps
CPU time 3.05 seconds
Started Jul 02 09:54:57 AM PDT 24
Finished Jul 02 09:55:01 AM PDT 24
Peak memory 215548 kb
Host smart-c521421c-6987-4e7f-bdcc-62be3dcf547e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232920472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4232920472
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3192256278
Short name T124
Test name
Test status
Simulation time 375185339 ps
CPU time 3.48 seconds
Started Jul 02 09:54:56 AM PDT 24
Finished Jul 02 09:55:01 AM PDT 24
Peak memory 215780 kb
Host smart-1ec52b37-2f91-40ed-b3d5-7e376f97391f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192256278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3192256278
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.36001397
Short name T1074
Test name
Test status
Simulation time 2237287929 ps
CPU time 8.28 seconds
Started Jul 02 09:55:01 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 215632 kb
Host smart-33745198-a3e1-4b47-b5e0-83e5fddd2474
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36001397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_
tl_intg_err.36001397
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1773092449
Short name T1061
Test name
Test status
Simulation time 626094870 ps
CPU time 3.66 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:42 AM PDT 24
Peak memory 217004 kb
Host smart-edad2eb1-4324-45e9-bba5-c67aa1ec59f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773092449 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1773092449
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1632793210
Short name T1087
Test name
Test status
Simulation time 377149569 ps
CPU time 1.86 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 215524 kb
Host smart-9d3e4671-4474-43bb-9bfc-f6408a6410bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632793210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1632793210
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1080609625
Short name T1079
Test name
Test status
Simulation time 46724689 ps
CPU time 0.71 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 203976 kb
Host smart-72a0d550-af9e-422f-a7be-b937a9944483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080609625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1080609625
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.795771788
Short name T165
Test name
Test status
Simulation time 151073694 ps
CPU time 2 seconds
Started Jul 02 09:54:50 AM PDT 24
Finished Jul 02 09:54:53 AM PDT 24
Peak memory 215576 kb
Host smart-ca0eaebf-bf72-4388-a88d-7b485642e29b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795771788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.795771788
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3256377439
Short name T1069
Test name
Test status
Simulation time 101555965 ps
CPU time 1.61 seconds
Started Jul 02 09:54:37 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 217000 kb
Host smart-d4ce3199-e20c-4274-b93e-76297a68b464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256377439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3256377439
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1137442887
Short name T107
Test name
Test status
Simulation time 529877023 ps
CPU time 14.83 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:53 AM PDT 24
Peak memory 223656 kb
Host smart-f6b5c036-7342-433d-ba8c-5140daffab44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137442887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1137442887
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4107828723
Short name T166
Test name
Test status
Simulation time 411596396 ps
CPU time 2.57 seconds
Started Jul 02 09:54:59 AM PDT 24
Finished Jul 02 09:55:03 AM PDT 24
Peak memory 216908 kb
Host smart-e1344194-97fa-47f9-920c-55d7b66ed2e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107828723 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4107828723
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1947940167
Short name T1127
Test name
Test status
Simulation time 93349649 ps
CPU time 2.22 seconds
Started Jul 02 09:54:42 AM PDT 24
Finished Jul 02 09:54:46 AM PDT 24
Peak memory 215576 kb
Host smart-5cf9609a-beeb-4432-867b-a0c9b6131bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947940167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1947940167
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2410749138
Short name T1096
Test name
Test status
Simulation time 15350353 ps
CPU time 0.71 seconds
Started Jul 02 09:54:36 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 204016 kb
Host smart-757b59bc-d14e-4277-a208-9cd5878e468b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410749138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2410749138
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2878196336
Short name T1114
Test name
Test status
Simulation time 1396069407 ps
CPU time 3.23 seconds
Started Jul 02 09:54:49 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 215552 kb
Host smart-89be1d5b-b961-47b8-a094-37db6cd0f2b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878196336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2878196336
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1679515469
Short name T128
Test name
Test status
Simulation time 3302212219 ps
CPU time 5.01 seconds
Started Jul 02 09:54:40 AM PDT 24
Finished Jul 02 09:54:46 AM PDT 24
Peak memory 215836 kb
Host smart-a1a3dd08-7ce2-4d28-8017-4f4dade38915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679515469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1679515469
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1002701563
Short name T1110
Test name
Test status
Simulation time 1435532286 ps
CPU time 8.7 seconds
Started Jul 02 09:54:36 AM PDT 24
Finished Jul 02 09:54:47 AM PDT 24
Peak memory 215544 kb
Host smart-83862903-198b-4c8c-8a6a-76d6fbb0e0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002701563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1002701563
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1121502849
Short name T139
Test name
Test status
Simulation time 957995243 ps
CPU time 23.47 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:53 AM PDT 24
Peak memory 215580 kb
Host smart-d5436a09-f453-4da8-a8de-dbf64106a3d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121502849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1121502849
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3686617642
Short name T136
Test name
Test status
Simulation time 2087537829 ps
CPU time 34.82 seconds
Started Jul 02 09:54:26 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 207288 kb
Host smart-d9337635-431f-48ce-bbe4-fc747e6ed51d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686617642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3686617642
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.493013285
Short name T90
Test name
Test status
Simulation time 23943373 ps
CPU time 0.98 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:34 AM PDT 24
Peak memory 207048 kb
Host smart-5de16a6b-600d-461d-a413-fc35ebac0fa3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493013285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.493013285
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.202848102
Short name T1057
Test name
Test status
Simulation time 392578591 ps
CPU time 2.68 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:32 AM PDT 24
Peak memory 216860 kb
Host smart-cd977b18-01f1-4b70-b2d5-c56859622579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202848102 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.202848102
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1506407131
Short name T141
Test name
Test status
Simulation time 133654181 ps
CPU time 2.47 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:36 AM PDT 24
Peak memory 220408 kb
Host smart-27011e55-3d0c-4c35-8beb-ac430ead9e8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506407131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
506407131
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1296498627
Short name T1037
Test name
Test status
Simulation time 19156219 ps
CPU time 0.76 seconds
Started Jul 02 09:54:31 AM PDT 24
Finished Jul 02 09:54:33 AM PDT 24
Peak memory 204016 kb
Host smart-5b8479de-a790-4a24-b3a7-8a93d6a08a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296498627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
296498627
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2394931280
Short name T1073
Test name
Test status
Simulation time 26424450 ps
CPU time 2.11 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:36 AM PDT 24
Peak memory 215588 kb
Host smart-9de5b794-fcdf-4329-8700-396a331db164
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394931280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2394931280
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1752986083
Short name T1119
Test name
Test status
Simulation time 11981389 ps
CPU time 0.67 seconds
Started Jul 02 09:54:23 AM PDT 24
Finished Jul 02 09:54:27 AM PDT 24
Peak memory 203920 kb
Host smart-52dde3a5-4b80-48f2-a2b0-f84c4028262b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752986083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1752986083
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.996180530
Short name T1051
Test name
Test status
Simulation time 101801910 ps
CPU time 1.93 seconds
Started Jul 02 09:54:24 AM PDT 24
Finished Jul 02 09:54:29 AM PDT 24
Peak memory 215448 kb
Host smart-4597976f-cf26-4364-8c75-9c6553bb5f26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996180530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.996180530
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1923071910
Short name T1039
Test name
Test status
Simulation time 14641728 ps
CPU time 0.72 seconds
Started Jul 02 09:54:53 AM PDT 24
Finished Jul 02 09:54:56 AM PDT 24
Peak memory 204048 kb
Host smart-ca42cc5a-aec8-464f-8788-4c78ade88232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923071910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1923071910
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1072502299
Short name T1036
Test name
Test status
Simulation time 11021351 ps
CPU time 0.74 seconds
Started Jul 02 09:54:36 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 204012 kb
Host smart-4cf9e54c-131a-49a1-b192-75540db18261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072502299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1072502299
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1018839109
Short name T1113
Test name
Test status
Simulation time 38943344 ps
CPU time 0.7 seconds
Started Jul 02 09:54:45 AM PDT 24
Finished Jul 02 09:54:47 AM PDT 24
Peak memory 204012 kb
Host smart-26152e5b-6407-4104-9b18-f01962d945f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018839109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1018839109
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1340025274
Short name T1138
Test name
Test status
Simulation time 174139491 ps
CPU time 0.76 seconds
Started Jul 02 09:55:03 AM PDT 24
Finished Jul 02 09:55:05 AM PDT 24
Peak memory 204352 kb
Host smart-498eac9b-7038-4cca-8945-bc0c5d9751cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340025274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1340025274
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4118829646
Short name T1044
Test name
Test status
Simulation time 29525055 ps
CPU time 0.77 seconds
Started Jul 02 09:54:57 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 203908 kb
Host smart-9f058a5b-bcd6-40a9-9c6d-1be37445d120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118829646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4118829646
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.463187571
Short name T1041
Test name
Test status
Simulation time 23384627 ps
CPU time 0.76 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 204052 kb
Host smart-583236dd-d16d-4d1b-86c5-b05fb11a79d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463187571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.463187571
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2677990557
Short name T1042
Test name
Test status
Simulation time 20885626 ps
CPU time 0.69 seconds
Started Jul 02 09:54:49 AM PDT 24
Finished Jul 02 09:54:51 AM PDT 24
Peak memory 203996 kb
Host smart-d59bf91b-0d60-43b9-a073-eb3b64e02b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677990557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2677990557
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3121975100
Short name T1077
Test name
Test status
Simulation time 16470540 ps
CPU time 0.76 seconds
Started Jul 02 09:54:46 AM PDT 24
Finished Jul 02 09:54:48 AM PDT 24
Peak memory 204244 kb
Host smart-a19bee40-c811-4e56-ad26-63867f0165e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121975100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3121975100
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.703853589
Short name T1049
Test name
Test status
Simulation time 12633953 ps
CPU time 0.71 seconds
Started Jul 02 09:54:41 AM PDT 24
Finished Jul 02 09:54:42 AM PDT 24
Peak memory 203944 kb
Host smart-0772353e-9f24-4a2e-ad86-ce9c28b681fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703853589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.703853589
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1475650569
Short name T1052
Test name
Test status
Simulation time 17413778 ps
CPU time 0.8 seconds
Started Jul 02 09:54:52 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 204356 kb
Host smart-32cce377-aa62-4579-bd47-ca7bd79036fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475650569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1475650569
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2655366113
Short name T1086
Test name
Test status
Simulation time 1295357907 ps
CPU time 21.84 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:52 AM PDT 24
Peak memory 215512 kb
Host smart-27948267-b9c8-498c-8701-3b17de03cc65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655366113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2655366113
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3014035980
Short name T1109
Test name
Test status
Simulation time 2703837179 ps
CPU time 41.37 seconds
Started Jul 02 09:54:28 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 207336 kb
Host smart-5709e89b-8dfa-4b01-bc3f-7bf41e3eeed9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014035980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3014035980
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1959855418
Short name T89
Test name
Test status
Simulation time 89051018 ps
CPU time 1.16 seconds
Started Jul 02 09:54:31 AM PDT 24
Finished Jul 02 09:54:33 AM PDT 24
Peak memory 215464 kb
Host smart-c746a3a1-ac3e-4f4e-b642-3d09859c1490
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959855418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1959855418
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2318682960
Short name T129
Test name
Test status
Simulation time 113206673 ps
CPU time 4.18 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:38 AM PDT 24
Peak memory 217152 kb
Host smart-06a51fb2-f822-4c50-9353-1b1489e8d6e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318682960 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2318682960
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3940277691
Short name T137
Test name
Test status
Simulation time 25451965 ps
CPU time 1.19 seconds
Started Jul 02 09:54:48 AM PDT 24
Finished Jul 02 09:54:56 AM PDT 24
Peak memory 207328 kb
Host smart-2c105758-62ac-43d8-9cd7-d63c35bb137e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940277691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
940277691
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1879495042
Short name T1141
Test name
Test status
Simulation time 22241640 ps
CPU time 0.72 seconds
Started Jul 02 09:54:26 AM PDT 24
Finished Jul 02 09:54:30 AM PDT 24
Peak memory 204032 kb
Host smart-2a129ee1-787e-4552-a9b0-a2436150573d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879495042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
879495042
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.60525750
Short name T1072
Test name
Test status
Simulation time 135266143 ps
CPU time 1.3 seconds
Started Jul 02 09:54:31 AM PDT 24
Finished Jul 02 09:54:33 AM PDT 24
Peak memory 215540 kb
Host smart-f3e6311e-00c9-4092-9e03-761bfcfc20d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60525750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_d
evice_mem_partial_access.60525750
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3272855875
Short name T1134
Test name
Test status
Simulation time 31948650 ps
CPU time 0.69 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:30 AM PDT 24
Peak memory 204268 kb
Host smart-ef33fc56-a606-49d8-a62f-03cde1d6863c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272855875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3272855875
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2694121620
Short name T1118
Test name
Test status
Simulation time 175140846 ps
CPU time 2.69 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:32 AM PDT 24
Peak memory 215532 kb
Host smart-508cee2c-28ba-49ab-b817-799589150395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694121620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2694121620
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3985668848
Short name T1145
Test name
Test status
Simulation time 179193509 ps
CPU time 5.01 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 215772 kb
Host smart-ac592265-5026-4305-8d80-e14f50334805
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985668848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
985668848
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.875597361
Short name T1054
Test name
Test status
Simulation time 608470448 ps
CPU time 7.61 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:43 AM PDT 24
Peak memory 215632 kb
Host smart-60d05a80-7fe2-4ee4-8cc8-b5f1cda3e575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875597361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.875597361
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.764507828
Short name T1136
Test name
Test status
Simulation time 16181111 ps
CPU time 0.78 seconds
Started Jul 02 09:54:48 AM PDT 24
Finished Jul 02 09:54:51 AM PDT 24
Peak memory 204048 kb
Host smart-b81cca82-10a6-44ab-932e-2b16571bc805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764507828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.764507828
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3637402084
Short name T1063
Test name
Test status
Simulation time 13734967 ps
CPU time 0.71 seconds
Started Jul 02 09:55:04 AM PDT 24
Finished Jul 02 09:55:06 AM PDT 24
Peak memory 203908 kb
Host smart-72499048-7ed1-4ae7-a6ea-e34418928cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637402084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3637402084
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3941392635
Short name T1103
Test name
Test status
Simulation time 10908962 ps
CPU time 0.72 seconds
Started Jul 02 09:54:51 AM PDT 24
Finished Jul 02 09:54:53 AM PDT 24
Peak memory 204012 kb
Host smart-f3582a32-867b-47d1-a64b-7050d3c85120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941392635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3941392635
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2747589161
Short name T1124
Test name
Test status
Simulation time 39587909 ps
CPU time 0.76 seconds
Started Jul 02 09:55:03 AM PDT 24
Finished Jul 02 09:55:05 AM PDT 24
Peak memory 204064 kb
Host smart-186690ae-3bb0-43ab-8dfc-a2b7cb10e037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747589161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2747589161
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3616056441
Short name T1093
Test name
Test status
Simulation time 36819745 ps
CPU time 0.73 seconds
Started Jul 02 09:54:41 AM PDT 24
Finished Jul 02 09:54:42 AM PDT 24
Peak memory 204036 kb
Host smart-180a52cf-3dfa-46bc-be4d-26fc1ac07d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616056441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3616056441
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1597160045
Short name T1048
Test name
Test status
Simulation time 36756267 ps
CPU time 0.69 seconds
Started Jul 02 09:54:38 AM PDT 24
Finished Jul 02 09:54:45 AM PDT 24
Peak memory 204008 kb
Host smart-b3331634-0174-433f-96d0-0d0edee86888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597160045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1597160045
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.345188771
Short name T1089
Test name
Test status
Simulation time 21605462 ps
CPU time 0.72 seconds
Started Jul 02 09:54:54 AM PDT 24
Finished Jul 02 09:54:56 AM PDT 24
Peak memory 204004 kb
Host smart-cbeffc63-4884-4a7a-a179-3d0497d5b996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345188771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.345188771
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1568310791
Short name T1053
Test name
Test status
Simulation time 10952920 ps
CPU time 0.69 seconds
Started Jul 02 09:55:14 AM PDT 24
Finished Jul 02 09:55:17 AM PDT 24
Peak memory 203924 kb
Host smart-b598d128-37d0-4c5a-a8dd-727bde5a3299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568310791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1568310791
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3880963923
Short name T1139
Test name
Test status
Simulation time 14989753 ps
CPU time 0.79 seconds
Started Jul 02 09:54:45 AM PDT 24
Finished Jul 02 09:54:47 AM PDT 24
Peak memory 204088 kb
Host smart-3e0de8b6-a81f-47a0-9262-fe3df38c05b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880963923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3880963923
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.436288913
Short name T1040
Test name
Test status
Simulation time 14619588 ps
CPU time 0.74 seconds
Started Jul 02 09:54:39 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 204304 kb
Host smart-4a220aa4-83c3-4963-b02e-87bfe251f7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436288913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.436288913
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1767562509
Short name T1100
Test name
Test status
Simulation time 322651458 ps
CPU time 7.83 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:44 AM PDT 24
Peak memory 207356 kb
Host smart-808b8082-21f9-4179-8617-d6f4f9f499bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767562509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1767562509
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.481545170
Short name T1045
Test name
Test status
Simulation time 1455590935 ps
CPU time 23.42 seconds
Started Jul 02 09:54:30 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 207340 kb
Host smart-506a92e3-5785-4831-8b8f-dae4a0db87c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481545170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.481545170
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2622905411
Short name T91
Test name
Test status
Simulation time 24572989 ps
CPU time 1.35 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 207364 kb
Host smart-4a279541-3b9c-472a-aa1a-ff3d74f7a2c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622905411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2622905411
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1282058921
Short name T1102
Test name
Test status
Simulation time 88860893 ps
CPU time 2.72 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:32 AM PDT 24
Peak memory 216760 kb
Host smart-6cec4efe-6b24-4041-b770-a98d3922cb80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282058921 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1282058921
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2528314802
Short name T167
Test name
Test status
Simulation time 74295022 ps
CPU time 1.39 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:36 AM PDT 24
Peak memory 207284 kb
Host smart-258efc46-c36c-4494-aef1-6e6856e20d5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528314802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
528314802
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2524288822
Short name T1046
Test name
Test status
Simulation time 39717688 ps
CPU time 0.73 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:36 AM PDT 24
Peak memory 204368 kb
Host smart-926d7d0f-9b48-438c-be68-611996ce1b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524288822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
524288822
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.999082975
Short name T1117
Test name
Test status
Simulation time 25124757 ps
CPU time 2.06 seconds
Started Jul 02 09:54:44 AM PDT 24
Finished Jul 02 09:54:47 AM PDT 24
Peak memory 215540 kb
Host smart-af63a75a-0ad3-454b-b8e5-05c6ecc454c1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999082975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.999082975
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4188709357
Short name T1090
Test name
Test status
Simulation time 20426967 ps
CPU time 0.69 seconds
Started Jul 02 09:54:29 AM PDT 24
Finished Jul 02 09:54:31 AM PDT 24
Peak memory 204268 kb
Host smart-3483759e-9d25-409a-9498-696cdb0f5c9e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188709357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4188709357
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2094759169
Short name T153
Test name
Test status
Simulation time 56570064 ps
CPU time 1.87 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:38 AM PDT 24
Peak memory 215552 kb
Host smart-141bf6df-43cd-4654-a119-5c84ebb31448
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094759169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2094759169
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2859178437
Short name T122
Test name
Test status
Simulation time 45503430 ps
CPU time 2.99 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:38 AM PDT 24
Peak memory 215796 kb
Host smart-1397d42a-8d34-4fa5-ae39-30ee878c082d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859178437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
859178437
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.276523040
Short name T188
Test name
Test status
Simulation time 396402089 ps
CPU time 12.44 seconds
Started Jul 02 09:54:48 AM PDT 24
Finished Jul 02 09:55:03 AM PDT 24
Peak memory 215536 kb
Host smart-c7bae21a-bfc3-41f0-9a3c-ff06b848004e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276523040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.276523040
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2749664791
Short name T1082
Test name
Test status
Simulation time 12800561 ps
CPU time 0.73 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 204320 kb
Host smart-634dea65-827f-4610-b230-1ce9f7faab4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749664791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2749664791
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4287973996
Short name T1101
Test name
Test status
Simulation time 10832289 ps
CPU time 0.71 seconds
Started Jul 02 09:54:50 AM PDT 24
Finished Jul 02 09:54:52 AM PDT 24
Peak memory 204376 kb
Host smart-e90e7569-7fe6-42dd-a10c-c670cbdbd1f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287973996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4287973996
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2496216854
Short name T1129
Test name
Test status
Simulation time 11910566 ps
CPU time 0.71 seconds
Started Jul 02 09:54:52 AM PDT 24
Finished Jul 02 09:54:53 AM PDT 24
Peak memory 204036 kb
Host smart-95df23f1-8f15-4c8f-abbe-f4947672164a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496216854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2496216854
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3854815003
Short name T1076
Test name
Test status
Simulation time 54711596 ps
CPU time 0.68 seconds
Started Jul 02 09:54:39 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 204240 kb
Host smart-a7650d78-9a37-4719-be77-3d699b8edf1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854815003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3854815003
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3954006548
Short name T1058
Test name
Test status
Simulation time 17848625 ps
CPU time 0.76 seconds
Started Jul 02 09:54:48 AM PDT 24
Finished Jul 02 09:54:50 AM PDT 24
Peak memory 204044 kb
Host smart-22806654-1554-48c0-98e6-e84132384fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954006548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3954006548
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.808843656
Short name T1150
Test name
Test status
Simulation time 51206417 ps
CPU time 0.73 seconds
Started Jul 02 09:54:38 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 204044 kb
Host smart-90b80466-a994-455b-a16e-35e118b22d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808843656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.808843656
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2947343246
Short name T1149
Test name
Test status
Simulation time 31976382 ps
CPU time 0.73 seconds
Started Jul 02 09:55:01 AM PDT 24
Finished Jul 02 09:55:02 AM PDT 24
Peak memory 203968 kb
Host smart-2a0c62b4-d82c-465b-b510-da05a82054f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947343246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2947343246
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4258099716
Short name T1121
Test name
Test status
Simulation time 17423697 ps
CPU time 0.74 seconds
Started Jul 02 09:54:37 AM PDT 24
Finished Jul 02 09:54:40 AM PDT 24
Peak memory 204100 kb
Host smart-a55752a1-f95e-4886-af92-c921b5b80249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258099716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4258099716
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2344044780
Short name T1035
Test name
Test status
Simulation time 14977402 ps
CPU time 0.8 seconds
Started Jul 02 09:54:39 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 204024 kb
Host smart-d867dd32-da7c-4ed2-86b9-5aaca65d26f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344044780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2344044780
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3769020524
Short name T1050
Test name
Test status
Simulation time 44728988 ps
CPU time 0.75 seconds
Started Jul 02 09:55:07 AM PDT 24
Finished Jul 02 09:55:08 AM PDT 24
Peak memory 204076 kb
Host smart-97fbc78e-daf3-4c5e-8035-1da342863478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769020524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3769020524
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2617852631
Short name T1120
Test name
Test status
Simulation time 29292022 ps
CPU time 1.75 seconds
Started Jul 02 09:54:30 AM PDT 24
Finished Jul 02 09:54:33 AM PDT 24
Peak memory 216664 kb
Host smart-a69bcee9-3e2e-4376-b3fc-c71888b0885f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617852631 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2617852631
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2985480571
Short name T144
Test name
Test status
Simulation time 28629892 ps
CPU time 1.96 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 207400 kb
Host smart-dd258fe3-0f0c-409c-bed2-3a7c2aefdce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985480571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
985480571
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2986130735
Short name T1055
Test name
Test status
Simulation time 43616333 ps
CPU time 0.74 seconds
Started Jul 02 09:54:31 AM PDT 24
Finished Jul 02 09:54:33 AM PDT 24
Peak memory 204068 kb
Host smart-eb295be1-fd73-4ed2-a3ba-d70120ec0061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986130735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
986130735
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4012899489
Short name T155
Test name
Test status
Simulation time 160746422 ps
CPU time 4.11 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 215544 kb
Host smart-46b15e99-fefa-4dd2-9749-a22ed2883da8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012899489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4012899489
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.108114902
Short name T1148
Test name
Test status
Simulation time 103056461 ps
CPU time 2.94 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 215800 kb
Host smart-0120576f-956d-44cd-9d6a-9474c263bcfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108114902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.108114902
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2595753015
Short name T1137
Test name
Test status
Simulation time 336437950 ps
CPU time 6.94 seconds
Started Jul 02 09:55:03 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 215544 kb
Host smart-22fa08de-9ba1-4344-84f1-d20c37789ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595753015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2595753015
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.28928927
Short name T1068
Test name
Test status
Simulation time 886685971 ps
CPU time 3.32 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 216992 kb
Host smart-42a042c3-cfb4-4a4b-ba25-c75f182b67cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28928927 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.28928927
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.149960141
Short name T1142
Test name
Test status
Simulation time 56853254 ps
CPU time 0.75 seconds
Started Jul 02 09:54:32 AM PDT 24
Finished Jul 02 09:54:34 AM PDT 24
Peak memory 204376 kb
Host smart-9e3ea8f5-a6e7-4d42-97a6-75f241be439f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149960141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.149960141
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.600156709
Short name T1122
Test name
Test status
Simulation time 46564874 ps
CPU time 2.55 seconds
Started Jul 02 09:54:51 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 215496 kb
Host smart-2a9d394a-abc2-4ccc-b001-61d24f66deeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600156709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.600156709
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2660599620
Short name T118
Test name
Test status
Simulation time 159179236 ps
CPU time 3.84 seconds
Started Jul 02 09:54:29 AM PDT 24
Finished Jul 02 09:54:34 AM PDT 24
Peak memory 215908 kb
Host smart-2079e2f9-2f62-43ef-972e-17adefd51603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660599620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
660599620
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1417511363
Short name T1105
Test name
Test status
Simulation time 1088403666 ps
CPU time 23.62 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:55:01 AM PDT 24
Peak memory 215692 kb
Host smart-4cb998d2-5457-4bba-a758-fb471dc1736f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417511363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1417511363
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3932309707
Short name T123
Test name
Test status
Simulation time 47814335 ps
CPU time 3.28 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 216484 kb
Host smart-ddb66d62-c199-40a8-be93-545fdf11dd61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932309707 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3932309707
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1155749690
Short name T1132
Test name
Test status
Simulation time 367651612 ps
CPU time 2.39 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:32 AM PDT 24
Peak memory 215508 kb
Host smart-976ef2de-3742-442c-bb5f-f18dc718264b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155749690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
155749690
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3169379256
Short name T1056
Test name
Test status
Simulation time 21963884 ps
CPU time 0.74 seconds
Started Jul 02 09:54:41 AM PDT 24
Finished Jul 02 09:54:42 AM PDT 24
Peak memory 204364 kb
Host smart-0efdad55-73b8-4851-8256-2a898dc00f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169379256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
169379256
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.143552968
Short name T1115
Test name
Test status
Simulation time 1036123170 ps
CPU time 4.03 seconds
Started Jul 02 09:54:58 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 216288 kb
Host smart-240ebfe6-7a6f-467d-a66a-e891b6eb3ef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143552968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.143552968
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1353972398
Short name T125
Test name
Test status
Simulation time 145307657 ps
CPU time 3.48 seconds
Started Jul 02 09:54:35 AM PDT 24
Finished Jul 02 09:54:41 AM PDT 24
Peak memory 215780 kb
Host smart-e030d1fc-5123-45eb-a779-102664265c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353972398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
353972398
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2787580415
Short name T103
Test name
Test status
Simulation time 1102428302 ps
CPU time 14.03 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:51 AM PDT 24
Peak memory 215504 kb
Host smart-f192694b-0f12-4759-8335-b920491ce6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787580415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2787580415
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3806543873
Short name T1083
Test name
Test status
Simulation time 428060134 ps
CPU time 2.78 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 216948 kb
Host smart-2e71ec48-4715-4bbd-8a30-521c23bc983e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806543873 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3806543873
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1172382004
Short name T140
Test name
Test status
Simulation time 236669467 ps
CPU time 1.31 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:31 AM PDT 24
Peak memory 207292 kb
Host smart-450280c5-86a9-4117-87e3-0f1f9813a994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172382004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
172382004
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.572550261
Short name T1099
Test name
Test status
Simulation time 11964493 ps
CPU time 0.73 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:37 AM PDT 24
Peak memory 204088 kb
Host smart-556e1eb8-b5e6-43de-9fe6-2f80da59dd59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572550261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.572550261
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.684131101
Short name T1125
Test name
Test status
Simulation time 1345631146 ps
CPU time 4.09 seconds
Started Jul 02 09:54:40 AM PDT 24
Finished Jul 02 09:54:45 AM PDT 24
Peak memory 215580 kb
Host smart-9878dc26-3896-4f2f-be1b-8420d146af8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684131101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.684131101
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2291311824
Short name T126
Test name
Test status
Simulation time 71327434 ps
CPU time 2.42 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 215936 kb
Host smart-4ff8b84e-6a49-4b3f-bd00-d9977cd4a25b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291311824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
291311824
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2179327236
Short name T187
Test name
Test status
Simulation time 206089171 ps
CPU time 12.07 seconds
Started Jul 02 09:54:27 AM PDT 24
Finished Jul 02 09:54:42 AM PDT 24
Peak memory 215456 kb
Host smart-32012e18-0ae6-468b-b92e-7bf97e501775
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179327236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2179327236
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1159727106
Short name T106
Test name
Test status
Simulation time 139706551 ps
CPU time 1.79 seconds
Started Jul 02 09:55:03 AM PDT 24
Finished Jul 02 09:55:06 AM PDT 24
Peak memory 216620 kb
Host smart-298221fb-239d-4bc4-9ac3-d91b434f96d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159727106 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1159727106
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1718542919
Short name T1133
Test name
Test status
Simulation time 253782945 ps
CPU time 2.28 seconds
Started Jul 02 09:54:42 AM PDT 24
Finished Jul 02 09:54:46 AM PDT 24
Peak memory 215560 kb
Host smart-bafdd5b1-f4b3-4296-990d-4843fc35acc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718542919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
718542919
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.106837511
Short name T1146
Test name
Test status
Simulation time 12896198 ps
CPU time 0.72 seconds
Started Jul 02 09:54:33 AM PDT 24
Finished Jul 02 09:54:37 AM PDT 24
Peak memory 203980 kb
Host smart-60e245e2-eaaa-49ba-9ab3-ada28e91f0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106837511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.106837511
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1021000056
Short name T154
Test name
Test status
Simulation time 758785881 ps
CPU time 3.57 seconds
Started Jul 02 09:54:53 AM PDT 24
Finished Jul 02 09:54:58 AM PDT 24
Peak memory 215456 kb
Host smart-c2c48f63-23e1-4803-bbf1-356b69681fca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021000056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1021000056
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3997132690
Short name T105
Test name
Test status
Simulation time 48726971 ps
CPU time 1.49 seconds
Started Jul 02 09:54:34 AM PDT 24
Finished Jul 02 09:54:38 AM PDT 24
Peak memory 215864 kb
Host smart-1fb7f014-ffaa-474b-a4a8-e652bec26dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997132690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
997132690
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.674056215
Short name T1095
Test name
Test status
Simulation time 3651575911 ps
CPU time 14.11 seconds
Started Jul 02 09:54:25 AM PDT 24
Finished Jul 02 09:54:43 AM PDT 24
Peak memory 215624 kb
Host smart-51b116a6-928a-4644-980c-f9131131fdd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674056215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.674056215
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3589779175
Short name T486
Test name
Test status
Simulation time 24780478 ps
CPU time 0.72 seconds
Started Jul 02 09:50:27 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 206380 kb
Host smart-66ef3c29-c247-4b45-bb3c-f52598eee91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589779175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
589779175
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1954820849
Short name T727
Test name
Test status
Simulation time 756937229 ps
CPU time 5.92 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 225632 kb
Host smart-bd02a431-e4bb-440c-b7cf-c1a7c91d9954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954820849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1954820849
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.376926735
Short name T717
Test name
Test status
Simulation time 229383708 ps
CPU time 0.73 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 207472 kb
Host smart-a8a2a13c-2de1-47ed-8d83-48bf471f2133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376926735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.376926735
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4205953443
Short name T51
Test name
Test status
Simulation time 4623154525 ps
CPU time 20.47 seconds
Started Jul 02 09:50:16 AM PDT 24
Finished Jul 02 09:50:45 AM PDT 24
Peak memory 237684 kb
Host smart-1280c9d1-f1f3-41de-ac96-f7910606a8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205953443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4205953443
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1371173212
Short name T657
Test name
Test status
Simulation time 4183486360 ps
CPU time 59.19 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:51:22 AM PDT 24
Peak memory 250420 kb
Host smart-6455019e-bedb-4491-bbfb-5db28279a9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371173212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1371173212
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3008776503
Short name T784
Test name
Test status
Simulation time 132178566712 ps
CPU time 285.12 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:55:06 AM PDT 24
Peak memory 258500 kb
Host smart-f9ab3268-d19c-4052-a1a7-40ac8bde6a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008776503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3008776503
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2231535398
Short name T314
Test name
Test status
Simulation time 3161826488 ps
CPU time 46.41 seconds
Started Jul 02 09:50:26 AM PDT 24
Finished Jul 02 09:51:19 AM PDT 24
Peak memory 242132 kb
Host smart-8d4eeadb-e580-44a0-bdbf-51cd9a6840b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231535398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2231535398
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.61463539
Short name T535
Test name
Test status
Simulation time 18313838 ps
CPU time 0.78 seconds
Started Jul 02 09:50:43 AM PDT 24
Finished Jul 02 09:50:45 AM PDT 24
Peak memory 216876 kb
Host smart-e19a67de-e699-4130-a141-2bca5dd61e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61463539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.61463539
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1373476670
Short name T226
Test name
Test status
Simulation time 400423299 ps
CPU time 6.2 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 233932 kb
Host smart-8c5db320-db65-46ce-af9e-1453326a2116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373476670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1373476670
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3972211403
Short name T1032
Test name
Test status
Simulation time 1355308346 ps
CPU time 3.56 seconds
Started Jul 02 09:50:54 AM PDT 24
Finished Jul 02 09:50:58 AM PDT 24
Peak memory 233776 kb
Host smart-6ef3e162-cd3e-4230-b022-5d70fc58a35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972211403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3972211403
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.538145631
Short name T218
Test name
Test status
Simulation time 500769983 ps
CPU time 4.52 seconds
Started Jul 02 09:50:29 AM PDT 24
Finished Jul 02 09:50:39 AM PDT 24
Peak memory 241628 kb
Host smart-58487fcb-6e46-4eaf-bfb4-517ebf61afff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538145631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
538145631
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3600634784
Short name T282
Test name
Test status
Simulation time 35415939 ps
CPU time 2.11 seconds
Started Jul 02 09:50:39 AM PDT 24
Finished Jul 02 09:50:42 AM PDT 24
Peak memory 225500 kb
Host smart-d1a172d2-af5b-491f-869e-8a51af7a03cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600634784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3600634784
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.459788338
Short name T160
Test name
Test status
Simulation time 3117215115 ps
CPU time 9.26 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 223216 kb
Host smart-b7d0fdfd-f60c-4b61-9774-036f06c82878
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459788338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.459788338
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.262965951
Short name T77
Test name
Test status
Simulation time 140407047 ps
CPU time 0.93 seconds
Started Jul 02 09:50:15 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 236296 kb
Host smart-7bc889bd-48af-4fa6-a6a6-cc4ecfa072f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262965951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.262965951
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.316665928
Short name T173
Test name
Test status
Simulation time 93757367078 ps
CPU time 313.2 seconds
Started Jul 02 09:50:12 AM PDT 24
Finished Jul 02 09:55:34 AM PDT 24
Peak memory 252220 kb
Host smart-ae382bba-d553-4bda-94a2-eb087fc20bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316665928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.316665928
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3590536611
Short name T318
Test name
Test status
Simulation time 463180746 ps
CPU time 4.49 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 219736 kb
Host smart-cd632c30-f7d3-425f-a63f-0443a4cacff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590536611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3590536611
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1299903694
Short name T738
Test name
Test status
Simulation time 21456973 ps
CPU time 0.78 seconds
Started Jul 02 09:50:15 AM PDT 24
Finished Jul 02 09:50:24 AM PDT 24
Peak memory 206976 kb
Host smart-808bdd36-5f3a-41fa-b5d4-a6aae4740320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299903694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1299903694
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3620296192
Short name T1008
Test name
Test status
Simulation time 41847598 ps
CPU time 0.83 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 208016 kb
Host smart-cdc1d383-ec5a-45de-b9e9-461fa676de01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620296192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3620296192
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1407850451
Short name T911
Test name
Test status
Simulation time 3372654314 ps
CPU time 7.44 seconds
Started Jul 02 09:50:34 AM PDT 24
Finished Jul 02 09:50:45 AM PDT 24
Peak memory 239000 kb
Host smart-1e8db457-1345-43e1-ade5-5ff06239cbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407850451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1407850451
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.249038914
Short name T694
Test name
Test status
Simulation time 44178937 ps
CPU time 0.76 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:28 AM PDT 24
Peak memory 206384 kb
Host smart-90338c3f-8f12-4ae7-b9aa-e52b61151bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249038914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.249038914
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.945420518
Short name T192
Test name
Test status
Simulation time 235387084 ps
CPU time 3.42 seconds
Started Jul 02 09:50:29 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 225516 kb
Host smart-9854586f-a4c3-4a13-85e5-596fce43dc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945420518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.945420518
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.732251657
Short name T375
Test name
Test status
Simulation time 14702032 ps
CPU time 0.8 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 207480 kb
Host smart-cea52860-022e-44a9-8e62-abd5b47c9c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732251657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.732251657
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4182720216
Short name T912
Test name
Test status
Simulation time 74446923185 ps
CPU time 179.38 seconds
Started Jul 02 09:50:43 AM PDT 24
Finished Jul 02 09:53:43 AM PDT 24
Peak memory 265772 kb
Host smart-c22b8a90-f0ab-46b8-add2-cadb6f9ff32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182720216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4182720216
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3414039367
Short name T582
Test name
Test status
Simulation time 21601609449 ps
CPU time 65.8 seconds
Started Jul 02 09:50:33 AM PDT 24
Finished Jul 02 09:51:43 AM PDT 24
Peak memory 250364 kb
Host smart-41d65eb8-c6d9-4fb4-a0cc-77d743abb4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414039367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3414039367
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.346173095
Short name T405
Test name
Test status
Simulation time 54919052 ps
CPU time 3.04 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:31 AM PDT 24
Peak memory 233804 kb
Host smart-ca2a3513-08f6-4145-b4a7-4d2b67a0912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346173095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.346173095
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.987208312
Short name T590
Test name
Test status
Simulation time 2519765383 ps
CPU time 10.39 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 225736 kb
Host smart-c575932b-6d37-4ccd-a5c3-c2c9f60b7c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987208312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.987208312
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.809839401
Short name T116
Test name
Test status
Simulation time 4736680104 ps
CPU time 5.81 seconds
Started Jul 02 09:50:10 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 233972 kb
Host smart-cc9db6f5-76cd-44b7-8530-38a0ddf64f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809839401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.809839401
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4206466293
Short name T898
Test name
Test status
Simulation time 25638100 ps
CPU time 1.11 seconds
Started Jul 02 09:50:27 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 217680 kb
Host smart-72d0e454-99c8-4ee8-b1cd-851bf6af2dec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206466293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4206466293
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.884052943
Short name T607
Test name
Test status
Simulation time 246088080 ps
CPU time 2.72 seconds
Started Jul 02 09:50:27 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 233680 kb
Host smart-c805245c-c5f9-45cf-b1d9-a2edd80d9d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884052943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.884052943
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.47769928
Short name T554
Test name
Test status
Simulation time 87470726 ps
CPU time 3.81 seconds
Started Jul 02 09:50:29 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 224252 kb
Host smart-6153f2d8-2e31-4da4-8855-0357e8a5382b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=47769928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct
.47769928
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2128237154
Short name T76
Test name
Test status
Simulation time 238256151 ps
CPU time 1.32 seconds
Started Jul 02 09:50:21 AM PDT 24
Finished Jul 02 09:50:31 AM PDT 24
Peak memory 236376 kb
Host smart-90b3f4d5-d97d-4656-ae37-637805b40e8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128237154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2128237154
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3806766168
Short name T579
Test name
Test status
Simulation time 216398669 ps
CPU time 1.11 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 207944 kb
Host smart-015582b3-1398-4957-becb-2ea73be05403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806766168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3806766168
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3893186400
Short name T323
Test name
Test status
Simulation time 6267445705 ps
CPU time 30.87 seconds
Started Jul 02 09:50:18 AM PDT 24
Finished Jul 02 09:50:58 AM PDT 24
Peak memory 217524 kb
Host smart-d7da3928-233d-403b-8e19-bec26715c939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893186400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3893186400
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2757322904
Short name T624
Test name
Test status
Simulation time 29352300734 ps
CPU time 12.49 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:39 AM PDT 24
Peak memory 218712 kb
Host smart-9f359feb-9460-49f4-be3c-4a1d978e92a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757322904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2757322904
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2728985032
Short name T877
Test name
Test status
Simulation time 111874518 ps
CPU time 1.92 seconds
Started Jul 02 09:50:25 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 217396 kb
Host smart-3e2ad294-5ae6-4cf0-ba4c-8651256ebc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728985032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2728985032
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4120913898
Short name T29
Test name
Test status
Simulation time 108778036 ps
CPU time 0.99 seconds
Started Jul 02 09:50:42 AM PDT 24
Finished Jul 02 09:50:44 AM PDT 24
Peak memory 207988 kb
Host smart-c02d3991-b32c-4fbd-9427-e93926b71d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120913898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4120913898
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.153369371
Short name T212
Test name
Test status
Simulation time 552574771 ps
CPU time 8.94 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:50:37 AM PDT 24
Peak memory 250212 kb
Host smart-3efd68b2-4544-4d55-b907-20c054f3f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153369371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.153369371
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1849666047
Short name T690
Test name
Test status
Simulation time 11172447 ps
CPU time 0.73 seconds
Started Jul 02 09:50:57 AM PDT 24
Finished Jul 02 09:50:59 AM PDT 24
Peak memory 206392 kb
Host smart-80fa7d1f-9154-4a65-afa1-7e0b4bb84f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849666047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1849666047
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1389411360
Short name T642
Test name
Test status
Simulation time 1059451279 ps
CPU time 15.07 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:16 AM PDT 24
Peak memory 225580 kb
Host smart-b49dbcf5-f740-4b66-af0e-135d87baf7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389411360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1389411360
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2878967762
Short name T500
Test name
Test status
Simulation time 19138429 ps
CPU time 0.81 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:50:55 AM PDT 24
Peak memory 207520 kb
Host smart-620c4a9f-3ddf-4b63-8b7c-1af8e493a59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878967762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2878967762
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1694214590
Short name T23
Test name
Test status
Simulation time 50836935 ps
CPU time 0.77 seconds
Started Jul 02 09:50:57 AM PDT 24
Finished Jul 02 09:50:59 AM PDT 24
Peak memory 216940 kb
Host smart-d38fc3c9-be04-4eb0-a6dd-697c7b8d656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694214590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1694214590
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1135748459
Short name T1014
Test name
Test status
Simulation time 19504793441 ps
CPU time 19.69 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 218968 kb
Host smart-148f0236-6c71-4f07-88f3-eca4878f376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135748459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1135748459
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1990861562
Short name T503
Test name
Test status
Simulation time 1210381796 ps
CPU time 25.6 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:52:01 AM PDT 24
Peak memory 253888 kb
Host smart-d69ea600-7f27-438a-b844-36115111916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990861562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1990861562
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2083491912
Short name T521
Test name
Test status
Simulation time 44176053 ps
CPU time 2.71 seconds
Started Jul 02 09:51:14 AM PDT 24
Finished Jul 02 09:51:20 AM PDT 24
Peak memory 225588 kb
Host smart-a95f5e5d-afb6-40af-854b-a079d6a030a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083491912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2083491912
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2500910151
Short name T600
Test name
Test status
Simulation time 635644206 ps
CPU time 6.34 seconds
Started Jul 02 09:50:43 AM PDT 24
Finished Jul 02 09:50:50 AM PDT 24
Peak memory 233840 kb
Host smart-8503b252-c128-4d3c-a6a7-fb5a58db53fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500910151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2500910151
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4291754932
Short name T273
Test name
Test status
Simulation time 827514559 ps
CPU time 9.27 seconds
Started Jul 02 09:50:55 AM PDT 24
Finished Jul 02 09:51:05 AM PDT 24
Peak memory 225560 kb
Host smart-0f4f2498-8c81-4e80-8c08-6b4476f9d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291754932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4291754932
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1493442410
Short name T36
Test name
Test status
Simulation time 24906855 ps
CPU time 1.09 seconds
Started Jul 02 09:50:56 AM PDT 24
Finished Jul 02 09:50:58 AM PDT 24
Peak memory 217556 kb
Host smart-6674587d-11d2-4f42-8d97-7e9b7af6145d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493442410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1493442410
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2135811649
Short name T878
Test name
Test status
Simulation time 28720364 ps
CPU time 2.15 seconds
Started Jul 02 09:51:08 AM PDT 24
Finished Jul 02 09:51:13 AM PDT 24
Peak memory 224876 kb
Host smart-9218245c-cab5-4ba5-9e88-e3a30236ae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135811649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2135811649
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2667013556
Short name T257
Test name
Test status
Simulation time 30013330207 ps
CPU time 40.16 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:51:32 AM PDT 24
Peak memory 238036 kb
Host smart-a9bf4f31-29dd-40f9-ae44-8922c81d7c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667013556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2667013556
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4025203511
Short name T608
Test name
Test status
Simulation time 2883570757 ps
CPU time 10.66 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:12 AM PDT 24
Peak memory 223128 kb
Host smart-b555f189-462a-4efc-b4b1-4c042654541d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025203511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4025203511
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1696013715
Short name T939
Test name
Test status
Simulation time 1219251244 ps
CPU time 10.98 seconds
Started Jul 02 09:51:13 AM PDT 24
Finished Jul 02 09:51:28 AM PDT 24
Peak memory 217564 kb
Host smart-d9151602-b5cb-4473-9cfe-6c941f21c53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696013715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1696013715
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2138549440
Short name T919
Test name
Test status
Simulation time 4322344821 ps
CPU time 8.75 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:51:02 AM PDT 24
Peak memory 217500 kb
Host smart-117caf4f-498d-4093-8c40-bf24ec089a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138549440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2138549440
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3504122854
Short name T926
Test name
Test status
Simulation time 160900214 ps
CPU time 1.72 seconds
Started Jul 02 09:51:02 AM PDT 24
Finished Jul 02 09:51:06 AM PDT 24
Peak memory 217336 kb
Host smart-cd21c35e-44e1-4b01-8d0b-26f7b2a1719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504122854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3504122854
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.56584546
Short name T899
Test name
Test status
Simulation time 755863760 ps
CPU time 0.85 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:07 AM PDT 24
Peak memory 206976 kb
Host smart-cefc7728-c4b3-4251-81b1-550706dc2536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56584546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.56584546
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3535399130
Short name T235
Test name
Test status
Simulation time 2246941978 ps
CPU time 9.33 seconds
Started Jul 02 09:50:50 AM PDT 24
Finished Jul 02 09:51:00 AM PDT 24
Peak memory 233820 kb
Host smart-a997b325-ab9f-4315-b222-1216d98800a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535399130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3535399130
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1269124327
Short name T632
Test name
Test status
Simulation time 12065415 ps
CPU time 0.72 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:02 AM PDT 24
Peak memory 205816 kb
Host smart-5e2a5b35-308a-41f2-a8c0-b5c829900c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269124327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1269124327
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1327568576
Short name T531
Test name
Test status
Simulation time 88414613 ps
CPU time 2.22 seconds
Started Jul 02 09:50:49 AM PDT 24
Finished Jul 02 09:50:52 AM PDT 24
Peak memory 225300 kb
Host smart-eb40c47c-3a26-4afa-8be7-c09dd7ef5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327568576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1327568576
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2472687898
Short name T435
Test name
Test status
Simulation time 210412718 ps
CPU time 0.77 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:07 AM PDT 24
Peak memory 207544 kb
Host smart-9b6ca052-a96c-4ac9-a304-4c748dffef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472687898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2472687898
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1655650519
Short name T418
Test name
Test status
Simulation time 17409626612 ps
CPU time 22.22 seconds
Started Jul 02 09:50:54 AM PDT 24
Finished Jul 02 09:51:17 AM PDT 24
Peak memory 252332 kb
Host smart-e6127956-efa0-4515-8b65-254f5eb43169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655650519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1655650519
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2294515997
Short name T490
Test name
Test status
Simulation time 7658079599 ps
CPU time 77.27 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 250436 kb
Host smart-3aac8ffc-6540-4068-9183-c72509b66c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294515997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2294515997
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1168198917
Short name T805
Test name
Test status
Simulation time 240626900156 ps
CPU time 445.7 seconds
Started Jul 02 09:50:59 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 255364 kb
Host smart-742a2ba8-f52e-490b-a223-7be51dcf7ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168198917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1168198917
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2241945280
Short name T469
Test name
Test status
Simulation time 1234862038 ps
CPU time 15.03 seconds
Started Jul 02 09:50:50 AM PDT 24
Finished Jul 02 09:51:06 AM PDT 24
Peak memory 233752 kb
Host smart-a3e50206-61c0-4b0b-bffb-19493e7cf31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241945280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2241945280
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2596905385
Short name T808
Test name
Test status
Simulation time 756096266 ps
CPU time 3.5 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:11 AM PDT 24
Peak memory 225556 kb
Host smart-23402561-1197-48f9-9ea6-cc7f44c619f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596905385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2596905385
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2495993471
Short name T848
Test name
Test status
Simulation time 5190591729 ps
CPU time 45.43 seconds
Started Jul 02 09:51:07 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 233744 kb
Host smart-a349f01a-4124-4540-983a-7c7e13591aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495993471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2495993471
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3638366817
Short name T622
Test name
Test status
Simulation time 98958063 ps
CPU time 1.03 seconds
Started Jul 02 09:50:56 AM PDT 24
Finished Jul 02 09:50:58 AM PDT 24
Peak memory 218892 kb
Host smart-28474dbe-d5ca-4da2-8ad8-03f48dfd67d6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638366817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3638366817
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1828054547
Short name T267
Test name
Test status
Simulation time 125115480 ps
CPU time 2.07 seconds
Started Jul 02 09:50:57 AM PDT 24
Finished Jul 02 09:51:00 AM PDT 24
Peak memory 225392 kb
Host smart-117581f3-7955-48b7-bedd-3fd58edd7fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828054547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1828054547
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2955231779
Short name T884
Test name
Test status
Simulation time 424868636 ps
CPU time 7.3 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:09 AM PDT 24
Peak memory 233704 kb
Host smart-6126548a-bd28-47e2-9d39-fcca6231fd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955231779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2955231779
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1207326776
Short name T432
Test name
Test status
Simulation time 5982622229 ps
CPU time 11.05 seconds
Started Jul 02 09:50:58 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 220272 kb
Host smart-ab44d13b-209a-462d-bc2b-a2f21c8a660c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1207326776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1207326776
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.750434210
Short name T32
Test name
Test status
Simulation time 18916732978 ps
CPU time 201.16 seconds
Started Jul 02 09:51:07 AM PDT 24
Finished Jul 02 09:54:31 AM PDT 24
Peak memory 250412 kb
Host smart-02a36f64-91fc-4cbc-a46f-d61f01449997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750434210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.750434210
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1755679364
Short name T913
Test name
Test status
Simulation time 5589935518 ps
CPU time 28.01 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:33 AM PDT 24
Peak memory 222032 kb
Host smart-2fa66615-c024-410b-ae30-6ad3b6f01458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755679364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1755679364
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3255906854
Short name T334
Test name
Test status
Simulation time 8463884684 ps
CPU time 7.29 seconds
Started Jul 02 09:50:56 AM PDT 24
Finished Jul 02 09:51:04 AM PDT 24
Peak memory 217320 kb
Host smart-a869feb5-23fc-41ef-8d4a-97afe25de4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255906854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3255906854
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3993474064
Short name T917
Test name
Test status
Simulation time 1138253220 ps
CPU time 5.7 seconds
Started Jul 02 09:51:01 AM PDT 24
Finished Jul 02 09:51:07 AM PDT 24
Peak memory 217304 kb
Host smart-314089e6-ae28-48fb-a7dd-6a7e40cbf1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993474064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3993474064
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2675873018
Short name T614
Test name
Test status
Simulation time 21448505 ps
CPU time 0.77 seconds
Started Jul 02 09:50:53 AM PDT 24
Finished Jul 02 09:50:55 AM PDT 24
Peak memory 206984 kb
Host smart-4242bfa6-ec51-4f66-b221-3b8b65f15aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675873018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2675873018
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1488953614
Short name T692
Test name
Test status
Simulation time 11089853893 ps
CPU time 11.5 seconds
Started Jul 02 09:50:53 AM PDT 24
Finished Jul 02 09:51:06 AM PDT 24
Peak memory 233888 kb
Host smart-564fd455-6f94-465e-a3b2-c0ad08abe52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488953614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1488953614
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1137861111
Short name T698
Test name
Test status
Simulation time 42301166 ps
CPU time 0.73 seconds
Started Jul 02 09:51:02 AM PDT 24
Finished Jul 02 09:51:05 AM PDT 24
Peak memory 205824 kb
Host smart-5be225a1-cf77-4e81-9509-893857021224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137861111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1137861111
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2274493549
Short name T452
Test name
Test status
Simulation time 37268167 ps
CPU time 2.27 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 233776 kb
Host smart-fe29323f-c233-40f6-98e8-b22da007fc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274493549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2274493549
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3818290557
Short name T636
Test name
Test status
Simulation time 17307914 ps
CPU time 0.8 seconds
Started Jul 02 09:50:55 AM PDT 24
Finished Jul 02 09:50:56 AM PDT 24
Peak memory 207480 kb
Host smart-35f2f51d-587a-4cce-8dfd-f933350c1d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818290557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3818290557
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1574768545
Short name T515
Test name
Test status
Simulation time 37739804709 ps
CPU time 239.19 seconds
Started Jul 02 09:50:57 AM PDT 24
Finished Jul 02 09:54:58 AM PDT 24
Peak memory 254704 kb
Host smart-2dce0696-d793-49ad-aef2-ceb7811ba0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574768545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1574768545
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.567170636
Short name T320
Test name
Test status
Simulation time 3249666993 ps
CPU time 74.1 seconds
Started Jul 02 09:51:01 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 263064 kb
Host smart-09635aa7-f7f6-4e2d-bd7e-133b0ca06432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567170636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.567170636
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1630189569
Short name T656
Test name
Test status
Simulation time 18588520458 ps
CPU time 182.47 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:53:54 AM PDT 24
Peak memory 257144 kb
Host smart-3caca0b6-3023-4775-9494-c3fdf1e0ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630189569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1630189569
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2979193352
Short name T478
Test name
Test status
Simulation time 4780802920 ps
CPU time 20.73 seconds
Started Jul 02 09:50:50 AM PDT 24
Finished Jul 02 09:51:11 AM PDT 24
Peak memory 233912 kb
Host smart-4e251e31-2e56-4276-ac15-bd425c0d22f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979193352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2979193352
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3012643176
Short name T536
Test name
Test status
Simulation time 13651527051 ps
CPU time 34.62 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:43 AM PDT 24
Peak memory 242324 kb
Host smart-a8267095-714b-4999-80cd-5e63121fb5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012643176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3012643176
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2975009538
Short name T494
Test name
Test status
Simulation time 937551897 ps
CPU time 11.62 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:13 AM PDT 24
Peak memory 225548 kb
Host smart-e1e481a4-482d-4d64-b8ac-11a8d1b6799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975009538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2975009538
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3429076854
Short name T467
Test name
Test status
Simulation time 126020097 ps
CPU time 2.82 seconds
Started Jul 02 09:50:54 AM PDT 24
Finished Jul 02 09:50:58 AM PDT 24
Peak memory 233804 kb
Host smart-898b8dba-e2cb-4957-8f64-fee27b257e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429076854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3429076854
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.4053681426
Short name T573
Test name
Test status
Simulation time 59514679 ps
CPU time 1.09 seconds
Started Jul 02 09:50:59 AM PDT 24
Finished Jul 02 09:51:01 AM PDT 24
Peak memory 217696 kb
Host smart-415f1965-0575-457f-9ecf-1a76f5712245
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053681426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.4053681426
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.802070062
Short name T178
Test name
Test status
Simulation time 7153574295 ps
CPU time 20.52 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 240964 kb
Host smart-8fd4a06b-0645-494e-aef3-35642c098781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802070062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.802070062
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2686559662
Short name T601
Test name
Test status
Simulation time 1733106528 ps
CPU time 8.06 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:13 AM PDT 24
Peak memory 225596 kb
Host smart-b0ef8926-944d-4031-b586-c15bc8f7c6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686559662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2686559662
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3710700866
Short name T162
Test name
Test status
Simulation time 406746552 ps
CPU time 3.92 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 220280 kb
Host smart-390a00bb-5ca2-4770-9316-a68fc1e038c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3710700866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3710700866
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2388484963
Short name T239
Test name
Test status
Simulation time 1247610172 ps
CPU time 26.28 seconds
Started Jul 02 09:50:57 AM PDT 24
Finished Jul 02 09:51:24 AM PDT 24
Peak memory 250324 kb
Host smart-c61a63b6-fead-4b7a-bb19-f565f3e2658a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388484963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2388484963
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1321260394
Short name T822
Test name
Test status
Simulation time 119619720147 ps
CPU time 45.36 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:55 AM PDT 24
Peak memory 217492 kb
Host smart-b647eb2a-fa78-4450-b06f-cdbbabc30c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321260394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1321260394
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2158989942
Short name T651
Test name
Test status
Simulation time 9365408289 ps
CPU time 24.63 seconds
Started Jul 02 09:51:11 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 217524 kb
Host smart-33b5b1c8-dd8a-4934-9a96-c2899ed6fdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158989942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2158989942
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4155816944
Short name T370
Test name
Test status
Simulation time 28677840 ps
CPU time 1.69 seconds
Started Jul 02 09:51:01 AM PDT 24
Finished Jul 02 09:51:03 AM PDT 24
Peak memory 209188 kb
Host smart-b26c0579-54b3-41cf-b7c8-27b4bee47ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155816944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4155816944
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.962585319
Short name T653
Test name
Test status
Simulation time 117056009 ps
CPU time 0.79 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 206976 kb
Host smart-42e88610-9c9f-4a5c-9b95-9d1782241f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962585319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.962585319
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.713779795
Short name T574
Test name
Test status
Simulation time 714403032 ps
CPU time 3.61 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:17 AM PDT 24
Peak memory 233760 kb
Host smart-55b20ca7-6366-4b45-80c1-0ae5ad7ce36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713779795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.713779795
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.714614460
Short name T834
Test name
Test status
Simulation time 15902830 ps
CPU time 0.74 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 205804 kb
Host smart-9478f770-0bcc-4f92-8d13-82eb2074ba24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714614460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.714614460
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1119371370
Short name T480
Test name
Test status
Simulation time 1339369760 ps
CPU time 4.55 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:12 AM PDT 24
Peak memory 233740 kb
Host smart-defe1e9e-bb44-404d-9eb6-c395f03192f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119371370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1119371370
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2318365185
Short name T471
Test name
Test status
Simulation time 24787700 ps
CPU time 0.81 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:09 AM PDT 24
Peak memory 207512 kb
Host smart-e8af007e-d71f-4b02-9429-d567b0b508db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318365185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2318365185
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2856196650
Short name T484
Test name
Test status
Simulation time 89806407 ps
CPU time 0.97 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:50:53 AM PDT 24
Peak memory 216912 kb
Host smart-f4a869c1-1592-472c-8886-2e3031a3bc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856196650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2856196650
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3775400808
Short name T776
Test name
Test status
Simulation time 24780964867 ps
CPU time 35.21 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:44 AM PDT 24
Peak memory 241216 kb
Host smart-dd7f597d-55f0-44a1-a078-45bd0d553fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775400808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3775400808
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1084266624
Short name T305
Test name
Test status
Simulation time 140728720547 ps
CPU time 542.71 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 10:00:38 AM PDT 24
Peak memory 266072 kb
Host smart-cd94b51b-9098-4a1c-97d8-7b72e05b3351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084266624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1084266624
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1394260041
Short name T949
Test name
Test status
Simulation time 253524721 ps
CPU time 10.1 seconds
Started Jul 02 09:51:02 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 250176 kb
Host smart-83165658-ef94-4b8d-9328-a92081831ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394260041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1394260041
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2206289507
Short name T537
Test name
Test status
Simulation time 29979674206 ps
CPU time 189.22 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:54:22 AM PDT 24
Peak memory 252380 kb
Host smart-0ff290c8-e73a-4197-a503-d28a53ad95e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206289507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2206289507
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.547656452
Short name T256
Test name
Test status
Simulation time 520775260 ps
CPU time 5.44 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:51:18 AM PDT 24
Peak memory 225604 kb
Host smart-eb130b40-9667-42b6-a7f1-93f25336a77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547656452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.547656452
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4082218605
Short name T997
Test name
Test status
Simulation time 74898614 ps
CPU time 2.31 seconds
Started Jul 02 09:50:58 AM PDT 24
Finished Jul 02 09:51:01 AM PDT 24
Peak memory 225248 kb
Host smart-31a39f41-ab9c-4529-b8bb-132eda02cdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082218605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4082218605
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1423370335
Short name T991
Test name
Test status
Simulation time 44571832 ps
CPU time 1.06 seconds
Started Jul 02 09:50:53 AM PDT 24
Finished Jul 02 09:50:56 AM PDT 24
Peak memory 217600 kb
Host smart-103af60b-2aea-42be-9f35-4e99ce357293
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423370335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1423370335
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.561250357
Short name T474
Test name
Test status
Simulation time 52605062 ps
CPU time 2.25 seconds
Started Jul 02 09:51:07 AM PDT 24
Finished Jul 02 09:51:18 AM PDT 24
Peak memory 225556 kb
Host smart-78932714-23d7-40e1-b5dc-8103a6367b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561250357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.561250357
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1348458353
Short name T982
Test name
Test status
Simulation time 807201860 ps
CPU time 5.7 seconds
Started Jul 02 09:51:12 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 220256 kb
Host smart-b70a04e9-ba32-41ad-a657-1f100744d9b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1348458353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1348458353
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.382374024
Short name T787
Test name
Test status
Simulation time 5464634959 ps
CPU time 15.77 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:22 AM PDT 24
Peak memory 217528 kb
Host smart-7154a1a9-4e33-4684-af69-2cc69007a613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382374024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.382374024
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3459076144
Short name T504
Test name
Test status
Simulation time 1818717479 ps
CPU time 4.17 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:50:58 AM PDT 24
Peak memory 217256 kb
Host smart-dbd69a36-e6e3-4ad8-9768-ac37fe75ff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459076144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3459076144
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3488232131
Short name T437
Test name
Test status
Simulation time 43978772 ps
CPU time 1.6 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:08 AM PDT 24
Peak memory 217400 kb
Host smart-336cbc38-247a-407d-8961-22798256d540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488232131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3488232131
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1162989806
Short name T400
Test name
Test status
Simulation time 119584369 ps
CPU time 1.05 seconds
Started Jul 02 09:51:02 AM PDT 24
Finished Jul 02 09:51:04 AM PDT 24
Peak memory 207004 kb
Host smart-1b9267d1-35d0-492a-bf62-88aa59bcf3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162989806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1162989806
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1856621481
Short name T391
Test name
Test status
Simulation time 5995186239 ps
CPU time 20.63 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:27 AM PDT 24
Peak memory 242040 kb
Host smart-5ac8468f-fe00-47db-a864-c1f1e6d417ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856621481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1856621481
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1586380061
Short name T986
Test name
Test status
Simulation time 40453114 ps
CPU time 0.71 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:09 AM PDT 24
Peak memory 205832 kb
Host smart-5b9cb1f5-83d1-4ddf-a350-ece368480430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586380061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1586380061
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1242002844
Short name T259
Test name
Test status
Simulation time 91404308 ps
CPU time 2.29 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 225592 kb
Host smart-53394364-b28e-4bd4-a962-ab464d1909e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242002844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1242002844
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1535931818
Short name T871
Test name
Test status
Simulation time 24078281 ps
CPU time 0.76 seconds
Started Jul 02 09:51:02 AM PDT 24
Finished Jul 02 09:51:05 AM PDT 24
Peak memory 207480 kb
Host smart-4656bcd6-ad39-4c9c-86e2-354f3885f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535931818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1535931818
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3797354971
Short name T979
Test name
Test status
Simulation time 10090200192 ps
CPU time 66.11 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:52:25 AM PDT 24
Peak memory 225824 kb
Host smart-3e255ed3-dd34-48b6-97f3-f141a0df0303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797354971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3797354971
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1154109169
Short name T860
Test name
Test status
Simulation time 6525304189 ps
CPU time 98 seconds
Started Jul 02 09:51:01 AM PDT 24
Finished Jul 02 09:52:40 AM PDT 24
Peak memory 258588 kb
Host smart-c386a918-e233-4af6-94c9-e863ff300982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154109169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1154109169
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4258356849
Short name T309
Test name
Test status
Simulation time 7171199424 ps
CPU time 17.73 seconds
Started Jul 02 09:51:07 AM PDT 24
Finished Jul 02 09:51:29 AM PDT 24
Peak memory 233944 kb
Host smart-61f42913-1479-41c0-a9f7-75b34683d92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258356849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4258356849
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.223013034
Short name T398
Test name
Test status
Simulation time 104709768 ps
CPU time 0.73 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:51:13 AM PDT 24
Peak memory 216916 kb
Host smart-200c8a94-2dac-4eb7-a2c0-26e70a811f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223013034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.223013034
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1110468697
Short name T534
Test name
Test status
Simulation time 34116084 ps
CPU time 2.43 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:11 AM PDT 24
Peak memory 233524 kb
Host smart-41b31bd8-4f43-4e7d-a5b2-e72565417aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110468697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1110468697
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1236993862
Short name T482
Test name
Test status
Simulation time 421049264 ps
CPU time 4.38 seconds
Started Jul 02 09:51:22 AM PDT 24
Finished Jul 02 09:51:28 AM PDT 24
Peak memory 233792 kb
Host smart-ae8b6837-fb80-4634-98a9-9f586150ab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236993862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1236993862
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3838135124
Short name T37
Test name
Test status
Simulation time 48405932 ps
CPU time 1.05 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:50:54 AM PDT 24
Peak memory 218584 kb
Host smart-33c43354-87b4-461d-82a6-3037218eaa96
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838135124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3838135124
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2687735373
Short name T48
Test name
Test status
Simulation time 1361141790 ps
CPU time 3.36 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:04 AM PDT 24
Peak memory 225588 kb
Host smart-48a689d7-69b3-43e5-ae0e-fce840df47e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687735373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2687735373
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2951065739
Short name T865
Test name
Test status
Simulation time 2481150465 ps
CPU time 7.95 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 233880 kb
Host smart-da55efcb-10f6-4ed9-ae2e-ee9e63fef265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951065739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2951065739
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1082627440
Short name T755
Test name
Test status
Simulation time 652899607 ps
CPU time 7.41 seconds
Started Jul 02 09:51:16 AM PDT 24
Finished Jul 02 09:51:26 AM PDT 24
Peak memory 220116 kb
Host smart-3633ebaf-8d6e-43df-abf5-4c92cf7e7365
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1082627440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1082627440
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1863463294
Short name T661
Test name
Test status
Simulation time 116465403 ps
CPU time 1.21 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 208308 kb
Host smart-b9ccf556-4939-45dc-a3ee-dec3ef03316e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863463294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1863463294
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1772165345
Short name T566
Test name
Test status
Simulation time 1660220471 ps
CPU time 18.1 seconds
Started Jul 02 09:50:57 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 217424 kb
Host smart-b70695fd-6b41-4a10-a2b3-6c777a010e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772165345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1772165345
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3090056666
Short name T479
Test name
Test status
Simulation time 703111437 ps
CPU time 4.44 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:11 AM PDT 24
Peak memory 217444 kb
Host smart-6a947338-55ac-4860-b26f-7a854044e6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090056666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3090056666
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2709049636
Short name T327
Test name
Test status
Simulation time 642992845 ps
CPU time 2.05 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:07 AM PDT 24
Peak memory 217316 kb
Host smart-fb84c3dd-af20-4bfe-bc31-7061b8c9d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709049636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2709049636
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.786506625
Short name T639
Test name
Test status
Simulation time 139866467 ps
CPU time 1.11 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 207984 kb
Host smart-e16060fd-5470-40d4-990a-98acd2d28153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786506625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.786506625
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3874232302
Short name T897
Test name
Test status
Simulation time 1789380621 ps
CPU time 5.51 seconds
Started Jul 02 09:51:32 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 238444 kb
Host smart-7d873725-da55-4f08-b2ec-cd6c4f5a5edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874232302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3874232302
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2503876939
Short name T578
Test name
Test status
Simulation time 14847641 ps
CPU time 0.73 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 206744 kb
Host smart-04d0f31c-0132-46ac-9684-52928c736234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503876939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2503876939
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2671014143
Short name T876
Test name
Test status
Simulation time 109326306 ps
CPU time 3.02 seconds
Started Jul 02 09:51:26 AM PDT 24
Finished Jul 02 09:51:32 AM PDT 24
Peak memory 233772 kb
Host smart-5b400837-c8d1-46c7-9d66-be52476c5885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671014143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2671014143
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3223952146
Short name T444
Test name
Test status
Simulation time 16641203 ps
CPU time 0.76 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:09 AM PDT 24
Peak memory 206824 kb
Host smart-52fb7e0c-978b-4495-8c0e-f10bcc015d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223952146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3223952146
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3672529526
Short name T230
Test name
Test status
Simulation time 974741713 ps
CPU time 20.89 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:30 AM PDT 24
Peak memory 233792 kb
Host smart-ba022ae2-f0bb-49b0-bf38-258b8f3b5471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672529526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3672529526
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.969070100
Short name T706
Test name
Test status
Simulation time 8782688703 ps
CPU time 68.47 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 251416 kb
Host smart-0e2412ae-e968-4bc9-8883-01edb4d379a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969070100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.969070100
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3657036649
Short name T312
Test name
Test status
Simulation time 534551319 ps
CPU time 6.6 seconds
Started Jul 02 09:51:02 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 239712 kb
Host smart-c2543563-87b1-4e20-9745-7c9feb319609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657036649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3657036649
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2296308789
Short name T145
Test name
Test status
Simulation time 897095557 ps
CPU time 12.49 seconds
Started Jul 02 09:51:12 AM PDT 24
Finished Jul 02 09:51:28 AM PDT 24
Peak memory 225492 kb
Host smart-ed5b7768-aedf-44e8-a52e-37f785580ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296308789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2296308789
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1401964222
Short name T713
Test name
Test status
Simulation time 4933370582 ps
CPU time 18.65 seconds
Started Jul 02 09:51:08 AM PDT 24
Finished Jul 02 09:51:30 AM PDT 24
Peak memory 233936 kb
Host smart-bbb61177-ffd2-4351-895b-3dec36615200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401964222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1401964222
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1676730101
Short name T1022
Test name
Test status
Simulation time 31733067 ps
CPU time 0.96 seconds
Started Jul 02 09:51:19 AM PDT 24
Finished Jul 02 09:51:21 AM PDT 24
Peak memory 218864 kb
Host smart-52c3c8aa-08fd-4149-a8a5-22f9bf9773ba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676730101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1676730101
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2370017
Short name T451
Test name
Test status
Simulation time 653417013 ps
CPU time 2.83 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:11 AM PDT 24
Peak memory 233780 kb
Host smart-dd514fc9-fe22-4df9-ade2-d905d7908138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.2370017
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2379984265
Short name T414
Test name
Test status
Simulation time 810723892 ps
CPU time 7.72 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 241888 kb
Host smart-19a3f707-4b90-40c4-a7e5-26877ce28fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379984265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2379984265
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3657969769
Short name T650
Test name
Test status
Simulation time 3397157885 ps
CPU time 17.79 seconds
Started Jul 02 09:51:16 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 223328 kb
Host smart-496d40bf-7a98-49ab-89b2-9d4546e2e012
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3657969769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3657969769
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1384430250
Short name T170
Test name
Test status
Simulation time 3723820584 ps
CPU time 74.39 seconds
Started Jul 02 09:50:59 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 258288 kb
Host smart-a0611358-7b23-4f05-a9e1-9a620b32dde3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384430250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1384430250
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.494146041
Short name T659
Test name
Test status
Simulation time 3264804412 ps
CPU time 6.09 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:51:42 AM PDT 24
Peak memory 217480 kb
Host smart-9d1beb2a-88a5-4821-9144-5aca84cfe788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494146041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.494146041
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1068657537
Short name T461
Test name
Test status
Simulation time 58140426 ps
CPU time 3.42 seconds
Started Jul 02 09:51:07 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 217320 kb
Host smart-41950472-2584-42d9-8bb5-83a4e11dbc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068657537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1068657537
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.121542861
Short name T95
Test name
Test status
Simulation time 32522693 ps
CPU time 0.82 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:07 AM PDT 24
Peak memory 206960 kb
Host smart-423d97a6-0acf-417a-9477-efe0f16ac128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121542861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.121542861
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1379321739
Short name T384
Test name
Test status
Simulation time 3938518343 ps
CPU time 14.63 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:51:27 AM PDT 24
Peak memory 233896 kb
Host smart-81f974b1-3470-4658-94df-9901b131f0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379321739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1379321739
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2944934628
Short name T1015
Test name
Test status
Simulation time 14839541 ps
CPU time 0.72 seconds
Started Jul 02 09:51:16 AM PDT 24
Finished Jul 02 09:51:19 AM PDT 24
Peak memory 205988 kb
Host smart-8ff4522a-3cb3-476d-afc7-80f007dda274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944934628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2944934628
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2913844353
Short name T242
Test name
Test status
Simulation time 15797073409 ps
CPU time 31.9 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 225688 kb
Host smart-d6997cd9-1b28-4435-855d-d7bfe0153ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913844353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2913844353
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1770080395
Short name T987
Test name
Test status
Simulation time 39957724 ps
CPU time 0.76 seconds
Started Jul 02 09:51:20 AM PDT 24
Finished Jul 02 09:51:22 AM PDT 24
Peak memory 206788 kb
Host smart-ef1b620f-179d-4b03-bd75-1f55f269a921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770080395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1770080395
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1447044158
Short name T238
Test name
Test status
Simulation time 9845286741 ps
CPU time 70.62 seconds
Started Jul 02 09:51:34 AM PDT 24
Finished Jul 02 09:52:48 AM PDT 24
Peak memory 258308 kb
Host smart-e0345472-b6a7-4592-ac4c-2e801749bfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447044158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1447044158
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.213639753
Short name T779
Test name
Test status
Simulation time 864283758 ps
CPU time 12.49 seconds
Started Jul 02 09:51:15 AM PDT 24
Finished Jul 02 09:51:30 AM PDT 24
Peak memory 236304 kb
Host smart-42111fff-4a45-44a8-89f8-42a453de2f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213639753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.213639753
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2395272337
Short name T971
Test name
Test status
Simulation time 5797493956 ps
CPU time 91.82 seconds
Started Jul 02 09:51:01 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 252436 kb
Host smart-3664feeb-8946-45ae-9d36-6dec6a3786d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395272337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2395272337
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2136929296
Short name T923
Test name
Test status
Simulation time 1375835070 ps
CPU time 24.09 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:33 AM PDT 24
Peak memory 234000 kb
Host smart-a2ea101c-8c88-46f0-803d-3bdc272d0642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136929296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2136929296
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2786240718
Short name T999
Test name
Test status
Simulation time 9962719491 ps
CPU time 58.06 seconds
Started Jul 02 09:51:14 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 250528 kb
Host smart-2b3c9048-b90d-4c47-8ec9-026036a4b4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786240718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2786240718
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1577093430
Short name T699
Test name
Test status
Simulation time 4807336675 ps
CPU time 8.28 seconds
Started Jul 02 09:51:08 AM PDT 24
Finished Jul 02 09:51:20 AM PDT 24
Peak memory 228452 kb
Host smart-bc2344c6-cb27-41a2-8302-650fb743b58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577093430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1577093430
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.904687963
Short name T1001
Test name
Test status
Simulation time 10406430803 ps
CPU time 100.15 seconds
Started Jul 02 09:51:13 AM PDT 24
Finished Jul 02 09:52:57 AM PDT 24
Peak memory 233872 kb
Host smart-2d16bdf1-b682-4704-a6f4-8ec08f67ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904687963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.904687963
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2872368033
Short name T948
Test name
Test status
Simulation time 15792388 ps
CPU time 1.03 seconds
Started Jul 02 09:51:22 AM PDT 24
Finished Jul 02 09:51:24 AM PDT 24
Peak memory 217632 kb
Host smart-322f2226-aaab-4387-a9bc-84ca6f479a30
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872368033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2872368033
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3249095963
Short name T807
Test name
Test status
Simulation time 5726491713 ps
CPU time 6.82 seconds
Started Jul 02 09:51:24 AM PDT 24
Finished Jul 02 09:51:32 AM PDT 24
Peak memory 225664 kb
Host smart-cce1e351-3a74-43c4-b45d-f3876464a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249095963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3249095963
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2589180505
Short name T251
Test name
Test status
Simulation time 233123583 ps
CPU time 2.34 seconds
Started Jul 02 09:51:40 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 225640 kb
Host smart-1054be16-701b-4f3b-a547-dfc39beb9045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589180505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2589180505
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3701543544
Short name T454
Test name
Test status
Simulation time 100437956 ps
CPU time 3.69 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 223564 kb
Host smart-105b5b83-394e-4883-a5b8-90a72410cc66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3701543544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3701543544
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3287828275
Short name T61
Test name
Test status
Simulation time 26206933777 ps
CPU time 135.2 seconds
Started Jul 02 09:51:08 AM PDT 24
Finished Jul 02 09:53:30 AM PDT 24
Peak memory 258644 kb
Host smart-e1de621c-7474-4bca-b8d9-2170f6fc7d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287828275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3287828275
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3941585940
Short name T570
Test name
Test status
Simulation time 2101200513 ps
CPU time 30.46 seconds
Started Jul 02 09:51:29 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 217516 kb
Host smart-f156ddc9-4660-4454-be33-83e3dde448d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941585940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3941585940
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.862089596
Short name T936
Test name
Test status
Simulation time 1346101645 ps
CPU time 6.34 seconds
Started Jul 02 09:51:16 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 217592 kb
Host smart-f4fc4a00-6352-4561-bb09-7f069aca71aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862089596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.862089596
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3223471514
Short name T629
Test name
Test status
Simulation time 25817871 ps
CPU time 0.84 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:09 AM PDT 24
Peak memory 207640 kb
Host smart-cace5582-88eb-4cab-b666-b681f87e3ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223471514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3223471514
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1511846433
Short name T748
Test name
Test status
Simulation time 182623166 ps
CPU time 0.81 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:11 AM PDT 24
Peak memory 206948 kb
Host smart-896712e2-bd8a-48b2-8921-b593ba68983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511846433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1511846433
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3093331417
Short name T862
Test name
Test status
Simulation time 919387380 ps
CPU time 4.6 seconds
Started Jul 02 09:51:11 AM PDT 24
Finished Jul 02 09:51:20 AM PDT 24
Peak memory 233600 kb
Host smart-6a022d84-5926-42f8-9416-6c4d2660504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093331417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3093331417
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1771509718
Short name T754
Test name
Test status
Simulation time 12433934 ps
CPU time 0.72 seconds
Started Jul 02 09:51:12 AM PDT 24
Finished Jul 02 09:51:17 AM PDT 24
Peak memory 206676 kb
Host smart-64ea2eb8-1046-4875-be4f-51b0fa8b791e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771509718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1771509718
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2682680426
Short name T524
Test name
Test status
Simulation time 356148055 ps
CPU time 6.74 seconds
Started Jul 02 09:51:07 AM PDT 24
Finished Jul 02 09:51:18 AM PDT 24
Peak memory 225576 kb
Host smart-fa461694-ad00-42c8-87e0-9fe1868e58c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682680426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2682680426
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4245493956
Short name T627
Test name
Test status
Simulation time 60349295 ps
CPU time 0.74 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 206488 kb
Host smart-4476f2a6-b849-4f7f-ae46-41295b90c043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245493956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4245493956
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.669350042
Short name T285
Test name
Test status
Simulation time 13242151031 ps
CPU time 48 seconds
Started Jul 02 09:51:14 AM PDT 24
Finished Jul 02 09:52:05 AM PDT 24
Peak memory 236112 kb
Host smart-aa7d763d-c9c6-47a5-bae6-3daf130d163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669350042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.669350042
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1881218260
Short name T526
Test name
Test status
Simulation time 2882507688 ps
CPU time 71.91 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:52:50 AM PDT 24
Peak memory 251408 kb
Host smart-6947dd7b-4caa-47c0-bcd0-91336ee70cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881218260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1881218260
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3534255343
Short name T408
Test name
Test status
Simulation time 2139183293 ps
CPU time 54.31 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:52:04 AM PDT 24
Peak memory 252788 kb
Host smart-d31c3a8e-a34d-4908-99ac-287afac2a9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534255343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3534255343
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.480770080
Short name T308
Test name
Test status
Simulation time 7594056458 ps
CPU time 30.92 seconds
Started Jul 02 09:51:24 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 233892 kb
Host smart-0ec557a8-6abd-4b2e-a60c-9043260b3143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480770080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.480770080
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3775752792
Short name T342
Test name
Test status
Simulation time 20498375 ps
CPU time 0.75 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:08 AM PDT 24
Peak memory 216912 kb
Host smart-f84df189-1e6d-4ecf-91ce-35db264cb9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775752792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3775752792
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1869264489
Short name T998
Test name
Test status
Simulation time 607725337 ps
CPU time 4.12 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:51:17 AM PDT 24
Peak memory 225588 kb
Host smart-7e743e8f-4d8b-4b23-bb2c-49ffca82b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869264489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1869264489
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3131058772
Short name T70
Test name
Test status
Simulation time 1252568340 ps
CPU time 14.49 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:24 AM PDT 24
Peak memory 233760 kb
Host smart-3afe75e8-b506-4a67-809d-2e58ba3e6ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131058772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3131058772
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3040420889
Short name T857
Test name
Test status
Simulation time 92195222 ps
CPU time 1.01 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:01 AM PDT 24
Peak memory 218916 kb
Host smart-f71adfab-c5ce-4e69-bb3c-35c4a87e5d9e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040420889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3040420889
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3225502927
Short name T13
Test name
Test status
Simulation time 386103816 ps
CPU time 6.74 seconds
Started Jul 02 09:51:20 AM PDT 24
Finished Jul 02 09:51:29 AM PDT 24
Peak memory 233760 kb
Host smart-8abff1a9-3ab6-4a20-ba8f-b847bcc35fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225502927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3225502927
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2285373515
Short name T796
Test name
Test status
Simulation time 445069776 ps
CPU time 2.79 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:17 AM PDT 24
Peak memory 233812 kb
Host smart-b62feb12-afe2-4830-ac20-b82a74609472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285373515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2285373515
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3696786939
Short name T16
Test name
Test status
Simulation time 2378744137 ps
CPU time 18.73 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 220460 kb
Host smart-514b1506-8f6b-4439-a6d3-d66d9b2c30dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3696786939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3696786939
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.859981290
Short name T225
Test name
Test status
Simulation time 2273010371 ps
CPU time 50.55 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:58 AM PDT 24
Peak memory 254940 kb
Host smart-5617e0b2-cd4f-4620-95e0-6e8023a35c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859981290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.859981290
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.307810199
Short name T1028
Test name
Test status
Simulation time 21170560327 ps
CPU time 17.67 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 217360 kb
Host smart-8f53875d-af6d-4cac-a9d7-6f818153aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307810199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.307810199
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3073905900
Short name T873
Test name
Test status
Simulation time 1641772300 ps
CPU time 3.03 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:12 AM PDT 24
Peak memory 208936 kb
Host smart-df2954a2-1667-4d48-9eb6-66237a252fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073905900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3073905900
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.404802064
Short name T891
Test name
Test status
Simulation time 54946424 ps
CPU time 1.66 seconds
Started Jul 02 09:51:26 AM PDT 24
Finished Jul 02 09:51:30 AM PDT 24
Peak memory 217316 kb
Host smart-30025a00-3320-4fee-9eb0-7f015187755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404802064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.404802064
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3643755303
Short name T392
Test name
Test status
Simulation time 68590078 ps
CPU time 0.9 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:51:17 AM PDT 24
Peak memory 208036 kb
Host smart-819d4107-56dc-4eb7-96b8-0b465679463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643755303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3643755303
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3619884527
Short name T62
Test name
Test status
Simulation time 2941900755 ps
CPU time 7.6 seconds
Started Jul 02 09:51:24 AM PDT 24
Finished Jul 02 09:51:33 AM PDT 24
Peak memory 233884 kb
Host smart-17820725-1540-418a-9f93-8f24d12bbc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619884527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3619884527
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3479498866
Short name T468
Test name
Test status
Simulation time 62281569 ps
CPU time 0.71 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:06 AM PDT 24
Peak memory 205796 kb
Host smart-a34f4a1e-e2ca-4894-92cc-36556161041f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479498866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3479498866
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1215130077
Short name T100
Test name
Test status
Simulation time 133313759 ps
CPU time 3.84 seconds
Started Jul 02 09:51:31 AM PDT 24
Finished Jul 02 09:51:37 AM PDT 24
Peak memory 233764 kb
Host smart-7a2d8c40-59da-4672-a225-48f1dc8e59c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215130077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1215130077
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1237417766
Short name T605
Test name
Test status
Simulation time 46460731 ps
CPU time 0.76 seconds
Started Jul 02 09:51:21 AM PDT 24
Finished Jul 02 09:51:23 AM PDT 24
Peak memory 206484 kb
Host smart-ad4df9e2-4ddb-4ffe-910d-8c52cf4dfec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237417766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1237417766
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2817069128
Short name T102
Test name
Test status
Simulation time 5813628486 ps
CPU time 46.47 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:56 AM PDT 24
Peak memory 250292 kb
Host smart-f112200a-16fc-42c9-a4e2-c9e3de164436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817069128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2817069128
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2349500994
Short name T597
Test name
Test status
Simulation time 4209686331 ps
CPU time 46.63 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 250460 kb
Host smart-fd5fabdb-c280-46da-a79c-490128512997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349500994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2349500994
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1319722627
Short name T795
Test name
Test status
Simulation time 33514115042 ps
CPU time 66.61 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 240924 kb
Host smart-e984f43b-cd92-4d31-80c1-6fc0b4e0ad83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319722627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1319722627
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3281100299
Short name T953
Test name
Test status
Simulation time 8905900011 ps
CPU time 49.43 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:52:03 AM PDT 24
Peak memory 241916 kb
Host smart-26a358ad-789d-43f5-aef2-f9150541e8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281100299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3281100299
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.418661061
Short name T146
Test name
Test status
Simulation time 6105984036 ps
CPU time 22.49 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 225688 kb
Host smart-895932fe-6bfb-4fc5-827c-3bbf76a81095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418661061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.418661061
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3061335782
Short name T994
Test name
Test status
Simulation time 1685115306 ps
CPU time 17.66 seconds
Started Jul 02 09:51:16 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 240904 kb
Host smart-ad9ea0e5-424a-41df-b456-ca7fbf11172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061335782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3061335782
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3645939038
Short name T620
Test name
Test status
Simulation time 87441592 ps
CPU time 1.04 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:51:20 AM PDT 24
Peak memory 217652 kb
Host smart-726aeb68-dacf-492d-8b1d-c7a557e58733
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645939038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3645939038
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1705421773
Short name T569
Test name
Test status
Simulation time 229579809 ps
CPU time 3.84 seconds
Started Jul 02 09:51:42 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 225588 kb
Host smart-24a18ef2-d70d-4c6d-be5c-83440f23ba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705421773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1705421773
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2161172630
Short name T685
Test name
Test status
Simulation time 398495771 ps
CPU time 2.65 seconds
Started Jul 02 09:51:12 AM PDT 24
Finished Jul 02 09:51:19 AM PDT 24
Peak memory 225544 kb
Host smart-8999a44c-81c4-4f9b-81f1-abe7c672b980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161172630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2161172630
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2239673416
Short name T645
Test name
Test status
Simulation time 674872749 ps
CPU time 7.17 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:51:16 AM PDT 24
Peak memory 219752 kb
Host smart-695c498e-c62f-4613-ae55-5fc00e2f783d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2239673416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2239673416
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1545424726
Short name T946
Test name
Test status
Simulation time 18418389 ps
CPU time 0.77 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 206832 kb
Host smart-6dc9611c-37a9-43f1-9236-537c7041c5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545424726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1545424726
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.448006304
Short name T386
Test name
Test status
Simulation time 14491273979 ps
CPU time 8.95 seconds
Started Jul 02 09:51:08 AM PDT 24
Finished Jul 02 09:51:21 AM PDT 24
Peak memory 217312 kb
Host smart-b020dd77-1290-4786-8597-5061aaf581d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448006304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.448006304
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3318678940
Short name T619
Test name
Test status
Simulation time 215064912 ps
CPU time 1.37 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:08 AM PDT 24
Peak memory 209136 kb
Host smart-4b207522-773f-4361-a121-22e36de63bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318678940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3318678940
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2381938974
Short name T493
Test name
Test status
Simulation time 101091610 ps
CPU time 0.83 seconds
Started Jul 02 09:51:11 AM PDT 24
Finished Jul 02 09:51:16 AM PDT 24
Peak memory 206796 kb
Host smart-6e7fc921-a6c0-40f3-ab2d-89eda9ba8c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381938974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2381938974
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2986257354
Short name T1025
Test name
Test status
Simulation time 3675468167 ps
CPU time 20.43 seconds
Started Jul 02 09:51:14 AM PDT 24
Finished Jul 02 09:51:37 AM PDT 24
Peak memory 233808 kb
Host smart-4c7ba5a4-361d-462a-b93b-6dc1c37f4bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986257354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2986257354
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4140209340
Short name T460
Test name
Test status
Simulation time 13664946 ps
CPU time 0.73 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 205848 kb
Host smart-2ca99cb8-0539-429d-935c-6a6b7bd8fb7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140209340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4140209340
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1557068163
Short name T643
Test name
Test status
Simulation time 1037710802 ps
CPU time 6.04 seconds
Started Jul 02 09:51:43 AM PDT 24
Finished Jul 02 09:51:51 AM PDT 24
Peak memory 233724 kb
Host smart-a19a7ef3-6795-4009-aa43-4428e47aeea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557068163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1557068163
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3474651686
Short name T613
Test name
Test status
Simulation time 47109412 ps
CPU time 0.77 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 207508 kb
Host smart-e70746d9-a942-4653-ac52-eaa9a09bec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474651686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3474651686
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.737114328
Short name T466
Test name
Test status
Simulation time 3038825952 ps
CPU time 34.46 seconds
Started Jul 02 09:51:14 AM PDT 24
Finished Jul 02 09:51:52 AM PDT 24
Peak memory 253080 kb
Host smart-33f4528d-fe0f-41d8-b396-58a72ec8d066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737114328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.737114328
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1899498905
Short name T934
Test name
Test status
Simulation time 2347282822 ps
CPU time 54.51 seconds
Started Jul 02 09:51:12 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 258612 kb
Host smart-2b709fdf-b73f-48fd-b9af-7cba680a54ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899498905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1899498905
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2626375783
Short name T756
Test name
Test status
Simulation time 22791334866 ps
CPU time 84.45 seconds
Started Jul 02 09:51:20 AM PDT 24
Finished Jul 02 09:52:46 AM PDT 24
Peak memory 256824 kb
Host smart-3ad1410e-c144-4e3a-8b01-06818bf6f20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626375783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2626375783
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.622691483
Short name T634
Test name
Test status
Simulation time 2026959168 ps
CPU time 34.59 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 233804 kb
Host smart-00c97f2e-3e47-465f-88ee-2c6c3ef070a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622691483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.622691483
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4049418755
Short name T50
Test name
Test status
Simulation time 31847178356 ps
CPU time 112.95 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:53:20 AM PDT 24
Peak memory 253956 kb
Host smart-f2781235-ac4c-498e-82e2-6c0bb6d9287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049418755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4049418755
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3150787444
Short name T715
Test name
Test status
Simulation time 196533719 ps
CPU time 3.83 seconds
Started Jul 02 09:51:26 AM PDT 24
Finished Jul 02 09:51:31 AM PDT 24
Peak memory 233804 kb
Host smart-edb8ec05-541c-427d-b75a-26cc7f88296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150787444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3150787444
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2501990359
Short name T826
Test name
Test status
Simulation time 2476511732 ps
CPU time 34.71 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 238864 kb
Host smart-6d63ddb6-6df1-4f30-becb-59b42776c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501990359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2501990359
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2518673614
Short name T870
Test name
Test status
Simulation time 65670776 ps
CPU time 1.06 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:08 AM PDT 24
Peak memory 217644 kb
Host smart-66b64176-5052-4b5d-ac0b-e73ee9e70c9e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518673614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2518673614
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2766471926
Short name T197
Test name
Test status
Simulation time 866600049 ps
CPU time 8.01 seconds
Started Jul 02 09:51:04 AM PDT 24
Finished Jul 02 09:51:16 AM PDT 24
Peak memory 238572 kb
Host smart-f8a60237-4140-4182-a28c-33fbd101923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766471926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2766471926
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2418348722
Short name T489
Test name
Test status
Simulation time 10775379766 ps
CPU time 23.56 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:30 AM PDT 24
Peak memory 250276 kb
Host smart-1dbf4032-271a-4709-af9c-043f72888ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418348722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2418348722
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3299778811
Short name T770
Test name
Test status
Simulation time 382871486 ps
CPU time 3.84 seconds
Started Jul 02 09:51:23 AM PDT 24
Finished Jul 02 09:51:27 AM PDT 24
Peak memory 223436 kb
Host smart-b49234e8-ca07-4f15-92ba-02bed5db8b19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299778811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3299778811
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2189178903
Short name T962
Test name
Test status
Simulation time 470984474672 ps
CPU time 339.52 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:57:06 AM PDT 24
Peak memory 266764 kb
Host smart-a5a358b8-db24-4106-b1fa-a2a7f90fcf27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189178903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2189178903
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1326361220
Short name T530
Test name
Test status
Simulation time 6974713328 ps
CPU time 23.02 seconds
Started Jul 02 09:51:12 AM PDT 24
Finished Jul 02 09:51:39 AM PDT 24
Peak memory 217388 kb
Host smart-a44f2ad9-d0e9-4f0a-9c9f-7e816e6492f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326361220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1326361220
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3393077495
Short name T618
Test name
Test status
Simulation time 3360397240 ps
CPU time 3.36 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:51:44 AM PDT 24
Peak memory 209076 kb
Host smart-e7fb8a9b-5fca-4f57-8ca0-fef1e571b5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393077495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3393077495
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1598499411
Short name T53
Test name
Test status
Simulation time 36361666 ps
CPU time 0.79 seconds
Started Jul 02 09:51:20 AM PDT 24
Finished Jul 02 09:51:23 AM PDT 24
Peak memory 207180 kb
Host smart-b0e9d68a-13db-4577-8552-8c7ff3314723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598499411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1598499411
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1002259046
Short name T606
Test name
Test status
Simulation time 195182717 ps
CPU time 0.88 seconds
Started Jul 02 09:51:13 AM PDT 24
Finished Jul 02 09:51:17 AM PDT 24
Peak memory 206976 kb
Host smart-6068fd74-5bd7-404d-9181-9844b6a19c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002259046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1002259046
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2065138046
Short name T904
Test name
Test status
Simulation time 760226513 ps
CPU time 9.27 seconds
Started Jul 02 09:51:26 AM PDT 24
Finished Jul 02 09:51:38 AM PDT 24
Peak memory 225628 kb
Host smart-40dce9fc-cff6-4b69-a8af-557e81ebec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065138046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2065138046
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.100716374
Short name T371
Test name
Test status
Simulation time 57126290 ps
CPU time 2.63 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 233572 kb
Host smart-3b5135ed-52ea-495f-ba93-9cef9f0f3a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100716374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.100716374
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4000847188
Short name T964
Test name
Test status
Simulation time 48620295 ps
CPU time 0.79 seconds
Started Jul 02 09:50:43 AM PDT 24
Finished Jul 02 09:50:45 AM PDT 24
Peak memory 207504 kb
Host smart-c0584285-ecd0-4fa3-b5a6-da0dde7d971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000847188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4000847188
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1986916930
Short name T1
Test name
Test status
Simulation time 2763780507 ps
CPU time 56.71 seconds
Started Jul 02 09:50:34 AM PDT 24
Finished Jul 02 09:51:34 AM PDT 24
Peak memory 255464 kb
Host smart-c717e712-7de5-4d5d-9953-3168140836cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986916930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1986916930
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3450687615
Short name T866
Test name
Test status
Simulation time 2860199393 ps
CPU time 30.09 seconds
Started Jul 02 09:50:49 AM PDT 24
Finished Jul 02 09:51:20 AM PDT 24
Peak memory 218660 kb
Host smart-3b8879ac-9f9b-4521-b69d-2a821e7c347e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450687615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3450687615
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.429309811
Short name T635
Test name
Test status
Simulation time 11735150770 ps
CPU time 29.31 seconds
Started Jul 02 09:50:50 AM PDT 24
Finished Jul 02 09:51:20 AM PDT 24
Peak memory 251204 kb
Host smart-3226a01b-0c80-40ca-b45e-79b3c5d09d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429309811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
429309811
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3224158956
Short name T313
Test name
Test status
Simulation time 1062886570 ps
CPU time 7.89 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 225608 kb
Host smart-098fd323-972a-4cee-a628-431b3de9395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224158956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3224158956
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2995622512
Short name T721
Test name
Test status
Simulation time 3022903658 ps
CPU time 4.02 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:30 AM PDT 24
Peak memory 225688 kb
Host smart-de6a46e3-04a4-41d2-add9-0909a7764cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995622512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2995622512
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3726461088
Short name T350
Test name
Test status
Simulation time 28695714115 ps
CPU time 54.67 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:51:12 AM PDT 24
Peak memory 233864 kb
Host smart-516d9c68-bce5-448b-9c57-53d25ce97e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726461088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3726461088
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.898744566
Short name T38
Test name
Test status
Simulation time 110282521 ps
CPU time 1.04 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:19 AM PDT 24
Peak memory 217680 kb
Host smart-75c3c265-5515-4bb0-abae-d74700dbaa80
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898744566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.898744566
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3425753110
Short name T261
Test name
Test status
Simulation time 221758966 ps
CPU time 5.7 seconds
Started Jul 02 09:50:22 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 241352 kb
Host smart-9fca1f54-625d-4d4d-b9b3-a4853147bb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425753110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3425753110
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1943351570
Short name T794
Test name
Test status
Simulation time 1911883932 ps
CPU time 4.04 seconds
Started Jul 02 09:50:09 AM PDT 24
Finished Jul 02 09:50:21 AM PDT 24
Peak memory 225564 kb
Host smart-e28bcc11-0112-4a1d-8256-4b45f02ce4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943351570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1943351570
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2574755814
Short name T416
Test name
Test status
Simulation time 2653644721 ps
CPU time 6.8 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:50:35 AM PDT 24
Peak memory 219920 kb
Host smart-560a9f14-eb12-4e53-acea-7cfdff48f8bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2574755814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2574755814
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.829794284
Short name T78
Test name
Test status
Simulation time 67636716 ps
CPU time 1.09 seconds
Started Jul 02 09:50:48 AM PDT 24
Finished Jul 02 09:50:50 AM PDT 24
Peak memory 236400 kb
Host smart-57e279de-aa1b-476a-9301-163a749f0d2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829794284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.829794284
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3131718777
Short name T851
Test name
Test status
Simulation time 16821103097 ps
CPU time 167.93 seconds
Started Jul 02 09:50:35 AM PDT 24
Finished Jul 02 09:53:26 AM PDT 24
Peak memory 266156 kb
Host smart-f7bd92a8-ce27-438d-baf1-76cfa8d5bcf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131718777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3131718777
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.296581528
Short name T1019
Test name
Test status
Simulation time 479034729 ps
CPU time 5.21 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:39 AM PDT 24
Peak memory 219972 kb
Host smart-da9cbed3-3767-412b-9a5f-69cebab879ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296581528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.296581528
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3785040561
Short name T750
Test name
Test status
Simulation time 51770314 ps
CPU time 0.7 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 206644 kb
Host smart-9c719718-d9e6-4fec-8c48-8aa2ede4a85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785040561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3785040561
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.491800730
Short name T382
Test name
Test status
Simulation time 17315940 ps
CPU time 1.1 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:27 AM PDT 24
Peak memory 217292 kb
Host smart-ade55733-3cc6-4271-a0de-adc27e3d73b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491800730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.491800730
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3448902913
Short name T638
Test name
Test status
Simulation time 110950781 ps
CPU time 0.88 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 206960 kb
Host smart-47a588af-0644-4b0b-960f-57fe09a86033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448902913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3448902913
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2736961878
Short name T835
Test name
Test status
Simulation time 32640901 ps
CPU time 2.14 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 224256 kb
Host smart-473c6982-94ac-4fe3-959d-086a1bd18ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736961878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2736961878
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2628767117
Short name T72
Test name
Test status
Simulation time 20391890 ps
CPU time 0.73 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:42 AM PDT 24
Peak memory 205796 kb
Host smart-fe46d7f7-54bb-4e56-ab34-ef508e7ac29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628767117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2628767117
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2217602400
Short name T425
Test name
Test status
Simulation time 100052561 ps
CPU time 2.87 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:51:29 AM PDT 24
Peak memory 233792 kb
Host smart-9e323b65-8607-4525-9d73-4fa56d81f00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217602400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2217602400
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2315938639
Short name T547
Test name
Test status
Simulation time 34645458 ps
CPU time 0.76 seconds
Started Jul 02 09:51:28 AM PDT 24
Finished Jul 02 09:51:32 AM PDT 24
Peak memory 206496 kb
Host smart-c430a0e1-5b0f-4bb5-8308-2a9fcf39cdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315938639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2315938639
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1729702699
Short name T213
Test name
Test status
Simulation time 86246322502 ps
CPU time 152.58 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:53:41 AM PDT 24
Peak memory 250304 kb
Host smart-de222035-69ee-45db-8809-744f222f4d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729702699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1729702699
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2489182859
Short name T1006
Test name
Test status
Simulation time 86602936301 ps
CPU time 204.26 seconds
Started Jul 02 09:51:27 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 250548 kb
Host smart-2a4e1ce1-db97-4e29-860d-1e94a5096786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489182859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2489182859
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2788665193
Short name T92
Test name
Test status
Simulation time 5549336961 ps
CPU time 42.78 seconds
Started Jul 02 09:51:29 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 250404 kb
Host smart-07cc4049-2b00-4f43-a792-b1fb5ccd2908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788665193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2788665193
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3903345195
Short name T447
Test name
Test status
Simulation time 516726224 ps
CPU time 6.72 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:51:29 AM PDT 24
Peak memory 225580 kb
Host smart-ae3b451e-4f92-44f3-ad67-84084f3dfd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903345195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3903345195
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3156258324
Short name T266
Test name
Test status
Simulation time 10177531476 ps
CPU time 74.72 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:52:57 AM PDT 24
Peak memory 237516 kb
Host smart-dd62b129-dd00-45c8-8604-d67d605015b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156258324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3156258324
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1693889198
Short name T901
Test name
Test status
Simulation time 9881988499 ps
CPU time 20.98 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:52:01 AM PDT 24
Peak memory 225608 kb
Host smart-181eedf7-fef5-4ece-bd70-45de03effbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693889198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1693889198
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4075537865
Short name T921
Test name
Test status
Simulation time 95994955 ps
CPU time 4.41 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 233808 kb
Host smart-448c6af4-ecc6-4588-8c04-dba6eae8f860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075537865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4075537865
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2437685033
Short name T562
Test name
Test status
Simulation time 30874535 ps
CPU time 2.5 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:00 AM PDT 24
Peak memory 233504 kb
Host smart-2d720bdb-1793-455c-9e49-78f574278791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437685033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2437685033
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3027642678
Short name T221
Test name
Test status
Simulation time 8277648142 ps
CPU time 14.59 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 230572 kb
Host smart-84bcb743-0e1e-48a8-9f19-c7789b75908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027642678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3027642678
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3619401885
Short name T564
Test name
Test status
Simulation time 1915578741 ps
CPU time 8.69 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:18 AM PDT 24
Peak memory 221348 kb
Host smart-4a43d778-d478-4dce-b719-1915ed8e0653
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3619401885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3619401885
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.543099726
Short name T679
Test name
Test status
Simulation time 24352766013 ps
CPU time 96.69 seconds
Started Jul 02 09:51:49 AM PDT 24
Finished Jul 02 09:53:27 AM PDT 24
Peak memory 267840 kb
Host smart-b7de54d7-9b54-4180-90ef-b3e939341ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543099726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.543099726
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3909844833
Short name T412
Test name
Test status
Simulation time 4313706531 ps
CPU time 15.66 seconds
Started Jul 02 09:51:13 AM PDT 24
Finished Jul 02 09:51:32 AM PDT 24
Peak memory 217572 kb
Host smart-cc9461a8-1286-4a0b-97a2-009f094179d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909844833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3909844833
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3319142306
Short name T729
Test name
Test status
Simulation time 5535589830 ps
CPU time 9.78 seconds
Started Jul 02 09:51:42 AM PDT 24
Finished Jul 02 09:51:54 AM PDT 24
Peak memory 217452 kb
Host smart-becfbdc6-f683-45b5-865b-0071548c4d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319142306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3319142306
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1130659971
Short name T424
Test name
Test status
Simulation time 27100824 ps
CPU time 1.08 seconds
Started Jul 02 09:51:11 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 208184 kb
Host smart-e68dbe8a-6d17-482c-a8d7-fdc287e4260f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130659971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1130659971
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.257110803
Short name T633
Test name
Test status
Simulation time 106561508 ps
CPU time 0.93 seconds
Started Jul 02 09:51:08 AM PDT 24
Finished Jul 02 09:51:12 AM PDT 24
Peak memory 206956 kb
Host smart-0a32f215-7298-48e7-8dee-c246ccd5d8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257110803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.257110803
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3877027006
Short name T279
Test name
Test status
Simulation time 10283606312 ps
CPU time 27.98 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 225668 kb
Host smart-bd863c6f-f390-49c8-8958-0a3c410f8000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877027006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3877027006
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3532287629
Short name T985
Test name
Test status
Simulation time 44556448 ps
CPU time 0.72 seconds
Started Jul 02 09:51:20 AM PDT 24
Finished Jul 02 09:51:22 AM PDT 24
Peak memory 205804 kb
Host smart-8635441c-ea06-4f05-aa06-3035c57ae1d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532287629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3532287629
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3629738074
Short name T260
Test name
Test status
Simulation time 3999278613 ps
CPU time 9.18 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 225688 kb
Host smart-f12184c8-05a1-4f74-ad52-df491cb376cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629738074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3629738074
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2086913276
Short name T889
Test name
Test status
Simulation time 15972377 ps
CPU time 0.8 seconds
Started Jul 02 09:51:23 AM PDT 24
Finished Jul 02 09:51:24 AM PDT 24
Peak memory 207836 kb
Host smart-7869ac0c-568d-4c01-b67c-23bcc18ee8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086913276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2086913276
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3166197196
Short name T858
Test name
Test status
Simulation time 3648452436 ps
CPU time 59.3 seconds
Started Jul 02 09:51:05 AM PDT 24
Finished Jul 02 09:52:09 AM PDT 24
Peak memory 254072 kb
Host smart-7bc5e3d2-cbfb-4ea5-b571-662d9ccf703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166197196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3166197196
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.446885012
Short name T491
Test name
Test status
Simulation time 59070167931 ps
CPU time 90.91 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:52:45 AM PDT 24
Peak memory 242260 kb
Host smart-8405cb03-e1c5-4bce-9511-8f379b48170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446885012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.446885012
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2943156868
Short name T733
Test name
Test status
Simulation time 654334313 ps
CPU time 4.33 seconds
Started Jul 02 09:51:40 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 225564 kb
Host smart-65e39ab4-788f-47e7-ae2a-e132209078a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943156868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2943156868
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1773269521
Short name T874
Test name
Test status
Simulation time 8787808845 ps
CPU time 48.77 seconds
Started Jul 02 09:51:20 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 253004 kb
Host smart-e71050fd-b6a5-4cae-b13b-96d485a7a8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773269521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1773269521
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3368550464
Short name T448
Test name
Test status
Simulation time 453078431 ps
CPU time 4.81 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 233804 kb
Host smart-98d70c05-b93b-4c51-86a3-805301796035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368550464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3368550464
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.729969212
Short name T846
Test name
Test status
Simulation time 1780546158 ps
CPU time 13.07 seconds
Started Jul 02 09:51:16 AM PDT 24
Finished Jul 02 09:51:32 AM PDT 24
Peak memory 225532 kb
Host smart-095b6c92-eaae-41a4-94e2-2c907e1116d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729969212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.729969212
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2350957417
Short name T271
Test name
Test status
Simulation time 479050389 ps
CPU time 4.22 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:51:23 AM PDT 24
Peak memory 225604 kb
Host smart-819ea341-d0e1-4b67-8ba6-8446fb125d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350957417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2350957417
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4045976549
Short name T887
Test name
Test status
Simulation time 54621332 ps
CPU time 2.47 seconds
Started Jul 02 09:51:13 AM PDT 24
Finished Jul 02 09:51:19 AM PDT 24
Peak memory 233508 kb
Host smart-9d940230-f819-4e13-a006-8db7d515d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045976549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4045976549
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1509296621
Short name T676
Test name
Test status
Simulation time 1678157954 ps
CPU time 23.44 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 220796 kb
Host smart-528a1bc7-9274-458d-a260-facd6367de3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1509296621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1509296621
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.553859169
Short name T736
Test name
Test status
Simulation time 1317789814 ps
CPU time 5.93 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:49 AM PDT 24
Peak memory 218856 kb
Host smart-1099fe09-2f45-4348-b0e2-ea1846f18c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553859169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.553859169
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2808462748
Short name T885
Test name
Test status
Simulation time 3636191917 ps
CPU time 15.78 seconds
Started Jul 02 09:51:27 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 217548 kb
Host smart-f0cf2d95-865d-4656-8f1c-c9e251a717cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808462748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2808462748
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.154606760
Short name T707
Test name
Test status
Simulation time 21515772 ps
CPU time 1.26 seconds
Started Jul 02 09:51:07 AM PDT 24
Finished Jul 02 09:51:12 AM PDT 24
Peak memory 209176 kb
Host smart-51b7471e-0317-4716-961d-072731e72ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154606760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.154606760
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.402047996
Short name T501
Test name
Test status
Simulation time 46470995 ps
CPU time 0.71 seconds
Started Jul 02 09:51:15 AM PDT 24
Finished Jul 02 09:51:18 AM PDT 24
Peak memory 206980 kb
Host smart-fc0c66ba-c0fe-4f15-8378-54d56a87dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402047996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.402047996
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3239080364
Short name T496
Test name
Test status
Simulation time 19429797197 ps
CPU time 27.98 seconds
Started Jul 02 09:51:09 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 233928 kb
Host smart-3614d473-5c1f-4213-a4d7-eb7316143bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239080364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3239080364
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.913764256
Short name T583
Test name
Test status
Simulation time 12665324 ps
CPU time 0.73 seconds
Started Jul 02 09:51:29 AM PDT 24
Finished Jul 02 09:51:33 AM PDT 24
Peak memory 206412 kb
Host smart-476b20b5-60ea-4ca4-875d-9606a3912886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913764256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.913764256
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3061098364
Short name T693
Test name
Test status
Simulation time 125033883 ps
CPU time 2.25 seconds
Started Jul 02 09:51:13 AM PDT 24
Finished Jul 02 09:51:19 AM PDT 24
Peak memory 233796 kb
Host smart-a4afc10d-5b23-4a48-af8f-c010b6dfbec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061098364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3061098364
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1384314222
Short name T734
Test name
Test status
Simulation time 63417164 ps
CPU time 0.76 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:39 AM PDT 24
Peak memory 206828 kb
Host smart-2f1e2bf0-8830-4605-a430-2a17253988af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384314222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1384314222
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.284220796
Short name T1011
Test name
Test status
Simulation time 5256082746 ps
CPU time 25.3 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:51:52 AM PDT 24
Peak memory 235412 kb
Host smart-498cfdf9-b4c2-4cc8-b331-6848ecf816ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284220796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.284220796
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3292600671
Short name T431
Test name
Test status
Simulation time 14156120908 ps
CPU time 81.2 seconds
Started Jul 02 09:51:40 AM PDT 24
Finished Jul 02 09:53:04 AM PDT 24
Peak memory 250372 kb
Host smart-a40cf313-6fc0-496d-9a4c-f379161daffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292600671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3292600671
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2879954581
Short name T1007
Test name
Test status
Simulation time 12908275329 ps
CPU time 122.33 seconds
Started Jul 02 09:51:13 AM PDT 24
Finished Jul 02 09:53:18 AM PDT 24
Peak memory 234028 kb
Host smart-1cfbaa61-8993-4ade-97d4-234fcb80dfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879954581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2879954581
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.15154716
Short name T310
Test name
Test status
Simulation time 6067280543 ps
CPU time 13.8 seconds
Started Jul 02 09:51:19 AM PDT 24
Finished Jul 02 09:51:34 AM PDT 24
Peak memory 233908 kb
Host smart-3eeedb2e-66f9-4fb0-8c44-5bd64e9afd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15154716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.15154716
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.556921282
Short name T47
Test name
Test status
Simulation time 5713140711 ps
CPU time 59.18 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 253656 kb
Host smart-80791d5a-819c-4086-8e2d-52ad3ff93d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556921282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.556921282
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2051797329
Short name T338
Test name
Test status
Simulation time 374817760 ps
CPU time 2.16 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:51:43 AM PDT 24
Peak memory 225036 kb
Host smart-efbc1352-d784-4f7c-9e96-24db51218e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051797329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2051797329
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2436433263
Short name T446
Test name
Test status
Simulation time 719426248 ps
CPU time 9.4 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:51:29 AM PDT 24
Peak memory 233812 kb
Host smart-c8301ad5-06f7-4b7b-bec8-7dbe1bd8a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436433263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2436433263
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.778221068
Short name T298
Test name
Test status
Simulation time 634235796 ps
CPU time 9.77 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 233800 kb
Host smart-3faff128-99a7-41f1-bcc6-0b26b4c9940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778221068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.778221068
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2620210157
Short name T177
Test name
Test status
Simulation time 12247703794 ps
CPU time 7.84 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:51:34 AM PDT 24
Peak memory 233840 kb
Host smart-886d9198-a2ce-4037-a18a-bf23d02dad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620210157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2620210157
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.578081519
Short name T906
Test name
Test status
Simulation time 1159720448 ps
CPU time 14.94 seconds
Started Jul 02 09:51:21 AM PDT 24
Finished Jul 02 09:51:37 AM PDT 24
Peak memory 221672 kb
Host smart-c291ff48-5dcb-4743-a48c-bd56e6676698
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=578081519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.578081519
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4123466855
Short name T22
Test name
Test status
Simulation time 65793719452 ps
CPU time 202.63 seconds
Started Jul 02 09:51:30 AM PDT 24
Finished Jul 02 09:54:55 AM PDT 24
Peak memory 273832 kb
Host smart-2973afa0-a6d3-4904-a0ef-cb63834ce4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123466855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4123466855
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2404661919
Short name T689
Test name
Test status
Simulation time 1253952359 ps
CPU time 3.66 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:42 AM PDT 24
Peak memory 217504 kb
Host smart-e0f46a66-0c63-4ddd-8d6c-9ac77954ebb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404661919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2404661919
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3375751918
Short name T737
Test name
Test status
Simulation time 8659924452 ps
CPU time 7.87 seconds
Started Jul 02 09:51:18 AM PDT 24
Finished Jul 02 09:51:28 AM PDT 24
Peak memory 217548 kb
Host smart-93f95d70-5adc-417e-84b4-415c84d87592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375751918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3375751918
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.251343412
Short name T895
Test name
Test status
Simulation time 35250920 ps
CPU time 0.68 seconds
Started Jul 02 09:51:11 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 206580 kb
Host smart-e2901c2b-583c-4716-bcf0-bc298c9c4885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251343412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.251343412
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1996536953
Short name T519
Test name
Test status
Simulation time 75530786 ps
CPU time 0.86 seconds
Started Jul 02 09:51:29 AM PDT 24
Finished Jul 02 09:51:33 AM PDT 24
Peak memory 206960 kb
Host smart-22fa7a53-1ff2-4912-95aa-77135dccfc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996536953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1996536953
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.879996988
Short name T12
Test name
Test status
Simulation time 303147774 ps
CPU time 5.52 seconds
Started Jul 02 09:51:18 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 233776 kb
Host smart-43c079fd-68ca-4aaa-9f78-3e9332dbeb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879996988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.879996988
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1848529448
Short name T33
Test name
Test status
Simulation time 100923354 ps
CPU time 0.69 seconds
Started Jul 02 09:51:26 AM PDT 24
Finished Jul 02 09:51:29 AM PDT 24
Peak memory 206308 kb
Host smart-1aabc3ec-39e0-4f2e-845c-e5ebceee7682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848529448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1848529448
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.436299712
Short name T98
Test name
Test status
Simulation time 274353933 ps
CPU time 4.95 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:51:32 AM PDT 24
Peak memory 233804 kb
Host smart-5c404d2b-f6fd-4c88-acf9-64a426e15086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436299712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.436299712
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3808737368
Short name T567
Test name
Test status
Simulation time 65686221 ps
CPU time 0.8 seconds
Started Jul 02 09:51:21 AM PDT 24
Finished Jul 02 09:51:23 AM PDT 24
Peak memory 207876 kb
Host smart-4bb029d8-4167-4c99-90af-14b53c4a823a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808737368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3808737368
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2690446580
Short name T200
Test name
Test status
Simulation time 57588050448 ps
CPU time 75.67 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:52:56 AM PDT 24
Peak memory 250304 kb
Host smart-ac2cdcfb-762b-4dae-8a3b-b623188a27ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690446580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2690446580
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2683915995
Short name T306
Test name
Test status
Simulation time 32537143566 ps
CPU time 305.9 seconds
Started Jul 02 09:51:19 AM PDT 24
Finished Jul 02 09:56:26 AM PDT 24
Peak memory 252616 kb
Host smart-8ba212b1-a520-4d41-a916-b145a18616a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683915995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2683915995
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2257339395
Short name T655
Test name
Test status
Simulation time 108035235 ps
CPU time 4.14 seconds
Started Jul 02 09:51:41 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 233776 kb
Host smart-0093224e-4403-42fb-af5c-d3147676dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257339395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2257339395
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3300333262
Short name T204
Test name
Test status
Simulation time 28024926190 ps
CPU time 190.81 seconds
Started Jul 02 09:51:16 AM PDT 24
Finished Jul 02 09:54:29 AM PDT 24
Peak memory 252340 kb
Host smart-8ab26e17-b7cf-4bd9-b9c1-668745e063b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300333262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3300333262
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1953714740
Short name T961
Test name
Test status
Simulation time 309377141 ps
CPU time 3.19 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:51:44 AM PDT 24
Peak memory 225352 kb
Host smart-9c890eeb-5e85-4427-9796-1b3f9f1d0e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953714740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1953714740
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.607471763
Short name T445
Test name
Test status
Simulation time 4201212055 ps
CPU time 25.24 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:52:00 AM PDT 24
Peak memory 233804 kb
Host smart-8438d4f2-17a7-4284-9292-7ed5c52f665e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607471763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.607471763
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1577235352
Short name T280
Test name
Test status
Simulation time 21165969061 ps
CPU time 18.78 seconds
Started Jul 02 09:51:45 AM PDT 24
Finished Jul 02 09:52:06 AM PDT 24
Peak memory 233948 kb
Host smart-fe4a7f32-bc14-4c59-9dd4-83f6e4c2d1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577235352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1577235352
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2958844980
Short name T602
Test name
Test status
Simulation time 673500940 ps
CPU time 6.12 seconds
Started Jul 02 09:51:11 AM PDT 24
Finished Jul 02 09:51:21 AM PDT 24
Peak memory 225580 kb
Host smart-2b251eef-ceb0-46c2-82c9-f7de9fca3b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958844980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2958844980
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.761264046
Short name T765
Test name
Test status
Simulation time 5284464685 ps
CPU time 16.62 seconds
Started Jul 02 09:51:15 AM PDT 24
Finished Jul 02 09:51:34 AM PDT 24
Peak memory 223336 kb
Host smart-ed63587b-dc25-4d8f-85b8-057b4e7b6fed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=761264046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.761264046
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2280990566
Short name T15
Test name
Test status
Simulation time 283265762 ps
CPU time 1.1 seconds
Started Jul 02 09:51:32 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 207952 kb
Host smart-a8524513-ae0d-40fe-a163-d962da0162be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280990566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2280990566
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.551749287
Short name T956
Test name
Test status
Simulation time 7954529946 ps
CPU time 15.23 seconds
Started Jul 02 09:51:18 AM PDT 24
Finished Jul 02 09:51:35 AM PDT 24
Peak memory 217452 kb
Host smart-c5135894-1225-4328-a7f2-0d09a9c7a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551749287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.551749287
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3396298484
Short name T766
Test name
Test status
Simulation time 3609777160 ps
CPU time 11.67 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 217476 kb
Host smart-a14822b3-2b80-4d62-bbaa-19f074cedba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396298484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3396298484
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1834940
Short name T404
Test name
Test status
Simulation time 450138568 ps
CPU time 4.57 seconds
Started Jul 02 09:51:12 AM PDT 24
Finished Jul 02 09:51:21 AM PDT 24
Peak memory 217276 kb
Host smart-9c398a48-1ba5-4ebf-bd94-f0eab2592940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1834940
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.800919162
Short name T747
Test name
Test status
Simulation time 47632667 ps
CPU time 0.69 seconds
Started Jul 02 09:51:12 AM PDT 24
Finished Jul 02 09:51:16 AM PDT 24
Peak memory 206996 kb
Host smart-e7e121af-7254-4fd9-9819-5bc926753a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800919162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.800919162
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3937938783
Short name T703
Test name
Test status
Simulation time 5008190337 ps
CPU time 20.01 seconds
Started Jul 02 09:51:23 AM PDT 24
Finished Jul 02 09:51:44 AM PDT 24
Peak memory 225688 kb
Host smart-0b14dcc8-1069-497e-a982-3a5972a0f779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937938783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3937938783
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1099037159
Short name T442
Test name
Test status
Simulation time 13646064 ps
CPU time 0.71 seconds
Started Jul 02 09:51:43 AM PDT 24
Finished Jul 02 09:51:46 AM PDT 24
Peak memory 206424 kb
Host smart-3f9cca88-a6d4-42c7-b65c-9e752cdf48fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099037159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1099037159
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2825568105
Short name T587
Test name
Test status
Simulation time 222792865 ps
CPU time 2.93 seconds
Started Jul 02 09:51:31 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 233780 kb
Host smart-2e75b9f2-717e-4aa9-bfc0-20bf017530dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825568105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2825568105
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1373938732
Short name T798
Test name
Test status
Simulation time 22687347 ps
CPU time 0.78 seconds
Started Jul 02 09:51:22 AM PDT 24
Finished Jul 02 09:51:24 AM PDT 24
Peak memory 207524 kb
Host smart-3a7245d9-72f8-4c23-aada-af6ea55960b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373938732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1373938732
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4081290899
Short name T932
Test name
Test status
Simulation time 6950286175 ps
CPU time 38.11 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 250320 kb
Host smart-c12a2af5-76fa-4a0f-afa2-bd12da2af2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081290899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4081290899
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2897994022
Short name T193
Test name
Test status
Simulation time 2827274448 ps
CPU time 32.05 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 237668 kb
Host smart-d89ceec2-751c-43bc-a6b3-23f603a1aedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897994022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2897994022
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1001648611
Short name T658
Test name
Test status
Simulation time 78229876847 ps
CPU time 218.43 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 258596 kb
Host smart-0bb6b644-892d-4d9d-8367-0d7d2aa047b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001648611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1001648611
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2234742955
Short name T339
Test name
Test status
Simulation time 346624982 ps
CPU time 7.66 seconds
Started Jul 02 09:51:46 AM PDT 24
Finished Jul 02 09:51:55 AM PDT 24
Peak memory 241728 kb
Host smart-4272f527-6254-4822-936d-b11495f85e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234742955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2234742955
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1086616534
Short name T940
Test name
Test status
Simulation time 3811047971 ps
CPU time 18.22 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 242092 kb
Host smart-55c1a97a-1378-4271-90e0-ae2517c222cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086616534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1086616534
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2109097393
Short name T701
Test name
Test status
Simulation time 646637363 ps
CPU time 8.79 seconds
Started Jul 02 09:51:30 AM PDT 24
Finished Jul 02 09:51:42 AM PDT 24
Peak memory 225752 kb
Host smart-3fd8ea98-0006-43be-814b-7e79f066a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109097393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2109097393
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.550792872
Short name T429
Test name
Test status
Simulation time 9750238515 ps
CPU time 25.93 seconds
Started Jul 02 09:51:26 AM PDT 24
Finished Jul 02 09:51:55 AM PDT 24
Peak memory 233692 kb
Host smart-28e8e3f9-21a7-41a5-80d7-1daca74b71c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550792872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.550792872
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3387048011
Short name T265
Test name
Test status
Simulation time 1069652471 ps
CPU time 3.44 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:51:23 AM PDT 24
Peak memory 233780 kb
Host smart-8dc619ef-9481-43e5-88ba-5e9554b20258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387048011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3387048011
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3826530101
Short name T816
Test name
Test status
Simulation time 2875019566 ps
CPU time 10.42 seconds
Started Jul 02 09:51:29 AM PDT 24
Finished Jul 02 09:51:42 AM PDT 24
Peak memory 233844 kb
Host smart-4126ca3b-94f6-4d18-9980-bf00b6422b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826530101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3826530101
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4266224068
Short name T818
Test name
Test status
Simulation time 788466640 ps
CPU time 10.27 seconds
Started Jul 02 09:51:22 AM PDT 24
Finished Jul 02 09:51:34 AM PDT 24
Peak memory 221504 kb
Host smart-913916d5-cabf-48d3-84c6-407711576e0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4266224068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4266224068
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.274560141
Short name T93
Test name
Test status
Simulation time 4857127252 ps
CPU time 21.31 seconds
Started Jul 02 09:51:27 AM PDT 24
Finished Jul 02 09:51:51 AM PDT 24
Peak memory 217828 kb
Host smart-c4ee8741-7778-43a3-8315-13ad09e291fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274560141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.274560141
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.515883811
Short name T390
Test name
Test status
Simulation time 11476386 ps
CPU time 0.68 seconds
Started Jul 02 09:51:28 AM PDT 24
Finished Jul 02 09:51:32 AM PDT 24
Peak memory 206664 kb
Host smart-f86cd0a0-5bf6-48dd-8d16-1e01ca20a795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515883811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.515883811
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3700715741
Short name T1029
Test name
Test status
Simulation time 160893448 ps
CPU time 2.26 seconds
Started Jul 02 09:51:45 AM PDT 24
Finished Jul 02 09:51:49 AM PDT 24
Peak memory 217392 kb
Host smart-78d27779-26ec-4f59-bb4e-f464e17b408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700715741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3700715741
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.296363613
Short name T626
Test name
Test status
Simulation time 133067253 ps
CPU time 0.9 seconds
Started Jul 02 09:51:15 AM PDT 24
Finished Jul 02 09:51:18 AM PDT 24
Peak memory 206980 kb
Host smart-7ee4de2b-20ab-404a-be72-33355df63125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296363613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.296363613
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1438837027
Short name T513
Test name
Test status
Simulation time 6346149887 ps
CPU time 19.9 seconds
Started Jul 02 09:51:27 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 225528 kb
Host smart-e92e21f4-cc23-4c33-a3b5-ea1e409b410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438837027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1438837027
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.834625357
Short name T957
Test name
Test status
Simulation time 42344982 ps
CPU time 0.72 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:51:20 AM PDT 24
Peak memory 205848 kb
Host smart-586592c0-3c85-474e-afb0-a7f709de88ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834625357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.834625357
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2457805198
Short name T814
Test name
Test status
Simulation time 2368043202 ps
CPU time 12.61 seconds
Started Jul 02 09:51:41 AM PDT 24
Finished Jul 02 09:51:56 AM PDT 24
Peak memory 233868 kb
Host smart-fe9e6173-0a0f-4390-828a-8585943b0567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457805198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2457805198
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1340998948
Short name T875
Test name
Test status
Simulation time 20087018 ps
CPU time 0.8 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:46 AM PDT 24
Peak memory 207524 kb
Host smart-c8ecb5d9-2e3d-4ec4-8963-19a1603fc411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340998948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1340998948
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1923116391
Short name T449
Test name
Test status
Simulation time 24863430261 ps
CPU time 175.45 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:54:38 AM PDT 24
Peak memory 255072 kb
Host smart-c6ae5565-5d31-492e-9ced-972e58ef59ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923116391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1923116391
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.820241133
Short name T436
Test name
Test status
Simulation time 5483357376 ps
CPU time 66.69 seconds
Started Jul 02 09:51:28 AM PDT 24
Finished Jul 02 09:52:37 AM PDT 24
Peak memory 254988 kb
Host smart-821c66bd-a7cc-41d6-bfc6-7961335419f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820241133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.820241133
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1767693128
Short name T411
Test name
Test status
Simulation time 58494700079 ps
CPU time 132.96 seconds
Started Jul 02 09:51:49 AM PDT 24
Finished Jul 02 09:54:03 AM PDT 24
Peak memory 242228 kb
Host smart-a1199513-311a-4a4c-962d-e516d1ee3b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767693128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1767693128
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3046467546
Short name T345
Test name
Test status
Simulation time 176453435 ps
CPU time 3.18 seconds
Started Jul 02 09:51:22 AM PDT 24
Finished Jul 02 09:51:26 AM PDT 24
Peak memory 233804 kb
Host smart-64feff5b-f6c6-4efb-a614-673773c6cc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046467546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3046467546
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.200143056
Short name T406
Test name
Test status
Simulation time 30487270 ps
CPU time 0.76 seconds
Started Jul 02 09:51:45 AM PDT 24
Finished Jul 02 09:51:47 AM PDT 24
Peak memory 216940 kb
Host smart-021c205c-6ef8-4a32-9249-f2de4388f7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200143056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.200143056
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.555874036
Short name T381
Test name
Test status
Simulation time 1686813082 ps
CPU time 6.37 seconds
Started Jul 02 09:51:40 AM PDT 24
Finished Jul 02 09:51:49 AM PDT 24
Peak memory 228792 kb
Host smart-89400e0f-f21d-4b34-9562-103380157198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555874036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.555874036
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1098481616
Short name T347
Test name
Test status
Simulation time 117040831 ps
CPU time 2.23 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 233496 kb
Host smart-e10eb5bb-f3cc-48d9-ac37-801f77efd760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098481616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1098481616
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2487742510
Short name T557
Test name
Test status
Simulation time 1312247207 ps
CPU time 4.38 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 233628 kb
Host smart-75330e70-7a05-49ce-aa1d-f20e1688bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487742510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2487742510
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.4166612351
Short name T231
Test name
Test status
Simulation time 8763270394 ps
CPU time 13.63 seconds
Started Jul 02 09:51:32 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 233864 kb
Host smart-bce66bad-0522-43de-9dfc-91b35829dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166612351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4166612351
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1655120397
Short name T159
Test name
Test status
Simulation time 108756337 ps
CPU time 3.19 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:51:38 AM PDT 24
Peak memory 219964 kb
Host smart-f5a56805-0343-4916-bac1-a97f9dc1dc61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1655120397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1655120397
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.990157543
Short name T174
Test name
Test status
Simulation time 36297595942 ps
CPU time 158.47 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:54:00 AM PDT 24
Peak memory 250480 kb
Host smart-9d136ded-0607-43c2-8f08-6a3bf2a68094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990157543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.990157543
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.627133865
Short name T927
Test name
Test status
Simulation time 708122502 ps
CPU time 7.95 seconds
Started Jul 02 09:51:36 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 217304 kb
Host smart-bf2aa339-d560-4f3d-b0d0-0006c5de4cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627133865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.627133865
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3429612404
Short name T455
Test name
Test status
Simulation time 3498522280 ps
CPU time 3.47 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:51:46 AM PDT 24
Peak memory 217272 kb
Host smart-5ed4b32a-f871-4687-8c3f-77fd6dbe349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429612404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3429612404
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.361489907
Short name T616
Test name
Test status
Simulation time 36565939 ps
CPU time 0.84 seconds
Started Jul 02 09:51:23 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 207672 kb
Host smart-f571a173-7602-4577-ae3a-6699fcfe291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361489907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.361489907
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.913654630
Short name T355
Test name
Test status
Simulation time 37219060 ps
CPU time 0.8 seconds
Started Jul 02 09:51:32 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 207000 kb
Host smart-f64547dc-f8b0-49c8-b5a4-da1db763fbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913654630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.913654630
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.662976093
Short name T565
Test name
Test status
Simulation time 339245296 ps
CPU time 3.33 seconds
Started Jul 02 09:51:21 AM PDT 24
Finished Jul 02 09:51:26 AM PDT 24
Peak memory 225520 kb
Host smart-beb1e603-6767-4f95-afc1-771a645b2c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662976093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.662976093
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.314750499
Short name T514
Test name
Test status
Simulation time 14888320 ps
CPU time 0.78 seconds
Started Jul 02 09:51:36 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 205844 kb
Host smart-1f4278f8-9814-495f-b935-47cfe63bb03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314750499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.314750499
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.364135952
Short name T111
Test name
Test status
Simulation time 390223434 ps
CPU time 3.32 seconds
Started Jul 02 09:51:20 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 233816 kb
Host smart-3dae4da1-d975-4eaa-a9fc-2caf488e0282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364135952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.364135952
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2801553651
Short name T362
Test name
Test status
Simulation time 38528021 ps
CPU time 0.73 seconds
Started Jul 02 09:51:31 AM PDT 24
Finished Jul 02 09:51:34 AM PDT 24
Peak memory 206780 kb
Host smart-9143bc8b-6c06-4efd-9d6b-e4de3068210c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801553651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2801553651
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1383979419
Short name T1031
Test name
Test status
Simulation time 4738265200 ps
CPU time 10.05 seconds
Started Jul 02 09:51:17 AM PDT 24
Finished Jul 02 09:51:30 AM PDT 24
Peak memory 236360 kb
Host smart-1afee06c-e7cc-4ed7-a915-9c990b76dcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383979419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1383979419
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.671513065
Short name T977
Test name
Test status
Simulation time 29129601387 ps
CPU time 35.95 seconds
Started Jul 02 09:51:47 AM PDT 24
Finished Jul 02 09:52:25 AM PDT 24
Peak memory 225808 kb
Host smart-45c86939-64e6-4a61-ba75-a91db74f3048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671513065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.671513065
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2243658920
Short name T752
Test name
Test status
Simulation time 999568783 ps
CPU time 18.8 seconds
Started Jul 02 09:51:41 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 233932 kb
Host smart-f0014321-18c6-41e1-8f5e-7cd9496f3ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243658920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2243658920
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3934248837
Short name T317
Test name
Test status
Simulation time 3302877492 ps
CPU time 20.27 seconds
Started Jul 02 09:51:27 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 256580 kb
Host smart-896f7d21-0dc2-47fd-ad35-20a8db159c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934248837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3934248837
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2603809087
Short name T572
Test name
Test status
Simulation time 42559196016 ps
CPU time 94.68 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:53:16 AM PDT 24
Peak memory 251884 kb
Host smart-9f4ecbee-150c-401d-8f12-6436360784c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603809087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2603809087
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2002873807
Short name T724
Test name
Test status
Simulation time 468395436 ps
CPU time 2.24 seconds
Started Jul 02 09:51:22 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 233512 kb
Host smart-ba7f9f79-6978-4174-be79-e1b3c65f9665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002873807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2002873807
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3434777656
Short name T631
Test name
Test status
Simulation time 965144396 ps
CPU time 5.93 seconds
Started Jul 02 09:51:28 AM PDT 24
Finished Jul 02 09:51:37 AM PDT 24
Peak memory 239816 kb
Host smart-20d63a8d-92e2-4330-92ff-2a1a880c7a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434777656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3434777656
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1205785380
Short name T290
Test name
Test status
Simulation time 1622575538 ps
CPU time 6.89 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 233748 kb
Host smart-28745cfe-b9c3-426d-bac0-f5291df61c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205785380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1205785380
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1624707735
Short name T802
Test name
Test status
Simulation time 28494671 ps
CPU time 2.43 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 233452 kb
Host smart-8547e0fd-677a-4f5f-ab1c-bbf35e8163c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624707735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1624707735
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2020181917
Short name T1027
Test name
Test status
Simulation time 567044582 ps
CPU time 5.75 seconds
Started Jul 02 09:51:21 AM PDT 24
Finished Jul 02 09:51:28 AM PDT 24
Peak memory 221540 kb
Host smart-eb85e67b-ecf9-42cd-838b-29c25f1aadce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2020181917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2020181917
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.867390457
Short name T888
Test name
Test status
Simulation time 412716136 ps
CPU time 1.1 seconds
Started Jul 02 09:51:36 AM PDT 24
Finished Jul 02 09:51:41 AM PDT 24
Peak memory 208136 kb
Host smart-b6c793fb-b80a-4090-9577-eda5dd5e1aa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867390457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.867390457
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2322451566
Short name T150
Test name
Test status
Simulation time 3432423609 ps
CPU time 18.47 seconds
Started Jul 02 09:51:28 AM PDT 24
Finished Jul 02 09:51:49 AM PDT 24
Peak memory 217512 kb
Host smart-90bedcc2-b1e1-42e8-987e-9386e2752f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322451566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2322451566
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4293021048
Short name T831
Test name
Test status
Simulation time 742661196 ps
CPU time 4.54 seconds
Started Jul 02 09:51:18 AM PDT 24
Finished Jul 02 09:51:24 AM PDT 24
Peak memory 217324 kb
Host smart-748039f4-e29b-4baf-9817-7b0843748ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293021048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4293021048
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3918632010
Short name T423
Test name
Test status
Simulation time 69527066 ps
CPU time 2.96 seconds
Started Jul 02 09:51:32 AM PDT 24
Finished Jul 02 09:51:37 AM PDT 24
Peak memory 217404 kb
Host smart-d49a1507-6513-4dae-8e74-dec0e8382ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918632010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3918632010
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1540180868
Short name T588
Test name
Test status
Simulation time 232944382 ps
CPU time 0.85 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:47 AM PDT 24
Peak memory 206952 kb
Host smart-7b29b9a9-8f5e-41e4-b212-b350529bd53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540180868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1540180868
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.585404106
Short name T9
Test name
Test status
Simulation time 253761507 ps
CPU time 2.54 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:41 AM PDT 24
Peak memory 233804 kb
Host smart-e1d2e4fd-7b7d-4094-925b-f51337af0e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585404106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.585404106
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.634589932
Short name T849
Test name
Test status
Simulation time 14835672 ps
CPU time 0.79 seconds
Started Jul 02 09:51:47 AM PDT 24
Finished Jul 02 09:51:49 AM PDT 24
Peak memory 206408 kb
Host smart-b5c8e5c5-964e-4b67-8ed0-9c90a8bf39ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634589932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.634589932
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.539144897
Short name T812
Test name
Test status
Simulation time 1576519432 ps
CPU time 4.78 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:51:47 AM PDT 24
Peak memory 233720 kb
Host smart-981132e6-69aa-4c24-80b6-e181ce374455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539144897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.539144897
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2682981784
Short name T71
Test name
Test status
Simulation time 16992475 ps
CPU time 0.79 seconds
Started Jul 02 09:51:43 AM PDT 24
Finished Jul 02 09:51:46 AM PDT 24
Peak memory 206488 kb
Host smart-1a115faa-00fa-40a1-b80b-5b33db35df0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682981784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2682981784
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2134923829
Short name T859
Test name
Test status
Simulation time 860791743 ps
CPU time 8.99 seconds
Started Jul 02 09:51:25 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 233696 kb
Host smart-db78932f-e978-4e0c-8eff-b2c748d6f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134923829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2134923829
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2615602438
Short name T202
Test name
Test status
Simulation time 191384330494 ps
CPU time 176.4 seconds
Started Jul 02 09:51:29 AM PDT 24
Finished Jul 02 09:54:29 AM PDT 24
Peak memory 250392 kb
Host smart-351a4aa2-7b05-4a9a-9e69-dccb7ede48a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615602438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2615602438
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.689243676
Short name T301
Test name
Test status
Simulation time 10702914451 ps
CPU time 73.37 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:52:59 AM PDT 24
Peak memory 254432 kb
Host smart-ce8ded58-0870-41ef-9855-83480778c536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689243676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.689243676
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4294473890
Short name T373
Test name
Test status
Simulation time 30421507681 ps
CPU time 52.6 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 242112 kb
Host smart-8b0d6b55-b78f-49db-acef-4a32da85145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294473890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4294473890
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.372888736
Short name T723
Test name
Test status
Simulation time 2773144111 ps
CPU time 11.08 seconds
Started Jul 02 09:51:47 AM PDT 24
Finished Jul 02 09:52:00 AM PDT 24
Peak memory 233900 kb
Host smart-264f2043-eaa1-42af-9070-6c56412c80ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372888736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.372888736
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3540290592
Short name T351
Test name
Test status
Simulation time 3301369663 ps
CPU time 12.89 seconds
Started Jul 02 09:51:47 AM PDT 24
Finished Jul 02 09:52:01 AM PDT 24
Peak memory 225624 kb
Host smart-35e4e9e9-8937-4ff1-a7cd-a39b04aff1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540290592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3540290592
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2776049188
Short name T272
Test name
Test status
Simulation time 1204452450 ps
CPU time 5.44 seconds
Started Jul 02 09:51:32 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 225640 kb
Host smart-260e6b65-b337-43f8-ac21-460a661635be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776049188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2776049188
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3438707542
Short name T10
Test name
Test status
Simulation time 4574546547 ps
CPU time 16.33 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:58 AM PDT 24
Peak memory 233940 kb
Host smart-63f83f62-66f8-4fc2-a48f-8adfd1821d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438707542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3438707542
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.423529665
Short name T450
Test name
Test status
Simulation time 5434812523 ps
CPU time 13.77 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 223312 kb
Host smart-de4e35b4-1e9e-4b78-9025-dc051ccf97d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=423529665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.423529665
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2739970884
Short name T704
Test name
Test status
Simulation time 7399572086 ps
CPU time 11.49 seconds
Started Jul 02 09:51:33 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 217684 kb
Host smart-d82b1fbd-9e21-4417-9baf-716441c370da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739970884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2739970884
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.90710909
Short name T915
Test name
Test status
Simulation time 51422592325 ps
CPU time 21.02 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 217536 kb
Host smart-45275d29-da93-4f48-b063-6da0835a3c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90710909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.90710909
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3529573370
Short name T978
Test name
Test status
Simulation time 167341177 ps
CPU time 2.76 seconds
Started Jul 02 09:51:32 AM PDT 24
Finished Jul 02 09:51:37 AM PDT 24
Peak memory 217416 kb
Host smart-daaf093c-c343-4641-ade6-a24f28bc79e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529573370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3529573370
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1962725189
Short name T1000
Test name
Test status
Simulation time 61969502 ps
CPU time 0.92 seconds
Started Jul 02 09:51:34 AM PDT 24
Finished Jul 02 09:51:37 AM PDT 24
Peak memory 208028 kb
Host smart-89777357-f0d1-415c-b090-f6a718bb3b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962725189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1962725189
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1184099832
Short name T476
Test name
Test status
Simulation time 281558186 ps
CPU time 2.72 seconds
Started Jul 02 09:51:21 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 225640 kb
Host smart-0dce02f1-12de-4aa9-aa39-528a0d752e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184099832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1184099832
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3568431488
Short name T148
Test name
Test status
Simulation time 36516120 ps
CPU time 0.7 seconds
Started Jul 02 09:51:36 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 206408 kb
Host smart-9adc03b4-4067-4361-b8f9-b659d2890d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568431488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3568431488
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3335952273
Short name T276
Test name
Test status
Simulation time 232636562 ps
CPU time 2.72 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:51:43 AM PDT 24
Peak memory 233760 kb
Host smart-2a277731-09ca-474d-a815-c798315260e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335952273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3335952273
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2430218671
Short name T757
Test name
Test status
Simulation time 128086201 ps
CPU time 0.77 seconds
Started Jul 02 09:51:48 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 207480 kb
Host smart-f2b38ffc-9fe5-4096-9dac-6dce112516d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430218671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2430218671
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2163370244
Short name T970
Test name
Test status
Simulation time 19876624312 ps
CPU time 141.54 seconds
Started Jul 02 09:51:46 AM PDT 24
Finished Jul 02 09:54:10 AM PDT 24
Peak memory 262908 kb
Host smart-0d03a803-b4a9-4004-80d3-2958a9f48211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163370244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2163370244
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.588006588
Short name T941
Test name
Test status
Simulation time 19968871818 ps
CPU time 160.68 seconds
Started Jul 02 09:51:29 AM PDT 24
Finished Jul 02 09:54:12 AM PDT 24
Peak memory 252428 kb
Host smart-3de3caa2-f48d-42e7-8547-48ab50499f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588006588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.588006588
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1060396784
Short name T558
Test name
Test status
Simulation time 7604312407 ps
CPU time 30.73 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 225788 kb
Host smart-3283f8ae-aa76-4173-97a9-c899e43ff011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060396784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1060396784
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2673484507
Short name T378
Test name
Test status
Simulation time 115626632 ps
CPU time 2.61 seconds
Started Jul 02 09:51:31 AM PDT 24
Finished Jul 02 09:51:36 AM PDT 24
Peak memory 225608 kb
Host smart-6bc1452f-8f1c-4132-8e04-fa8323ec43c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673484507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2673484507
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.4167725987
Short name T1024
Test name
Test status
Simulation time 9669546234 ps
CPU time 32.97 seconds
Started Jul 02 09:51:30 AM PDT 24
Finished Jul 02 09:52:05 AM PDT 24
Peak memory 250292 kb
Host smart-85c12b47-218c-4a29-9c02-cf0f1040a8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167725987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.4167725987
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.313970817
Short name T505
Test name
Test status
Simulation time 155075313 ps
CPU time 2.64 seconds
Started Jul 02 09:51:35 AM PDT 24
Finished Jul 02 09:51:41 AM PDT 24
Peak memory 233780 kb
Host smart-bab69db2-a0c1-49c7-81e7-71efc8141954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313970817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.313970817
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3749474894
Short name T413
Test name
Test status
Simulation time 2230179482 ps
CPU time 14.81 seconds
Started Jul 02 09:51:41 AM PDT 24
Finished Jul 02 09:51:58 AM PDT 24
Peak memory 233960 kb
Host smart-2093fbd7-74b9-4073-82cb-6f460169c7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749474894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3749474894
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.783224451
Short name T222
Test name
Test status
Simulation time 4391806321 ps
CPU time 8.43 seconds
Started Jul 02 09:51:31 AM PDT 24
Finished Jul 02 09:51:42 AM PDT 24
Peak memory 233924 kb
Host smart-ee664b70-ca3b-49ec-9fac-37bce29c5a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783224451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.783224451
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3919387650
Short name T228
Test name
Test status
Simulation time 7787464654 ps
CPU time 14.27 seconds
Started Jul 02 09:51:52 AM PDT 24
Finished Jul 02 09:52:08 AM PDT 24
Peak memory 225620 kb
Host smart-0ec75f38-528c-47f7-808f-7a03904a6df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919387650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3919387650
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1431153414
Short name T1026
Test name
Test status
Simulation time 3676443396 ps
CPU time 11.44 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:51:54 AM PDT 24
Peak memory 222716 kb
Host smart-4c6c3f81-eb4b-4281-a7f3-b3065f36cc7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1431153414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1431153414
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.232300515
Short name T753
Test name
Test status
Simulation time 75165147536 ps
CPU time 171.45 seconds
Started Jul 02 09:51:36 AM PDT 24
Finished Jul 02 09:54:31 AM PDT 24
Peak memory 242140 kb
Host smart-45ea8abd-8a40-40b0-b2b6-a1df4a45ecb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232300515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.232300515
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2277870336
Short name T799
Test name
Test status
Simulation time 8419535745 ps
CPU time 23.06 seconds
Started Jul 02 09:51:27 AM PDT 24
Finished Jul 02 09:51:52 AM PDT 24
Peak memory 217464 kb
Host smart-8049ed49-75d2-4eca-a07e-df73414531d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277870336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2277870336
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.944003784
Short name T340
Test name
Test status
Simulation time 1474981872 ps
CPU time 2.54 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 217364 kb
Host smart-2286dd70-963d-48b7-b690-b3fbe663f704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944003784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.944003784
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2514726807
Short name T399
Test name
Test status
Simulation time 68308492 ps
CPU time 1.38 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:43 AM PDT 24
Peak memory 217428 kb
Host smart-019b2619-a2cd-4f98-a006-20e149cca9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514726807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2514726807
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1999784308
Short name T543
Test name
Test status
Simulation time 1211909205 ps
CPU time 1 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:47 AM PDT 24
Peak memory 207956 kb
Host smart-05cc733c-cdda-4c04-8607-d6b06a89b924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999784308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1999784308
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3642668658
Short name T933
Test name
Test status
Simulation time 21989912802 ps
CPU time 6.92 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 241960 kb
Host smart-f3a924e5-63f6-4f12-8829-2f511739e512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642668658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3642668658
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2292679955
Short name T665
Test name
Test status
Simulation time 40614840 ps
CPU time 0.73 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:51:54 AM PDT 24
Peak memory 206360 kb
Host smart-b128b915-a478-4724-a3e1-530ad884a968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292679955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2292679955
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3649297862
Short name T24
Test name
Test status
Simulation time 291924015 ps
CPU time 2.15 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:51:43 AM PDT 24
Peak memory 225052 kb
Host smart-911607d7-8cd6-4fc3-a08e-e35010d14852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649297862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3649297862
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.4145567316
Short name T365
Test name
Test status
Simulation time 16872916 ps
CPU time 0.78 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 207512 kb
Host smart-62dcd84b-5e93-4618-ae2e-96004055e6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145567316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4145567316
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1686013721
Short name T237
Test name
Test status
Simulation time 10476732504 ps
CPU time 163.53 seconds
Started Jul 02 09:51:36 AM PDT 24
Finished Jul 02 09:54:23 AM PDT 24
Peak memory 265256 kb
Host smart-f0a0bc94-4f36-4822-9126-244e3e65e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686013721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1686013721
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2579018881
Short name T740
Test name
Test status
Simulation time 16381793907 ps
CPU time 31.38 seconds
Started Jul 02 09:51:40 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 223920 kb
Host smart-308785af-aec0-4233-b77e-d8e8f6b89490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579018881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2579018881
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1681938069
Short name T958
Test name
Test status
Simulation time 8065060430 ps
CPU time 32.5 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:52:28 AM PDT 24
Peak memory 250280 kb
Host smart-b9d0400a-e542-46b8-b4e7-97de231b9f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681938069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1681938069
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.4133753086
Short name T959
Test name
Test status
Simulation time 27372734041 ps
CPU time 67.12 seconds
Started Jul 02 09:51:46 AM PDT 24
Finished Jul 02 09:52:55 AM PDT 24
Peak memory 253612 kb
Host smart-a0bced40-0685-40e0-9ad5-d48534d29fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133753086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.4133753086
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3466341357
Short name T1030
Test name
Test status
Simulation time 32095092 ps
CPU time 2.43 seconds
Started Jul 02 09:51:46 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 233572 kb
Host smart-dee89ca4-ac85-4f6c-8e4e-22e90201eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466341357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3466341357
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2685950249
Short name T233
Test name
Test status
Simulation time 13689343749 ps
CPU time 32.07 seconds
Started Jul 02 09:51:43 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 233924 kb
Host smart-20962315-e937-4ac6-8e43-c8b1c27c3c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685950249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2685950249
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2336063551
Short name T604
Test name
Test status
Simulation time 1944982540 ps
CPU time 7.01 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:51:49 AM PDT 24
Peak memory 233768 kb
Host smart-b1b3f9fe-b27f-446a-89de-3a1825ecc046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336063551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2336063551
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.502400217
Short name T1004
Test name
Test status
Simulation time 13752218559 ps
CPU time 10.13 seconds
Started Jul 02 09:51:42 AM PDT 24
Finished Jul 02 09:51:55 AM PDT 24
Peak memory 233896 kb
Host smart-fa129e72-2bb3-46c1-95ee-f817fd6b11a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502400217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.502400217
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3980157341
Short name T672
Test name
Test status
Simulation time 574744351 ps
CPU time 3.75 seconds
Started Jul 02 09:51:46 AM PDT 24
Finished Jul 02 09:51:51 AM PDT 24
Peak memory 219948 kb
Host smart-b341ee88-1dcd-4213-8c2c-cc46156acea3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980157341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3980157341
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2559878062
Short name T172
Test name
Test status
Simulation time 165658749 ps
CPU time 0.99 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:51:56 AM PDT 24
Peak memory 208532 kb
Host smart-272e2e13-65f9-41fa-aff4-b8be983bf75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559878062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2559878062
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1470053977
Short name T113
Test name
Test status
Simulation time 24189553 ps
CPU time 0.7 seconds
Started Jul 02 09:51:31 AM PDT 24
Finished Jul 02 09:51:34 AM PDT 24
Peak memory 206660 kb
Host smart-103126d6-3123-4367-aafa-22da2d35f417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470053977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1470053977
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.510248886
Short name T838
Test name
Test status
Simulation time 3051718090 ps
CPU time 6.19 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:52:03 AM PDT 24
Peak memory 217508 kb
Host smart-f1a50ef5-3972-4a84-b299-2d93a98e3cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510248886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.510248886
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3746694019
Short name T751
Test name
Test status
Simulation time 414808472 ps
CPU time 1.19 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 208976 kb
Host smart-6ef48c48-0e85-4d87-8e6b-11c4d0a804e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746694019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3746694019
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2984784671
Short name T409
Test name
Test status
Simulation time 346673975 ps
CPU time 0.81 seconds
Started Jul 02 09:51:36 AM PDT 24
Finished Jul 02 09:51:40 AM PDT 24
Peak memory 206952 kb
Host smart-7247b7b6-b8ec-4719-8a17-998684df2851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984784671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2984784671
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2936614717
Short name T786
Test name
Test status
Simulation time 41255443 ps
CPU time 2.55 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:49 AM PDT 24
Peak memory 233668 kb
Host smart-aa75ad93-2c02-4c7d-ba4e-e92183c6d6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936614717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2936614717
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3329751649
Short name T652
Test name
Test status
Simulation time 14618881 ps
CPU time 0.68 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:50:31 AM PDT 24
Peak memory 206384 kb
Host smart-45ff834a-06d5-4b5c-9c36-027f5fa42c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329751649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
329751649
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4090424655
Short name T945
Test name
Test status
Simulation time 345755655 ps
CPU time 2.66 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 233768 kb
Host smart-79113e98-89fa-456a-a08e-d1b15bd5c04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090424655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4090424655
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1917463077
Short name T821
Test name
Test status
Simulation time 22401648 ps
CPU time 0.79 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:50:29 AM PDT 24
Peak memory 207864 kb
Host smart-80654cc7-f34a-43a7-8f7f-d83b3bb611a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917463077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1917463077
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3778208044
Short name T223
Test name
Test status
Simulation time 3484545478 ps
CPU time 64.77 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:51:39 AM PDT 24
Peak memory 274816 kb
Host smart-aabd5b46-0191-4b02-8c23-4d125e033b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778208044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3778208044
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3085146125
Short name T815
Test name
Test status
Simulation time 25478580428 ps
CPU time 165.36 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:53:21 AM PDT 24
Peak memory 250260 kb
Host smart-366aa207-fe0a-437e-85eb-cba0daf8af6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085146125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3085146125
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2301214655
Short name T783
Test name
Test status
Simulation time 29268183868 ps
CPU time 77.02 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 249924 kb
Host smart-9be4761f-1b24-40d5-a76c-cbc4d905405c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301214655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2301214655
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.178120856
Short name T735
Test name
Test status
Simulation time 76341552 ps
CPU time 2.54 seconds
Started Jul 02 09:50:25 AM PDT 24
Finished Jul 02 09:50:35 AM PDT 24
Peak memory 233772 kb
Host smart-ca6570ad-e7ab-4c8f-b3b1-adfef8298e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178120856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.178120856
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.458975120
Short name T254
Test name
Test status
Simulation time 14973155895 ps
CPU time 101.62 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 237776 kb
Host smart-e3899299-d9c7-4067-bedc-bf6ac0f75590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458975120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
458975120
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1582490067
Short name T549
Test name
Test status
Simulation time 1140891110 ps
CPU time 7.3 seconds
Started Jul 02 09:50:30 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 233756 kb
Host smart-473a4bd9-9b3c-42a2-af1e-5181a20e3d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582490067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1582490067
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1913087982
Short name T507
Test name
Test status
Simulation time 31254891 ps
CPU time 2.03 seconds
Started Jul 02 09:50:14 AM PDT 24
Finished Jul 02 09:50:25 AM PDT 24
Peak memory 225404 kb
Host smart-ed01815b-1c4c-49b0-a6e6-4442e19b0503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913087982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1913087982
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.944355644
Short name T495
Test name
Test status
Simulation time 94817984 ps
CPU time 1 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 218976 kb
Host smart-0e61705f-51e8-4979-8baa-dc3277f3e12c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944355644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.944355644
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.593726849
Short name T300
Test name
Test status
Simulation time 978190848 ps
CPU time 8.7 seconds
Started Jul 02 09:50:17 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 240400 kb
Host smart-4cda1a70-e300-4d7d-a800-d040b0b577d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593726849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
593726849
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2118351672
Short name T275
Test name
Test status
Simulation time 30897819705 ps
CPU time 22.83 seconds
Started Jul 02 09:50:25 AM PDT 24
Finished Jul 02 09:50:55 AM PDT 24
Peak memory 233912 kb
Host smart-2502eb0f-a5d1-4465-8b2a-8bf0966e575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118351672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2118351672
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.800603173
Short name T550
Test name
Test status
Simulation time 150655711 ps
CPU time 3.63 seconds
Started Jul 02 09:50:21 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 223604 kb
Host smart-cb64f983-d8c8-4092-aaa3-f156c7f2ca8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=800603173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.800603173
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1254049021
Short name T82
Test name
Test status
Simulation time 5820963847 ps
CPU time 119.61 seconds
Started Jul 02 09:50:29 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 265160 kb
Host smart-0dca3731-fae8-4443-b645-beecbe16e8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254049021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1254049021
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3353303658
Short name T374
Test name
Test status
Simulation time 642558692 ps
CPU time 8.96 seconds
Started Jul 02 09:50:34 AM PDT 24
Finished Jul 02 09:50:47 AM PDT 24
Peak memory 217608 kb
Host smart-b89409cf-47bd-4328-bb62-ec386ad099ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353303658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3353303658
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2964487916
Short name T438
Test name
Test status
Simulation time 3673501707 ps
CPU time 8.3 seconds
Started Jul 02 09:50:18 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 217524 kb
Host smart-c2c2c69b-04b5-42c9-b9a6-07866e3b2a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964487916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2964487916
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1333935342
Short name T11
Test name
Test status
Simulation time 680372623 ps
CPU time 3.53 seconds
Started Jul 02 09:50:41 AM PDT 24
Finished Jul 02 09:50:46 AM PDT 24
Peak memory 217400 kb
Host smart-9f6d5352-6b0a-4943-b59e-1c93700b9f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333935342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1333935342
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3065053466
Short name T472
Test name
Test status
Simulation time 124176339 ps
CPU time 0.97 seconds
Started Jul 02 09:50:38 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 206988 kb
Host smart-369d8217-4283-4b82-a72f-4040b05fd518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065053466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3065053466
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.273152937
Short name T980
Test name
Test status
Simulation time 12985444 ps
CPU time 0.7 seconds
Started Jul 02 09:51:48 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 205728 kb
Host smart-2b0cb464-ceb0-4ff2-bc19-464410962185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273152937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.273152937
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3733583881
Short name T905
Test name
Test status
Simulation time 683360285 ps
CPU time 5.5 seconds
Started Jul 02 09:51:42 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 233800 kb
Host smart-29b8ce13-42aa-44b0-9f4e-0149f4c100f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733583881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3733583881
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2598657958
Short name T397
Test name
Test status
Simulation time 93368835 ps
CPU time 0.77 seconds
Started Jul 02 09:51:41 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 207556 kb
Host smart-a387c102-4432-4153-aa27-8bda7db2a6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598657958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2598657958
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.670697338
Short name T407
Test name
Test status
Simulation time 2318121178 ps
CPU time 9.55 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:08 AM PDT 24
Peak memory 238344 kb
Host smart-3d821ca6-4d08-4e45-83d3-28180a543033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670697338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.670697338
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1581529823
Short name T924
Test name
Test status
Simulation time 22651689759 ps
CPU time 289.1 seconds
Started Jul 02 09:51:59 AM PDT 24
Finished Jul 02 09:56:52 AM PDT 24
Peak memory 266084 kb
Host smart-9e2dc56f-aeac-4f97-b157-7d5cb9496a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581529823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1581529823
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1155202056
Short name T591
Test name
Test status
Simulation time 56267317512 ps
CPU time 50.81 seconds
Started Jul 02 09:51:46 AM PDT 24
Finished Jul 02 09:52:38 AM PDT 24
Peak memory 237692 kb
Host smart-0bf85d83-764c-4c7c-9dfd-1406ff497e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155202056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1155202056
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3343237032
Short name T377
Test name
Test status
Simulation time 886440945 ps
CPU time 8.45 seconds
Started Jul 02 09:51:37 AM PDT 24
Finished Jul 02 09:51:49 AM PDT 24
Peak memory 233808 kb
Host smart-97675465-b5a2-4a8d-899f-239c02729c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343237032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3343237032
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3455516179
Short name T281
Test name
Test status
Simulation time 33004301949 ps
CPU time 119.67 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:53:59 AM PDT 24
Peak memory 267008 kb
Host smart-374ec01b-0a6a-46b6-a416-2c783edec436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455516179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3455516179
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1596675945
Short name T749
Test name
Test status
Simulation time 220734044 ps
CPU time 2.78 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:44 AM PDT 24
Peak memory 225584 kb
Host smart-3edcc42e-dca2-4064-845b-faf81a8344f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596675945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1596675945
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3455516985
Short name T598
Test name
Test status
Simulation time 12128991952 ps
CPU time 3.8 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 225720 kb
Host smart-fc587064-8356-4135-af84-68e7db95eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455516985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3455516985
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3783676828
Short name T790
Test name
Test status
Simulation time 914426805 ps
CPU time 9.74 seconds
Started Jul 02 09:51:40 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 250232 kb
Host smart-5a9d6ddc-9f21-4716-9053-30ee2e77ed2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783676828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3783676828
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1138912542
Short name T894
Test name
Test status
Simulation time 1443965953 ps
CPU time 11.13 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 223448 kb
Host smart-c85a3da9-2d27-4f92-a603-becfd2e44713
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1138912542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1138912542
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1689895186
Short name T775
Test name
Test status
Simulation time 28842303569 ps
CPU time 232.85 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:55:50 AM PDT 24
Peak memory 257656 kb
Host smart-b2076eed-2d20-4f2b-890e-0cdcdd88bdc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689895186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1689895186
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1363143544
Short name T403
Test name
Test status
Simulation time 2305660264 ps
CPU time 6.36 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 217632 kb
Host smart-ff60ddd0-aedf-4d2c-a52a-53c576637bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363143544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1363143544
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.884783919
Short name T388
Test name
Test status
Simulation time 208521873 ps
CPU time 2.2 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:51:44 AM PDT 24
Peak memory 217352 kb
Host smart-bb65884c-90f2-4f6e-a0c6-96eb6178d2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884783919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.884783919
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1021152393
Short name T506
Test name
Test status
Simulation time 292760510 ps
CPU time 2.39 seconds
Started Jul 02 09:51:48 AM PDT 24
Finished Jul 02 09:51:51 AM PDT 24
Peak memory 217356 kb
Host smart-cf2e5813-e0e8-4456-a06e-94e214e89917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021152393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1021152393
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3172192848
Short name T854
Test name
Test status
Simulation time 12468742 ps
CPU time 0.7 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 206968 kb
Host smart-5dc2e2b1-e8cd-4447-a303-28d33f8f6ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172192848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3172192848
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1621377055
Short name T415
Test name
Test status
Simulation time 802197071 ps
CPU time 6.37 seconds
Started Jul 02 09:51:41 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 241408 kb
Host smart-83268259-b6b4-4012-98aa-c802e8f4f55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621377055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1621377055
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4239568016
Short name T555
Test name
Test status
Simulation time 53893144 ps
CPU time 0.72 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:51:52 AM PDT 24
Peak memory 206728 kb
Host smart-729f6a51-1374-457b-86b2-8fc97b7c7680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239568016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4239568016
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2626983300
Short name T988
Test name
Test status
Simulation time 402759674 ps
CPU time 2.97 seconds
Started Jul 02 09:51:43 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 225536 kb
Host smart-de642e2d-30e9-4f4e-b04d-f90aad255f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626983300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2626983300
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3900577640
Short name T458
Test name
Test status
Simulation time 29999472 ps
CPU time 0.77 seconds
Started Jul 02 09:51:47 AM PDT 24
Finished Jul 02 09:51:55 AM PDT 24
Peak memory 207864 kb
Host smart-bb160e62-62c3-4731-8e6c-fd2e22508de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900577640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3900577640
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1281987744
Short name T743
Test name
Test status
Simulation time 11675026169 ps
CPU time 61.56 seconds
Started Jul 02 09:51:49 AM PDT 24
Finished Jul 02 09:52:51 AM PDT 24
Peak memory 250292 kb
Host smart-fb3ab4f7-be27-4376-9ec9-3f086a7b58d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281987744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1281987744
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.720852340
Short name T457
Test name
Test status
Simulation time 10307699059 ps
CPU time 61.41 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:52:47 AM PDT 24
Peak memory 255260 kb
Host smart-c6a1d96b-bc9c-4dcc-a48d-669a1101b647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720852340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.720852340
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2481983542
Short name T243
Test name
Test status
Simulation time 6737640875 ps
CPU time 92.31 seconds
Started Jul 02 09:51:45 AM PDT 24
Finished Jul 02 09:53:19 AM PDT 24
Peak memory 253492 kb
Host smart-ebdea298-ad5f-477a-8a8c-596e874880ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481983542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2481983542
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3589379373
Short name T473
Test name
Test status
Simulation time 868795578 ps
CPU time 11.46 seconds
Started Jul 02 09:51:44 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 234848 kb
Host smart-b73b353b-eeec-415f-b6f3-eed7f78f766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589379373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3589379373
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2535757494
Short name T532
Test name
Test status
Simulation time 12662249738 ps
CPU time 80 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:53:15 AM PDT 24
Peak memory 258516 kb
Host smart-f3fbdbf3-8830-49df-9691-224cc12945f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535757494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2535757494
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3395669890
Short name T691
Test name
Test status
Simulation time 525163096 ps
CPU time 3.75 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:51:58 AM PDT 24
Peak memory 233772 kb
Host smart-87bea081-6a31-4b7d-a8f7-0df36e2986bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395669890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3395669890
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4078446839
Short name T674
Test name
Test status
Simulation time 8565323206 ps
CPU time 73.15 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:53:13 AM PDT 24
Peak memory 233940 kb
Host smart-152ae9e1-4023-4cc5-8c34-a8bfb7f3132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078446839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4078446839
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1435088955
Short name T229
Test name
Test status
Simulation time 3898217592 ps
CPU time 17.39 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 242040 kb
Host smart-72278f28-7368-4914-873a-37b560e390a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435088955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1435088955
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1799294968
Short name T516
Test name
Test status
Simulation time 1003728024 ps
CPU time 8.53 seconds
Started Jul 02 09:51:49 AM PDT 24
Finished Jul 02 09:51:58 AM PDT 24
Peak memory 233800 kb
Host smart-b587f94f-6983-4f5d-a36f-0bf2458377b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799294968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1799294968
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2908601180
Short name T360
Test name
Test status
Simulation time 1277657717 ps
CPU time 11.52 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:51:54 AM PDT 24
Peak memory 222672 kb
Host smart-cc492d58-5427-43cf-be46-185ea22e91c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2908601180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2908601180
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4269463867
Short name T963
Test name
Test status
Simulation time 96442159934 ps
CPU time 22.49 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:22 AM PDT 24
Peak memory 225880 kb
Host smart-3c85badb-eb33-4442-a961-71020784d95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269463867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4269463867
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1008295481
Short name T430
Test name
Test status
Simulation time 1428683170 ps
CPU time 2.97 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:44 AM PDT 24
Peak memory 217404 kb
Host smart-ae77f3c3-ba86-49f1-b84f-bcd8f8d0c5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008295481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1008295481
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2166627105
Short name T920
Test name
Test status
Simulation time 3758667182 ps
CPU time 4.61 seconds
Started Jul 02 09:51:38 AM PDT 24
Finished Jul 02 09:51:46 AM PDT 24
Peak memory 217508 kb
Host smart-02d90f05-bba9-4cbc-986f-597bc47d9464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166627105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2166627105
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1525305149
Short name T918
Test name
Test status
Simulation time 115766831 ps
CPU time 1.13 seconds
Started Jul 02 09:51:39 AM PDT 24
Finished Jul 02 09:51:44 AM PDT 24
Peak memory 217388 kb
Host smart-6bd0c601-7bd0-47f6-9e0d-5f2f5a32a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525305149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1525305149
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3669916523
Short name T335
Test name
Test status
Simulation time 124553971 ps
CPU time 0.87 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:51:52 AM PDT 24
Peak memory 206972 kb
Host smart-f581a6c0-9760-4f49-b402-457905356714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669916523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3669916523
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3172380909
Short name T856
Test name
Test status
Simulation time 482117074 ps
CPU time 2.46 seconds
Started Jul 02 09:51:48 AM PDT 24
Finished Jul 02 09:51:51 AM PDT 24
Peak memory 225328 kb
Host smart-6b47a1d1-e388-4566-abab-5924cb022a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172380909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3172380909
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2437569633
Short name T487
Test name
Test status
Simulation time 30605121 ps
CPU time 0.7 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 205628 kb
Host smart-9f902b61-c5ff-4a6e-a4c9-558e801d3072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437569633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2437569633
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1789353073
Short name T850
Test name
Test status
Simulation time 6679730040 ps
CPU time 7.85 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:52:06 AM PDT 24
Peak memory 233876 kb
Host smart-6193b24b-21d3-4f81-8108-e13e4c406554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789353073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1789353073
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1970024972
Short name T462
Test name
Test status
Simulation time 49577445 ps
CPU time 0.78 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 206472 kb
Host smart-cb877820-61f4-486f-9c2c-e8a6ca17cc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970024972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1970024972
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3816363399
Short name T778
Test name
Test status
Simulation time 4567550021 ps
CPU time 26.06 seconds
Started Jul 02 09:51:43 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 250728 kb
Host smart-ce02d001-f88f-4e49-a510-53cf0b93311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816363399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3816363399
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.173413392
Short name T198
Test name
Test status
Simulation time 63148987140 ps
CPU time 634.93 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 10:02:26 AM PDT 24
Peak memory 257124 kb
Host smart-5c1d0a62-04ad-463a-b912-03d124bd63a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173413392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.173413392
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.610601614
Short name T718
Test name
Test status
Simulation time 65215447569 ps
CPU time 97.65 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:53:41 AM PDT 24
Peak memory 239624 kb
Host smart-ba25eb9e-331b-416b-acb8-77d433e14031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610601614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.610601614
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2189965031
Short name T379
Test name
Test status
Simulation time 453539045 ps
CPU time 8.38 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:52:06 AM PDT 24
Peak memory 225544 kb
Host smart-7f38520d-e897-431f-96ab-d069b21a079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189965031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2189965031
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3988785724
Short name T839
Test name
Test status
Simulation time 8689757043 ps
CPU time 28.02 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:52:19 AM PDT 24
Peak memory 233968 kb
Host smart-d2737b60-b74f-415c-bf2e-907455317f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988785724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3988785724
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3702763084
Short name T681
Test name
Test status
Simulation time 192191398 ps
CPU time 3.92 seconds
Started Jul 02 09:51:41 AM PDT 24
Finished Jul 02 09:51:47 AM PDT 24
Peak memory 225608 kb
Host smart-3020dcb7-ac5c-4896-acfd-2a9ac6e7960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702763084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3702763084
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3277884830
Short name T115
Test name
Test status
Simulation time 42781738704 ps
CPU time 78.75 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:53:19 AM PDT 24
Peak memory 233840 kb
Host smart-c6d730bc-b795-41b4-a93c-77986d19d1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277884830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3277884830
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4216270610
Short name T264
Test name
Test status
Simulation time 12491070536 ps
CPU time 17.16 seconds
Started Jul 02 09:51:46 AM PDT 24
Finished Jul 02 09:52:05 AM PDT 24
Peak memory 225724 kb
Host smart-b5bb54f1-e1ec-40bd-bedc-aadbc240713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216270610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4216270610
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3505945117
Short name T844
Test name
Test status
Simulation time 361996084 ps
CPU time 2.29 seconds
Started Jul 02 09:51:59 AM PDT 24
Finished Jul 02 09:52:04 AM PDT 24
Peak memory 233500 kb
Host smart-b130cf57-9abd-4db1-b604-950c32090460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505945117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3505945117
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1699383676
Short name T968
Test name
Test status
Simulation time 1682026633 ps
CPU time 5.15 seconds
Started Jul 02 09:51:49 AM PDT 24
Finished Jul 02 09:51:55 AM PDT 24
Peak memory 221200 kb
Host smart-526bf8dd-5adb-4629-b322-e4f5f3ad9b34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1699383676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1699383676
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2067937097
Short name T929
Test name
Test status
Simulation time 31325488472 ps
CPU time 150.36 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:54:26 AM PDT 24
Peak memory 267964 kb
Host smart-d4bdb7bc-bda7-4584-817a-4c9e25127b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067937097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2067937097
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2015518559
Short name T761
Test name
Test status
Simulation time 1548035436 ps
CPU time 15.58 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 217500 kb
Host smart-d3e67646-38d1-4a78-8f6e-c3526fa76e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015518559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2015518559
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.487136154
Short name T542
Test name
Test status
Simulation time 5015400476 ps
CPU time 4.24 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 217540 kb
Host smart-2ede229c-804e-4049-8267-d038ddf0963e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487136154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.487136154
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1156671317
Short name T329
Test name
Test status
Simulation time 32717280 ps
CPU time 1.27 seconds
Started Jul 02 09:51:40 AM PDT 24
Finished Jul 02 09:51:45 AM PDT 24
Peak memory 217328 kb
Host smart-3d273997-df10-4d0a-8b1a-526a0d600bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156671317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1156671317
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.4283425829
Short name T666
Test name
Test status
Simulation time 30731416 ps
CPU time 0.78 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:05 AM PDT 24
Peak memory 206936 kb
Host smart-000e2d51-dbf9-4078-89ff-349efc222a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283425829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4283425829
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.98028686
Short name T481
Test name
Test status
Simulation time 3186314670 ps
CPU time 12.15 seconds
Started Jul 02 09:51:52 AM PDT 24
Finished Jul 02 09:52:06 AM PDT 24
Peak memory 233940 kb
Host smart-47cd98b0-4825-47a4-ae9f-b2a302783690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98028686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.98028686
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2527641601
Short name T349
Test name
Test status
Simulation time 71140444 ps
CPU time 0.73 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 205824 kb
Host smart-bd8db4b9-3608-44ec-bac0-0273e73385fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527641601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2527641601
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.481269776
Short name T792
Test name
Test status
Simulation time 670815695 ps
CPU time 2.53 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 233812 kb
Host smart-04eafc3b-463f-417c-8773-35e1b150a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481269776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.481269776
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1862150313
Short name T663
Test name
Test status
Simulation time 19585916 ps
CPU time 0.8 seconds
Started Jul 02 09:51:48 AM PDT 24
Finished Jul 02 09:51:50 AM PDT 24
Peak memory 206512 kb
Host smart-d327c074-738b-418a-bf01-0f390e514c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862150313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1862150313
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2676344137
Short name T847
Test name
Test status
Simulation time 6826702165 ps
CPU time 59.42 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:52:55 AM PDT 24
Peak memory 239464 kb
Host smart-12971ba6-f514-472b-9335-70cc16ca3bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676344137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2676344137
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3507146183
Short name T563
Test name
Test status
Simulation time 1294804801 ps
CPU time 26.42 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 242064 kb
Host smart-9dba2cdc-dc64-462b-b6db-0bad7a8a5856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507146183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3507146183
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3919010424
Short name T993
Test name
Test status
Simulation time 131097773698 ps
CPU time 272.54 seconds
Started Jul 02 09:51:43 AM PDT 24
Finished Jul 02 09:56:18 AM PDT 24
Peak memory 254828 kb
Host smart-8df3427c-1d41-4dcb-8022-bc7346607568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919010424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3919010424
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1295837725
Short name T952
Test name
Test status
Simulation time 689946675 ps
CPU time 8.29 seconds
Started Jul 02 09:52:03 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 225580 kb
Host smart-668cbd6f-27e3-4eb3-9027-92f5b7a9788e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295837725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1295837725
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3043937074
Short name T96
Test name
Test status
Simulation time 9654737501 ps
CPU time 83.79 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:53:23 AM PDT 24
Peak memory 262564 kb
Host smart-93d86ccc-e9a6-4655-9d0a-92f903ddd200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043937074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3043937074
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1925164497
Short name T660
Test name
Test status
Simulation time 402862395 ps
CPU time 4.55 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:52:08 AM PDT 24
Peak memory 225568 kb
Host smart-b19e9e70-9ffe-44a6-a8d2-974e7cbd12f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925164497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1925164497
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2447831722
Short name T670
Test name
Test status
Simulation time 8903767655 ps
CPU time 44.45 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:52:36 AM PDT 24
Peak memory 233932 kb
Host smart-00915f1d-7800-4219-926d-f0f3edeeb1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447831722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2447831722
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1213444761
Short name T81
Test name
Test status
Simulation time 473174946 ps
CPU time 5.51 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 241892 kb
Host smart-6f8ee5b2-374c-4e05-ad61-2812d5e14820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213444761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1213444761
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3733004850
Short name T843
Test name
Test status
Simulation time 3962751845 ps
CPU time 8.64 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:52:04 AM PDT 24
Peak memory 233916 kb
Host smart-4945e80b-1985-4ac3-bcae-03820287e06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733004850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3733004850
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1877376202
Short name T1009
Test name
Test status
Simulation time 382108853 ps
CPU time 3.77 seconds
Started Jul 02 09:51:52 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 220216 kb
Host smart-f9d14a82-8995-4b02-be61-e1bb2cbe354b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1877376202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1877376202
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1013801200
Short name T169
Test name
Test status
Simulation time 329635193 ps
CPU time 1.13 seconds
Started Jul 02 09:51:58 AM PDT 24
Finished Jul 02 09:52:03 AM PDT 24
Peak memory 208076 kb
Host smart-caa83a71-f5f0-4464-8c7d-3a1c2c1b53d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013801200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1013801200
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2444823342
Short name T485
Test name
Test status
Simulation time 6965371442 ps
CPU time 15.13 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 217544 kb
Host smart-b8c5ad5c-1310-46a6-9475-bbff3aea9614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444823342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2444823342
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2523872673
Short name T401
Test name
Test status
Simulation time 307890854 ps
CPU time 2.48 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 217404 kb
Host smart-9724ddfb-27f5-4692-8cce-a999df020850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523872673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2523872673
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1907738623
Short name T525
Test name
Test status
Simulation time 71606983 ps
CPU time 0.69 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:51:53 AM PDT 24
Peak memory 206572 kb
Host smart-d391a4f6-4277-4b7d-9b33-0553b9057996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907738623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1907738623
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2109690202
Short name T820
Test name
Test status
Simulation time 11636041 ps
CPU time 0.67 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 206544 kb
Host smart-abe8843c-e143-45d1-b30f-baafdffd6fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109690202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2109690202
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1047364885
Short name T250
Test name
Test status
Simulation time 2817366114 ps
CPU time 6.78 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:51:58 AM PDT 24
Peak memory 233928 kb
Host smart-e81c1046-60b4-4f9e-8888-c1d5f9364033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047364885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1047364885
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2666430777
Short name T73
Test name
Test status
Simulation time 12141413 ps
CPU time 0.73 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:01 AM PDT 24
Peak memory 206700 kb
Host smart-648098c6-41e3-4fcf-908d-5587057087d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666430777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2666430777
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1442297862
Short name T680
Test name
Test status
Simulation time 1229992764 ps
CPU time 15.73 seconds
Started Jul 02 09:52:03 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 225596 kb
Host smart-1677fb50-d6cc-4aab-89d9-e386994e56f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442297862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1442297862
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.538776113
Short name T872
Test name
Test status
Simulation time 36995618 ps
CPU time 0.79 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:51:54 AM PDT 24
Peak memory 207524 kb
Host smart-7db65f97-80fe-4712-bdf9-695a9f41bf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538776113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.538776113
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2419704672
Short name T760
Test name
Test status
Simulation time 7035294980 ps
CPU time 48.42 seconds
Started Jul 02 09:52:04 AM PDT 24
Finished Jul 02 09:52:54 AM PDT 24
Peak memory 250568 kb
Host smart-f96bbec7-e108-4e97-9493-b2f2f1891c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419704672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2419704672
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1179616278
Short name T201
Test name
Test status
Simulation time 92776579944 ps
CPU time 447.74 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:59:28 AM PDT 24
Peak memory 263176 kb
Host smart-01c352dc-b2cc-46b4-9816-922639f5ef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179616278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1179616278
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2690849894
Short name T80
Test name
Test status
Simulation time 57188281308 ps
CPU time 150.85 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:54:31 AM PDT 24
Peak memory 250440 kb
Host smart-de1c6615-59b5-402b-95a2-d683fbcd5ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690849894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2690849894
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3685274337
Short name T311
Test name
Test status
Simulation time 187790297 ps
CPU time 4.61 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 225620 kb
Host smart-d0457b00-c899-44c6-827e-5b93a1088dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685274337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3685274337
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.437367073
Short name T68
Test name
Test status
Simulation time 30007957222 ps
CPU time 99.56 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:53:36 AM PDT 24
Peak memory 250292 kb
Host smart-4a33cf56-c217-40b2-bffa-370a3a96f01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437367073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.437367073
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2487072073
Short name T625
Test name
Test status
Simulation time 20641934587 ps
CPU time 21.34 seconds
Started Jul 02 09:51:58 AM PDT 24
Finished Jul 02 09:52:23 AM PDT 24
Peak memory 233888 kb
Host smart-2c6fe90b-b85a-4e96-a62a-a308d59bbe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487072073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2487072073
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.847122488
Short name T664
Test name
Test status
Simulation time 2379071666 ps
CPU time 17.32 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:52:09 AM PDT 24
Peak memory 233880 kb
Host smart-705a2ed5-21f4-4591-a8f6-1c4c0a869944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847122488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.847122488
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3569480955
Short name T726
Test name
Test status
Simulation time 28178983139 ps
CPU time 19.69 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:20 AM PDT 24
Peak memory 233864 kb
Host smart-f37f5554-632a-4ab9-84f2-2a8e462dc58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569480955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3569480955
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.902972319
Short name T428
Test name
Test status
Simulation time 138733831 ps
CPU time 2.85 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:01 AM PDT 24
Peak memory 233736 kb
Host smart-5e0ac54c-580a-420f-a457-247584ff4c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902972319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.902972319
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3597378482
Short name T716
Test name
Test status
Simulation time 1045622382 ps
CPU time 12.92 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 223092 kb
Host smart-23b31e24-b8f6-41a8-987a-3c94bfb5cd2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3597378482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3597378482
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2550651175
Short name T720
Test name
Test status
Simulation time 241845795 ps
CPU time 1 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 207872 kb
Host smart-d165f007-eb1b-4cf7-b142-eafd12afc3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550651175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2550651175
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.182784762
Short name T823
Test name
Test status
Simulation time 3795583442 ps
CPU time 5.96 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:51:59 AM PDT 24
Peak memory 217428 kb
Host smart-20fd9b7c-e1f3-447d-9cca-97b4b497f41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182784762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.182784762
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1240817856
Short name T811
Test name
Test status
Simulation time 37050447 ps
CPU time 0.72 seconds
Started Jul 02 09:51:52 AM PDT 24
Finished Jul 02 09:51:54 AM PDT 24
Peak memory 206644 kb
Host smart-991faec4-5175-4cec-a0c0-dfadbcfe1c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240817856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1240817856
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1035765683
Short name T510
Test name
Test status
Simulation time 24047052 ps
CPU time 1.52 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 217372 kb
Host smart-bea64887-422b-48eb-a2f1-262fe1b0955d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035765683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1035765683
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2108632839
Short name T393
Test name
Test status
Simulation time 87961704 ps
CPU time 0.85 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 207208 kb
Host smart-3eb6d965-0f5b-4717-bc2c-db0508c87dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108632839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2108632839
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.503254938
Short name T232
Test name
Test status
Simulation time 176894180894 ps
CPU time 44.67 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:52:48 AM PDT 24
Peak memory 242084 kb
Host smart-0c8cea9d-2c2f-4e68-8d2d-d3f0503e0f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503254938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.503254938
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1331162532
Short name T675
Test name
Test status
Simulation time 40943876 ps
CPU time 0.75 seconds
Started Jul 02 09:52:05 AM PDT 24
Finished Jul 02 09:52:08 AM PDT 24
Peak memory 206412 kb
Host smart-ebc6011c-cd4c-4ae5-83ab-6ea22e9ce3ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331162532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1331162532
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.235321569
Short name T492
Test name
Test status
Simulation time 1596647979 ps
CPU time 12.31 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 233676 kb
Host smart-e7da65f5-8c38-49fa-ac9c-052d5ead6d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235321569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.235321569
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2623068273
Short name T863
Test name
Test status
Simulation time 17984869 ps
CPU time 0.77 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:51:55 AM PDT 24
Peak memory 206452 kb
Host smart-dd08df65-c939-47cc-9671-e88108e1c132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623068273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2623068273
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2734489672
Short name T559
Test name
Test status
Simulation time 6834454356 ps
CPU time 71.32 seconds
Started Jul 02 09:51:52 AM PDT 24
Finished Jul 02 09:53:05 AM PDT 24
Peak memory 266888 kb
Host smart-4576026b-8603-428e-b5cb-cf234e86b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734489672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2734489672
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2116415408
Short name T767
Test name
Test status
Simulation time 26752956860 ps
CPU time 96.63 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:53:32 AM PDT 24
Peak memory 252628 kb
Host smart-91503dde-eda4-4388-a8d8-aa9c6a942bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116415408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2116415408
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1012669259
Short name T509
Test name
Test status
Simulation time 1683749397 ps
CPU time 25.45 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 218656 kb
Host smart-f772b80a-2418-48b1-80a7-03c222124b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012669259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1012669259
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3092464800
Short name T539
Test name
Test status
Simulation time 524585216 ps
CPU time 5.72 seconds
Started Jul 02 09:52:01 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 236336 kb
Host smart-bd405df4-79bf-4e15-a915-93952bc50529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092464800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3092464800
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2471198560
Short name T101
Test name
Test status
Simulation time 9766106934 ps
CPU time 50.27 seconds
Started Jul 02 09:52:02 AM PDT 24
Finished Jul 02 09:52:55 AM PDT 24
Peak memory 250300 kb
Host smart-5ac3fd82-be47-4af8-9740-d4642ff7a4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471198560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2471198560
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2712352053
Short name T196
Test name
Test status
Simulation time 5311148895 ps
CPU time 14.39 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 229468 kb
Host smart-729e8b66-e421-4bc1-810b-2413fde13cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712352053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2712352053
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1468871589
Short name T584
Test name
Test status
Simulation time 1238990797 ps
CPU time 16.87 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 239900 kb
Host smart-b0c00760-7fe8-4734-a56b-4a928ad3f406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468871589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1468871589
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3072124159
Short name T782
Test name
Test status
Simulation time 38380963 ps
CPU time 2.33 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:03 AM PDT 24
Peak memory 225500 kb
Host smart-d7338ec0-9274-4719-9d57-129ebd827f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072124159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3072124159
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3331739710
Short name T246
Test name
Test status
Simulation time 18683294069 ps
CPU time 9.16 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 233832 kb
Host smart-3bf754af-8590-4310-8e0e-a282b5140451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331739710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3331739710
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1443505171
Short name T810
Test name
Test status
Simulation time 645866561 ps
CPU time 4.24 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:04 AM PDT 24
Peak memory 224144 kb
Host smart-3907715e-8d96-4341-9adc-864282336cb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1443505171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1443505171
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3584790636
Short name T545
Test name
Test status
Simulation time 22433101091 ps
CPU time 23.83 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 217544 kb
Host smart-a671f914-ee86-4587-8060-9255142f4800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584790636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3584790636
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3617158871
Short name T930
Test name
Test status
Simulation time 28463804009 ps
CPU time 21.62 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 217472 kb
Host smart-0dbd05f5-f5c3-4893-adaf-adbe3418a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617158871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3617158871
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3220274481
Short name T376
Test name
Test status
Simulation time 156850215 ps
CPU time 0.99 seconds
Started Jul 02 09:51:53 AM PDT 24
Finished Jul 02 09:51:56 AM PDT 24
Peak memory 208224 kb
Host smart-f18adb9f-1200-4f5c-ad6c-704b2dd405c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220274481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3220274481
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2215596693
Short name T417
Test name
Test status
Simulation time 12145334 ps
CPU time 0.7 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:00 AM PDT 24
Peak memory 206572 kb
Host smart-2f49b71b-939e-4c55-94ad-8097285cd91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215596693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2215596693
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2350031397
Short name T992
Test name
Test status
Simulation time 25173725541 ps
CPU time 23.18 seconds
Started Jul 02 09:51:59 AM PDT 24
Finished Jul 02 09:52:25 AM PDT 24
Peak memory 231256 kb
Host smart-aab6dcb1-b61b-4d80-86fe-fb5780657fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350031397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2350031397
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2358142427
Short name T965
Test name
Test status
Simulation time 23923818 ps
CPU time 0.77 seconds
Started Jul 02 09:52:05 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 206356 kb
Host smart-33a9a595-3bb8-4242-b31b-f4829f52ba4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358142427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2358142427
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1456513284
Short name T684
Test name
Test status
Simulation time 247510319 ps
CPU time 2.32 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 225480 kb
Host smart-dd6a46b3-e774-4a4e-afa5-23326a5109db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456513284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1456513284
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2332884992
Short name T960
Test name
Test status
Simulation time 42099413 ps
CPU time 0.82 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 207308 kb
Host smart-3c472f25-c79b-4e8f-ba3c-67688d95f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332884992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2332884992
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3973958932
Short name T944
Test name
Test status
Simulation time 161977122234 ps
CPU time 230.25 seconds
Started Jul 02 09:52:01 AM PDT 24
Finished Jul 02 09:55:55 AM PDT 24
Peak memory 255072 kb
Host smart-72d87889-3ce4-4222-b23b-fa46ea3e0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973958932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3973958932
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1412208921
Short name T969
Test name
Test status
Simulation time 6299513386 ps
CPU time 21.43 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:52:31 AM PDT 24
Peak memory 218864 kb
Host smart-84b1bc1c-57a7-4745-9b0f-70293824016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412208921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1412208921
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.141070391
Short name T315
Test name
Test status
Simulation time 256582588 ps
CPU time 8.53 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:06 AM PDT 24
Peak memory 233764 kb
Host smart-75e0e498-7c3d-432c-bb4b-8c79efad9d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141070391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.141070391
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1092303686
Short name T421
Test name
Test status
Simulation time 68705055 ps
CPU time 0.77 seconds
Started Jul 02 09:51:55 AM PDT 24
Finished Jul 02 09:52:00 AM PDT 24
Peak memory 216888 kb
Host smart-64e900d7-178a-4920-9684-c0fec2fabb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092303686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1092303686
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2574989854
Short name T434
Test name
Test status
Simulation time 497516957 ps
CPU time 4.41 seconds
Started Jul 02 09:51:59 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 225432 kb
Host smart-c8fa42f1-3797-4a0c-af4f-31adce0438d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574989854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2574989854
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2786168321
Short name T149
Test name
Test status
Simulation time 10990681144 ps
CPU time 85.92 seconds
Started Jul 02 09:52:14 AM PDT 24
Finished Jul 02 09:53:42 AM PDT 24
Peak memory 240708 kb
Host smart-60a8bedc-0362-494a-a871-7d690bd4a577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786168321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2786168321
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3743006678
Short name T867
Test name
Test status
Simulation time 5973857362 ps
CPU time 7.33 seconds
Started Jul 02 09:52:20 AM PDT 24
Finished Jul 02 09:52:28 AM PDT 24
Peak memory 233772 kb
Host smart-bf864903-f2e4-4dbc-8359-a889c8fe15a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743006678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3743006678
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3043357343
Short name T730
Test name
Test status
Simulation time 2910472731 ps
CPU time 8.64 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 225704 kb
Host smart-e9cd75b8-c1bc-46b7-b714-2dc342e6e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043357343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3043357343
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.774275805
Short name T596
Test name
Test status
Simulation time 926799030 ps
CPU time 5.35 seconds
Started Jul 02 09:52:02 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 224192 kb
Host smart-2942c518-cf6a-4754-a6d4-44c583cd40d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=774275805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.774275805
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1552709210
Short name T17
Test name
Test status
Simulation time 100782287766 ps
CPU time 455.42 seconds
Started Jul 02 09:51:50 AM PDT 24
Finished Jul 02 09:59:27 AM PDT 24
Peak memory 274996 kb
Host smart-b0b098d8-e063-48f1-aca7-d9bd3dade6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552709210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1552709210
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1234976706
Short name T649
Test name
Test status
Simulation time 32760174592 ps
CPU time 42.67 seconds
Started Jul 02 09:51:51 AM PDT 24
Finished Jul 02 09:52:35 AM PDT 24
Peak memory 217552 kb
Host smart-b949c80c-deac-4339-b626-effebaa737e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234976706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1234976706
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1902890531
Short name T426
Test name
Test status
Simulation time 4138848719 ps
CPU time 5.83 seconds
Started Jul 02 09:51:58 AM PDT 24
Finished Jul 02 09:52:08 AM PDT 24
Peak memory 217500 kb
Host smart-5b97d0f2-6fa9-4edb-a07c-370b6ce0c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902890531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1902890531
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3421191566
Short name T696
Test name
Test status
Simulation time 223957671 ps
CPU time 3.68 seconds
Started Jul 02 09:51:58 AM PDT 24
Finished Jul 02 09:52:06 AM PDT 24
Peak memory 217352 kb
Host smart-552a598b-703e-4ce9-8698-0fc2a6b36fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421191566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3421191566
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3330322241
Short name T686
Test name
Test status
Simulation time 105801637 ps
CPU time 0.92 seconds
Started Jul 02 09:51:58 AM PDT 24
Finished Jul 02 09:52:03 AM PDT 24
Peak memory 207976 kb
Host smart-50c2926e-5bf5-40de-b892-43b58781fcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330322241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3330322241
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.216781884
Short name T855
Test name
Test status
Simulation time 12993938015 ps
CPU time 39.29 seconds
Started Jul 02 09:52:02 AM PDT 24
Finished Jul 02 09:52:44 AM PDT 24
Peak memory 250264 kb
Host smart-842950ed-3375-4293-a731-0973d3ac3006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216781884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.216781884
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2839117554
Short name T943
Test name
Test status
Simulation time 56962200 ps
CPU time 0.74 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 205780 kb
Host smart-5b9f50f7-08d6-41ce-afdf-6484cef621d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839117554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2839117554
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.998611434
Short name T797
Test name
Test status
Simulation time 139257168 ps
CPU time 2.27 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:52:05 AM PDT 24
Peak memory 225552 kb
Host smart-b42fe5ca-867c-453c-a19d-e0ac7e86232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998611434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.998611434
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1794507322
Short name T928
Test name
Test status
Simulation time 36668475 ps
CPU time 0.75 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:02 AM PDT 24
Peak memory 207308 kb
Host smart-4894151b-b7e9-4e67-91ec-4e7868b145c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794507322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1794507322
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3518246647
Short name T236
Test name
Test status
Simulation time 48196387843 ps
CPU time 95.66 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:53:39 AM PDT 24
Peak memory 250308 kb
Host smart-e2421c94-5be9-4b65-a4ab-0800faa44e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518246647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3518246647
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1325256865
Short name T1020
Test name
Test status
Simulation time 487153633710 ps
CPU time 416.38 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:58:57 AM PDT 24
Peak memory 258332 kb
Host smart-8fecd2d9-cf4b-41d5-814a-4e0f6bea1274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325256865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1325256865
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3024143511
Short name T677
Test name
Test status
Simulation time 6663862361 ps
CPU time 96.6 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:53:46 AM PDT 24
Peak memory 251444 kb
Host smart-39de97a1-e551-42ca-b01d-9fed85d41cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024143511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3024143511
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2082539141
Short name T892
Test name
Test status
Simulation time 4030731939 ps
CPU time 18.68 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:52:28 AM PDT 24
Peak memory 250260 kb
Host smart-6bdee43f-3df3-4ddf-916f-3f66866c7143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082539141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2082539141
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2716229532
Short name T984
Test name
Test status
Simulation time 260360372 ps
CPU time 2.18 seconds
Started Jul 02 09:52:05 AM PDT 24
Finished Jul 02 09:52:09 AM PDT 24
Peak memory 225392 kb
Host smart-daad6b80-c96a-4f96-9fc4-5e597626db7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716229532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2716229532
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3398871001
Short name T907
Test name
Test status
Simulation time 597870869 ps
CPU time 5.78 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:06 AM PDT 24
Peak memory 239144 kb
Host smart-afd29745-29ea-4a4f-9a3f-e40964c7e4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398871001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3398871001
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2526389877
Short name T353
Test name
Test status
Simulation time 23855445006 ps
CPU time 12.58 seconds
Started Jul 02 09:52:06 AM PDT 24
Finished Jul 02 09:52:20 AM PDT 24
Peak memory 233896 kb
Host smart-93541ca8-ce16-4482-8f5f-cec258ce0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526389877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2526389877
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3885304363
Short name T955
Test name
Test status
Simulation time 1121209449 ps
CPU time 4.64 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:05 AM PDT 24
Peak memory 225584 kb
Host smart-ea1286a2-a4b8-45fb-8d5b-b51fdad2128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885304363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3885304363
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3321143279
Short name T43
Test name
Test status
Simulation time 352505287 ps
CPU time 3.61 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:03 AM PDT 24
Peak memory 223628 kb
Host smart-7163d6ad-8a08-40dd-a234-41c06c7765f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3321143279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3321143279
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3200419226
Short name T288
Test name
Test status
Simulation time 39967706741 ps
CPU time 378.69 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 272796 kb
Host smart-b1e2e0dc-64ff-40df-a546-d869af18c43d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200419226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3200419226
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.79818666
Short name T441
Test name
Test status
Simulation time 6017877784 ps
CPU time 27.26 seconds
Started Jul 02 09:52:01 AM PDT 24
Finished Jul 02 09:52:31 AM PDT 24
Peak memory 217484 kb
Host smart-dd1380d3-5ab7-431e-aa2a-a6227077ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79818666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.79818666
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.520117191
Short name T3
Test name
Test status
Simulation time 1581900444 ps
CPU time 4.56 seconds
Started Jul 02 09:51:59 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 217388 kb
Host smart-2f1a9424-ef3d-429c-8047-32e9bd0c0e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520117191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.520117191
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2822903690
Short name T27
Test name
Test status
Simulation time 21488340 ps
CPU time 0.86 seconds
Started Jul 02 09:52:16 AM PDT 24
Finished Jul 02 09:52:18 AM PDT 24
Peak memory 207020 kb
Host smart-940614f1-8125-4a16-8c06-656777430d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822903690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2822903690
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2227812138
Short name T488
Test name
Test status
Simulation time 203897275 ps
CPU time 1 seconds
Started Jul 02 09:51:54 AM PDT 24
Finished Jul 02 09:51:57 AM PDT 24
Peak memory 208008 kb
Host smart-a2fd32dc-cd9b-4007-8373-fab8c8b54f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227812138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2227812138
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2435218102
Short name T546
Test name
Test status
Simulation time 305085854 ps
CPU time 5.44 seconds
Started Jul 02 09:51:58 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 233760 kb
Host smart-6f8471e6-5893-4ab3-aff2-b4f23cce556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435218102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2435218102
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4162945023
Short name T742
Test name
Test status
Simulation time 21063502 ps
CPU time 0.75 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 205848 kb
Host smart-3536be9c-3043-429c-b62f-275523c3da78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162945023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4162945023
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.980042028
Short name T777
Test name
Test status
Simulation time 2653121230 ps
CPU time 7.47 seconds
Started Jul 02 09:52:06 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 225672 kb
Host smart-01953ae2-9285-41a1-b3da-8d7199bf2f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980042028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.980042028
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3660618123
Short name T937
Test name
Test status
Simulation time 82345485 ps
CPU time 0.8 seconds
Started Jul 02 09:52:04 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 207472 kb
Host smart-6234e8b3-f5df-46f8-9d26-49f241d2b2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660618123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3660618123
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.520451091
Short name T65
Test name
Test status
Simulation time 22503162661 ps
CPU time 38.4 seconds
Started Jul 02 09:52:12 AM PDT 24
Finished Jul 02 09:52:54 AM PDT 24
Peak memory 233852 kb
Host smart-fe29ec74-a1b9-4214-ae45-6f5c6d7d3318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520451091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.520451091
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3062717948
Short name T46
Test name
Test status
Simulation time 82297304294 ps
CPU time 228.77 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:55:52 AM PDT 24
Peak memory 241612 kb
Host smart-cfa80d5a-4d70-404f-adb8-731e652cf3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062717948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3062717948
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3389353383
Short name T255
Test name
Test status
Simulation time 76748944063 ps
CPU time 222.04 seconds
Started Jul 02 09:51:58 AM PDT 24
Finished Jul 02 09:55:44 AM PDT 24
Peak memory 274696 kb
Host smart-913df7ec-932e-4c5c-afd7-e68dae9afc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389353383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3389353383
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1483984744
Short name T420
Test name
Test status
Simulation time 27636023 ps
CPU time 0.77 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:52:04 AM PDT 24
Peak memory 216924 kb
Host smart-b4109c05-3c87-4d1d-9079-fdb3eb8703aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483984744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1483984744
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3478519658
Short name T508
Test name
Test status
Simulation time 7182231186 ps
CPU time 11.02 seconds
Started Jul 02 09:52:01 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 233896 kb
Host smart-fe44d906-c3eb-4105-8594-efbccea6146d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478519658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3478519658
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4176145472
Short name T722
Test name
Test status
Simulation time 20198443484 ps
CPU time 42.4 seconds
Started Jul 02 09:52:03 AM PDT 24
Finished Jul 02 09:52:48 AM PDT 24
Peak memory 225700 kb
Host smart-221a8932-e860-4f0c-988f-915fa29abfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176145472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4176145472
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2330143591
Short name T269
Test name
Test status
Simulation time 7704160976 ps
CPU time 14.34 seconds
Started Jul 02 09:52:10 AM PDT 24
Finished Jul 02 09:52:27 AM PDT 24
Peak memory 225720 kb
Host smart-6076926b-8525-4a49-83e8-3521454480a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330143591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2330143591
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1024947194
Short name T886
Test name
Test status
Simulation time 31041238 ps
CPU time 2.23 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:04 AM PDT 24
Peak memory 225460 kb
Host smart-55aff55f-e266-41eb-a8cd-1e5a5ad096b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024947194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1024947194
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1697466597
Short name T84
Test name
Test status
Simulation time 2824962024 ps
CPU time 7.62 seconds
Started Jul 02 09:51:58 AM PDT 24
Finished Jul 02 09:52:09 AM PDT 24
Peak memory 221260 kb
Host smart-686fcd4d-58ce-4f86-b65d-abb895dd58e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1697466597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1697466597
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3047340042
Short name T30
Test name
Test status
Simulation time 87481735 ps
CPU time 0.99 seconds
Started Jul 02 09:52:02 AM PDT 24
Finished Jul 02 09:52:06 AM PDT 24
Peak memory 207896 kb
Host smart-461829e7-d842-4195-bfa7-e891a7858d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047340042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3047340042
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.234476023
Short name T1018
Test name
Test status
Simulation time 8169226207 ps
CPU time 23.48 seconds
Started Jul 02 09:52:02 AM PDT 24
Finished Jul 02 09:52:28 AM PDT 24
Peak memory 217556 kb
Host smart-964e285e-425e-43c5-b50f-514bb88f6eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234476023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.234476023
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3063697292
Short name T470
Test name
Test status
Simulation time 501877736 ps
CPU time 3.62 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 217392 kb
Host smart-9149a858-572e-4325-b666-722be16aab16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063697292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3063697292
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2376459474
Short name T372
Test name
Test status
Simulation time 177848039 ps
CPU time 1.5 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 217352 kb
Host smart-bbe5656b-3ba9-47bf-8acd-d88e50c2fa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376459474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2376459474
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1986139919
Short name T610
Test name
Test status
Simulation time 29296514 ps
CPU time 0.84 seconds
Started Jul 02 09:51:56 AM PDT 24
Finished Jul 02 09:52:01 AM PDT 24
Peak memory 206972 kb
Host smart-dfa70769-d2e6-4112-b2c5-845d35bba37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986139919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1986139919
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2047414697
Short name T216
Test name
Test status
Simulation time 241789087 ps
CPU time 5.65 seconds
Started Jul 02 09:51:57 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 233820 kb
Host smart-edcda61c-9cec-4cc6-8119-5bac974e004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047414697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2047414697
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1702319782
Short name T683
Test name
Test status
Simulation time 27988037 ps
CPU time 0.72 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 205856 kb
Host smart-61874fbf-dab4-4525-847b-62f23d832b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702319782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1702319782
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4199778409
Short name T422
Test name
Test status
Simulation time 84621114 ps
CPU time 2.94 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 233720 kb
Host smart-05c34891-d604-4d0d-a662-26613e56adf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199778409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4199778409
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2521100352
Short name T443
Test name
Test status
Simulation time 37258347 ps
CPU time 0.84 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:52:12 AM PDT 24
Peak memory 207824 kb
Host smart-e5596357-c693-4e7b-9f1d-d121ece7a87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521100352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2521100352
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2413861572
Short name T263
Test name
Test status
Simulation time 8172969379 ps
CPU time 103.96 seconds
Started Jul 02 09:52:00 AM PDT 24
Finished Jul 02 09:53:47 AM PDT 24
Peak memory 257720 kb
Host smart-3b9e0193-1e8f-43db-be99-89084a515add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413861572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2413861572
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2908171401
Short name T210
Test name
Test status
Simulation time 61429508284 ps
CPU time 445.95 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:59:36 AM PDT 24
Peak memory 266284 kb
Host smart-b3b235cb-aeba-4743-9b1b-ce13ad0fe273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908171401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2908171401
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.770761718
Short name T56
Test name
Test status
Simulation time 303245667116 ps
CPU time 205.95 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 258220 kb
Host smart-ba40f8de-4f5c-46e1-83fb-2fc6cf0b9f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770761718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.770761718
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.369334672
Short name T861
Test name
Test status
Simulation time 7669512646 ps
CPU time 15.24 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:27 AM PDT 24
Peak memory 235768 kb
Host smart-bb19c20e-ac7b-4f40-abe9-4ed39867490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369334672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.369334672
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.856291315
Short name T938
Test name
Test status
Simulation time 141787926141 ps
CPU time 240.04 seconds
Started Jul 02 09:52:04 AM PDT 24
Finished Jul 02 09:56:07 AM PDT 24
Peak memory 254224 kb
Host smart-1ebce20f-04b7-4016-9c46-b23e3c70e19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856291315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.856291315
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2709670850
Short name T678
Test name
Test status
Simulation time 202026034 ps
CPU time 5.54 seconds
Started Jul 02 09:52:03 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 225572 kb
Host smart-2f3b1f97-bb46-4d29-961e-41b399a30e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709670850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2709670850
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3153585104
Short name T219
Test name
Test status
Simulation time 13501439856 ps
CPU time 76.77 seconds
Started Jul 02 09:52:03 AM PDT 24
Finished Jul 02 09:53:22 AM PDT 24
Peak memory 233916 kb
Host smart-c8010d97-927c-40a4-ac95-c1ea4588b954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153585104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3153585104
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3960852181
Short name T909
Test name
Test status
Simulation time 193290281 ps
CPU time 3.62 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 225552 kb
Host smart-17010a52-4d44-4c96-9a2f-d9fcd7b1713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960852181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3960852181
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4249310060
Short name T673
Test name
Test status
Simulation time 8073993187 ps
CPU time 7.9 seconds
Started Jul 02 09:52:03 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 233868 kb
Host smart-24005eda-b2ec-4527-a3b3-62107e2cd0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249310060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4249310060
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3277190994
Short name T561
Test name
Test status
Simulation time 449264976 ps
CPU time 4.02 seconds
Started Jul 02 09:52:12 AM PDT 24
Finished Jul 02 09:52:19 AM PDT 24
Peak memory 222828 kb
Host smart-b231e101-1355-4e60-9e19-69d583f0e52d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3277190994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3277190994
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3429445249
Short name T21
Test name
Test status
Simulation time 54512006457 ps
CPU time 246.31 seconds
Started Jul 02 09:52:06 AM PDT 24
Finished Jul 02 09:56:14 AM PDT 24
Peak memory 252440 kb
Host smart-d0e556e5-2082-4551-8957-fd99d74e9075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429445249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3429445249
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1355078305
Short name T621
Test name
Test status
Simulation time 5878670934 ps
CPU time 36.89 seconds
Started Jul 02 09:52:02 AM PDT 24
Finished Jul 02 09:52:42 AM PDT 24
Peak memory 217740 kb
Host smart-7cef252c-4baa-4c4e-acf8-c6842e23f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355078305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1355078305
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2021976180
Short name T523
Test name
Test status
Simulation time 2377230031 ps
CPU time 7.09 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 217548 kb
Host smart-01e9737f-96b4-41e4-a2b7-91df31cad9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021976180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2021976180
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.139271819
Short name T806
Test name
Test status
Simulation time 12828283 ps
CPU time 0.78 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 206980 kb
Host smart-0b905ece-d63c-4b7d-912a-6cd5ac8c2aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139271819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.139271819
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1665733471
Short name T593
Test name
Test status
Simulation time 53811399 ps
CPU time 0.91 seconds
Started Jul 02 09:52:04 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 208024 kb
Host smart-c56eb3fc-8984-4c66-9890-2fb470a6c05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665733471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1665733471
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2708797168
Short name T553
Test name
Test status
Simulation time 5621451771 ps
CPU time 8.98 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:22 AM PDT 24
Peak memory 241952 kb
Host smart-e26ea80a-e05b-4019-9681-e45c58adc23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708797168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2708797168
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2887023090
Short name T830
Test name
Test status
Simulation time 15728936 ps
CPU time 0.74 seconds
Started Jul 02 09:50:46 AM PDT 24
Finished Jul 02 09:50:48 AM PDT 24
Peak memory 206344 kb
Host smart-e8ac7633-3730-4f16-9542-79772cc85ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887023090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
887023090
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.65064611
Short name T576
Test name
Test status
Simulation time 1501192728 ps
CPU time 2.31 seconds
Started Jul 02 09:50:46 AM PDT 24
Finished Jul 02 09:50:49 AM PDT 24
Peak memory 225528 kb
Host smart-d31ecd66-8e87-4945-b07d-009c2137c3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65064611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.65064611
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3849370261
Short name T464
Test name
Test status
Simulation time 119160641 ps
CPU time 0.81 seconds
Started Jul 02 09:50:22 AM PDT 24
Finished Jul 02 09:50:31 AM PDT 24
Peak memory 207492 kb
Host smart-39308c75-7d6b-4eec-8099-acf8daf68ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849370261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3849370261
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3249874859
Short name T641
Test name
Test status
Simulation time 3051295809 ps
CPU time 28.71 seconds
Started Jul 02 09:50:41 AM PDT 24
Finished Jul 02 09:51:11 AM PDT 24
Peak memory 242064 kb
Host smart-a653dfcb-8d9b-4060-9ac9-610978aa701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249874859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3249874859
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1698597497
Short name T883
Test name
Test status
Simulation time 4872415311 ps
CPU time 16.41 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:50 AM PDT 24
Peak memory 225440 kb
Host smart-b00d01c2-c650-4fa2-8ab0-8ea9d841e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698597497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1698597497
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1688853245
Short name T589
Test name
Test status
Simulation time 6321100362 ps
CPU time 64.12 seconds
Started Jul 02 09:50:43 AM PDT 24
Finished Jul 02 09:51:48 AM PDT 24
Peak memory 242196 kb
Host smart-6380cd5b-0f29-45af-af32-ba42903a515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688853245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1688853245
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3997309679
Short name T695
Test name
Test status
Simulation time 1165742422 ps
CPU time 9.69 seconds
Started Jul 02 09:50:40 AM PDT 24
Finished Jul 02 09:50:51 AM PDT 24
Peak memory 225556 kb
Host smart-f86db7d0-6c2a-4086-9fb1-625d255f1273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997309679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3997309679
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1141801889
Short name T711
Test name
Test status
Simulation time 16975071401 ps
CPU time 51.91 seconds
Started Jul 02 09:50:23 AM PDT 24
Finished Jul 02 09:51:23 AM PDT 24
Peak memory 250496 kb
Host smart-2cc0b5e2-312c-4b98-9497-a70279d67f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141801889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1141801889
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1113607003
Short name T203
Test name
Test status
Simulation time 477416793 ps
CPU time 5.31 seconds
Started Jul 02 09:50:29 AM PDT 24
Finished Jul 02 09:50:40 AM PDT 24
Peak memory 233836 kb
Host smart-4d8b57f1-a5dc-441f-b767-b1e2c3578ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113607003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1113607003
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.36165201
Short name T702
Test name
Test status
Simulation time 18325548977 ps
CPU time 30.51 seconds
Started Jul 02 09:50:45 AM PDT 24
Finished Jul 02 09:51:16 AM PDT 24
Peak memory 240540 kb
Host smart-7e53b786-f8f0-4a0f-9e72-49b3dbf298ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36165201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.36165201
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1697675326
Short name T771
Test name
Test status
Simulation time 56442112 ps
CPU time 1.03 seconds
Started Jul 02 09:50:38 AM PDT 24
Finished Jul 02 09:50:40 AM PDT 24
Peak memory 218900 kb
Host smart-18d81f85-c461-44e4-95f5-82a8b50710bd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697675326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1697675326
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.986294966
Short name T292
Test name
Test status
Simulation time 27268587150 ps
CPU time 8.18 seconds
Started Jul 02 09:50:25 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 233832 kb
Host smart-43b27fb7-04d4-443b-aa07-5c12fc90c251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986294966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
986294966
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2733215843
Short name T882
Test name
Test status
Simulation time 8214508124 ps
CPU time 15.81 seconds
Started Jul 02 09:50:27 AM PDT 24
Finished Jul 02 09:50:49 AM PDT 24
Peak memory 239948 kb
Host smart-bb39ffc2-5b55-4efa-b5e9-9e16f2256f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733215843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2733215843
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1868210336
Short name T477
Test name
Test status
Simulation time 261242442 ps
CPU time 3.97 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 221460 kb
Host smart-b6c6f718-2904-408d-9c6a-cebee5999a92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1868210336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1868210336
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.5224096
Short name T79
Test name
Test status
Simulation time 139833008 ps
CPU time 1.1 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 236324 kb
Host smart-6df59ead-47bd-4faf-b8fb-5d0ffa53f8e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5224096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.5224096
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1502533904
Short name T789
Test name
Test status
Simulation time 68464282571 ps
CPU time 375.92 seconds
Started Jul 02 09:50:43 AM PDT 24
Finished Jul 02 09:57:00 AM PDT 24
Peak memory 276480 kb
Host smart-9696967e-bfa7-466a-9679-a97f6bf9b443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502533904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1502533904
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1883796488
Short name T712
Test name
Test status
Simulation time 12697749999 ps
CPU time 6.89 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 217496 kb
Host smart-32094423-3e76-4fba-a8af-66ffe550bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883796488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1883796488
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4065088108
Short name T8
Test name
Test status
Simulation time 8352844292 ps
CPU time 21.41 seconds
Started Jul 02 09:50:35 AM PDT 24
Finished Jul 02 09:51:00 AM PDT 24
Peak memory 217496 kb
Host smart-b168951a-3e5e-49ba-b0ba-072a14324575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065088108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4065088108
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2497339809
Short name T781
Test name
Test status
Simulation time 689116338 ps
CPU time 1.36 seconds
Started Jul 02 09:50:50 AM PDT 24
Finished Jul 02 09:50:52 AM PDT 24
Peak memory 217372 kb
Host smart-c56130ac-5cee-4044-9d83-fb0acb94d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497339809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2497339809
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.362023564
Short name T358
Test name
Test status
Simulation time 280685073 ps
CPU time 0.91 seconds
Started Jul 02 09:50:21 AM PDT 24
Finished Jul 02 09:50:30 AM PDT 24
Peak memory 207160 kb
Host smart-55d9ba60-3fd4-4dfb-b2e0-b3906a08d8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362023564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.362023564
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1323870944
Short name T278
Test name
Test status
Simulation time 20740487686 ps
CPU time 8.16 seconds
Started Jul 02 09:50:22 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 242044 kb
Host smart-75de0f14-a90f-43a7-946a-4e9a1914eb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323870944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1323870944
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2748443438
Short name T1003
Test name
Test status
Simulation time 39038320 ps
CPU time 0.72 seconds
Started Jul 02 09:52:17 AM PDT 24
Finished Jul 02 09:52:18 AM PDT 24
Peak memory 206348 kb
Host smart-2d643cb4-1e09-4883-869c-77156f7b0bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748443438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2748443438
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1159668593
Short name T253
Test name
Test status
Simulation time 2620666866 ps
CPU time 7.73 seconds
Started Jul 02 09:52:10 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 233892 kb
Host smart-f0fa88a4-6f7a-4d2f-b0d9-d8d3196da7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159668593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1159668593
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2419572862
Short name T368
Test name
Test status
Simulation time 37814139 ps
CPU time 0.82 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 207508 kb
Host smart-939ceb43-d655-4a2b-a7f7-dcddf739ce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419572862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2419572862
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.652716408
Short name T195
Test name
Test status
Simulation time 3024164974 ps
CPU time 39.33 seconds
Started Jul 02 09:52:21 AM PDT 24
Finished Jul 02 09:53:01 AM PDT 24
Peak memory 256764 kb
Host smart-aaf42b89-6ac3-444c-8f5e-0f7f586184f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652716408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.652716408
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4285412360
Short name T294
Test name
Test status
Simulation time 63927412776 ps
CPU time 314.52 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:57:24 AM PDT 24
Peak memory 250648 kb
Host smart-597e1bd3-621d-4f6b-88d5-b5265df77335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285412360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4285412360
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3549827122
Short name T925
Test name
Test status
Simulation time 3588329964 ps
CPU time 82.01 seconds
Started Jul 02 09:52:06 AM PDT 24
Finished Jul 02 09:53:30 AM PDT 24
Peak memory 252160 kb
Host smart-46487d91-bc7d-472d-9b3f-1e722ea18f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549827122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3549827122
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1765058411
Short name T731
Test name
Test status
Simulation time 268764918 ps
CPU time 6.12 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:18 AM PDT 24
Peak memory 234984 kb
Host smart-0883d0af-cc6b-4463-bb56-25e16bf0cd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765058411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1765058411
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3979963492
Short name T833
Test name
Test status
Simulation time 1095449342 ps
CPU time 8.97 seconds
Started Jul 02 09:52:05 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 233804 kb
Host smart-00fbc9d9-0001-4c6d-b224-e3c725a0a7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979963492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3979963492
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.129660628
Short name T114
Test name
Test status
Simulation time 478796135 ps
CPU time 7.51 seconds
Started Jul 02 09:52:02 AM PDT 24
Finished Jul 02 09:52:12 AM PDT 24
Peak memory 233772 kb
Host smart-9e571840-ab2f-4195-920b-d776fbfe9d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129660628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.129660628
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2091554580
Short name T769
Test name
Test status
Simulation time 11949305695 ps
CPU time 32.96 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:52:44 AM PDT 24
Peak memory 225744 kb
Host smart-4d4f9799-365c-4da7-abd2-b3b7f384db87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091554580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2091554580
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3116875551
Short name T896
Test name
Test status
Simulation time 526806315 ps
CPU time 6.29 seconds
Started Jul 02 09:52:12 AM PDT 24
Finished Jul 02 09:52:22 AM PDT 24
Peak memory 241748 kb
Host smart-9a8dba4c-b9f1-474f-a504-1e4740873861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116875551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3116875551
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1109834843
Short name T612
Test name
Test status
Simulation time 5828691057 ps
CPU time 14.13 seconds
Started Jul 02 09:52:06 AM PDT 24
Finished Jul 02 09:52:23 AM PDT 24
Peak memory 220600 kb
Host smart-ee8d84d4-25fe-4596-b782-ce466f3bd325
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1109834843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1109834843
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4066438778
Short name T361
Test name
Test status
Simulation time 2433002412 ps
CPU time 9.84 seconds
Started Jul 02 09:52:03 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 220556 kb
Host smart-c39d7baa-1aaf-4acb-82cc-e79cd8559269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066438778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4066438778
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2281568240
Short name T951
Test name
Test status
Simulation time 8630405462 ps
CPU time 8.05 seconds
Started Jul 02 09:52:19 AM PDT 24
Finished Jul 02 09:52:27 AM PDT 24
Peak memory 217464 kb
Host smart-eff40011-b2bd-4583-8dc4-cd37d55625b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281568240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2281568240
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3865449515
Short name T356
Test name
Test status
Simulation time 184832795 ps
CPU time 1.65 seconds
Started Jul 02 09:52:01 AM PDT 24
Finished Jul 02 09:52:05 AM PDT 24
Peak memory 217328 kb
Host smart-c5f081a2-5031-4b2a-bc16-cc40d3d7ed1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865449515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3865449515
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.361358324
Short name T367
Test name
Test status
Simulation time 29296232 ps
CPU time 0.77 seconds
Started Jul 02 09:52:04 AM PDT 24
Finished Jul 02 09:52:07 AM PDT 24
Peak memory 206952 kb
Host smart-7c0d0f3f-6c39-4e39-8039-6f68704fcf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361358324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.361358324
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3527888805
Short name T617
Test name
Test status
Simulation time 12752799851 ps
CPU time 12.61 seconds
Started Jul 02 09:52:04 AM PDT 24
Finished Jul 02 09:52:19 AM PDT 24
Peak memory 233888 kb
Host smart-ecb596b0-4504-401c-ba1f-614928b4dfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527888805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3527888805
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2394591412
Short name T2
Test name
Test status
Simulation time 19066489 ps
CPU time 0.74 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 206460 kb
Host smart-26e92ca7-ef87-4dd0-ab2b-0bcad413f42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394591412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2394591412
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2434235523
Short name T67
Test name
Test status
Simulation time 2701326520 ps
CPU time 13.72 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 225636 kb
Host smart-8574b710-56bd-428e-bfa3-bfa68e05710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434235523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2434235523
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.65152496
Short name T548
Test name
Test status
Simulation time 17066038 ps
CPU time 0.81 seconds
Started Jul 02 09:52:09 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 207480 kb
Host smart-dbd61850-7d92-4d4c-9220-cbcd2f43fa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65152496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.65152496
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.107562303
Short name T324
Test name
Test status
Simulation time 23282462893 ps
CPU time 153.14 seconds
Started Jul 02 09:52:03 AM PDT 24
Finished Jul 02 09:54:39 AM PDT 24
Peak memory 250400 kb
Host smart-17296546-fcea-49c5-9edf-959c3c844697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107562303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.107562303
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2195502916
Short name T244
Test name
Test status
Simulation time 15408067296 ps
CPU time 69.1 seconds
Started Jul 02 09:52:10 AM PDT 24
Finished Jul 02 09:53:22 AM PDT 24
Peak memory 251428 kb
Host smart-fd3b2fba-3c1c-4724-a846-e7cddf2cada7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195502916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2195502916
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2863586288
Short name T708
Test name
Test status
Simulation time 134794300 ps
CPU time 3.96 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 233844 kb
Host smart-ae62a23a-831b-44ab-a9c3-fe542d1c4dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863586288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2863586288
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.417428571
Short name T864
Test name
Test status
Simulation time 51673929792 ps
CPU time 118.74 seconds
Started Jul 02 09:52:14 AM PDT 24
Finished Jul 02 09:54:15 AM PDT 24
Peak memory 250312 kb
Host smart-ef2de1e6-f6da-4d6c-be66-665296588e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417428571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.417428571
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3322411682
Short name T247
Test name
Test status
Simulation time 3122198817 ps
CPU time 8.19 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:24 AM PDT 24
Peak memory 233900 kb
Host smart-2b9d78cf-270b-44f7-8966-9d0c07db88fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322411682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3322411682
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2558176000
Short name T817
Test name
Test status
Simulation time 5023213523 ps
CPU time 25.61 seconds
Started Jul 02 09:52:22 AM PDT 24
Finished Jul 02 09:52:49 AM PDT 24
Peak memory 241792 kb
Host smart-1a908f13-11af-44b2-9298-cee8e11623cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558176000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2558176000
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4082485671
Short name T551
Test name
Test status
Simulation time 97344442 ps
CPU time 2.09 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 224300 kb
Host smart-11a28695-4b30-41b9-ab34-6a11fed9bfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082485671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4082485671
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2687761271
Short name T852
Test name
Test status
Simulation time 403173541 ps
CPU time 3.65 seconds
Started Jul 02 09:52:22 AM PDT 24
Finished Jul 02 09:52:26 AM PDT 24
Peak memory 225548 kb
Host smart-4094fff1-9521-406a-81df-f75283657777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687761271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2687761271
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.544882778
Short name T880
Test name
Test status
Simulation time 7608857085 ps
CPU time 17.12 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:52:27 AM PDT 24
Peak memory 221468 kb
Host smart-3c0aab5e-da84-447d-94fe-8f6bb04e589c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=544882778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.544882778
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1504786605
Short name T1012
Test name
Test status
Simulation time 48072292898 ps
CPU time 188.57 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 266828 kb
Host smart-8b2c66ab-ecc3-4cb8-84ef-6736e506ac5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504786605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1504786605
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.279221637
Short name T615
Test name
Test status
Simulation time 1745235320 ps
CPU time 23.59 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:39 AM PDT 24
Peak memory 217424 kb
Host smart-3b5ca030-1dfd-4cee-83e1-4c2cfb1a0a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279221637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.279221637
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.263473963
Short name T687
Test name
Test status
Simulation time 7945487301 ps
CPU time 14.38 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 217468 kb
Host smart-0eb42746-031e-4457-878c-6223d0787fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263473963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.263473963
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1169103008
Short name T394
Test name
Test status
Simulation time 36720866 ps
CPU time 1.47 seconds
Started Jul 02 09:52:06 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 217392 kb
Host smart-2c5c31fb-40d0-40ee-9333-2e862eec6a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169103008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1169103008
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.657392281
Short name T337
Test name
Test status
Simulation time 95535846 ps
CPU time 0.94 seconds
Started Jul 02 09:52:10 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 208008 kb
Host smart-4b9a0af2-f9eb-43c7-a99a-3947157be688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657392281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.657392281
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1079106496
Short name T581
Test name
Test status
Simulation time 105412895 ps
CPU time 3.8 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:20 AM PDT 24
Peak memory 233820 kb
Host smart-338dbf1f-1914-4cda-a9b9-6071582f43e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079106496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1079106496
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1795326725
Short name T387
Test name
Test status
Simulation time 12826105 ps
CPU time 0.73 seconds
Started Jul 02 09:52:25 AM PDT 24
Finished Jul 02 09:52:28 AM PDT 24
Peak memory 206736 kb
Host smart-31c4ecda-54e7-476b-ae86-11626d028d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795326725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1795326725
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1076354232
Short name T112
Test name
Test status
Simulation time 31494841 ps
CPU time 2.35 seconds
Started Jul 02 09:52:06 AM PDT 24
Finished Jul 02 09:52:10 AM PDT 24
Peak memory 233528 kb
Host smart-718bd859-8aae-4d05-b3e8-d3343efd7a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076354232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1076354232
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2304166749
Short name T609
Test name
Test status
Simulation time 37094384 ps
CPU time 0.76 seconds
Started Jul 02 09:52:11 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 207888 kb
Host smart-3c7725cf-865a-4b78-9b95-23b85264db57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304166749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2304166749
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4203871485
Short name T842
Test name
Test status
Simulation time 363968423119 ps
CPU time 328.46 seconds
Started Jul 02 09:52:24 AM PDT 24
Finished Jul 02 09:57:53 AM PDT 24
Peak memory 266936 kb
Host smart-7aae2310-c336-4382-94d9-aa2ef55d6195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203871485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4203871485
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4130804402
Short name T774
Test name
Test status
Simulation time 127604477789 ps
CPU time 140.74 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:54:37 AM PDT 24
Peak memory 250652 kb
Host smart-5eaa19cb-730f-4983-839a-b1e12b8eec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130804402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4130804402
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1581417804
Short name T35
Test name
Test status
Simulation time 75485214758 ps
CPU time 362.55 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:58:14 AM PDT 24
Peak memory 255548 kb
Host smart-93a84ef5-4c1e-4758-b507-39907ccca1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581417804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1581417804
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1782146353
Short name T97
Test name
Test status
Simulation time 676924877 ps
CPU time 14.62 seconds
Started Jul 02 09:52:12 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 233804 kb
Host smart-376b80a9-d08e-4381-9c62-6818d392903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782146353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1782146353
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1732753166
Short name T544
Test name
Test status
Simulation time 1487138702 ps
CPU time 25 seconds
Started Jul 02 09:52:11 AM PDT 24
Finished Jul 02 09:52:39 AM PDT 24
Peak memory 250188 kb
Host smart-23ddeb62-a8b7-43f1-8510-659b7167ed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732753166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1732753166
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.151803269
Short name T719
Test name
Test status
Simulation time 3173667853 ps
CPU time 11.58 seconds
Started Jul 02 09:52:10 AM PDT 24
Finished Jul 02 09:52:25 AM PDT 24
Peak memory 233868 kb
Host smart-81b81785-7fac-4a9a-a8de-763124d713bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151803269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.151803269
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1996005750
Short name T520
Test name
Test status
Simulation time 934389510 ps
CPU time 10.38 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:26 AM PDT 24
Peak memory 225552 kb
Host smart-7d3f9c7f-7611-4dd2-b397-2d8e4408e35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996005750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1996005750
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1685847037
Short name T303
Test name
Test status
Simulation time 5453720091 ps
CPU time 5.56 seconds
Started Jul 02 09:52:11 AM PDT 24
Finished Jul 02 09:52:20 AM PDT 24
Peak memory 233908 kb
Host smart-57dcdb73-8aa0-4e40-b618-76ca2bb37ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685847037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1685847037
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2172753549
Short name T1016
Test name
Test status
Simulation time 4657840873 ps
CPU time 14.9 seconds
Started Jul 02 09:52:10 AM PDT 24
Finished Jul 02 09:52:28 AM PDT 24
Peak memory 234088 kb
Host smart-0fba6fdb-575b-4103-9cc7-ceee6a6604c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172753549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2172753549
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.252346844
Short name T881
Test name
Test status
Simulation time 276452250 ps
CPU time 6.08 seconds
Started Jul 02 09:52:12 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 223992 kb
Host smart-2564e7be-7db3-48c6-9897-63932a42bb7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=252346844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.252346844
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3442344988
Short name T556
Test name
Test status
Simulation time 893006721 ps
CPU time 13.56 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 217592 kb
Host smart-66d927a8-ad01-4cda-9b34-16ee5757795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442344988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3442344988
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.157679784
Short name T383
Test name
Test status
Simulation time 299982168 ps
CPU time 2.2 seconds
Started Jul 02 09:52:07 AM PDT 24
Finished Jul 02 09:52:11 AM PDT 24
Peak memory 217444 kb
Host smart-5fa6f03f-ec6f-4a5b-bb8d-aa8068b97a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157679784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.157679784
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3349375062
Short name T603
Test name
Test status
Simulation time 65216866 ps
CPU time 1.74 seconds
Started Jul 02 09:52:10 AM PDT 24
Finished Jul 02 09:52:15 AM PDT 24
Peak memory 217576 kb
Host smart-54062496-44b8-4b1b-90a5-d9b6ca30ed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349375062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3349375062
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2295157469
Short name T592
Test name
Test status
Simulation time 10290378 ps
CPU time 0.77 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:52:12 AM PDT 24
Peak memory 206588 kb
Host smart-b2df8596-4c78-4d01-9da6-e110eea629c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295157469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2295157469
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.22775718
Short name T132
Test name
Test status
Simulation time 194164617 ps
CPU time 3.33 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 233756 kb
Host smart-1651a6e7-ea2c-4f10-b7bf-731cfe476ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22775718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.22775718
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2331686285
Short name T1017
Test name
Test status
Simulation time 48593892 ps
CPU time 0.7 seconds
Started Jul 02 09:52:28 AM PDT 24
Finished Jul 02 09:52:32 AM PDT 24
Peak memory 206420 kb
Host smart-80e4283c-38f9-49af-8e21-aa506bbd1afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331686285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2331686285
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4032306229
Short name T599
Test name
Test status
Simulation time 7321105597 ps
CPU time 4.86 seconds
Started Jul 02 09:52:17 AM PDT 24
Finished Jul 02 09:52:23 AM PDT 24
Peak memory 233904 kb
Host smart-fc491465-cd7b-43cd-89d7-aed3c1f93acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032306229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4032306229
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.20688426
Short name T682
Test name
Test status
Simulation time 16061002 ps
CPU time 0.76 seconds
Started Jul 02 09:52:08 AM PDT 24
Finished Jul 02 09:52:12 AM PDT 24
Peak memory 206816 kb
Host smart-8dc53243-8dae-4b0b-a62f-8c4ad8f0bd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20688426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.20688426
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.74965490
Short name T258
Test name
Test status
Simulation time 22586705073 ps
CPU time 283.04 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:56:59 AM PDT 24
Peak memory 257988 kb
Host smart-ac64348f-98fb-4269-8da7-de5361227eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74965490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.74965490
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3721327842
Short name T28
Test name
Test status
Simulation time 6932224783 ps
CPU time 33.67 seconds
Started Jul 02 09:52:22 AM PDT 24
Finished Jul 02 09:52:56 AM PDT 24
Peak memory 218880 kb
Host smart-cf7adb47-a5c2-469c-9d12-c353edc385f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721327842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3721327842
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1789044577
Short name T465
Test name
Test status
Simulation time 5571319243 ps
CPU time 23.43 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:56 AM PDT 24
Peak memory 234504 kb
Host smart-c9784058-486e-4bb0-9cfe-ba089dcfc8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789044577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1789044577
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2071395490
Short name T975
Test name
Test status
Simulation time 38535880771 ps
CPU time 240.44 seconds
Started Jul 02 09:52:20 AM PDT 24
Finished Jul 02 09:56:21 AM PDT 24
Peak memory 250312 kb
Host smart-0471f27c-ec15-470a-b023-dccb422713e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071395490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2071395490
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.719144681
Short name T667
Test name
Test status
Simulation time 9605572084 ps
CPU time 22.57 seconds
Started Jul 02 09:52:22 AM PDT 24
Finished Jul 02 09:52:46 AM PDT 24
Peak memory 233936 kb
Host smart-71bf3088-de7d-44bc-aa68-5c1fd08a6e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719144681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.719144681
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.691661448
Short name T793
Test name
Test status
Simulation time 174371685 ps
CPU time 3.77 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:20 AM PDT 24
Peak memory 225472 kb
Host smart-2b5cd45d-484d-4ed6-9449-03cdb6260009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691661448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.691661448
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3869628344
Short name T268
Test name
Test status
Simulation time 5444530040 ps
CPU time 12.3 seconds
Started Jul 02 09:52:16 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 242012 kb
Host smart-12cb2407-0b82-4915-879c-7a3acc9651ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869628344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3869628344
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.694507941
Short name T7
Test name
Test status
Simulation time 738279087 ps
CPU time 4.98 seconds
Started Jul 02 09:52:14 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 233780 kb
Host smart-cc6ebfdb-75d4-4ccf-a77c-ee6463109e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694507941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.694507941
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4002329105
Short name T1033
Test name
Test status
Simulation time 89836279 ps
CPU time 3.77 seconds
Started Jul 02 09:52:14 AM PDT 24
Finished Jul 02 09:52:20 AM PDT 24
Peak memory 221788 kb
Host smart-1f52c968-30cd-4632-aca0-8f73b5f82da6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4002329105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4002329105
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3598046890
Short name T176
Test name
Test status
Simulation time 50272925891 ps
CPU time 128.73 seconds
Started Jul 02 09:52:20 AM PDT 24
Finished Jul 02 09:54:30 AM PDT 24
Peak memory 265440 kb
Host smart-7c45aeb6-5912-4c2b-aec9-d01b61572ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598046890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3598046890
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2037480213
Short name T772
Test name
Test status
Simulation time 23106938705 ps
CPU time 52.06 seconds
Started Jul 02 09:52:15 AM PDT 24
Finished Jul 02 09:53:09 AM PDT 24
Peak memory 217496 kb
Host smart-aaadcd03-7905-4c0d-bec1-db862ee2fd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037480213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2037480213
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.568167976
Short name T741
Test name
Test status
Simulation time 5423316095 ps
CPU time 9.19 seconds
Started Jul 02 09:52:11 AM PDT 24
Finished Jul 02 09:52:23 AM PDT 24
Peak memory 217496 kb
Host smart-d596a872-92f0-4f4d-bda5-fef5a3851e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568167976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.568167976
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.721056124
Short name T456
Test name
Test status
Simulation time 107992325 ps
CPU time 1.1 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 208172 kb
Host smart-385dfa3a-e8bb-4394-b83e-a7ea5f2cec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721056124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.721056124
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.634317030
Short name T908
Test name
Test status
Simulation time 188834789 ps
CPU time 0.94 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 207200 kb
Host smart-c554187e-3b3c-4a34-b3a8-7253765af93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634317030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.634317030
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3576980626
Short name T804
Test name
Test status
Simulation time 154320750 ps
CPU time 2.48 seconds
Started Jul 02 09:52:18 AM PDT 24
Finished Jul 02 09:52:21 AM PDT 24
Peak memory 225296 kb
Host smart-c793b948-3ce1-4e09-9fb0-febdeba9cc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576980626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3576980626
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2178629687
Short name T440
Test name
Test status
Simulation time 88193086 ps
CPU time 0.71 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 205800 kb
Host smart-6d42967a-f84d-4af3-830d-79df0ffb2f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178629687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2178629687
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1123729758
Short name T710
Test name
Test status
Simulation time 73637616 ps
CPU time 2.56 seconds
Started Jul 02 09:52:14 AM PDT 24
Finished Jul 02 09:52:19 AM PDT 24
Peak memory 233780 kb
Host smart-ba874241-67f4-4761-902a-9efe05e96999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123729758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1123729758
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.423330283
Short name T869
Test name
Test status
Simulation time 35110120 ps
CPU time 0.71 seconds
Started Jul 02 09:52:28 AM PDT 24
Finished Jul 02 09:52:32 AM PDT 24
Peak memory 206336 kb
Host smart-9d47deec-40f6-4a26-b83e-452cc33a18af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423330283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.423330283
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1242128720
Short name T296
Test name
Test status
Simulation time 16000685938 ps
CPU time 176.46 seconds
Started Jul 02 09:52:23 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 267928 kb
Host smart-cc85b3b0-6d78-406a-9f12-46bbdddc8381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242128720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1242128720
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4006355676
Short name T768
Test name
Test status
Simulation time 3502304634 ps
CPU time 67.76 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:53:37 AM PDT 24
Peak memory 252048 kb
Host smart-05159414-063e-406f-97f7-bc8ad52e14c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006355676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4006355676
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3160726500
Short name T206
Test name
Test status
Simulation time 22354175489 ps
CPU time 120.46 seconds
Started Jul 02 09:52:24 AM PDT 24
Finished Jul 02 09:54:25 AM PDT 24
Peak memory 258160 kb
Host smart-724a9f39-a3a3-48e9-b13e-78e01eaa40b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160726500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3160726500
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1628278545
Short name T825
Test name
Test status
Simulation time 670154627 ps
CPU time 12.05 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:52:40 AM PDT 24
Peak memory 225584 kb
Host smart-12f60a90-a0e2-4d8b-8411-3d80427845ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628278545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1628278545
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.872328956
Short name T215
Test name
Test status
Simulation time 6180456898 ps
CPU time 81.09 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:53:49 AM PDT 24
Peak memory 255392 kb
Host smart-61101fca-3cf5-46d5-9cdf-4dea408fa4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872328956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.872328956
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.511143240
Short name T560
Test name
Test status
Simulation time 264577616 ps
CPU time 3.04 seconds
Started Jul 02 09:52:23 AM PDT 24
Finished Jul 02 09:52:26 AM PDT 24
Peak memory 225532 kb
Host smart-22632624-f61d-4840-b262-bfc5241b60c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511143240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.511143240
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1866377861
Short name T586
Test name
Test status
Simulation time 290669432 ps
CPU time 10.6 seconds
Started Jul 02 09:52:13 AM PDT 24
Finished Jul 02 09:52:27 AM PDT 24
Peak memory 241740 kb
Host smart-973cb6d4-189a-4338-8e92-02fe8e317f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866377861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1866377861
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.69199873
Short name T954
Test name
Test status
Simulation time 5663135323 ps
CPU time 5.24 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 225692 kb
Host smart-a5ac5b86-840c-492f-9c84-4d7ccf9c7b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69199873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.69199873
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1227494648
Short name T644
Test name
Test status
Simulation time 36398483 ps
CPU time 2.29 seconds
Started Jul 02 09:52:11 AM PDT 24
Finished Jul 02 09:52:17 AM PDT 24
Peak memory 233524 kb
Host smart-70d5e7d3-8637-4f8d-8f34-a6714bf60f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227494648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1227494648
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1057309373
Short name T1002
Test name
Test status
Simulation time 460279833 ps
CPU time 6.64 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:37 AM PDT 24
Peak memory 223032 kb
Host smart-9ca3cf8b-ffc8-425b-b200-bd3eefd2f6e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1057309373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1057309373
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.311910051
Short name T900
Test name
Test status
Simulation time 73912643 ps
CPU time 0.94 seconds
Started Jul 02 09:52:28 AM PDT 24
Finished Jul 02 09:52:32 AM PDT 24
Peak memory 208320 kb
Host smart-cb95907a-f822-4b89-b1c1-3e05dc09c49a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311910051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.311910051
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3577021626
Short name T326
Test name
Test status
Simulation time 14455367416 ps
CPU time 28.42 seconds
Started Jul 02 09:52:23 AM PDT 24
Finished Jul 02 09:52:52 AM PDT 24
Peak memory 217500 kb
Host smart-eeb56aed-f5c4-426e-aa53-ee20a37a72fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577021626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3577021626
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1628796646
Short name T744
Test name
Test status
Simulation time 108058119 ps
CPU time 1.22 seconds
Started Jul 02 09:52:20 AM PDT 24
Finished Jul 02 09:52:22 AM PDT 24
Peak memory 208780 kb
Host smart-d00080ee-c18a-4b54-a772-3cad7725e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628796646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1628796646
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.688049593
Short name T325
Test name
Test status
Simulation time 198377161 ps
CPU time 1.28 seconds
Started Jul 02 09:52:18 AM PDT 24
Finished Jul 02 09:52:20 AM PDT 24
Peak memory 217336 kb
Host smart-1e3f649e-f729-44dd-9e0f-d18fac8dd5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688049593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.688049593
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4203264215
Short name T83
Test name
Test status
Simulation time 51128823 ps
CPU time 0.84 seconds
Started Jul 02 09:52:17 AM PDT 24
Finished Jul 02 09:52:19 AM PDT 24
Peak memory 206984 kb
Host smart-a053fd55-9bc8-457e-a39e-6829003b1aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203264215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4203264215
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3636040844
Short name T571
Test name
Test status
Simulation time 195308333 ps
CPU time 2.35 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:52:31 AM PDT 24
Peak memory 225232 kb
Host smart-9b7439e3-cd80-418e-a044-d57c0338a089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636040844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3636040844
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.527231557
Short name T343
Test name
Test status
Simulation time 10989161 ps
CPU time 0.77 seconds
Started Jul 02 09:52:31 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 206764 kb
Host smart-e911acf0-adba-4e21-b824-67a9c9838bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527231557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.527231557
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3178291344
Short name T475
Test name
Test status
Simulation time 548799460 ps
CPU time 8.3 seconds
Started Jul 02 09:52:17 AM PDT 24
Finished Jul 02 09:52:26 AM PDT 24
Peak memory 233624 kb
Host smart-aabbea21-5f34-4406-a422-bac8b5c05a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178291344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3178291344
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4194823368
Short name T705
Test name
Test status
Simulation time 56857760 ps
CPU time 0.83 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 206480 kb
Host smart-972109a1-d5f3-4d6f-aeab-5056cea83c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194823368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4194823368
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.71364704
Short name T497
Test name
Test status
Simulation time 3973786482 ps
CPU time 10.34 seconds
Started Jul 02 09:52:25 AM PDT 24
Finished Jul 02 09:52:38 AM PDT 24
Peak memory 238040 kb
Host smart-653aea09-0844-4c1d-99b4-e93c4e0aea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71364704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.71364704
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.634484885
Short name T332
Test name
Test status
Simulation time 3513396309 ps
CPU time 20.4 seconds
Started Jul 02 09:52:35 AM PDT 24
Finished Jul 02 09:52:56 AM PDT 24
Peak memory 225832 kb
Host smart-76052b51-f346-483c-8a0a-55d4637b4af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634484885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.634484885
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3078620666
Short name T291
Test name
Test status
Simulation time 74447658422 ps
CPU time 136.06 seconds
Started Jul 02 09:52:30 AM PDT 24
Finished Jul 02 09:54:49 AM PDT 24
Peak memory 262412 kb
Host smart-c4f2e7a2-7983-421b-b36c-dd3ae209bec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078620666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3078620666
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3156808941
Short name T369
Test name
Test status
Simulation time 1626507966 ps
CPU time 23.78 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:53 AM PDT 24
Peak memory 233752 kb
Host smart-ee04ca39-9f85-49ba-a210-8ee31c0defcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156808941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3156808941
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.990418684
Short name T628
Test name
Test status
Simulation time 22736904801 ps
CPU time 76.29 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:53:51 AM PDT 24
Peak memory 238276 kb
Host smart-69f51540-c646-4241-9801-38690ca92dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990418684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.990418684
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3048742727
Short name T966
Test name
Test status
Simulation time 147661315 ps
CPU time 5.08 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:35 AM PDT 24
Peak memory 233800 kb
Host smart-589d630b-dd20-4206-8538-95c258ef350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048742727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3048742727
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3158369951
Short name T499
Test name
Test status
Simulation time 31650435891 ps
CPU time 23.21 seconds
Started Jul 02 09:52:22 AM PDT 24
Finished Jul 02 09:52:45 AM PDT 24
Peak memory 225620 kb
Host smart-3a0a50f1-6117-438b-876b-a3e123193274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158369951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3158369951
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2926725866
Short name T284
Test name
Test status
Simulation time 5716188384 ps
CPU time 3.69 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:35 AM PDT 24
Peak memory 225664 kb
Host smart-ec1af503-aaee-434b-ab9a-ad249dbb7a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926725866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2926725866
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1017067533
Short name T1013
Test name
Test status
Simulation time 1527719881 ps
CPU time 4.14 seconds
Started Jul 02 09:52:24 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 233708 kb
Host smart-c0bc9dd2-b3ea-4516-8f6e-d127b54acad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017067533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1017067533
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3812821078
Short name T321
Test name
Test status
Simulation time 2502706044 ps
CPU time 32.06 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:53:04 AM PDT 24
Peak memory 217524 kb
Host smart-2e6b9b6e-10d6-4c96-83f5-46c324e7dc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812821078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3812821078
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1959681959
Short name T346
Test name
Test status
Simulation time 9121010095 ps
CPU time 10.29 seconds
Started Jul 02 09:52:36 AM PDT 24
Finished Jul 02 09:52:48 AM PDT 24
Peak memory 217508 kb
Host smart-3db3be49-d01b-44c4-8a59-a3f7c94ff4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959681959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1959681959
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3136456243
Short name T611
Test name
Test status
Simulation time 80324181 ps
CPU time 0.92 seconds
Started Jul 02 09:52:30 AM PDT 24
Finished Jul 02 09:52:33 AM PDT 24
Peak memory 207472 kb
Host smart-c94501e3-95ca-4cc2-9a0b-7f336016dc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136456243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3136456243
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3731941825
Short name T463
Test name
Test status
Simulation time 17319198 ps
CPU time 0.75 seconds
Started Jul 02 09:52:28 AM PDT 24
Finished Jul 02 09:52:31 AM PDT 24
Peak memory 206932 kb
Host smart-50428c77-83bb-4765-bd97-8c5162000ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731941825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3731941825
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.519262661
Short name T528
Test name
Test status
Simulation time 11242844472 ps
CPU time 10.74 seconds
Started Jul 02 09:52:23 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 233896 kb
Host smart-f0a5d5c9-b3ae-4b2e-bf04-033b2f44796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519262661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.519262661
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.407192643
Short name T725
Test name
Test status
Simulation time 15230517 ps
CPU time 0.72 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:52:35 AM PDT 24
Peak memory 205836 kb
Host smart-fa01d077-a3d9-4cc6-acdd-a7787cd132f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407192643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.407192643
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2886631330
Short name T803
Test name
Test status
Simulation time 1356006126 ps
CPU time 7.26 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:52:41 AM PDT 24
Peak memory 225624 kb
Host smart-21bbb8d2-4f17-465b-9f3f-b395d072542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886631330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2886631330
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1392834271
Short name T845
Test name
Test status
Simulation time 22553159 ps
CPU time 0.82 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:31 AM PDT 24
Peak memory 207532 kb
Host smart-5536118a-1009-4d29-b64c-c7c95360b566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392834271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1392834271
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.95899303
Short name T853
Test name
Test status
Simulation time 108036148137 ps
CPU time 92.26 seconds
Started Jul 02 09:52:36 AM PDT 24
Finished Jul 02 09:54:10 AM PDT 24
Peak memory 273836 kb
Host smart-f0729541-411d-43fc-82dd-f42f5001b960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95899303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.95899303
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1115478283
Short name T453
Test name
Test status
Simulation time 108550610108 ps
CPU time 263.05 seconds
Started Jul 02 09:52:24 AM PDT 24
Finished Jul 02 09:56:48 AM PDT 24
Peak memory 253004 kb
Host smart-3a084caf-7e26-4436-8e72-e231397f5d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115478283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1115478283
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.307910614
Short name T262
Test name
Test status
Simulation time 208894156339 ps
CPU time 501.05 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 10:00:50 AM PDT 24
Peak memory 268632 kb
Host smart-d215344b-d73c-4bc1-bb85-1068f73339a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307910614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.307910614
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2433027385
Short name T950
Test name
Test status
Simulation time 4233180801 ps
CPU time 23.29 seconds
Started Jul 02 09:52:30 AM PDT 24
Finished Jul 02 09:52:56 AM PDT 24
Peak memory 250288 kb
Host smart-87f57b70-2128-4a02-bd93-0b8a2144f1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433027385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2433027385
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4102599252
Short name T427
Test name
Test status
Simulation time 38857989 ps
CPU time 0.76 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:32 AM PDT 24
Peak memory 216896 kb
Host smart-fb08af2c-405b-4c87-b950-9e36b59a721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102599252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4102599252
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.367467637
Short name T359
Test name
Test status
Simulation time 368749527 ps
CPU time 2.13 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:31 AM PDT 24
Peak memory 224132 kb
Host smart-990458ae-4619-492d-8b61-5f730d7641dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367467637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.367467637
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.564970048
Short name T234
Test name
Test status
Simulation time 781069404 ps
CPU time 11.15 seconds
Started Jul 02 09:52:30 AM PDT 24
Finished Jul 02 09:52:43 AM PDT 24
Peak memory 225612 kb
Host smart-519faa1a-ff8b-4425-b3e7-690bff1f6c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564970048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.564970048
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3368646748
Short name T208
Test name
Test status
Simulation time 3111113853 ps
CPU time 8.57 seconds
Started Jul 02 09:52:32 AM PDT 24
Finished Jul 02 09:52:42 AM PDT 24
Peak memory 233832 kb
Host smart-e901a8ac-df88-4e3a-b3ba-a6a3ffbdfd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368646748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3368646748
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2578764650
Short name T439
Test name
Test status
Simulation time 5148715869 ps
CPU time 11.5 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:52:46 AM PDT 24
Peak memory 233900 kb
Host smart-c984a8d7-e672-4941-8d94-9e0f0bf7c50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578764650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2578764650
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4189754667
Short name T914
Test name
Test status
Simulation time 738891167 ps
CPU time 4.64 seconds
Started Jul 02 09:52:42 AM PDT 24
Finished Jul 02 09:52:47 AM PDT 24
Peak memory 221608 kb
Host smart-5db854f2-f0c7-4989-8cab-b4b75a28c089
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4189754667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4189754667
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1288351573
Short name T395
Test name
Test status
Simulation time 173207118 ps
CPU time 1.02 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:33 AM PDT 24
Peak memory 207968 kb
Host smart-e00fbcb4-4a41-420c-bb4d-cf0af71c4b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288351573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1288351573
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.94073676
Short name T879
Test name
Test status
Simulation time 23411190 ps
CPU time 0.79 seconds
Started Jul 02 09:52:25 AM PDT 24
Finished Jul 02 09:52:28 AM PDT 24
Peak memory 206636 kb
Host smart-b539dc56-d30c-411d-b3bd-6f64e457ba09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94073676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.94073676
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3735931893
Short name T623
Test name
Test status
Simulation time 358021507 ps
CPU time 1.61 seconds
Started Jul 02 09:52:22 AM PDT 24
Finished Jul 02 09:52:25 AM PDT 24
Peak memory 208980 kb
Host smart-e2051b4c-0972-456b-9ca9-9c6f0922ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735931893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3735931893
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1819517862
Short name T147
Test name
Test status
Simulation time 98985706 ps
CPU time 3.38 seconds
Started Jul 02 09:52:24 AM PDT 24
Finished Jul 02 09:52:28 AM PDT 24
Peak memory 217324 kb
Host smart-21397459-242b-4530-a482-dfb757748fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819517862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1819517862
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2138790851
Short name T922
Test name
Test status
Simulation time 62361994 ps
CPU time 0.87 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:33 AM PDT 24
Peak memory 208004 kb
Host smart-27087416-c1dc-4438-9227-d8025e768d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138790851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2138790851
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2574489875
Short name T1023
Test name
Test status
Simulation time 406819561 ps
CPU time 7.8 seconds
Started Jul 02 09:52:26 AM PDT 24
Finished Jul 02 09:52:37 AM PDT 24
Peak memory 225488 kb
Host smart-7eca56e4-4974-4285-82b0-46e7adde0f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574489875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2574489875
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1474721712
Short name T791
Test name
Test status
Simulation time 14841265 ps
CPU time 0.71 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:33 AM PDT 24
Peak memory 206728 kb
Host smart-1d11a1f3-a47a-4801-b396-35744e16b56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474721712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1474721712
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1919574740
Short name T800
Test name
Test status
Simulation time 118805599 ps
CPU time 3.35 seconds
Started Jul 02 09:52:37 AM PDT 24
Finished Jul 02 09:52:41 AM PDT 24
Peak memory 233776 kb
Host smart-0795ebd5-43e5-4f05-b7ce-096dd19a7c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919574740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1919574740
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2212341117
Short name T389
Test name
Test status
Simulation time 33069995 ps
CPU time 0.77 seconds
Started Jul 02 09:52:42 AM PDT 24
Finished Jul 02 09:52:43 AM PDT 24
Peak memory 207468 kb
Host smart-df4c4f3a-512a-416a-9935-e86244a33f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212341117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2212341117
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.227275770
Short name T295
Test name
Test status
Simulation time 7565986271 ps
CPU time 71.51 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:53:40 AM PDT 24
Peak memory 251908 kb
Host smart-5e7066c9-cf7c-481d-8570-4019cbdf536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227275770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.227275770
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.369959022
Short name T54
Test name
Test status
Simulation time 105714642535 ps
CPU time 211 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:56:00 AM PDT 24
Peak memory 250240 kb
Host smart-00dcbe5a-c48e-45a6-b761-a802b8ac33f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369959022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.369959022
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2091171305
Short name T328
Test name
Test status
Simulation time 1158225168 ps
CPU time 10.61 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:42 AM PDT 24
Peak memory 218420 kb
Host smart-0493e23b-081d-4cf7-a6d5-58faee365559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091171305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2091171305
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2864683877
Short name T502
Test name
Test status
Simulation time 1321474471 ps
CPU time 4.71 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:37 AM PDT 24
Peak memory 225548 kb
Host smart-ba16f413-e8c9-4f1f-8b20-2d864613f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864683877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2864683877
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.4048865858
Short name T179
Test name
Test status
Simulation time 431210422 ps
CPU time 8.27 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:52:43 AM PDT 24
Peak memory 225564 kb
Host smart-a322a188-fb0f-490d-9bdb-43f2fadb7ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048865858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.4048865858
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1959054835
Short name T348
Test name
Test status
Simulation time 96133725 ps
CPU time 2.16 seconds
Started Jul 02 09:52:32 AM PDT 24
Finished Jul 02 09:52:36 AM PDT 24
Peak memory 224248 kb
Host smart-1a983717-c638-4d31-a50c-b81f610d411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959054835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1959054835
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1420425459
Short name T714
Test name
Test status
Simulation time 9796002024 ps
CPU time 18.77 seconds
Started Jul 02 09:52:31 AM PDT 24
Finished Jul 02 09:52:52 AM PDT 24
Peak memory 233876 kb
Host smart-7c186a38-2ebb-48e7-b525-8df44dd52427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420425459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1420425459
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3438695611
Short name T801
Test name
Test status
Simulation time 69575649 ps
CPU time 2.09 seconds
Started Jul 02 09:52:30 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 225496 kb
Host smart-a911f192-5b5a-434d-8835-76a57369b460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438695611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3438695611
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2191910532
Short name T283
Test name
Test status
Simulation time 3309438472 ps
CPU time 8.99 seconds
Started Jul 02 09:52:25 AM PDT 24
Finished Jul 02 09:52:36 AM PDT 24
Peak memory 238088 kb
Host smart-e4dd2e34-d92a-424d-b62a-604ba516e9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191910532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2191910532
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.836711012
Short name T758
Test name
Test status
Simulation time 786946365 ps
CPU time 8.24 seconds
Started Jul 02 09:52:36 AM PDT 24
Finished Jul 02 09:52:45 AM PDT 24
Peak memory 222828 kb
Host smart-5ae2455d-d0e5-48dc-beef-f9a319f5b33c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=836711012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.836711012
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.257200713
Short name T916
Test name
Test status
Simulation time 4672318660 ps
CPU time 4.71 seconds
Started Jul 02 09:52:32 AM PDT 24
Finished Jul 02 09:52:38 AM PDT 24
Peak memory 217548 kb
Host smart-5d5d52bb-74b2-417c-9cd0-c200878ef1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257200713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.257200713
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.956351751
Short name T363
Test name
Test status
Simulation time 14002365321 ps
CPU time 13.32 seconds
Started Jul 02 09:52:32 AM PDT 24
Finished Jul 02 09:52:47 AM PDT 24
Peak memory 217496 kb
Host smart-1cac4031-7f6d-40ee-935c-4d765344fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956351751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.956351751
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.280726326
Short name T780
Test name
Test status
Simulation time 1546462288 ps
CPU time 3.3 seconds
Started Jul 02 09:52:28 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 217404 kb
Host smart-30a3002c-b7dc-40fb-8c8b-c5ee0b0599c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280726326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.280726326
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.641961159
Short name T344
Test name
Test status
Simulation time 20929009 ps
CPU time 0.7 seconds
Started Jul 02 09:52:30 AM PDT 24
Finished Jul 02 09:52:33 AM PDT 24
Peak memory 206948 kb
Host smart-ae4d721d-aad5-43b9-86a4-4593cec5bdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641961159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.641961159
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2288320302
Short name T630
Test name
Test status
Simulation time 841092081 ps
CPU time 2.73 seconds
Started Jul 02 09:52:36 AM PDT 24
Finished Jul 02 09:52:40 AM PDT 24
Peak memory 225580 kb
Host smart-97fb675f-7c25-4d89-8b19-bff2c6f706f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288320302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2288320302
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3508116988
Short name T640
Test name
Test status
Simulation time 95253225 ps
CPU time 0.75 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:33 AM PDT 24
Peak memory 205812 kb
Host smart-afc64597-0f93-4b6e-8814-97cb874faafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508116988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3508116988
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1393850939
Short name T69
Test name
Test status
Simulation time 222722746 ps
CPU time 3.74 seconds
Started Jul 02 09:52:34 AM PDT 24
Finished Jul 02 09:52:39 AM PDT 24
Peak memory 233788 kb
Host smart-d8e54bb5-bcde-47e5-9198-cad6ad3ea453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393850939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1393850939
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2172859513
Short name T764
Test name
Test status
Simulation time 18505509 ps
CPU time 0.8 seconds
Started Jul 02 09:52:46 AM PDT 24
Finished Jul 02 09:52:47 AM PDT 24
Peak memory 207500 kb
Host smart-1b94ea13-d086-4dba-a997-e81441b49521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172859513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2172859513
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4095107689
Short name T540
Test name
Test status
Simulation time 43268793982 ps
CPU time 90.11 seconds
Started Jul 02 09:52:34 AM PDT 24
Finished Jul 02 09:54:05 AM PDT 24
Peak memory 250332 kb
Host smart-2d32c63c-973d-4a84-9991-f2da231df6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095107689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4095107689
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1291079029
Short name T989
Test name
Test status
Simulation time 120706019535 ps
CPU time 368.74 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:58:41 AM PDT 24
Peak memory 274628 kb
Host smart-898c4e77-f2f4-4075-b5d8-773d17f36175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291079029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1291079029
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.564830386
Short name T594
Test name
Test status
Simulation time 6879891238 ps
CPU time 15.86 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:48 AM PDT 24
Peak memory 225796 kb
Host smart-059c1c6f-f2d5-430d-81cf-12c3809d2df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564830386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.564830386
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2372213474
Short name T42
Test name
Test status
Simulation time 1131055523 ps
CPU time 11.04 seconds
Started Jul 02 09:52:32 AM PDT 24
Finished Jul 02 09:52:45 AM PDT 24
Peak memory 241980 kb
Host smart-a59ed0d9-0cf6-40d7-b481-27b066b3c01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372213474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2372213474
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3092440063
Short name T86
Test name
Test status
Simulation time 151274115515 ps
CPU time 272.64 seconds
Started Jul 02 09:52:49 AM PDT 24
Finished Jul 02 09:57:22 AM PDT 24
Peak memory 250252 kb
Host smart-657f0bc3-26ff-49db-b522-e32d8c73e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092440063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3092440063
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.162226718
Short name T890
Test name
Test status
Simulation time 81762179 ps
CPU time 2.53 seconds
Started Jul 02 09:52:31 AM PDT 24
Finished Jul 02 09:52:36 AM PDT 24
Peak memory 228464 kb
Host smart-600b07da-8bc1-4169-9aac-8a63089276cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162226718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.162226718
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3406442327
Short name T577
Test name
Test status
Simulation time 1961050179 ps
CPU time 26.01 seconds
Started Jul 02 09:52:34 AM PDT 24
Finished Jul 02 09:53:01 AM PDT 24
Peak memory 241936 kb
Host smart-6ee07ff1-51ef-44a7-b929-6a0c3c055012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406442327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3406442327
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1790415481
Short name T785
Test name
Test status
Simulation time 8647838075 ps
CPU time 8.26 seconds
Started Jul 02 09:52:27 AM PDT 24
Finished Jul 02 09:52:38 AM PDT 24
Peak memory 233932 kb
Host smart-81101563-4199-4699-828f-3c308882ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790415481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1790415481
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.912391279
Short name T947
Test name
Test status
Simulation time 2559150011 ps
CPU time 9.26 seconds
Started Jul 02 09:52:31 AM PDT 24
Finished Jul 02 09:52:42 AM PDT 24
Peak memory 225680 kb
Host smart-90004029-9c05-43fd-9ed1-3df51ed2c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912391279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.912391279
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1091208798
Short name T156
Test name
Test status
Simulation time 2333733635 ps
CPU time 6.17 seconds
Started Jul 02 09:52:31 AM PDT 24
Finished Jul 02 09:52:39 AM PDT 24
Peak memory 223256 kb
Host smart-9cbfbf4e-57de-4f0c-b7be-401abeb0e30b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1091208798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1091208798
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1199576026
Short name T175
Test name
Test status
Simulation time 152141903 ps
CPU time 1.21 seconds
Started Jul 02 09:52:45 AM PDT 24
Finished Jul 02 09:52:46 AM PDT 24
Peak memory 208068 kb
Host smart-823ec7df-75bf-406b-91cf-ada44dfa8ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199576026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1199576026
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1068822867
Short name T700
Test name
Test status
Simulation time 3720897561 ps
CPU time 17.44 seconds
Started Jul 02 09:52:42 AM PDT 24
Finished Jul 02 09:53:00 AM PDT 24
Peak memory 217596 kb
Host smart-f73a70b0-3668-4f66-abf4-e6c6c625560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068822867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1068822867
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.959304894
Short name T402
Test name
Test status
Simulation time 83526062 ps
CPU time 1.06 seconds
Started Jul 02 09:52:31 AM PDT 24
Finished Jul 02 09:52:34 AM PDT 24
Peak memory 208076 kb
Host smart-62478422-70e7-4fd4-a978-9ff5673907cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959304894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.959304894
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3006888343
Short name T1010
Test name
Test status
Simulation time 31069589 ps
CPU time 1.12 seconds
Started Jul 02 09:52:32 AM PDT 24
Finished Jul 02 09:52:35 AM PDT 24
Peak memory 208932 kb
Host smart-9781cec8-6396-4bec-a2ba-9774530479ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006888343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3006888343
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.77127278
Short name T341
Test name
Test status
Simulation time 84517709 ps
CPU time 0.84 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:52:36 AM PDT 24
Peak memory 206936 kb
Host smart-053783c3-8e72-4d44-9e72-f787fd6d1c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77127278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.77127278
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1363583463
Short name T595
Test name
Test status
Simulation time 677924414 ps
CPU time 5.76 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:52:38 AM PDT 24
Peak memory 233712 kb
Host smart-12e3d158-f775-4e09-88db-6557e628963e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363583463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1363583463
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3740963960
Short name T637
Test name
Test status
Simulation time 24195603 ps
CPU time 0.73 seconds
Started Jul 02 09:52:48 AM PDT 24
Finished Jul 02 09:52:49 AM PDT 24
Peak memory 205784 kb
Host smart-e21dcd9d-e2f3-4374-99ea-9b6938ca94f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740963960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3740963960
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.769479945
Short name T841
Test name
Test status
Simulation time 802824078 ps
CPU time 7.73 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:52:42 AM PDT 24
Peak memory 233780 kb
Host smart-2d709225-db50-4d45-8faf-16fb1de6a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769479945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.769479945
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.119542385
Short name T732
Test name
Test status
Simulation time 58920316 ps
CPU time 0.86 seconds
Started Jul 02 09:52:45 AM PDT 24
Finished Jul 02 09:52:46 AM PDT 24
Peak memory 207536 kb
Host smart-22b7b0c8-7162-429c-bd82-885244d66975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119542385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.119542385
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2743936079
Short name T824
Test name
Test status
Simulation time 9342996094 ps
CPU time 101.5 seconds
Started Jul 02 09:52:44 AM PDT 24
Finished Jul 02 09:54:26 AM PDT 24
Peak memory 250300 kb
Host smart-2d6b7827-12c5-4ea9-bc60-0e44d1cf53e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743936079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2743936079
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1611989467
Short name T538
Test name
Test status
Simulation time 9082500379 ps
CPU time 66.96 seconds
Started Jul 02 09:52:34 AM PDT 24
Finished Jul 02 09:53:42 AM PDT 24
Peak memory 256364 kb
Host smart-d91985f4-df24-4424-bd27-ae5abbe0fc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611989467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1611989467
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.179018657
Short name T151
Test name
Test status
Simulation time 23907201297 ps
CPU time 83.57 seconds
Started Jul 02 09:52:42 AM PDT 24
Finished Jul 02 09:54:06 AM PDT 24
Peak memory 254940 kb
Host smart-28dfaff4-8cd9-44d8-8b9b-ea220fc5610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179018657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.179018657
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3601637821
Short name T191
Test name
Test status
Simulation time 18426734175 ps
CPU time 134.34 seconds
Started Jul 02 09:52:34 AM PDT 24
Finished Jul 02 09:54:50 AM PDT 24
Peak memory 257252 kb
Host smart-8e770998-c70e-4934-b9c9-c45ebf91aaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601637821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3601637821
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.474029124
Short name T868
Test name
Test status
Simulation time 16885546605 ps
CPU time 36.44 seconds
Started Jul 02 09:52:29 AM PDT 24
Finished Jul 02 09:53:08 AM PDT 24
Peak memory 233904 kb
Host smart-1dc07a9c-2b6d-47bb-82e1-71a5e46267c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474029124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.474029124
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.627408078
Short name T646
Test name
Test status
Simulation time 9016114560 ps
CPU time 25.81 seconds
Started Jul 02 09:52:42 AM PDT 24
Finished Jul 02 09:53:08 AM PDT 24
Peak memory 250060 kb
Host smart-3552fb90-752a-4d6e-89e9-cdb8fdaebd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627408078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.627408078
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1550545548
Short name T972
Test name
Test status
Simulation time 12590431933 ps
CPU time 12.63 seconds
Started Jul 02 09:52:40 AM PDT 24
Finished Jul 02 09:52:53 AM PDT 24
Peak memory 236476 kb
Host smart-a4312da1-8703-4a9b-a4ee-86917ae3a0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550545548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1550545548
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1209704219
Short name T585
Test name
Test status
Simulation time 2531499189 ps
CPU time 3.85 seconds
Started Jul 02 09:52:52 AM PDT 24
Finished Jul 02 09:52:57 AM PDT 24
Peak memory 225656 kb
Host smart-99f678e3-ed19-47d7-8649-7a1e26168e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209704219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1209704219
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1822441339
Short name T157
Test name
Test status
Simulation time 377721908 ps
CPU time 4.05 seconds
Started Jul 02 09:52:48 AM PDT 24
Finished Jul 02 09:52:53 AM PDT 24
Peak memory 224068 kb
Host smart-3352204d-ca7e-463e-8990-74d93c69443c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1822441339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1822441339
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2228371887
Short name T249
Test name
Test status
Simulation time 57029553826 ps
CPU time 284.01 seconds
Started Jul 02 09:52:46 AM PDT 24
Finished Jul 02 09:57:30 AM PDT 24
Peak memory 253300 kb
Host smart-58469101-50ce-4642-86c3-ec04f868e2a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228371887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2228371887
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1386062521
Short name T671
Test name
Test status
Simulation time 647212309 ps
CPU time 5.45 seconds
Started Jul 02 09:52:34 AM PDT 24
Finished Jul 02 09:52:41 AM PDT 24
Peak memory 217564 kb
Host smart-cf0cd1ee-21db-49a7-9285-6052c21d32d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386062521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1386062521
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3484712769
Short name T336
Test name
Test status
Simulation time 19451801787 ps
CPU time 8.21 seconds
Started Jul 02 09:52:39 AM PDT 24
Finished Jul 02 09:52:48 AM PDT 24
Peak memory 217512 kb
Host smart-45b7cff9-6dd4-47e8-915c-0f499831bdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484712769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3484712769
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3415593043
Short name T688
Test name
Test status
Simulation time 164994235 ps
CPU time 1.13 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:52:36 AM PDT 24
Peak memory 208320 kb
Host smart-ba92ddc8-622e-46f7-8bfc-99e9d48de010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415593043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3415593043
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2968328981
Short name T580
Test name
Test status
Simulation time 22819460 ps
CPU time 0.85 seconds
Started Jul 02 09:52:48 AM PDT 24
Finished Jul 02 09:52:49 AM PDT 24
Peak memory 206984 kb
Host smart-3cd8c155-5015-4ba9-83cd-518cd80837e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968328981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2968328981
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3293524466
Short name T248
Test name
Test status
Simulation time 349422233 ps
CPU time 2.86 seconds
Started Jul 02 09:52:33 AM PDT 24
Finished Jul 02 09:52:37 AM PDT 24
Peak memory 233684 kb
Host smart-eb2968c5-d0ff-430a-a56b-56a50dcabd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293524466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3293524466
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4219199954
Short name T64
Test name
Test status
Simulation time 13875660 ps
CPU time 0.71 seconds
Started Jul 02 09:50:33 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 205828 kb
Host smart-f9fce889-e53b-43ef-a2d0-4a1a30a2e48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219199954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
219199954
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1195176171
Short name T252
Test name
Test status
Simulation time 285565334 ps
CPU time 3.76 seconds
Started Jul 02 09:50:42 AM PDT 24
Finished Jul 02 09:50:47 AM PDT 24
Peak memory 233712 kb
Host smart-36d6c9cb-9ea6-49a7-adf1-6a301d40dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195176171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1195176171
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1042059016
Short name T357
Test name
Test status
Simulation time 23773077 ps
CPU time 0.75 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:50:36 AM PDT 24
Peak memory 207848 kb
Host smart-e7cfc09d-4f4a-48f4-b1ed-b23d7203e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042059016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1042059016
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.681993930
Short name T931
Test name
Test status
Simulation time 2678421055 ps
CPU time 28.19 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:56 AM PDT 24
Peak memory 242104 kb
Host smart-9529ef71-4f10-4085-8676-24f8a4a9fe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681993930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.681993930
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1605932002
Short name T286
Test name
Test status
Simulation time 18634081758 ps
CPU time 143.89 seconds
Started Jul 02 09:50:43 AM PDT 24
Finished Jul 02 09:53:08 AM PDT 24
Peak memory 270288 kb
Host smart-0d717abb-9836-4ea3-af39-ede4157aa3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605932002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1605932002
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2812865499
Short name T364
Test name
Test status
Simulation time 12493851475 ps
CPU time 117.53 seconds
Started Jul 02 09:50:21 AM PDT 24
Finished Jul 02 09:52:30 AM PDT 24
Peak memory 255744 kb
Host smart-bd6a20dd-febe-403d-8381-c6b18ef346c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812865499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2812865499
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3281057071
Short name T529
Test name
Test status
Simulation time 183688869 ps
CPU time 5.7 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 225576 kb
Host smart-ef12e117-1c78-41c4-8ed3-a5404d29c2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281057071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3281057071
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2115861625
Short name T575
Test name
Test status
Simulation time 29930094 ps
CPU time 0.77 seconds
Started Jul 02 09:50:32 AM PDT 24
Finished Jul 02 09:50:37 AM PDT 24
Peak memory 216912 kb
Host smart-52c122b5-40c5-491e-828f-1a3d8a28be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115861625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2115861625
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.206136426
Short name T274
Test name
Test status
Simulation time 3077929310 ps
CPU time 22.34 seconds
Started Jul 02 09:50:21 AM PDT 24
Finished Jul 02 09:50:51 AM PDT 24
Peak memory 225716 kb
Host smart-d912a5d0-e93e-4e4e-8aca-f15d55ac0c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206136426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.206136426
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2470764831
Short name T533
Test name
Test status
Simulation time 531789104 ps
CPU time 3.31 seconds
Started Jul 02 09:50:28 AM PDT 24
Finished Jul 02 09:50:37 AM PDT 24
Peak memory 225524 kb
Host smart-d0372d71-a1e1-4923-b9da-5c03e11ebdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470764831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2470764831
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3111764351
Short name T648
Test name
Test status
Simulation time 27715485 ps
CPU time 1.11 seconds
Started Jul 02 09:50:34 AM PDT 24
Finished Jul 02 09:50:39 AM PDT 24
Peak memory 218940 kb
Host smart-ff868193-37c4-4a36-b45e-d2c59e9cd05a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111764351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3111764351
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2757322719
Short name T270
Test name
Test status
Simulation time 7727512487 ps
CPU time 10.2 seconds
Started Jul 02 09:50:50 AM PDT 24
Finished Jul 02 09:51:01 AM PDT 24
Peak memory 233920 kb
Host smart-c10b7d20-c208-41c4-b2d8-0b7c88cb1343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757322719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2757322719
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.984323345
Short name T762
Test name
Test status
Simulation time 8212172256 ps
CPU time 9.45 seconds
Started Jul 02 09:50:38 AM PDT 24
Finished Jul 02 09:50:49 AM PDT 24
Peak memory 233884 kb
Host smart-e913a702-136d-4e5b-b434-0fdee7674d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984323345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.984323345
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4120036948
Short name T41
Test name
Test status
Simulation time 474566331 ps
CPU time 3.89 seconds
Started Jul 02 09:50:30 AM PDT 24
Finished Jul 02 09:50:39 AM PDT 24
Peak memory 223616 kb
Host smart-04e8eecf-2829-4a7d-971e-25d7b1eebf18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4120036948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4120036948
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3190907797
Short name T59
Test name
Test status
Simulation time 76977934454 ps
CPU time 198.16 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:53:50 AM PDT 24
Peak memory 255556 kb
Host smart-231a002a-16be-4722-858a-44468dddf9d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190907797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3190907797
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1063443745
Short name T990
Test name
Test status
Simulation time 7928228840 ps
CPU time 33.24 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 217476 kb
Host smart-ca2422b2-6c01-4943-a2ea-41211b69fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063443745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1063443745
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2589497478
Short name T893
Test name
Test status
Simulation time 2010682601 ps
CPU time 2.37 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:34 AM PDT 24
Peak memory 208064 kb
Host smart-b488fed9-61f7-4b20-9617-00382862781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589497478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2589497478
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.265198128
Short name T813
Test name
Test status
Simulation time 17797010 ps
CPU time 0.8 seconds
Started Jul 02 09:50:35 AM PDT 24
Finished Jul 02 09:50:39 AM PDT 24
Peak memory 207688 kb
Host smart-f304b79d-a122-4e8d-a868-0f4eb46493d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265198128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.265198128
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1652641953
Short name T498
Test name
Test status
Simulation time 84628031 ps
CPU time 0.8 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 206964 kb
Host smart-fbc056ba-de01-47ce-8fd7-6959d58e2f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652641953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1652641953
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3943072506
Short name T410
Test name
Test status
Simulation time 258726708 ps
CPU time 2.37 seconds
Started Jul 02 09:50:19 AM PDT 24
Finished Jul 02 09:50:30 AM PDT 24
Peak memory 225320 kb
Host smart-e481bab0-5c72-48c8-a8cf-da5db756fecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943072506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3943072506
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2792166266
Short name T728
Test name
Test status
Simulation time 40894394 ps
CPU time 0.71 seconds
Started Jul 02 09:50:59 AM PDT 24
Finished Jul 02 09:51:01 AM PDT 24
Peak memory 206408 kb
Host smart-097bb96b-9728-4142-ae32-050cf4b1c340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792166266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
792166266
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3368149015
Short name T983
Test name
Test status
Simulation time 392938488 ps
CPU time 3.79 seconds
Started Jul 02 09:50:39 AM PDT 24
Finished Jul 02 09:50:54 AM PDT 24
Peak memory 233752 kb
Host smart-765d6215-035d-427a-9025-db674245057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368149015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3368149015
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.913926452
Short name T1005
Test name
Test status
Simulation time 18102333 ps
CPU time 0.8 seconds
Started Jul 02 09:50:54 AM PDT 24
Finished Jul 02 09:50:56 AM PDT 24
Peak memory 207492 kb
Host smart-6979541e-50bc-4b6f-ac1e-febb2dde3817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913926452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.913926452
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2967925546
Short name T220
Test name
Test status
Simulation time 174681369280 ps
CPU time 299.64 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 266288 kb
Host smart-37d6ba4c-a13a-43d4-b4c9-cad9bdc4e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967925546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2967925546
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.687672677
Short name T40
Test name
Test status
Simulation time 1711113052 ps
CPU time 37.86 seconds
Started Jul 02 09:50:46 AM PDT 24
Finished Jul 02 09:51:24 AM PDT 24
Peak memory 250956 kb
Host smart-842a3847-e27c-4ec0-8aee-12d21c178753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687672677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.687672677
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1114747824
Short name T152
Test name
Test status
Simulation time 69655371460 ps
CPU time 131.58 seconds
Started Jul 02 09:50:46 AM PDT 24
Finished Jul 02 09:52:59 AM PDT 24
Peak memory 241172 kb
Host smart-6b070d3c-598a-4148-8447-c90db9aa65c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114747824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1114747824
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2636458711
Short name T837
Test name
Test status
Simulation time 834555901 ps
CPU time 3.94 seconds
Started Jul 02 09:50:22 AM PDT 24
Finished Jul 02 09:50:33 AM PDT 24
Peak memory 225580 kb
Host smart-a6123001-7bf0-4c27-9ef9-75239cd31973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636458711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2636458711
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3486529546
Short name T942
Test name
Test status
Simulation time 55255093 ps
CPU time 0.78 seconds
Started Jul 02 09:50:32 AM PDT 24
Finished Jul 02 09:50:37 AM PDT 24
Peak memory 216956 kb
Host smart-1c7f285c-694c-4180-bc93-f79ec92ac8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486529546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3486529546
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3267298360
Short name T87
Test name
Test status
Simulation time 134046422 ps
CPU time 2.36 seconds
Started Jul 02 09:50:34 AM PDT 24
Finished Jul 02 09:50:40 AM PDT 24
Peak memory 225520 kb
Host smart-1f9f0798-5c68-41bd-940e-dc0ec1e46b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267298360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3267298360
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3359195427
Short name T227
Test name
Test status
Simulation time 20904843517 ps
CPU time 40.83 seconds
Started Jul 02 09:50:44 AM PDT 24
Finished Jul 02 09:51:26 AM PDT 24
Peak memory 225656 kb
Host smart-f5963f75-8b06-44f5-a2bd-fce108bf3262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359195427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3359195427
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2696665797
Short name T759
Test name
Test status
Simulation time 19760938 ps
CPU time 0.99 seconds
Started Jul 02 09:50:34 AM PDT 24
Finished Jul 02 09:50:38 AM PDT 24
Peak memory 217640 kb
Host smart-4dce619c-00d3-4479-b7ac-99c7a7dcf78a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696665797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2696665797
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3118768957
Short name T49
Test name
Test status
Simulation time 580676900 ps
CPU time 3.07 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:08 AM PDT 24
Peak memory 225592 kb
Host smart-7af8ee74-a2f8-4f99-b2ce-63a3ff5f92a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118768957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3118768957
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1902568514
Short name T224
Test name
Test status
Simulation time 3380975334 ps
CPU time 17.02 seconds
Started Jul 02 09:50:20 AM PDT 24
Finished Jul 02 09:50:45 AM PDT 24
Peak memory 250264 kb
Host smart-5e4db550-677b-4d78-94cc-ad3fb1c9bfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902568514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1902568514
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1024065887
Short name T981
Test name
Test status
Simulation time 1587859023 ps
CPU time 10.03 seconds
Started Jul 02 09:50:21 AM PDT 24
Finished Jul 02 09:50:39 AM PDT 24
Peak memory 222572 kb
Host smart-3f2cfb14-5a0d-4a54-b636-18f816f4e199
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1024065887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1024065887
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2455056182
Short name T214
Test name
Test status
Simulation time 31415577359 ps
CPU time 266.19 seconds
Started Jul 02 09:50:39 AM PDT 24
Finished Jul 02 09:55:06 AM PDT 24
Peak memory 274896 kb
Host smart-e721fb0a-592f-413c-8d6c-602e312d544f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455056182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2455056182
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2891847214
Short name T322
Test name
Test status
Simulation time 505125782 ps
CPU time 7.6 seconds
Started Jul 02 09:50:45 AM PDT 24
Finished Jul 02 09:50:53 AM PDT 24
Peak memory 217508 kb
Host smart-c0932488-da73-4d21-a591-b653a524610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891847214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2891847214
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3459081833
Short name T568
Test name
Test status
Simulation time 107655637 ps
CPU time 1.52 seconds
Started Jul 02 09:50:53 AM PDT 24
Finished Jul 02 09:50:56 AM PDT 24
Peak memory 208960 kb
Host smart-c9f52d3c-3326-46e6-8f15-391541679a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459081833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3459081833
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2839094824
Short name T433
Test name
Test status
Simulation time 48795332 ps
CPU time 1.21 seconds
Started Jul 02 09:50:41 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 209188 kb
Host smart-122fa220-57b5-4476-99d0-d84531bcaa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839094824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2839094824
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3136612043
Short name T333
Test name
Test status
Simulation time 11347449 ps
CPU time 0.69 seconds
Started Jul 02 09:50:24 AM PDT 24
Finished Jul 02 09:50:32 AM PDT 24
Peak memory 206544 kb
Host smart-4005bf54-fcf5-4985-9db5-714d256c332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136612043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3136612043
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1205791673
Short name T483
Test name
Test status
Simulation time 1625124268 ps
CPU time 7.13 seconds
Started Jul 02 09:50:42 AM PDT 24
Finished Jul 02 09:50:50 AM PDT 24
Peak memory 225652 kb
Host smart-80d4fdcb-c119-428c-b3f9-5baea15d1e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205791673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1205791673
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2623888674
Short name T527
Test name
Test status
Simulation time 50374509 ps
CPU time 0.73 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:50:53 AM PDT 24
Peak memory 206752 kb
Host smart-d5d97a14-98a9-4031-b0ef-ba72c533257c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623888674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
623888674
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4139177570
Short name T518
Test name
Test status
Simulation time 195863114 ps
CPU time 2.24 seconds
Started Jul 02 09:50:47 AM PDT 24
Finished Jul 02 09:50:50 AM PDT 24
Peak memory 224652 kb
Host smart-da568e92-7f1e-46aa-9ea6-68ed41a9868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139177570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4139177570
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3252527966
Short name T829
Test name
Test status
Simulation time 32517747 ps
CPU time 0.8 seconds
Started Jul 02 09:50:42 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 207536 kb
Host smart-ff6bbe57-94c2-490b-bc68-4352cbcd6618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252527966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3252527966
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3130910302
Short name T995
Test name
Test status
Simulation time 47920882565 ps
CPU time 186.77 seconds
Started Jul 02 09:50:49 AM PDT 24
Finished Jul 02 09:53:56 AM PDT 24
Peak memory 266680 kb
Host smart-bee39758-f441-4d6a-ad66-7e7c20d9283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130910302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3130910302
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3878984001
Short name T819
Test name
Test status
Simulation time 15310034076 ps
CPU time 143.49 seconds
Started Jul 02 09:50:37 AM PDT 24
Finished Jul 02 09:53:03 AM PDT 24
Peak memory 250428 kb
Host smart-72e3ad2e-3819-496d-855b-e213544fca8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878984001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3878984001
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1750363543
Short name T419
Test name
Test status
Simulation time 551849740 ps
CPU time 9.19 seconds
Started Jul 02 09:50:42 AM PDT 24
Finished Jul 02 09:50:52 AM PDT 24
Peak memory 225524 kb
Host smart-00791122-5e28-46e5-ac64-37486f02d656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750363543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1750363543
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.404478625
Short name T739
Test name
Test status
Simulation time 22700231183 ps
CPU time 50.4 seconds
Started Jul 02 09:50:56 AM PDT 24
Finished Jul 02 09:51:47 AM PDT 24
Peak memory 250324 kb
Host smart-240c3fca-7c17-4a7e-8eb2-b0e1650ce4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404478625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
404478625
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1058156411
Short name T66
Test name
Test status
Simulation time 922330212 ps
CPU time 5.12 seconds
Started Jul 02 09:50:49 AM PDT 24
Finished Jul 02 09:50:55 AM PDT 24
Peak memory 225588 kb
Host smart-a430ff82-79f9-4e3c-81ac-502832020b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058156411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1058156411
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.509507424
Short name T654
Test name
Test status
Simulation time 43694362 ps
CPU time 2.41 seconds
Started Jul 02 09:50:45 AM PDT 24
Finished Jul 02 09:50:48 AM PDT 24
Peak memory 233528 kb
Host smart-13d861a8-fa5c-42a6-9d85-1dca6ba517f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509507424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.509507424
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1866457509
Short name T522
Test name
Test status
Simulation time 96684429 ps
CPU time 1.07 seconds
Started Jul 02 09:50:38 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 217664 kb
Host smart-c451b16d-82f1-4cbb-8ec3-d34a9ed90e24
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866457509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1866457509
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4138214156
Short name T366
Test name
Test status
Simulation time 3928964116 ps
CPU time 8.86 seconds
Started Jul 02 09:51:10 AM PDT 24
Finished Jul 02 09:51:23 AM PDT 24
Peak memory 233892 kb
Host smart-7e366ace-07a4-4c23-8181-21f075f604fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138214156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4138214156
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1340728433
Short name T45
Test name
Test status
Simulation time 7102207348 ps
CPU time 17.06 seconds
Started Jul 02 09:50:56 AM PDT 24
Finished Jul 02 09:51:14 AM PDT 24
Peak memory 225624 kb
Host smart-40529477-ec31-4f64-a75d-8c2b2952e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340728433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1340728433
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1981323547
Short name T396
Test name
Test status
Simulation time 3918781684 ps
CPU time 11.16 seconds
Started Jul 02 09:50:49 AM PDT 24
Finished Jul 02 09:51:01 AM PDT 24
Peak memory 223444 kb
Host smart-ebf300f0-dd87-46c5-9899-c562eede7f02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1981323547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1981323547
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2466582492
Short name T354
Test name
Test status
Simulation time 54611951 ps
CPU time 1.07 seconds
Started Jul 02 09:50:40 AM PDT 24
Finished Jul 02 09:50:42 AM PDT 24
Peak memory 208680 kb
Host smart-7873b76e-4f7c-45da-b067-b8af9027d8d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466582492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2466582492
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1330089352
Short name T319
Test name
Test status
Simulation time 2345860520 ps
CPU time 12.15 seconds
Started Jul 02 09:50:59 AM PDT 24
Finished Jul 02 09:51:12 AM PDT 24
Peak memory 217500 kb
Host smart-f573e705-1826-4379-b2e7-0a8658975c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330089352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1330089352
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3974751061
Short name T809
Test name
Test status
Simulation time 881235933 ps
CPU time 5.76 seconds
Started Jul 02 09:50:36 AM PDT 24
Finished Jul 02 09:50:45 AM PDT 24
Peak memory 217352 kb
Host smart-acf80813-33df-4c6a-ae1d-07b10389c594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974751061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3974751061
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.954824419
Short name T662
Test name
Test status
Simulation time 175605250 ps
CPU time 2.06 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:50:54 AM PDT 24
Peak memory 217332 kb
Host smart-bab3787a-f03b-4846-a79b-c3807f900140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954824419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.954824419
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4195086202
Short name T94
Test name
Test status
Simulation time 82488152 ps
CPU time 0.76 seconds
Started Jul 02 09:50:42 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 206940 kb
Host smart-1d1cc3f4-79ac-497a-b253-7fa39b77c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195086202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4195086202
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1968255109
Short name T240
Test name
Test status
Simulation time 306878939 ps
CPU time 5.23 seconds
Started Jul 02 09:50:36 AM PDT 24
Finished Jul 02 09:50:44 AM PDT 24
Peak memory 225592 kb
Host smart-2071f2c9-a17d-4109-9641-93ec6337b416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968255109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1968255109
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3578064125
Short name T974
Test name
Test status
Simulation time 23108690 ps
CPU time 0.76 seconds
Started Jul 02 09:50:44 AM PDT 24
Finished Jul 02 09:50:46 AM PDT 24
Peak memory 205828 kb
Host smart-74ed9b89-4c6a-41b8-8dbb-880742b28db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578064125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
578064125
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.28956309
Short name T996
Test name
Test status
Simulation time 291484980 ps
CPU time 2.92 seconds
Started Jul 02 09:50:41 AM PDT 24
Finished Jul 02 09:50:45 AM PDT 24
Peak memory 225536 kb
Host smart-e8c96316-424c-41b6-b5b4-0d93684bfad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28956309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.28956309
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3704831609
Short name T903
Test name
Test status
Simulation time 67587943 ps
CPU time 0.78 seconds
Started Jul 02 09:50:42 AM PDT 24
Finished Jul 02 09:50:44 AM PDT 24
Peak memory 207532 kb
Host smart-14425b10-1e18-4c15-b474-25c4e9405f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704831609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3704831609
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.780820359
Short name T85
Test name
Test status
Simulation time 4193871568 ps
CPU time 86.15 seconds
Started Jul 02 09:50:48 AM PDT 24
Finished Jul 02 09:52:14 AM PDT 24
Peak memory 256452 kb
Host smart-804940cd-b9de-45b4-be02-0f5ed26e8ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780820359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.780820359
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1609301270
Short name T647
Test name
Test status
Simulation time 9775200711 ps
CPU time 31.43 seconds
Started Jul 02 09:50:46 AM PDT 24
Finished Jul 02 09:51:18 AM PDT 24
Peak memory 250452 kb
Host smart-337a0309-1df7-4e28-9a67-4e881768cc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609301270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1609301270
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3417892181
Short name T44
Test name
Test status
Simulation time 282446222777 ps
CPU time 167.43 seconds
Started Jul 02 09:50:37 AM PDT 24
Finished Jul 02 09:53:27 AM PDT 24
Peak memory 258488 kb
Host smart-e88c31a2-c665-4e5a-9f2c-ce47a1ec7e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417892181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3417892181
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2380705737
Short name T836
Test name
Test status
Simulation time 4056810113 ps
CPU time 31.87 seconds
Started Jul 02 09:50:47 AM PDT 24
Finished Jul 02 09:51:19 AM PDT 24
Peak memory 240896 kb
Host smart-5fa9685b-4bec-400f-af53-528b671ae96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380705737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2380705737
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2383264706
Short name T277
Test name
Test status
Simulation time 132478217814 ps
CPU time 459.88 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 252548 kb
Host smart-d81bfff4-f5b6-41aa-8c18-9e0e295ca487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383264706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2383264706
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1717135372
Short name T669
Test name
Test status
Simulation time 1331687234 ps
CPU time 6.71 seconds
Started Jul 02 09:50:34 AM PDT 24
Finished Jul 02 09:50:44 AM PDT 24
Peak memory 225608 kb
Host smart-93eac335-3e8b-48be-8764-07350ca9242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717135372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1717135372
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3226571675
Short name T788
Test name
Test status
Simulation time 6186093516 ps
CPU time 45.14 seconds
Started Jul 02 09:50:38 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 233864 kb
Host smart-d24cf42b-9fae-4339-b6c2-c87bf41a9881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226571675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3226571675
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1024667680
Short name T541
Test name
Test status
Simulation time 45262848 ps
CPU time 1.04 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:50:53 AM PDT 24
Peak memory 217648 kb
Host smart-ee9bc196-4329-4089-88b2-1f78ea8af9f8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024667680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1024667680
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.647940741
Short name T385
Test name
Test status
Simulation time 571139199 ps
CPU time 4.44 seconds
Started Jul 02 09:50:48 AM PDT 24
Finished Jul 02 09:50:53 AM PDT 24
Peak memory 233728 kb
Host smart-76f75e61-3ca5-49e8-82d4-0c57e48e0131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647940741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
647940741
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3162815444
Short name T668
Test name
Test status
Simulation time 479445394 ps
CPU time 3.13 seconds
Started Jul 02 09:50:54 AM PDT 24
Finished Jul 02 09:50:58 AM PDT 24
Peak memory 233716 kb
Host smart-8f52c4f9-a66c-4022-abf8-557ee6911f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162815444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3162815444
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3046884458
Short name T161
Test name
Test status
Simulation time 322238453 ps
CPU time 4.52 seconds
Started Jul 02 09:50:35 AM PDT 24
Finished Jul 02 09:50:43 AM PDT 24
Peak memory 223596 kb
Host smart-aeba95bb-fe2d-41d2-a414-ddf2647a5aa1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3046884458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3046884458
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2493356493
Short name T709
Test name
Test status
Simulation time 203304947 ps
CPU time 1.17 seconds
Started Jul 02 09:50:38 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 208792 kb
Host smart-b8410ec8-149f-4c32-9901-82881424025b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493356493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2493356493
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.485307828
Short name T517
Test name
Test status
Simulation time 11309912922 ps
CPU time 19.1 seconds
Started Jul 02 09:50:31 AM PDT 24
Finished Jul 02 09:50:55 AM PDT 24
Peak memory 217456 kb
Host smart-d454656f-c740-4d7f-9917-4897bb95301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485307828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.485307828
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1875739326
Short name T973
Test name
Test status
Simulation time 3354861943 ps
CPU time 14.46 seconds
Started Jul 02 09:50:32 AM PDT 24
Finished Jul 02 09:50:50 AM PDT 24
Peak memory 217504 kb
Host smart-df47e5e9-cfb3-4c78-862a-7757967ff103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875739326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1875739326
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.384935556
Short name T967
Test name
Test status
Simulation time 180754909 ps
CPU time 1.43 seconds
Started Jul 02 09:50:42 AM PDT 24
Finished Jul 02 09:50:44 AM PDT 24
Peak memory 217400 kb
Host smart-ce049796-af7f-4252-834a-4e5f69602345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384935556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.384935556
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4189638059
Short name T697
Test name
Test status
Simulation time 14754548 ps
CPU time 0.74 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:50:54 AM PDT 24
Peak memory 206916 kb
Host smart-d377ec83-ec3c-4e01-99d8-e466800a8f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189638059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4189638059
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1111628803
Short name T840
Test name
Test status
Simulation time 4207719947 ps
CPU time 12.48 seconds
Started Jul 02 09:50:50 AM PDT 24
Finished Jul 02 09:51:03 AM PDT 24
Peak memory 233848 kb
Host smart-2f5004b1-9ab1-4915-abbd-7c1926febb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111628803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1111628803
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1643761789
Short name T459
Test name
Test status
Simulation time 50295655 ps
CPU time 0.72 seconds
Started Jul 02 09:50:59 AM PDT 24
Finished Jul 02 09:51:00 AM PDT 24
Peak memory 206332 kb
Host smart-5bfaa29a-e4b4-4e03-a2d3-3efdd6b35601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643761789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
643761789
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1935138569
Short name T194
Test name
Test status
Simulation time 187722505 ps
CPU time 2.62 seconds
Started Jul 02 09:51:02 AM PDT 24
Finished Jul 02 09:51:07 AM PDT 24
Peak memory 233788 kb
Host smart-5668c521-3a01-4b01-822e-1c20803d6cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935138569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1935138569
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3770681529
Short name T63
Test name
Test status
Simulation time 39047882 ps
CPU time 0.79 seconds
Started Jul 02 09:50:53 AM PDT 24
Finished Jul 02 09:50:55 AM PDT 24
Peak memory 207536 kb
Host smart-adb669d5-13c9-4e1e-a568-e8e7e12cdfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770681529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3770681529
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3839732000
Short name T55
Test name
Test status
Simulation time 5820980168 ps
CPU time 81.48 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:52:13 AM PDT 24
Peak memory 264008 kb
Host smart-8b03910f-307a-494c-ab58-f371bbba204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839732000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3839732000
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1728922481
Short name T746
Test name
Test status
Simulation time 139369751465 ps
CPU time 338.91 seconds
Started Jul 02 09:50:57 AM PDT 24
Finished Jul 02 09:56:37 AM PDT 24
Peak memory 253020 kb
Host smart-57c8a2e9-eb45-4d96-9e7d-c1156ebcde55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728922481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1728922481
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.163146136
Short name T26
Test name
Test status
Simulation time 4273466062 ps
CPU time 35.38 seconds
Started Jul 02 09:50:53 AM PDT 24
Finished Jul 02 09:51:30 AM PDT 24
Peak memory 250660 kb
Host smart-667dfb84-f043-44e8-b3bb-e1f5ee7101ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163146136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
163146136
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1246496124
Short name T745
Test name
Test status
Simulation time 2983042811 ps
CPU time 43.7 seconds
Started Jul 02 09:50:56 AM PDT 24
Finished Jul 02 09:51:46 AM PDT 24
Peak memory 241980 kb
Host smart-c3b69836-5d8d-4959-97e7-157b3781b378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246496124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1246496124
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1590062962
Short name T207
Test name
Test status
Simulation time 66343076496 ps
CPU time 75.71 seconds
Started Jul 02 09:50:49 AM PDT 24
Finished Jul 02 09:52:05 AM PDT 24
Peak memory 250304 kb
Host smart-3f236079-df16-4066-8f66-9c2e36cbbebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590062962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1590062962
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2637957500
Short name T935
Test name
Test status
Simulation time 580218998 ps
CPU time 4.86 seconds
Started Jul 02 09:51:06 AM PDT 24
Finished Jul 02 09:51:15 AM PDT 24
Peak memory 225624 kb
Host smart-df651762-49b4-46c5-9f94-bbbcad21ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637957500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2637957500
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3007645668
Short name T211
Test name
Test status
Simulation time 777468201 ps
CPU time 13.67 seconds
Started Jul 02 09:51:07 AM PDT 24
Finished Jul 02 09:51:25 AM PDT 24
Peak memory 230424 kb
Host smart-d1c2ef96-7b52-49b0-86b2-15ed62b893ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007645668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3007645668
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1132796990
Short name T910
Test name
Test status
Simulation time 17881929 ps
CPU time 0.99 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:50:53 AM PDT 24
Peak memory 218968 kb
Host smart-af2d2630-5f92-40f3-b840-d54b795784a4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132796990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1132796990
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3324596205
Short name T828
Test name
Test status
Simulation time 2108489622 ps
CPU time 7.06 seconds
Started Jul 02 09:50:57 AM PDT 24
Finished Jul 02 09:51:05 AM PDT 24
Peak memory 233796 kb
Host smart-23a730fa-df3d-4d80-a7a7-2de9e1bc1cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324596205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3324596205
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3629509915
Short name T827
Test name
Test status
Simulation time 7124433511 ps
CPU time 9.22 seconds
Started Jul 02 09:50:55 AM PDT 24
Finished Jul 02 09:51:05 AM PDT 24
Peak memory 240416 kb
Host smart-e12f0aba-cfdf-4c67-a2e6-a2d55b9d4e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629509915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3629509915
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2372507400
Short name T352
Test name
Test status
Simulation time 224135998 ps
CPU time 4.12 seconds
Started Jul 02 09:51:01 AM PDT 24
Finished Jul 02 09:51:06 AM PDT 24
Peak memory 223632 kb
Host smart-c92c10dd-a0d6-4e56-8342-659addedaebb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372507400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2372507400
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.72195727
Short name T19
Test name
Test status
Simulation time 170374378 ps
CPU time 0.95 seconds
Started Jul 02 09:51:03 AM PDT 24
Finished Jul 02 09:51:06 AM PDT 24
Peak memory 207580 kb
Host smart-94d4ef41-2dd0-4797-a8f8-1018bdbf7dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72195727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_
all.72195727
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3091752564
Short name T512
Test name
Test status
Simulation time 28643029 ps
CPU time 0.71 seconds
Started Jul 02 09:50:59 AM PDT 24
Finished Jul 02 09:51:01 AM PDT 24
Peak memory 206620 kb
Host smart-452aaf0b-a392-450d-88d5-bc2df730476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091752564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3091752564
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3463503465
Short name T773
Test name
Test status
Simulation time 9980578846 ps
CPU time 16.83 seconds
Started Jul 02 09:50:52 AM PDT 24
Finished Jul 02 09:51:10 AM PDT 24
Peak memory 217408 kb
Host smart-85ea7158-1182-4ce1-afac-6613710f065a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463503465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3463503465
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1549902198
Short name T511
Test name
Test status
Simulation time 444578591 ps
CPU time 1.68 seconds
Started Jul 02 09:50:51 AM PDT 24
Finished Jul 02 09:50:54 AM PDT 24
Peak memory 217380 kb
Host smart-7078f302-ed78-402d-bd5f-687b669727e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549902198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1549902198
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1007685220
Short name T976
Test name
Test status
Simulation time 40562755 ps
CPU time 0.72 seconds
Started Jul 02 09:51:00 AM PDT 24
Finished Jul 02 09:51:02 AM PDT 24
Peak memory 206992 kb
Host smart-cfc5967b-474e-448d-8596-dcf499942259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007685220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1007685220
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1056531559
Short name T763
Test name
Test status
Simulation time 461829101 ps
CPU time 6.97 seconds
Started Jul 02 09:50:36 AM PDT 24
Finished Jul 02 09:50:46 AM PDT 24
Peak memory 233804 kb
Host smart-4c54b45b-6f37-4582-95e3-f70bcf3deea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056531559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1056531559
Directory /workspace/9.spi_device_upload/latest
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