Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2564474	1			T1	1		T2	1		T3	1
all_values[1]	2564474	1			T1	1		T2	1		T3	1
all_values[2]	2564474	1			T1	1		T2	1		T3	1
all_values[3]	2564474	1			T1	1		T2	1		T3	1
all_values[4]	2564474	1			T1	1		T2	1		T3	1
all_values[5]	2564474	1			T1	1		T2	1		T3	1
all_values[6]	2564474	1			T1	1		T2	1		T3	1
all_values[7]	2564474	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20274881

1

T1

8

T2

8

T3

8

auto[1]

240911

1

T9

61

T18

114

T19

122

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20490684

1

T1

8

T2

8

T3

8

auto[1]

25108

1

T5

479

T9

238

T24

139

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2526438	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11765	1			T5	295		T9	147		T24	85
all_values[0]	auto[1]	auto[0]	25894	1			T9	10		T18	5		T19	10
all_values[0]	auto[1]	auto[1]	377	1			T18	7		T19	10		T20	1
all_values[1]	auto[0]	auto[0]	2529298	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	8128	1			T5	137		T9	55		T24	47
all_values[1]	auto[1]	auto[0]	26795	1			T9	5		T18	12		T19	7
all_values[1]	auto[1]	auto[1]	253	1			T9	2		T18	7		T19	13
all_values[2]	auto[0]	auto[0]	2523856	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2593	1			T5	47		T9	3		T24	7
all_values[2]	auto[1]	auto[0]	37818	1			T9	3		T18	4		T19	7
all_values[2]	auto[1]	auto[1]	207	1			T9	3		T18	4		T19	9
all_values[3]	auto[0]	auto[0]	2530396	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	193	1			T9	4		T18	8		T19	8
all_values[3]	auto[1]	auto[0]	33692	1			T9	1		T18	10		T19	5
all_values[3]	auto[1]	auto[1]	193	1			T9	2		T18	7		T19	7
all_values[4]	auto[0]	auto[0]	2540366	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	186	1			T9	4		T18	4		T19	6
all_values[4]	auto[1]	auto[0]	23753	1			T9	5		T18	10		T19	7
all_values[4]	auto[1]	auto[1]	169	1			T9	1		T18	8		T19	4
all_values[5]	auto[0]	auto[0]	2511469	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	157	1			T9	1		T18	7		T19	5
all_values[5]	auto[1]	auto[0]	52677	1			T9	9		T18	7		T19	5
all_values[5]	auto[1]	auto[1]	171	1			T9	2		T18	4		T19	10
all_values[6]	auto[0]	auto[0]	2535473	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	191	1			T9	2		T18	3		T19	4
all_values[6]	auto[1]	auto[0]	28627	1			T9	4		T18	13		T19	10
all_values[6]	auto[1]	auto[1]	183	1			T9	7		T18	1		T19	3
all_values[7]	auto[0]	auto[0]	2554227	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	145	1			T9	3		T18	4		T19	6
all_values[7]	auto[1]	auto[0]	9905	1			T9	5		T18	10		T19	10
all_values[7]	auto[1]	auto[1]	197	1			T9	2		T18	5		T19	5