Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36148	1			T1	16		T5	226		T6	6
auto[SpiFlashAddrCfg]	7632	1			T5	47		T6	4		T8	18
auto[SpiFlashAddr3b]	9304	1			T5	79		T6	2		T8	27
auto[SpiFlashAddr4b]	7784	1			T5	59		T6	8		T8	22

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33635

1

T1

16

T5

255

T6

20

auto[1]

27233

1

T5

156

T8

56

T9

259

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33291

1

T1

16

T5

228

T6

16

auto[1]

27577

1

T5

183

T6

4

T8

56

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40820	1			T1	16		T5	261		T6	6
values[1]	1087	1			T5	10		T8	1		T9	9
values[2]	1497	1			T5	8		T8	5		T9	15
values[3]	1484	1			T5	7		T8	4		T9	14
values[4]	1523	1			T5	10		T6	4		T8	3
values[5]	1446	1			T5	13		T8	5		T9	15
values[6]	1399	1			T5	5		T8	1		T9	23
values[7]	1599	1			T5	11		T8	2		T9	11
values[8]	10013	1			T5	86		T6	10		T8	33

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33733

1

T1

16

T5

68

T6

20

auto[1]

27135

1

T5

343

T8

120

T9

456

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57683

1

T1

16

T5

381

T6

20

write

3185

1

T5

30

T8

10

T9

35

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19550

1

T1

16

T5

176

T6

4

valids[0x1]

41318

1

T5

235

T6

16

T8

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1575	1			T5	10		T6	2		T8	8
internal_process_ops[0x5a]	1581	1			T5	10		T6	2		T8	4
internal_process_ops[0x05]	22339	1			T5	107		T6	2		T8	4
internal_process_ops[0x35]	1513	1			T5	13		T8	4		T9	15
internal_process_ops[0x15]	1547	1			T5	8		T6	2		T8	4
internal_process_ops[0x03]	1175	1			T5	3		T6	8		T9	6
internal_process_ops[0x0b]	1066	1			T5	4		T8	1		T9	9
internal_process_ops[0x3b]	1101	1			T5	10		T8	2		T9	8
internal_process_ops[0x6b]	1105	1			T5	6		T6	2		T9	9
internal_process_ops[0xbb]	1123	1			T5	2		T9	3		T12	2
internal_process_ops[0xeb]	1077	1			T5	6		T6	2		T8	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59318

1

T1

16

T5

400

T6

20

auto[1]

1550

1

T5

11

T8

5

T9

14

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58499

1

T1

16

T5

382

T6

20

auto[1]

2369

1

T5

29

T8

15

T9

27

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11138

1

T1

16

T5

27

T6

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7594

1

T5

6

T9

12

T24

18

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2165

1

T5

4

T6

4

T9

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1852

1

T9

15

T13

2

T24

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2623

1

T5

8

T6

2

T9

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2444

1

T5

12

T9

21

T13

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2180

1

T5

2

T6

8

T9

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2003

1

T5

4

T9

16

T13

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

132

1

T9

1

T24

2

T26

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

128

1

T24

3

T48

2

T49

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

84

1

T26

1

T48

1

T50

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

115

1

T5

1

T9

2

T24

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

113

1

T5

1

T26

1

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

91

1

T24

2

T37

5

T18

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T5

1

T9

1

T26

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T48

2

T38

3

T18

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

115

1

T5

1

T9

2

T14

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

124

1

T9

1

T26

2

T37

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

99

1

T26

1

T37

2

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T9

2

T24

4

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T24

1

T26

3

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

100

1

T26

2

T18

5

T134

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

109

1

T9

2

T24

1

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T5

1

T9

1

T24

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9113

1

T5

117

T8

33

T9

177

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7478

1

T5

63

T8

18

T9

115

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1469

1

T5

19

T8

6

T9

30

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1367

1

T5

15

T8

9

T9

23

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1801

1

T5

31

T8

14

T9

27

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1645

1

T5

22

T8

12

T9

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1436

1

T5

27

T8

7

T9

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1375

1

T5

24

T8

11

T9

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T5

5

T8

2

T12

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T5

4

T9

1

T88

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

80

1

T5

3

T36

1

T88

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

83

1

T9

2

T88

1

T170

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

99

1

T5

5

T9

1

T12

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

106

1

T8

2

T36

1

T170

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T9

1

T12

4

T36

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

76

1

T5

2

T8

1

T9

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

110

1

T5

3

T9

3

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

82

1

T5

1

T12

1

T36

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

78

1

T9

2

T12

2

T36

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

73

1

T5

1

T8

1

T9

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T9

5

T12

9

T88

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

83

1

T9

2

T12

3

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T8

3

T9

3

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

86

1

T5

1

T8

1

T9

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4099	1			T1	16		T5	17		T9	25
auto[0]	values[0]	valids[0x1]	17709	1			T5	21		T6	6		T9	140
auto[0]	values[1]	valids[0x1]	599	1			T9	3		T24	2		T26	7
auto[0]	values[2]	valids[0x0]	558	1			T5	2		T9	1		T24	1
auto[0]	values[2]	valids[0x1]	338	1			T5	1		T9	2		T45	2
auto[0]	values[3]	valids[0x0]	594	1			T9	5		T24	2		T26	2
auto[0]	values[3]	valids[0x1]	304	1			T5	1		T9	4		T14	2
auto[0]	values[4]	valids[0x0]	608	1			T5	1		T6	4		T9	4
auto[0]	values[4]	valids[0x1]	324	1			T9	3		T13	1		T24	2
auto[0]	values[5]	valids[0x0]	545	1			T5	1		T9	7		T24	3
auto[0]	values[5]	valids[0x1]	306	1			T9	3		T26	3		T53	1
auto[0]	values[6]	valids[0x0]	523	1			T5	1		T9	5		T13	2
auto[0]	values[6]	valids[0x1]	311	1			T24	1		T26	1		T53	1
auto[0]	values[7]	valids[0x0]	683	1			T5	2		T9	2		T14	2
auto[0]	values[7]	valids[0x1]	312	1			T5	1		T24	4		T26	1
auto[0]	values[8]	valids[0x0]	3701	1			T5	12		T9	28		T13	6
auto[0]	values[8]	valids[0x1]	2219	1			T5	8		T6	10		T9	22
auto[1]	values[0]	valids[0x0]	3649	1			T5	63		T8	30		T9	63
auto[1]	values[0]	valids[0x1]	15363	1			T5	160		T8	36		T9	258
auto[1]	values[1]	valids[0x1]	488	1			T5	10		T8	1		T9	6
auto[1]	values[2]	valids[0x0]	356	1			T5	5		T8	2		T9	8
auto[1]	values[2]	valids[0x1]	245	1			T8	3		T9	4		T12	4
auto[1]	values[3]	valids[0x0]	332	1			T5	5		T8	3		T9	4
auto[1]	values[3]	valids[0x1]	254	1			T5	1		T8	1		T9	1
auto[1]	values[4]	valids[0x0]	349	1			T5	4		T8	1		T9	8
auto[1]	values[4]	valids[0x1]	242	1			T5	5		T8	2		T9	3
auto[1]	values[5]	valids[0x0]	337	1			T5	7		T8	2		T9	3
auto[1]	values[5]	valids[0x1]	258	1			T5	5		T8	3		T9	2
auto[1]	values[6]	valids[0x0]	319	1			T5	2		T8	1		T9	5
auto[1]	values[6]	valids[0x1]	246	1			T5	2		T9	13		T12	2
auto[1]	values[7]	valids[0x0]	370	1			T5	6		T8	1		T9	9
auto[1]	values[7]	valids[0x1]	234	1			T5	2		T8	1		T12	2
auto[1]	values[8]	valids[0x0]	2527	1			T5	48		T8	24		T9	44
auto[1]	values[8]	valids[0x1]	1566	1			T5	18		T8	9		T9	25