Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3317005

1

T1

42

T5

18275

T6

7209

auto[1]

32168

1

T5

91

T8

445

T9

270

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

853574

1

T1

42

T5

125

T6

5221

auto[1]

2495599

1

T5

18241

T6

1988

T8

4413

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	617446	1			T1	6		T5	702		T6	1505
auto[524288:1048575]	434602	1			T1	29		T5	7		T6	17
auto[1048576:1572863]	391243	1			T5	2845		T6	81		T8	148
auto[1572864:2097151]	400522	1			T5	6389		T6	695		T8	2142
auto[2097152:2621439]	373742	1			T1	3		T5	1315		T6	1310
auto[2621440:3145727]	398155	1			T5	698		T8	56		T9	1021
auto[3145728:3670015]	361959	1			T5	299		T6	2315		T8	121
auto[3670016:4194303]	371504	1			T1	4		T5	6111		T6	1286

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2530768

1

T1

37

T5

18363

T6

2256

auto[1]

818405

1

T1

5

T5

3

T6

4953

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2851263

1

T1

6

T5

15371

T6

7209

auto[1]

497910

1

T1

36

T5

2995

T8

586

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	153018	1			T1	1		T5	10		T6	516
auto[0]	auto[0]	auto[0:524287]	auto[1]	379705	1			T5	134		T6	989		T9	1387
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	92589	1			T1	3		T5	3		T6	17
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	272981	1			T5	2		T8	640		T9	1838
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	99975	1			T5	8		T6	81		T8	20
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	211663	1			T5	2463		T8	128		T9	5649
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	75855	1			T5	2		T6	695		T8	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	255219	1			T5	6240		T8	2129		T9	3122
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	105593	1			T5	3		T6	1307		T8	7
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	214781	1			T5	390		T6	3		T8	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	117335	1			T5	18		T8	17		T9	9
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	225553	1			T5	671		T9	515		T12	823
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	90731	1			T5	5		T6	1997		T8	21
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	210997	1			T5	281		T6	318		T8	100
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	108574	1			T1	2		T5	13		T6	608
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	209040	1			T5	5064		T6	678		T8	544
auto[0]	auto[1]	auto[0:524287]	auto[0]	1238	1			T1	5		T5	5		T8	37
auto[0]	auto[1]	auto[0:524287]	auto[1]	79449	1			T5	515		T8	513		T9	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	675	1			T1	26		T9	1		T24	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	62857	1			T9	1926		T24	1		T48	3097
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	654	1			T5	5		T9	5		T12	16
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	75573	1			T5	359		T9	4111		T12	591
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	461	1			T5	8		T12	7		T24	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	64117	1			T5	130		T9	76		T12	1864
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	646	1			T1	3		T5	7		T9	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48501	1			T5	906		T9	260		T24	128
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1065	1			T8	9		T9	10		T12	34
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	50320	1			T9	388		T12	517		T36	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	573	1			T5	4		T12	4		T26	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	56552	1			T9	2921		T12	128		T48	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	804	1			T1	2		T5	5		T12	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	49911	1			T5	1024		T220	1798		T136	2136
auto[1]	auto[0]	auto[0:524287]	auto[0]	492	1			T5	6		T8	10		T9	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3171	1			T5	22		T14	61		T26	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	386	1			T5	2		T9	3		T12	11
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4499	1			T9	8		T12	10		T24	11
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	333	1			T5	3		T9	3		T24	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2382	1			T5	5		T9	17		T24	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	338	1			T8	3		T9	5		T12	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3815	1			T9	53		T24	14		T36	20
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	389	1			T5	1		T8	10		T9	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3441	1			T5	2		T9	31		T36	49
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	411	1			T5	6		T8	21		T9	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2591	1			T5	3		T9	84		T12	41
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	328	1			T5	2		T9	1		T12	16
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2248	1			T5	7		T9	16		T26	16
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	394	1			T5	2		T8	22		T9	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2436	1			T5	3		T8	352		T9	9
auto[1]	auto[1]	auto[0:524287]	auto[0]	106	1			T5	3		T8	18		T9	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	267	1			T5	7		T9	1		T12	7
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	68	1			T9	1		T24	1		T48	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	547	1			T9	1		T24	2		T48	12
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	96	1			T5	1		T12	9		T36	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	567	1			T5	1		T48	22		T79	175
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	80	1			T5	2		T12	5		T24	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	637	1			T5	7		T12	46		T24	12
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	55	1			T5	1		T9	2		T36	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	336	1			T5	5		T9	13		T170	38
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	114	1			T8	9		T9	2		T12	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	766	1			T9	10		T12	33		T37	97
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	90	1			T37	4		T220	11		T20	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	440	1			T20	28		T58	40		T22	37
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	108	1			T136	4		T82	1		T20	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	237	1			T136	5		T20	5		T22	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2007259	1			T1	2		T5	15305		T6	2256
auto[0]	auto[0]	auto[1]	816350	1			T1	4		T5	2		T6	4953
auto[0]	auto[1]	auto[0]	492051	1			T1	35		T5	2968		T8	559
auto[0]	auto[1]	auto[1]	1345	1			T1	1		T48	3		T88	2
auto[1]	auto[0]	auto[0]	27074	1			T5	63		T8	411		T9	235
auto[1]	auto[0]	auto[1]	580	1			T5	1		T8	7		T9	4
auto[1]	auto[1]	auto[0]	4384	1			T5	27		T8	24		T9	30
auto[1]	auto[1]	auto[1]	130	1			T8	3		T9	1		T12	5