Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2564474	1			T1	1		T2	1		T3	1
all_pins[1]	2564474	1			T1	1		T2	1		T3	1
all_pins[2]	2564474	1			T1	1		T2	1		T3	1
all_pins[3]	2564474	1			T1	1		T2	1		T3	1
all_pins[4]	2564474	1			T1	1		T2	1		T3	1
all_pins[5]	2564474	1			T1	1		T2	1		T3	1
all_pins[6]	2564474	1			T1	1		T2	1		T3	1
all_pins[7]	2564474	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20486391	1			T1	8		T2	8		T3	8
values[0x1]	29401	1			T9	19		T18	43		T19	61
transitions[0x0=>0x1]	28585	1			T9	17		T18	33		T19	40
transitions[0x1=>0x0]	28599	1			T9	17		T18	34		T19	40

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2564044	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	430	1			T18	7		T19	10		T20	1
all_pins[0]	transitions[0x0=>0x1]	380	1			T18	5		T19	2		T20	1
all_pins[0]	transitions[0x1=>0x0]	216	1			T9	2		T18	5		T19	5
all_pins[1]	values[0x0]	2564208	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	266	1			T9	2		T18	7		T19	13
all_pins[1]	transitions[0x0=>0x1]	193	1			T9	2		T18	6		T19	8
all_pins[1]	transitions[0x1=>0x0]	145	1			T9	3		T18	3		T19	4
all_pins[2]	values[0x0]	2564256	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	218	1			T9	3		T18	4		T19	9
all_pins[2]	transitions[0x0=>0x1]	174	1			T9	3		T18	2		T19	7
all_pins[2]	transitions[0x1=>0x0]	149	1			T9	2		T18	5		T19	5
all_pins[3]	values[0x0]	2564281	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	193	1			T9	2		T18	7		T19	7
all_pins[3]	transitions[0x0=>0x1]	147	1			T9	2		T18	6		T19	5
all_pins[3]	transitions[0x1=>0x0]	123	1			T9	1		T18	7		T19	2
all_pins[4]	values[0x0]	2564305	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	169	1			T9	1		T18	8		T19	4
all_pins[4]	transitions[0x0=>0x1]	126	1			T9	1		T18	7		T19	2
all_pins[4]	transitions[0x1=>0x0]	1628	1			T9	2		T18	3		T19	8
all_pins[5]	values[0x0]	2562803	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1671	1			T9	2		T18	4		T19	10
all_pins[5]	transitions[0x0=>0x1]	1224	1			T9	1		T18	3		T19	10
all_pins[5]	transitions[0x1=>0x0]	25810	1			T9	6		T19	3		T20	3
all_pins[6]	values[0x0]	2538217	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	26257	1			T9	7		T18	1		T19	3
all_pins[6]	transitions[0x0=>0x1]	26201	1			T9	6		T18	1		T19	2
all_pins[6]	transitions[0x1=>0x0]	141	1			T9	1		T18	5		T19	4
all_pins[7]	values[0x0]	2564277	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	197	1			T9	2		T18	5		T19	5
all_pins[7]	transitions[0x0=>0x1]	140	1			T9	2		T18	3		T19	4
all_pins[7]	transitions[0x1=>0x0]	387	1			T18	6		T19	9		T20	1