Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T1

16

T5

43

T6

20

auto[1]

14706

1

T5

25

T9

72

T13

7

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4504	1			T9	85		T24	22		T44	10
values[1]	4440	1			T24	72		T26	67		T221	4
values[2]	3930	1			T13	20		T14	79		T45	8
values[3]	4274	1			T9	85		T37	40		T52	20
values[4]	4391	1			T5	68		T6	20		T9	23
values[5]	3939	1			T24	34		T26	20		T48	27
values[6]	4141	1			T1	16		T9	28		T24	49
values[7]	4114	1			T9	33		T16	2		T47	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3774	1			T13	20		T24	52		T26	47
values[1]	4652	1			T9	28		T24	20		T44	10
values[2]	4309	1			T9	23		T15	2		T16	2
values[3]	4752	1			T5	45		T9	20		T46	8
values[4]	4084	1			T9	44		T26	64		T47	8
values[5]	3864	1			T1	16		T5	23		T9	41
values[6]	3921	1			T9	98		T24	42		T221	4
values[7]	4377	1			T6	20		T24	29		T45	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	179	1			T38	9		T32	10		T222	4
auto[0]	values[0]	values[1]	393	1			T44	10		T48	23		T58	11
auto[0]	values[0]	values[2]	447	1			T26	9		T30	8		T223	54
auto[0]	values[0]	values[3]	214	1			T58	48		T224	4		T184	12
auto[0]	values[0]	values[4]	304	1			T9	38		T49	28		T50	16
auto[0]	values[0]	values[5]	225	1			T9	32		T19	13		T82	11
auto[0]	values[0]	values[6]	326	1			T24	12		T134	9		T19	11
auto[0]	values[0]	values[7]	275	1			T50	9		T39	34		T139	9
auto[0]	values[1]	values[0]	321	1			T24	43		T26	20		T37	21
auto[0]	values[1]	values[1]	475	1			T24	12		T82	7		T181	17
auto[0]	values[1]	values[2]	312	1			T26	10		T48	10		T18	18
auto[0]	values[1]	values[3]	248	1			T134	12		T58	9		T79	8
auto[0]	values[1]	values[4]	385	1			T26	9		T19	6		T187	10
auto[0]	values[1]	values[5]	246	1			T38	12		T49	11		T181	14
auto[0]	values[1]	values[6]	360	1			T221	4		T37	14		T38	17
auto[0]	values[1]	values[7]	460	1			T37	10		T225	6		T82	24
auto[0]	values[2]	values[0]	171	1			T13	13		T134	11		T31	19
auto[0]	values[2]	values[1]	307	1			T77	11		T210	14		T188	20
auto[0]	values[2]	values[2]	169	1			T38	8		T77	8		T210	14
auto[0]	values[2]	values[3]	407	1			T46	8		T49	11		T183	13
auto[0]	values[2]	values[4]	228	1			T49	11		T82	4		T192	26
auto[0]	values[2]	values[5]	511	1			T14	79		T49	13		T39	9
auto[0]	values[2]	values[6]	205	1			T37	14		T49	8		T22	10
auto[0]	values[2]	values[7]	175	1			T37	9		T58	8		T226	2
auto[0]	values[3]	values[0]	304	1			T18	10		T134	10		T39	10
auto[0]	values[3]	values[1]	220	1			T39	9		T19	9		T204	6
auto[0]	values[3]	values[2]	271	1			T19	12		T22	15		T54	13
auto[0]	values[3]	values[3]	244	1			T9	11		T50	42		T82	13
auto[0]	values[3]	values[4]	369	1			T52	9		T217	18		T227	2
auto[0]	values[3]	values[5]	232	1			T37	30		T49	24		T58	11
auto[0]	values[3]	values[6]	236	1			T9	48		T50	15		T181	8
auto[0]	values[3]	values[7]	341	1			T39	11		T54	20		T183	12
auto[0]	values[4]	values[0]	338	1			T26	12		T38	13		T58	94
auto[0]	values[4]	values[1]	255	1			T22	12		T202	16		T228	6
auto[0]	values[4]	values[2]	432	1			T9	15		T15	2		T50	7
auto[0]	values[4]	values[3]	251	1			T5	33		T26	11		T50	14
auto[0]	values[4]	values[4]	283	1			T48	11		T92	20		T30	9
auto[0]	values[4]	values[5]	343	1			T5	10		T37	8		T38	13
auto[0]	values[4]	values[6]	362	1			T48	10		T49	11		T18	9
auto[0]	values[4]	values[7]	319	1			T6	20		T26	18		T37	7
auto[0]	values[5]	values[0]	323	1			T18	24		T39	12		T181	12
auto[0]	values[5]	values[1]	274	1			T139	10		T181	7		T79	12
auto[0]	values[5]	values[2]	240	1			T24	21		T22	9		T30	12
auto[0]	values[5]	values[3]	369	1			T48	12		T37	12		T229	88
auto[0]	values[5]	values[4]	290	1			T18	14		T134	12		T20	16
auto[0]	values[5]	values[5]	303	1			T26	4		T79	8		T201	38
auto[0]	values[5]	values[6]	223	1			T37	9		T50	12		T31	10
auto[0]	values[5]	values[7]	253	1			T37	14		T38	12		T210	12
auto[0]	values[6]	values[0]	232	1			T38	11		T134	6		T19	13
auto[0]	values[6]	values[1]	338	1			T9	14		T82	8		T22	22
auto[0]	values[6]	values[2]	376	1			T49	16		T138	12		T181	10
auto[0]	values[6]	values[3]	252	1			T20	15		T22	38		T183	13
auto[0]	values[6]	values[4]	299	1			T26	12		T201	28		T189	13
auto[0]	values[6]	values[5]	147	1			T1	16		T49	11		T181	11
auto[0]	values[6]	values[6]	411	1			T24	11		T19	28		T187	9
auto[0]	values[6]	values[7]	333	1			T24	18		T48	7		T38	15
auto[0]	values[7]	values[0]	394	1			T48	11		T139	14		T30	8
auto[0]	values[7]	values[1]	336	1			T82	15		T58	11		T181	5
auto[0]	values[7]	values[2]	221	1			T37	13		T230	12		T228	15
auto[0]	values[7]	values[3]	223	1			T231	4		T39	13		T204	11
auto[0]	values[7]	values[4]	169	1			T47	8		T82	50		T183	19
auto[0]	values[7]	values[5]	245	1			T50	14		T182	10		T183	79
auto[0]	values[7]	values[6]	356	1			T9	24		T53	13		T82	68
auto[0]	values[7]	values[7]	277	1			T50	14		T20	16		T183	26
auto[1]	values[0]	values[0]	149	1			T38	11		T32	12		T199	18
auto[1]	values[0]	values[1]	471	1			T48	40		T58	9		T183	8
auto[1]	values[0]	values[2]	399	1			T26	11		T30	12		T31	15
auto[1]	values[0]	values[3]	143	1			T58	8		T184	10		T201	35
auto[1]	values[0]	values[4]	416	1			T9	6		T49	12		T50	4
auto[1]	values[0]	values[5]	208	1			T9	9		T19	7		T82	25
auto[1]	values[0]	values[6]	199	1			T24	10		T134	15		T19	9
auto[1]	values[0]	values[7]	156	1			T50	11		T39	15		T139	11
auto[1]	values[1]	values[0]	212	1			T24	9		T26	7		T37	19
auto[1]	values[1]	values[1]	242	1			T24	8		T82	14		T181	3
auto[1]	values[1]	values[2]	123	1			T26	10		T48	23		T18	7
auto[1]	values[1]	values[3]	212	1			T134	48		T58	25		T79	12
auto[1]	values[1]	values[4]	185	1			T26	11		T19	14		T187	10
auto[1]	values[1]	values[5]	179	1			T38	8		T49	9		T181	6
auto[1]	values[1]	values[6]	206	1			T37	6		T38	23		T18	9
auto[1]	values[1]	values[7]	274	1			T37	10		T82	20		T232	8
auto[1]	values[2]	values[0]	100	1			T13	7		T134	9		T31	8
auto[1]	values[2]	values[1]	236	1			T77	12		T210	10		T188	3
auto[1]	values[2]	values[2]	172	1			T38	12		T77	12		T210	6
auto[1]	values[2]	values[3]	410	1			T49	9		T183	54		T212	6
auto[1]	values[2]	values[4]	160	1			T49	9		T82	20		T79	7
auto[1]	values[2]	values[5]	277	1			T49	7		T39	45		T58	20
auto[1]	values[2]	values[6]	245	1			T37	6		T49	12		T22	11
auto[1]	values[2]	values[7]	157	1			T45	8		T37	11		T58	12
auto[1]	values[3]	values[0]	265	1			T18	14		T134	36		T39	10
auto[1]	values[3]	values[1]	276	1			T39	44		T19	31		T204	15
auto[1]	values[3]	values[2]	396	1			T19	8		T22	7		T54	7
auto[1]	values[3]	values[3]	356	1			T9	9		T50	9		T82	48
auto[1]	values[3]	values[4]	253	1			T52	11		T201	9		T202	7
auto[1]	values[3]	values[5]	137	1			T37	10		T49	16		T58	9
auto[1]	values[3]	values[6]	125	1			T9	17		T50	5		T181	12
auto[1]	values[3]	values[7]	249	1			T39	9		T54	20		T183	15
auto[1]	values[4]	values[0]	163	1			T26	8		T38	7		T233	6
auto[1]	values[4]	values[1]	282	1			T22	11		T202	4		T228	15
auto[1]	values[4]	values[2]	200	1			T9	8		T50	13		T82	4
auto[1]	values[4]	values[3]	301	1			T5	12		T26	11		T50	11
auto[1]	values[4]	values[4]	200	1			T48	21		T30	16		T207	11
auto[1]	values[4]	values[5]	261	1			T5	13		T37	12		T38	7
auto[1]	values[4]	values[6]	135	1			T48	10		T49	9		T18	11
auto[1]	values[4]	values[7]	266	1			T26	8		T37	13		T38	8
auto[1]	values[5]	values[0]	222	1			T18	8		T39	8		T181	8
auto[1]	values[5]	values[1]	159	1			T139	10		T181	13		T79	8
auto[1]	values[5]	values[2]	198	1			T24	13		T22	14		T234	4
auto[1]	values[5]	values[3]	176	1			T48	15		T37	8		T32	6
auto[1]	values[5]	values[4]	162	1			T18	8		T134	8		T20	4
auto[1]	values[5]	values[5]	249	1			T26	16		T235	20		T79	12
auto[1]	values[5]	values[6]	227	1			T37	11		T50	12		T31	10
auto[1]	values[5]	values[7]	271	1			T37	6		T38	8		T210	9
auto[1]	values[6]	values[0]	194	1			T38	9		T134	21		T19	26
auto[1]	values[6]	values[1]	200	1			T9	14		T82	19		T93	14
auto[1]	values[6]	values[2]	264	1			T49	4		T181	10		T77	5
auto[1]	values[6]	values[3]	198	1			T20	5		T22	13		T183	30
auto[1]	values[6]	values[4]	299	1			T26	32		T201	8		T189	7
auto[1]	values[6]	values[5]	106	1			T49	9		T181	9		T212	6
auto[1]	values[6]	values[6]	133	1			T24	9		T19	9		T187	11
auto[1]	values[6]	values[7]	359	1			T24	11		T48	196		T38	5
auto[1]	values[7]	values[0]	207	1			T48	20		T139	6		T30	12
auto[1]	values[7]	values[1]	188	1			T82	5		T58	9		T181	15
auto[1]	values[7]	values[2]	89	1			T16	2		T37	7		T228	6
auto[1]	values[7]	values[3]	748	1			T39	8		T204	26		T236	55
auto[1]	values[7]	values[4]	82	1			T82	4		T183	8		T237	20
auto[1]	values[7]	values[5]	195	1			T50	6		T183	8		T238	6
auto[1]	values[7]	values[6]	172	1			T9	9		T53	7		T82	5
auto[1]	values[7]	values[7]	212	1			T50	6		T20	4		T183	11