Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	458	1			T6	8		T9	2		T26	4
auto[ReadAddrCrossIntoMailbox]	296	1			T9	4		T24	3		T53	2
auto[ReadAddrCrossOutOfMailbox]	313	1			T5	1		T9	1		T26	2
auto[ReadAddrCrossAllMailbox]	221	1			T9	2		T24	2		T26	1
auto[ReadAddrOutsideMailbox]	3851	1			T5	13		T6	4		T9	17

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2622

1

T5

12

T6

6

T9

13

auto[1]

2517

1

T5

2

T6

6

T9

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	925	1			T6	8		T9	5		T13	1
read_ops[0x0b]	814	1			T5	1		T9	5		T24	3
read_ops[0x3b]	825	1			T5	6		T9	5		T24	6
read_ops[0x6b]	869	1			T5	2		T6	2		T9	4
read_ops[0xbb]	871	1			T5	1		T9	1		T13	4
read_ops[0xeb]	835	1			T5	4		T6	2		T9	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T6	3		T37	1		T38	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T6	3		T37	1		T38	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T54	1		T201	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T38	1		T18	1		T50	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T134	1		T139	1		T77	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T48	1		T38	3		T18	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T181	1		T230	1		T188	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T58	1		T187	1		T230	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	369	1			T6	1		T9	3		T13	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T6	1		T9	2		T14	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T9	1		T53	1		T37	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T48	1		T50	1		T134	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T30	1		T210	1		T202	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	40	1			T9	1		T24	2		T48	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T38	1		T50	1		T139	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T18	1		T134	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T37	1		T49	1		T183	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T82	1		T22	1		T187	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	310	1			T5	1		T26	2		T37	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T9	3		T24	1		T26	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T50	1		T20	1		T58	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T26	1		T38	2		T134	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T9	1		T24	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T38	1		T50	2		T239	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T5	1		T26	1		T38	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T9	1		T26	1		T50	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T24	1		T22	1		T30	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T9	1		T240	1		T241	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T5	5		T9	1		T24	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T9	1		T24	1		T45	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T6	1		T9	1		T38	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T6	1		T37	2		T38	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T37	1		T38	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T18	2		T82	1		T58	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T49	1		T50	2		T39	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T48	1		T38	1		T49	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T37	1		T49	1		T50	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T37	2		T204	1		T30	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	364	1			T5	2		T9	3		T24	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T24	2		T26	2		T37	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T26	1		T48	1		T49	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T26	1		T48	1		T38	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T38	1		T204	1		T183	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T53	1		T38	2		T50	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T38	2		T49	1		T79	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T53	1		T37	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T24	1		T26	1		T242	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T50	2		T58	2		T77	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T5	1		T14	1		T24	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	327	1			T9	1		T13	4		T14	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T26	1		T58	1		T22	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T49	1		T39	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T9	1		T53	1		T50	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T9	1		T37	1		T58	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T37	1		T22	1		T77	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T58	1		T30	1		T184	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T38	1		T239	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T9	1		T18	1		T50	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T5	2		T6	1		T9	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T5	2		T6	1		T9	1