Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4111	1			T24	72		T44	10		T26	91
values[1]	4283	1			T9	45		T45	8		T26	26
values[2]	3858	1			T6	20		T9	40		T13	20
values[3]	4056	1			T5	24		T14	79		T26	20
values[4]	4198	1			T9	67		T16	2		T24	42
values[5]	4584	1			T1	16		T9	74		T46	8
values[6]	4406	1			T5	23		T26	22		T37	60
values[7]	4237	1			T5	21		T9	28		T15	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3426	1			T9	44		T24	49		T45	8
values[1]	4181	1			T1	16		T9	51		T13	20
values[2]	4523	1			T9	78		T14	79		T16	2
values[3]	4490	1			T37	60		T38	80		T92	20
values[4]	4810	1			T9	20		T24	22		T37	20
values[5]	4388	1			T5	44		T6	20		T9	41
values[6]	4268	1			T5	24		T24	20		T48	65
values[7]	3647	1			T9	20		T24	52		T46	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32864

1

T1

16

T5

66

T6

20

auto[1]

869

1

T5

2

T9

6

T24

14

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	509	1			T24	17		T26	45		T48	196
auto[0]	values[0]	values[1]	553	1			T26	41		T48	43		T18	20
auto[0]	values[0]	values[2]	423	1			T44	10		T48	20		T37	20
auto[0]	values[0]	values[3]	617	1			T37	19		T38	19		T22	21
auto[0]	values[0]	values[4]	529	1			T50	20		T39	20		T82	20
auto[0]	values[0]	values[5]	456	1			T52	19		T134	60		T184	20
auto[0]	values[0]	values[6]	634	1			T48	32		T216	8		T187	20
auto[0]	values[0]	values[7]	294	1			T24	45		T91	19		T243	42
auto[0]	values[1]	values[0]	211	1			T45	8		T49	20		T183	20
auto[0]	values[1]	values[1]	669	1			T50	19		T22	27		T184	20
auto[0]	values[1]	values[2]	613	1			T9	43		T26	26		T58	21
auto[0]	values[1]	values[3]	503	1			T37	17		T134	25		T139	17
auto[0]	values[1]	values[4]	688	1			T37	20		T82	70		T203	8
auto[0]	values[1]	values[5]	665	1			T215	54		T210	19		T237	18
auto[0]	values[1]	values[6]	355	1			T38	19		T49	20		T30	20
auto[0]	values[1]	values[7]	434	1			T49	20		T39	18		T181	20
auto[0]	values[2]	values[0]	419	1			T53	20		T48	31		T37	20
auto[0]	values[2]	values[1]	504	1			T13	20		T47	8		T38	20
auto[0]	values[2]	values[2]	427	1			T58	56		T183	20		T188	51
auto[0]	values[2]	values[3]	427	1			T38	19		T181	20		T77	21
auto[0]	values[2]	values[4]	491	1			T9	20		T183	85		T184	26
auto[0]	values[2]	values[5]	428	1			T6	20		T82	42		T223	54
auto[0]	values[2]	values[6]	564	1			T37	20		T50	25		T210	21
auto[0]	values[2]	values[7]	499	1			T9	18		T134	20		T139	19
auto[0]	values[3]	values[0]	453	1			T26	20		T37	19		T138	12
auto[0]	values[3]	values[1]	619	1			T32	20		T244	47		T245	35
auto[0]	values[3]	values[2]	533	1			T14	79		T37	20		T187	20
auto[0]	values[3]	values[3]	503	1			T38	18		T139	20		T58	33
auto[0]	values[3]	values[4]	526	1			T18	20		T58	70		T30	20
auto[0]	values[3]	values[5]	450	1			T18	26		T82	44		T58	20
auto[0]	values[3]	values[6]	451	1			T5	23		T50	31		T22	21
auto[0]	values[3]	values[7]	436	1			T49	39		T134	53		T19	37
auto[0]	values[4]	values[0]	389	1			T9	43		T134	15		T210	21
auto[0]	values[4]	values[1]	328	1			T9	23		T18	21		T50	20
auto[0]	values[4]	values[2]	709	1			T16	2		T37	20		T31	25
auto[0]	values[4]	values[3]	592	1			T18	62		T50	20		T134	46
auto[0]	values[4]	values[4]	697	1			T24	22		T49	40		T233	6
auto[0]	values[4]	values[5]	589	1			T82	61		T20	20		T181	20
auto[0]	values[4]	values[6]	425	1			T24	20		T50	20		T231	4
auto[0]	values[4]	values[7]	368	1			T49	20		T39	49		T82	21
auto[0]	values[5]	values[0]	456	1			T221	4		T134	24		T58	20
auto[0]	values[5]	values[1]	438	1			T1	16		T48	27		T18	32
auto[0]	values[5]	values[2]	505	1			T9	33		T26	20		T201	28
auto[0]	values[5]	values[3]	573	1			T39	20		T22	19		T183	20
auto[0]	values[5]	values[4]	666	1			T19	40		T82	24		T93	14
auto[0]	values[5]	values[5]	565	1			T9	41		T49	18		T82	71
auto[0]	values[5]	values[6]	676	1			T58	20		T204	20		T229	88
auto[0]	values[5]	values[7]	589	1			T46	8		T48	20		T235	20
auto[0]	values[6]	values[0]	339	1			T37	40		T58	20		T22	18
auto[0]	values[6]	values[1]	414	1			T38	19		T181	20		T219	20
auto[0]	values[6]	values[2]	624	1			T38	18		T30	20		T201	64
auto[0]	values[6]	values[3]	480	1			T92	20		T20	20		T22	20
auto[0]	values[6]	values[4]	556	1			T39	52		T139	19		T239	6
auto[0]	values[6]	values[5]	709	1			T5	22		T26	21		T49	20
auto[0]	values[6]	values[6]	592	1			T18	33		T58	20		T246	19
auto[0]	values[6]	values[7]	583	1			T37	20		T49	20		T188	20
auto[0]	values[7]	values[0]	547	1			T24	29		T39	34		T247	6
auto[0]	values[7]	values[1]	524	1			T9	27		T24	30		T38	19
auto[0]	values[7]	values[2]	582	1			T26	38		T50	20		T82	27
auto[0]	values[7]	values[3]	670	1			T37	17		T38	19		T20	20
auto[0]	values[7]	values[4]	545	1			T38	20		T192	26		T54	29
auto[0]	values[7]	values[5]	412	1			T5	21		T15	2		T37	20
auto[0]	values[7]	values[6]	490	1			T48	32		T190	19		T248	20
auto[0]	values[7]	values[7]	349	1			T39	51		T19	60		T183	39
auto[1]	values[0]	values[0]	18	1			T24	3		T26	2		T48	7
auto[1]	values[0]	values[1]	19	1			T26	3		T18	5		T19	2
auto[1]	values[0]	values[2]	6	1			T166	2		T244	2		T243	2
auto[1]	values[0]	values[3]	16	1			T37	1		T38	1		T22	3
auto[1]	values[0]	values[4]	5	1			T82	1		T197	1		T249	2
auto[1]	values[0]	values[5]	7	1			T52	1		T201	2		T91	1
auto[1]	values[0]	values[6]	10	1			T79	1		T250	3		T251	2
auto[1]	values[0]	values[7]	15	1			T24	7		T91	1		T243	1
auto[1]	values[1]	values[0]	2	1			T252	2		-	-		-	-
auto[1]	values[1]	values[1]	22	1			T50	1		T22	4		T189	1
auto[1]	values[1]	values[2]	20	1			T9	2		T190	1		T228	3
auto[1]	values[1]	values[3]	23	1			T37	3		T134	2		T139	3
auto[1]	values[1]	values[4]	19	1			T82	3		T201	1		T31	5
auto[1]	values[1]	values[5]	30	1			T210	1		T237	2		T214	1
auto[1]	values[1]	values[6]	9	1			T38	1		T79	1		T31	1
auto[1]	values[1]	values[7]	20	1			T39	2		T77	3		T212	3
auto[1]	values[2]	values[0]	7	1			T240	2		T253	1		T254	2
auto[1]	values[2]	values[1]	19	1			T58	3		T77	3		T79	2
auto[1]	values[2]	values[2]	10	1			T188	3		T248	1		T255	4
auto[1]	values[2]	values[3]	10	1			T38	1		T77	2		T219	2
auto[1]	values[2]	values[4]	13	1			T183	2		T209	2		T32	1
auto[1]	values[2]	values[5]	11	1			T82	2		T201	1		T255	2
auto[1]	values[2]	values[6]	11	1			T191	1		T256	2		T257	1
auto[1]	values[2]	values[7]	18	1			T9	2		T139	1		T181	3
auto[1]	values[3]	values[0]	5	1			T37	1		T202	1		T32	1
auto[1]	values[3]	values[1]	20	1			T244	1		T200	2		T254	5
auto[1]	values[3]	values[2]	7	1			T183	2		T202	2		T190	2
auto[1]	values[3]	values[3]	10	1			T38	2		T58	1		T258	4
auto[1]	values[3]	values[4]	16	1			T259	6		T256	6		T194	2
auto[1]	values[3]	values[5]	10	1			T18	2		T82	1		T201	2
auto[1]	values[3]	values[6]	11	1			T5	1		T200	5		T260	1
auto[1]	values[3]	values[7]	6	1			T49	1		T195	1		T261	3
auto[1]	values[4]	values[0]	25	1			T9	1		T134	5		T210	5
auto[1]	values[4]	values[1]	7	1			T18	1		T91	2		T190	4
auto[1]	values[4]	values[2]	16	1			T31	4		T209	1		T207	2
auto[1]	values[4]	values[3]	17	1			T18	2		T32	1		T248	3
auto[1]	values[4]	values[4]	18	1			T58	2		T202	1		T199	3
auto[1]	values[4]	values[5]	6	1			T190	1		T262	2		T263	2
auto[1]	values[4]	values[6]	6	1			T19	1		T22	2		T264	3
auto[1]	values[4]	values[7]	6	1			T184	2		T254	1		T264	2
auto[1]	values[5]	values[0]	19	1			T210	4		T209	1		T166	4
auto[1]	values[5]	values[1]	13	1			T77	1		T212	1		T207	4
auto[1]	values[5]	values[2]	12	1			T201	1		T209	1		T243	1
auto[1]	values[5]	values[3]	15	1			T22	3		T248	2		T166	2
auto[1]	values[5]	values[4]	11	1			T19	3		T79	2		T257	3
auto[1]	values[5]	values[5]	21	1			T49	2		T82	3		T79	2
auto[1]	values[5]	values[6]	13	1			T32	1		T244	6		T243	2
auto[1]	values[5]	values[7]	12	1			T204	4		T77	3		T246	1
auto[1]	values[6]	values[0]	15	1			T22	2		T236	2		T188	3
auto[1]	values[6]	values[1]	12	1			T38	1		T219	1		T188	1
auto[1]	values[6]	values[2]	12	1			T38	2		T201	1		T188	1
auto[1]	values[6]	values[3]	12	1			T265	6		T246	1		T142	1
auto[1]	values[6]	values[4]	19	1			T39	2		T139	1		T181	2
auto[1]	values[6]	values[5]	16	1			T5	1		T26	1		T245	1
auto[1]	values[6]	values[6]	11	1			T18	3		T246	1		T228	1
auto[1]	values[6]	values[7]	12	1			T243	2		T266	1		T142	3
auto[1]	values[7]	values[0]	12	1			T39	3		T248	5		T261	1
auto[1]	values[7]	values[1]	20	1			T9	1		T24	4		T38	1
auto[1]	values[7]	values[2]	24	1			T26	2		T22	2		T212	1
auto[1]	values[7]	values[3]	22	1			T37	3		T38	1		T58	2
auto[1]	values[7]	values[4]	11	1			T54	1		T210	2		T228	1
auto[1]	values[7]	values[5]	13	1			T49	1		T240	4		T244	2
auto[1]	values[7]	values[6]	10	1			T48	1		T190	1		T266	1
auto[1]	values[7]	values[7]	6	1			T39	2		T189	1		T256	1