Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	789	1			T9	11		T18	24		T19	24
all_values[1]	789	1			T9	11		T18	24		T19	24
all_values[2]	789	1			T9	11		T18	24		T19	24
all_values[3]	789	1			T9	11		T18	24		T19	24
all_values[4]	789	1			T9	11		T18	24		T19	24
all_values[5]	789	1			T9	11		T18	24		T19	24
all_values[6]	789	1			T9	11		T18	24		T19	24
all_values[7]	789	1			T9	11		T18	24		T19	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3321

1

T9

38

T18

103

T19

91

auto[1]

2991

1

T9

50

T18

89

T19

101

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2624

1

T9

38

T18

81

T19

63

auto[1]

3688

1

T9

50

T18

111

T19

129

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3654

1

T9

53

T18

110

T19

105

auto[1]

2658

1

T9

35

T18

82

T19

87

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	184	1			T9	2		T18	3		T19	2
all_values[0]	auto[0]	auto[0]	auto[1]	59	1			T18	3		T19	2		T77	2
all_values[0]	auto[0]	auto[1]	auto[0]	128	1			T9	6		T18	2		T19	4
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T18	2		T19	4		T21	1
all_values[0]	auto[1]	auto[0]	auto[1]	181	1			T9	1		T18	7		T19	5
all_values[0]	auto[1]	auto[1]	auto[1]	160	1			T9	2		T18	7		T19	7
all_values[1]	auto[0]	auto[0]	auto[0]	174	1			T9	1		T18	5		T20	2
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T9	2		T18	1		T19	5
all_values[1]	auto[0]	auto[1]	auto[0]	142	1			T9	4		T18	6		T19	1
all_values[1]	auto[0]	auto[1]	auto[1]	69	1			T18	1		T19	6		T20	2
all_values[1]	auto[1]	auto[0]	auto[1]	182	1			T9	2		T18	6		T19	5
all_values[1]	auto[1]	auto[1]	auto[1]	147	1			T9	2		T18	5		T19	7
all_values[2]	auto[0]	auto[0]	auto[0]	174	1			T9	3		T18	7		T19	2
all_values[2]	auto[0]	auto[0]	auto[1]	74	1			T9	1		T18	3		T19	3
all_values[2]	auto[0]	auto[1]	auto[0]	154	1			T9	1		T18	1		T19	3
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T9	1		T18	1		T19	5
all_values[2]	auto[1]	auto[0]	auto[1]	178	1			T9	2		T18	8		T19	6
all_values[2]	auto[1]	auto[1]	auto[1]	140	1			T9	3		T18	4		T19	5
all_values[3]	auto[0]	auto[0]	auto[0]	150	1			T9	4		T18	2		T19	3
all_values[3]	auto[0]	auto[0]	auto[1]	70	1			T9	3		T18	2		T19	3
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T18	4		T19	4		T20	2
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T18	3		T19	3		T20	4
all_values[3]	auto[1]	auto[0]	auto[1]	203	1			T9	1		T18	8		T19	7
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T9	3		T18	5		T19	4
all_values[4]	auto[0]	auto[0]	auto[0]	168	1			T9	1		T18	5		T19	5
all_values[4]	auto[0]	auto[0]	auto[1]	79	1			T9	1		T18	2		T20	3
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T9	3		T18	5		T19	6
all_values[4]	auto[0]	auto[1]	auto[1]	67	1			T18	4		T19	2		T21	1
all_values[4]	auto[1]	auto[0]	auto[1]	187	1			T9	5		T18	1		T19	7
all_values[4]	auto[1]	auto[1]	auto[1]	148	1			T9	1		T18	7		T19	4
all_values[5]	auto[0]	auto[0]	auto[0]	230	1			T9	1		T18	7		T19	5
all_values[5]	auto[0]	auto[1]	auto[0]	231	1			T9	7		T18	6		T19	4
all_values[5]	auto[1]	auto[0]	auto[1]	161	1			T9	1		T18	6		T19	5
all_values[5]	auto[1]	auto[1]	auto[1]	167	1			T9	2		T18	5		T19	10
all_values[6]	auto[0]	auto[0]	auto[0]	142	1			T18	9		T19	10		T77	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T18	2		T19	1		T21	4
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T18	7		T19	5		T20	1
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T9	3		T18	1		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	189	1			T9	2		T18	2		T19	4
all_values[6]	auto[1]	auto[1]	auto[1]	165	1			T9	6		T18	3		T19	3
all_values[7]	auto[0]	auto[0]	auto[0]	189	1			T9	1		T18	8		T19	4
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T9	2		T18	1		T19	3
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T9	4		T18	4		T19	5
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T9	2		T18	3		T19	4
all_values[7]	auto[1]	auto[0]	auto[1]	130	1			T9	2		T18	5		T19	4
all_values[7]	auto[1]	auto[1]	auto[1]	172	1			T18	3		T19	4		T20	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal