Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1693

1

T5

12

T9

9

T10

2

auto[1]

1686

1

T5

18

T9

10

T10

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1702

1

T5

23

T9

19

T13

7

auto[1]

1677

1

T5

7

T10

7

T11

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2737

1

T5

19

T9

9

T10

7

auto[1]

642

1

T5

11

T9

10

T13

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	687	1			T5	3		T9	7		T10	1
valid[1]	667	1			T5	6		T9	4		T24	3
valid[2]	692	1			T5	3		T9	2		T10	2
valid[3]	657	1			T5	8		T9	4		T10	3
valid[4]	676	1			T5	10		T9	2		T10	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	110	1			T9	2		T13	1		T27	1
auto[0]	auto[0]	valid[0]	auto[1]	164	1			T5	1		T89	2		T90	1
auto[0]	auto[0]	valid[1]	auto[0]	111	1			T5	1		T9	1		T24	3
auto[0]	auto[0]	valid[1]	auto[1]	164	1			T26	1		T89	1		T170	1
auto[0]	auto[0]	valid[2]	auto[0]	103	1			T9	1		T25	1		T52	1
auto[0]	auto[0]	valid[2]	auto[1]	169	1			T5	1		T11	1		T89	2
auto[0]	auto[0]	valid[3]	auto[0]	102	1			T5	1		T13	2		T26	1
auto[0]	auto[0]	valid[3]	auto[1]	155	1			T10	1		T89	1		T284	2
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T5	1		T9	2		T13	1
auto[0]	auto[0]	valid[4]	auto[1]	167	1			T10	1		T11	1		T26	1
auto[0]	auto[1]	valid[0]	auto[0]	100	1			T9	1		T24	4		T26	1
auto[0]	auto[1]	valid[0]	auto[1]	182	1			T5	1		T10	1		T26	1
auto[0]	auto[1]	valid[1]	auto[0]	111	1			T5	2		T9	1		T27	2
auto[0]	auto[1]	valid[1]	auto[1]	162	1			T5	1		T26	2		T90	1
auto[0]	auto[1]	valid[2]	auto[0]	107	1			T9	1		T13	1		T26	1
auto[0]	auto[1]	valid[2]	auto[1]	188	1			T5	1		T10	2		T26	1
auto[0]	auto[1]	valid[3]	auto[0]	97	1			T5	3		T24	1		T27	2
auto[0]	auto[1]	valid[3]	auto[1]	159	1			T10	2		T26	1		T89	1
auto[0]	auto[1]	valid[4]	auto[0]	102	1			T5	4		T51	1		T52	1
auto[0]	auto[1]	valid[4]	auto[1]	167	1			T5	2		T18	2		T90	1
auto[1]	auto[0]	valid[0]	auto[0]	75	1			T5	1		T9	2		T26	2
auto[1]	auto[0]	valid[1]	auto[0]	63	1			T5	2		T52	1		T18	1
auto[1]	auto[0]	valid[2]	auto[0]	58	1			T24	1		T27	3		T20	1
auto[1]	auto[0]	valid[3]	auto[0]	78	1			T5	2		T9	1		T24	1
auto[1]	auto[0]	valid[4]	auto[0]	57	1			T5	2		T13	1		T27	1
auto[1]	auto[1]	valid[0]	auto[0]	56	1			T9	2		T24	1		T27	2
auto[1]	auto[1]	valid[1]	auto[0]	56	1			T9	2		T26	2		T27	1
auto[1]	auto[1]	valid[2]	auto[0]	67	1			T5	1		T13	1		T26	1
auto[1]	auto[1]	valid[3]	auto[0]	66	1			T5	2		T9	3		T26	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T5	1		T27	1		T51	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal