Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47278

1

T5

814

T9

458

T13

216

auto[1]

17419

1

T5

70

T9

18

T10

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47272

1

T5

595

T9

294

T10

7

auto[1]

17425

1

T5

289

T9

182

T13

79

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33255	1			T5	483		T9	227		T10	7
others[1]	5499	1			T5	70		T9	34		T13	27
others[2]	5550	1			T5	69		T9	37		T13	20
others[3]	6205	1			T5	65		T9	57		T13	26
interest[1]	3468	1			T5	49		T9	33		T13	8
interest[4]	21788	1			T5	319		T9	151		T10	7
interest[64]	10720	1			T5	148		T9	88		T13	39

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15234	1			T5	292		T9	123		T13	59
auto[0]	auto[0]	others[1]	2563	1			T5	39		T9	23		T13	16
auto[0]	auto[0]	others[2]	2589	1			T5	45		T9	24		T13	13
auto[0]	auto[0]	others[3]	2865	1			T5	31		T9	37		T13	16
auto[0]	auto[0]	interest[1]	1628	1			T5	28		T9	18		T13	4
auto[0]	auto[0]	interest[4]	9903	1			T5	194		T9	82		T13	45
auto[0]	auto[0]	interest[64]	4974	1			T5	90		T9	51		T13	29
auto[0]	auto[1]	others[0]	9078	1			T5	31		T9	5		T10	7
auto[0]	auto[1]	others[1]	1468	1			T5	7		T9	2		T26	7
auto[0]	auto[1]	others[2]	1416	1			T5	5		T9	1		T26	8
auto[0]	auto[1]	others[3]	1673	1			T5	8		T26	9		T18	6
auto[0]	auto[1]	interest[1]	889	1			T5	5		T9	3		T26	2
auto[0]	auto[1]	interest[4]	5970	1			T5	21		T9	4		T10	7
auto[0]	auto[1]	interest[64]	2895	1			T5	14		T9	7		T26	20
auto[1]	auto[0]	others[0]	8943	1			T5	160		T9	99		T13	37
auto[1]	auto[0]	others[1]	1468	1			T5	24		T9	9		T13	11
auto[1]	auto[0]	others[2]	1545	1			T5	19		T9	12		T13	7
auto[1]	auto[0]	others[3]	1667	1			T5	26		T9	20		T13	10
auto[1]	auto[0]	interest[1]	951	1			T5	16		T9	12		T13	4
auto[1]	auto[0]	interest[4]	5915	1			T5	104		T9	65		T13	27
auto[1]	auto[0]	interest[64]	2851	1			T5	44		T9	30		T13	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal