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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.45 94.10 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
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T121 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2073848178 Jul 03 06:06:18 PM PDT 24 Jul 03 06:06:20 PM PDT 24 146878519 ps
T100 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1454018866 Jul 03 06:05:53 PM PDT 24 Jul 03 06:06:13 PM PDT 24 844434994 ps
T1047 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4114765083 Jul 03 06:06:18 PM PDT 24 Jul 03 06:06:21 PM PDT 24 158350071 ps
T118 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1021624985 Jul 03 06:05:56 PM PDT 24 Jul 03 06:06:10 PM PDT 24 199493562 ps
T1048 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2477477934 Jul 03 06:06:13 PM PDT 24 Jul 03 06:06:14 PM PDT 24 69606552 ps
T1049 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.122589002 Jul 03 06:06:15 PM PDT 24 Jul 03 06:06:16 PM PDT 24 40466575 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2181562441 Jul 03 06:06:08 PM PDT 24 Jul 03 06:06:09 PM PDT 24 91379627 ps
T1051 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2393099821 Jul 03 06:06:19 PM PDT 24 Jul 03 06:06:20 PM PDT 24 35937619 ps
T122 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.592220095 Jul 03 06:05:38 PM PDT 24 Jul 03 06:05:41 PM PDT 24 136865193 ps
T120 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3871899762 Jul 03 06:05:40 PM PDT 24 Jul 03 06:05:49 PM PDT 24 594621597 ps
T1052 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2568330059 Jul 03 06:06:14 PM PDT 24 Jul 03 06:06:15 PM PDT 24 24849625 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2188192823 Jul 03 06:05:42 PM PDT 24 Jul 03 06:05:50 PM PDT 24 108452263 ps
T119 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2981132259 Jul 03 06:05:55 PM PDT 24 Jul 03 06:06:15 PM PDT 24 296472064 ps
T1054 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.888279652 Jul 03 06:06:17 PM PDT 24 Jul 03 06:06:18 PM PDT 24 41692642 ps
T108 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2628951493 Jul 03 06:06:08 PM PDT 24 Jul 03 06:06:11 PM PDT 24 373326997 ps
T116 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1741504133 Jul 03 06:06:00 PM PDT 24 Jul 03 06:06:03 PM PDT 24 37181766 ps
T1055 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2123362925 Jul 03 06:06:08 PM PDT 24 Jul 03 06:06:12 PM PDT 24 66109909 ps
T161 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2201064021 Jul 03 06:06:04 PM PDT 24 Jul 03 06:06:07 PM PDT 24 84384905 ps
T162 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3856452971 Jul 03 06:06:08 PM PDT 24 Jul 03 06:06:11 PM PDT 24 413221655 ps
T123 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.509380532 Jul 03 06:06:09 PM PDT 24 Jul 03 06:06:13 PM PDT 24 345757940 ps
T101 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2168910280 Jul 03 06:05:49 PM PDT 24 Jul 03 06:05:53 PM PDT 24 815697826 ps
T1056 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1920961180 Jul 03 06:06:14 PM PDT 24 Jul 03 06:06:15 PM PDT 24 17736548 ps
T1057 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3492679181 Jul 03 06:05:48 PM PDT 24 Jul 03 06:05:49 PM PDT 24 21098919 ps
T1058 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3605488057 Jul 03 06:06:14 PM PDT 24 Jul 03 06:06:15 PM PDT 24 100752884 ps
T1059 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3269141993 Jul 03 06:06:14 PM PDT 24 Jul 03 06:06:15 PM PDT 24 14076012 ps
T102 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3102168129 Jul 03 06:05:56 PM PDT 24 Jul 03 06:06:00 PM PDT 24 124870643 ps
T107 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3518291134 Jul 03 06:05:46 PM PDT 24 Jul 03 06:05:48 PM PDT 24 161733899 ps
T1060 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.964547048 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:03 PM PDT 24 15509087 ps
T1061 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3148872561 Jul 03 06:06:09 PM PDT 24 Jul 03 06:06:11 PM PDT 24 219451013 ps
T1062 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2097775664 Jul 03 06:06:10 PM PDT 24 Jul 03 06:06:11 PM PDT 24 73364815 ps
T1063 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3538021747 Jul 03 06:06:04 PM PDT 24 Jul 03 06:06:11 PM PDT 24 2181528890 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4030026485 Jul 03 06:05:48 PM PDT 24 Jul 03 06:05:50 PM PDT 24 41351283 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3945295304 Jul 03 06:05:34 PM PDT 24 Jul 03 06:05:36 PM PDT 24 10935220 ps
T1065 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1432562696 Jul 03 06:05:37 PM PDT 24 Jul 03 06:05:38 PM PDT 24 27330218 ps
T113 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2539288465 Jul 03 06:06:03 PM PDT 24 Jul 03 06:06:05 PM PDT 24 63684374 ps
T125 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1315363768 Jul 03 06:05:42 PM PDT 24 Jul 03 06:05:45 PM PDT 24 444164787 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1340004326 Jul 03 06:05:37 PM PDT 24 Jul 03 06:05:39 PM PDT 24 69868323 ps
T127 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3824730405 Jul 03 06:05:59 PM PDT 24 Jul 03 06:06:02 PM PDT 24 200641779 ps
T163 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2000280081 Jul 03 06:05:52 PM PDT 24 Jul 03 06:05:56 PM PDT 24 152628939 ps
T164 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1103780746 Jul 03 06:05:53 PM PDT 24 Jul 03 06:05:56 PM PDT 24 125615786 ps
T1066 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3606227001 Jul 03 06:05:57 PM PDT 24 Jul 03 06:05:59 PM PDT 24 82930202 ps
T165 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3387913469 Jul 03 06:05:54 PM PDT 24 Jul 03 06:05:59 PM PDT 24 179654094 ps
T85 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2756484280 Jul 03 06:05:49 PM PDT 24 Jul 03 06:05:50 PM PDT 24 23050446 ps
T1067 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2521471559 Jul 03 06:06:07 PM PDT 24 Jul 03 06:06:09 PM PDT 24 52313902 ps
T128 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3105913258 Jul 03 06:05:37 PM PDT 24 Jul 03 06:05:40 PM PDT 24 75072380 ps
T1068 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.729370082 Jul 03 06:06:10 PM PDT 24 Jul 03 06:06:12 PM PDT 24 19236035 ps
T1069 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2785697101 Jul 03 06:06:17 PM PDT 24 Jul 03 06:06:18 PM PDT 24 14138128 ps
T1070 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3224815148 Jul 03 06:06:15 PM PDT 24 Jul 03 06:06:18 PM PDT 24 169056550 ps
T103 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2613941303 Jul 03 06:05:52 PM PDT 24 Jul 03 06:05:55 PM PDT 24 35937889 ps
T169 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1241384356 Jul 03 06:06:01 PM PDT 24 Jul 03 06:06:05 PM PDT 24 584629134 ps
T174 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2026747643 Jul 03 06:05:44 PM PDT 24 Jul 03 06:06:00 PM PDT 24 11169191027 ps
T1071 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2359579353 Jul 03 06:06:04 PM PDT 24 Jul 03 06:06:08 PM PDT 24 58932794 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4120412298 Jul 03 06:05:43 PM PDT 24 Jul 03 06:05:44 PM PDT 24 19590464 ps
T1073 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.293442761 Jul 03 06:06:11 PM PDT 24 Jul 03 06:06:12 PM PDT 24 28884179 ps
T1074 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.949279213 Jul 03 06:06:03 PM PDT 24 Jul 03 06:06:04 PM PDT 24 55532426 ps
T129 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3402983083 Jul 03 06:05:41 PM PDT 24 Jul 03 06:05:44 PM PDT 24 117370891 ps
T130 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1418146755 Jul 03 06:06:03 PM PDT 24 Jul 03 06:06:06 PM PDT 24 308708545 ps
T1075 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3653745989 Jul 03 06:05:55 PM PDT 24 Jul 03 06:05:59 PM PDT 24 123268942 ps
T1076 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1363143422 Jul 03 06:05:55 PM PDT 24 Jul 03 06:05:56 PM PDT 24 50242543 ps
T1077 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2878595522 Jul 03 06:05:58 PM PDT 24 Jul 03 06:06:02 PM PDT 24 311665913 ps
T1078 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.655792125 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:05 PM PDT 24 403680597 ps
T1079 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1834236483 Jul 03 06:06:07 PM PDT 24 Jul 03 06:06:08 PM PDT 24 17627394 ps
T112 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1532577542 Jul 03 06:06:18 PM PDT 24 Jul 03 06:06:20 PM PDT 24 167406659 ps
T172 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.444625723 Jul 03 06:06:08 PM PDT 24 Jul 03 06:06:29 PM PDT 24 11256771725 ps
T104 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.596439423 Jul 03 06:05:57 PM PDT 24 Jul 03 06:05:59 PM PDT 24 99598174 ps
T1080 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2677948634 Jul 03 06:06:05 PM PDT 24 Jul 03 06:06:21 PM PDT 24 690740991 ps
T131 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3179459918 Jul 03 06:05:50 PM PDT 24 Jul 03 06:05:54 PM PDT 24 126298865 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3220485523 Jul 03 06:05:37 PM PDT 24 Jul 03 06:05:40 PM PDT 24 849904033 ps
T105 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1800052360 Jul 03 06:05:53 PM PDT 24 Jul 03 06:05:55 PM PDT 24 25535955 ps
T1082 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2344512642 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:07 PM PDT 24 57593800 ps
T173 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1012051409 Jul 03 06:05:51 PM PDT 24 Jul 03 06:06:05 PM PDT 24 781400276 ps
T1083 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4039058029 Jul 03 06:06:13 PM PDT 24 Jul 03 06:06:14 PM PDT 24 44297662 ps
T1084 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2938076051 Jul 03 06:06:15 PM PDT 24 Jul 03 06:06:16 PM PDT 24 54947704 ps
T109 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3534708555 Jul 03 06:06:17 PM PDT 24 Jul 03 06:06:30 PM PDT 24 3408372495 ps
T1085 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2003256835 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:03 PM PDT 24 53358910 ps
T1086 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3140986226 Jul 03 06:06:14 PM PDT 24 Jul 03 06:06:19 PM PDT 24 464573333 ps
T1087 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1206956567 Jul 03 06:05:35 PM PDT 24 Jul 03 06:05:38 PM PDT 24 157781827 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2142099186 Jul 03 06:05:34 PM PDT 24 Jul 03 06:05:42 PM PDT 24 197503838 ps
T1089 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4042209129 Jul 03 06:05:35 PM PDT 24 Jul 03 06:05:47 PM PDT 24 1246976651 ps
T1090 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1136985998 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:06 PM PDT 24 233988106 ps
T175 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1208484115 Jul 03 06:06:05 PM PDT 24 Jul 03 06:06:25 PM PDT 24 314184473 ps
T1091 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1836188005 Jul 03 06:05:42 PM PDT 24 Jul 03 06:06:17 PM PDT 24 740562173 ps
T1092 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2862874399 Jul 03 06:06:07 PM PDT 24 Jul 03 06:06:08 PM PDT 24 99769286 ps
T132 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.951684759 Jul 03 06:05:50 PM PDT 24 Jul 03 06:05:52 PM PDT 24 172754562 ps
T1093 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.497958527 Jul 03 06:05:37 PM PDT 24 Jul 03 06:05:40 PM PDT 24 98726895 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2735194630 Jul 03 06:05:34 PM PDT 24 Jul 03 06:05:36 PM PDT 24 15572930 ps
T1095 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1723126703 Jul 03 06:06:13 PM PDT 24 Jul 03 06:06:14 PM PDT 24 23803602 ps
T1096 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2681521494 Jul 03 06:06:09 PM PDT 24 Jul 03 06:06:12 PM PDT 24 42239590 ps
T176 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.449579395 Jul 03 06:06:06 PM PDT 24 Jul 03 06:06:25 PM PDT 24 302484316 ps
T115 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1437054103 Jul 03 06:06:04 PM PDT 24 Jul 03 06:06:06 PM PDT 24 109176042 ps
T1097 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.124800416 Jul 03 06:06:12 PM PDT 24 Jul 03 06:06:13 PM PDT 24 55005044 ps
T1098 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.377973749 Jul 03 06:05:37 PM PDT 24 Jul 03 06:05:41 PM PDT 24 189260222 ps
T1099 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2712068260 Jul 03 06:06:13 PM PDT 24 Jul 03 06:06:14 PM PDT 24 13771002 ps
T1100 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4115868375 Jul 03 06:05:37 PM PDT 24 Jul 03 06:05:38 PM PDT 24 16231366 ps
T1101 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2343417425 Jul 03 06:06:09 PM PDT 24 Jul 03 06:06:13 PM PDT 24 321738864 ps
T1102 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2123442993 Jul 03 06:06:15 PM PDT 24 Jul 03 06:06:16 PM PDT 24 19258666 ps
T133 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3885925711 Jul 03 06:05:51 PM PDT 24 Jul 03 06:05:54 PM PDT 24 51269658 ps
T1103 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3845169635 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:03 PM PDT 24 15072764 ps
T1104 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2849202891 Jul 03 06:06:03 PM PDT 24 Jul 03 06:06:07 PM PDT 24 371207711 ps
T1105 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3398357053 Jul 03 06:06:10 PM PDT 24 Jul 03 06:06:11 PM PDT 24 18033398 ps
T86 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3480001892 Jul 03 06:05:38 PM PDT 24 Jul 03 06:05:40 PM PDT 24 72115669 ps
T1106 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1186716988 Jul 03 06:05:55 PM PDT 24 Jul 03 06:05:58 PM PDT 24 975146836 ps
T1107 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1031815121 Jul 03 06:06:17 PM PDT 24 Jul 03 06:06:19 PM PDT 24 282204154 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4044702648 Jul 03 06:05:48 PM PDT 24 Jul 03 06:06:24 PM PDT 24 3607949912 ps
T1109 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1944112391 Jul 03 06:05:35 PM PDT 24 Jul 03 06:05:36 PM PDT 24 10932379 ps
T1110 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3575590668 Jul 03 06:05:35 PM PDT 24 Jul 03 06:05:39 PM PDT 24 234389964 ps
T1111 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.12895787 Jul 03 06:06:03 PM PDT 24 Jul 03 06:06:07 PM PDT 24 451602737 ps
T1112 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.780293802 Jul 03 06:06:00 PM PDT 24 Jul 03 06:06:01 PM PDT 24 41941681 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3644468548 Jul 03 06:06:03 PM PDT 24 Jul 03 06:06:08 PM PDT 24 145517309 ps
T1114 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3244285442 Jul 03 06:06:09 PM PDT 24 Jul 03 06:06:12 PM PDT 24 190363560 ps
T1115 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3375437108 Jul 03 06:06:06 PM PDT 24 Jul 03 06:06:12 PM PDT 24 102677087 ps
T1116 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3636962334 Jul 03 06:06:14 PM PDT 24 Jul 03 06:06:16 PM PDT 24 14097287 ps
T1117 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1955975792 Jul 03 06:05:44 PM PDT 24 Jul 03 06:06:07 PM PDT 24 2075758669 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2328842355 Jul 03 06:05:45 PM PDT 24 Jul 03 06:05:46 PM PDT 24 13692317 ps
T1119 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.781790377 Jul 03 06:05:44 PM PDT 24 Jul 03 06:05:47 PM PDT 24 331278812 ps
T1120 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.366422048 Jul 03 06:06:03 PM PDT 24 Jul 03 06:06:06 PM PDT 24 139346429 ps
T1121 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1645282523 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:05 PM PDT 24 34061696 ps
T1122 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1269265481 Jul 03 06:06:00 PM PDT 24 Jul 03 06:06:03 PM PDT 24 38288488 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3985346075 Jul 03 06:05:39 PM PDT 24 Jul 03 06:05:42 PM PDT 24 43590238 ps
T106 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3207215468 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:05 PM PDT 24 43635018 ps
T1124 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3640967914 Jul 03 06:06:13 PM PDT 24 Jul 03 06:06:14 PM PDT 24 17177684 ps
T1125 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1980315344 Jul 03 06:06:00 PM PDT 24 Jul 03 06:06:03 PM PDT 24 97378619 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1831368032 Jul 03 06:05:36 PM PDT 24 Jul 03 06:05:40 PM PDT 24 176418808 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3804050438 Jul 03 06:05:42 PM PDT 24 Jul 03 06:05:46 PM PDT 24 172292395 ps
T1127 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.39762828 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:04 PM PDT 24 62006259 ps
T1128 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1805007304 Jul 03 06:05:43 PM PDT 24 Jul 03 06:06:22 PM PDT 24 1809640964 ps
T1129 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.370772574 Jul 03 06:05:49 PM PDT 24 Jul 03 06:05:58 PM PDT 24 373736463 ps
T1130 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2130276691 Jul 03 06:05:34 PM PDT 24 Jul 03 06:05:50 PM PDT 24 2846936015 ps
T111 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2389489435 Jul 03 06:06:02 PM PDT 24 Jul 03 06:06:05 PM PDT 24 120991678 ps
T1131 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3176694367 Jul 03 06:06:06 PM PDT 24 Jul 03 06:06:10 PM PDT 24 164169919 ps
T1132 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.447956910 Jul 03 06:06:09 PM PDT 24 Jul 03 06:06:11 PM PDT 24 39566064 ps
T1133 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4170084936 Jul 03 06:05:51 PM PDT 24 Jul 03 06:05:52 PM PDT 24 281368888 ps
T1134 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3462564290 Jul 03 06:06:00 PM PDT 24 Jul 03 06:06:16 PM PDT 24 576766421 ps
T171 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.607384479 Jul 03 06:05:35 PM PDT 24 Jul 03 06:05:39 PM PDT 24 878654838 ps
T1135 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4218234238 Jul 03 06:06:09 PM PDT 24 Jul 03 06:06:10 PM PDT 24 14866296 ps
T1136 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3563912733 Jul 03 06:06:14 PM PDT 24 Jul 03 06:06:16 PM PDT 24 37935584 ps
T1137 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2323405860 Jul 03 06:06:04 PM PDT 24 Jul 03 06:06:05 PM PDT 24 13922120 ps
T1138 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3095008896 Jul 03 06:06:13 PM PDT 24 Jul 03 06:06:14 PM PDT 24 18866586 ps
T1139 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1947460422 Jul 03 06:05:49 PM PDT 24 Jul 03 06:05:53 PM PDT 24 193603953 ps
T1140 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2371130623 Jul 03 06:06:18 PM PDT 24 Jul 03 06:06:36 PM PDT 24 1189224689 ps
T1141 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.110268951 Jul 03 06:05:40 PM PDT 24 Jul 03 06:05:49 PM PDT 24 345926193 ps
T1142 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3623110604 Jul 03 06:06:15 PM PDT 24 Jul 03 06:06:16 PM PDT 24 46360754 ps
T1143 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2730605654 Jul 03 06:05:59 PM PDT 24 Jul 03 06:06:17 PM PDT 24 2822150907 ps
T1144 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2522956291 Jul 03 06:06:10 PM PDT 24 Jul 03 06:06:11 PM PDT 24 21437224 ps
T1145 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1611291822 Jul 03 06:05:42 PM PDT 24 Jul 03 06:05:45 PM PDT 24 383130761 ps
T1146 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3796903107 Jul 03 06:05:53 PM PDT 24 Jul 03 06:05:54 PM PDT 24 90653810 ps
T1147 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4175986805 Jul 03 06:05:45 PM PDT 24 Jul 03 06:05:49 PM PDT 24 82469634 ps
T1148 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.656275981 Jul 03 06:05:43 PM PDT 24 Jul 03 06:05:53 PM PDT 24 3555134956 ps
T1149 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1266236728 Jul 03 06:05:39 PM PDT 24 Jul 03 06:06:08 PM PDT 24 1874863649 ps
T1150 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3779057739 Jul 03 06:06:06 PM PDT 24 Jul 03 06:06:09 PM PDT 24 89095639 ps
T1151 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1235453837 Jul 03 06:06:06 PM PDT 24 Jul 03 06:06:08 PM PDT 24 32999542 ps

Test location /workspace/coverage/default/48.spi_device_stress_all.2783477856
Short name T9
Test name
Test status
Simulation time 31899492921 ps
CPU time 294.68 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:09:30 PM PDT 24
Peak memory 274872 kb
Host smart-c48b3d13-1878-4ba5-95a3-c188fa649f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783477856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2783477856
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.186099755
Short name T24
Test name
Test status
Simulation time 11698630760 ps
CPU time 76.43 seconds
Started Jul 03 06:04:08 PM PDT 24
Finished Jul 03 06:05:25 PM PDT 24
Peak memory 253240 kb
Host smart-709ec776-e705-4925-9919-92f4453433f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186099755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.186099755
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.684727037
Short name T99
Test name
Test status
Simulation time 966914875 ps
CPU time 20.29 seconds
Started Jul 03 06:05:37 PM PDT 24
Finished Jul 03 06:05:57 PM PDT 24
Peak memory 216932 kb
Host smart-6869070a-e27f-4b4a-bb1b-db8902b96ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684727037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.684727037
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.29496342
Short name T18
Test name
Test status
Simulation time 18503398460 ps
CPU time 228.72 seconds
Started Jul 03 06:01:15 PM PDT 24
Finished Jul 03 06:05:04 PM PDT 24
Peak memory 250404 kb
Host smart-6284dbb2-3054-4a0c-afe8-54d6e1288f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_
all.29496342
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.991825048
Short name T22
Test name
Test status
Simulation time 51018856510 ps
CPU time 506.54 seconds
Started Jul 03 06:03:55 PM PDT 24
Finished Jul 03 06:12:22 PM PDT 24
Peak memory 286124 kb
Host smart-f58c1edf-68ee-454c-a570-8fb67bc49167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991825048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.991825048
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1539191535
Short name T67
Test name
Test status
Simulation time 20500124 ps
CPU time 0.73 seconds
Started Jul 03 06:00:44 PM PDT 24
Finished Jul 03 06:00:45 PM PDT 24
Peak memory 216996 kb
Host smart-c52457c3-bf1c-4e3e-91b2-753b8f06b9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539191535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1539191535
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2547404427
Short name T5
Test name
Test status
Simulation time 20639760326 ps
CPU time 253.49 seconds
Started Jul 03 06:04:25 PM PDT 24
Finished Jul 03 06:08:39 PM PDT 24
Peak memory 266416 kb
Host smart-62d76ffa-465b-49a5-adc8-8a0572d2e457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547404427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2547404427
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.470635463
Short name T228
Test name
Test status
Simulation time 246160496492 ps
CPU time 1077.2 seconds
Started Jul 03 06:02:27 PM PDT 24
Finished Jul 03 06:20:25 PM PDT 24
Peak memory 273016 kb
Host smart-175af22f-ed14-41e7-b418-221fe257d203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470635463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.470635463
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1091547215
Short name T38
Test name
Test status
Simulation time 3027889053 ps
CPU time 71.12 seconds
Started Jul 03 06:03:04 PM PDT 24
Finished Jul 03 06:04:16 PM PDT 24
Peak memory 258372 kb
Host smart-a73e955a-7bd0-4f99-99ed-a24f8b5943f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091547215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1091547215
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2228718056
Short name T30
Test name
Test status
Simulation time 133006745812 ps
CPU time 230.55 seconds
Started Jul 03 06:03:28 PM PDT 24
Finished Jul 03 06:07:19 PM PDT 24
Peak memory 275008 kb
Host smart-c0dce543-0ed5-48dc-ac64-e1314bbc0396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228718056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2228718056
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1864143754
Short name T68
Test name
Test status
Simulation time 40415034 ps
CPU time 1.04 seconds
Started Jul 03 06:00:59 PM PDT 24
Finished Jul 03 06:01:00 PM PDT 24
Peak memory 236348 kb
Host smart-0f133050-1108-4c30-92b4-7252dbff090f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864143754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1864143754
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2815629849
Short name T151
Test name
Test status
Simulation time 3083232541 ps
CPU time 18.35 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:36 PM PDT 24
Peak memory 250296 kb
Host smart-2bd6078b-c378-4628-b281-a0e91757fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815629849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2815629849
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3117145410
Short name T82
Test name
Test status
Simulation time 64657815681 ps
CPU time 585.11 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:12:02 PM PDT 24
Peak memory 274680 kb
Host smart-bb99596c-3aa9-4d6c-b066-e1527cb9ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117145410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3117145410
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2168910280
Short name T101
Test name
Test status
Simulation time 815697826 ps
CPU time 4.28 seconds
Started Jul 03 06:05:49 PM PDT 24
Finished Jul 03 06:05:53 PM PDT 24
Peak memory 215604 kb
Host smart-92350b9f-64a1-4584-a7d8-944010062b93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168910280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
168910280
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2976990378
Short name T202
Test name
Test status
Simulation time 27457384599 ps
CPU time 225.59 seconds
Started Jul 03 06:01:57 PM PDT 24
Finished Jul 03 06:05:43 PM PDT 24
Peak memory 250552 kb
Host smart-cd930bd8-b014-48bd-a397-8b0608e05ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976990378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2976990378
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1028233338
Short name T240
Test name
Test status
Simulation time 140049362470 ps
CPU time 625.62 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:12:40 PM PDT 24
Peak memory 266808 kb
Host smart-93e04851-5dc4-4e17-84cf-355908ce3f7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028233338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1028233338
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2756484280
Short name T85
Test name
Test status
Simulation time 23050446 ps
CPU time 1.37 seconds
Started Jul 03 06:05:49 PM PDT 24
Finished Jul 03 06:05:50 PM PDT 24
Peak memory 207376 kb
Host smart-25161d18-a915-41ca-a4d2-ed6f13247c3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756484280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2756484280
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1165691717
Short name T31
Test name
Test status
Simulation time 77201890436 ps
CPU time 736.99 seconds
Started Jul 03 06:02:40 PM PDT 24
Finished Jul 03 06:14:58 PM PDT 24
Peak memory 274076 kb
Host smart-961fcb1e-aa32-490d-adf4-d678a36dcc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165691717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1165691717
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4134379104
Short name T200
Test name
Test status
Simulation time 46189358993 ps
CPU time 158.41 seconds
Started Jul 03 06:03:20 PM PDT 24
Finished Jul 03 06:05:59 PM PDT 24
Peak memory 272896 kb
Host smart-a0900a4a-9d37-4a58-8fb8-70a71ef7027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134379104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4134379104
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2744835473
Short name T515
Test name
Test status
Simulation time 27359544 ps
CPU time 1.04 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:01:39 PM PDT 24
Peak memory 217644 kb
Host smart-48e60059-2a90-4df7-9e4d-41613f5fa360
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744835473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2744835473
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1983386220
Short name T142
Test name
Test status
Simulation time 30022694999 ps
CPU time 121.55 seconds
Started Jul 03 06:04:42 PM PDT 24
Finished Jul 03 06:06:44 PM PDT 24
Peak memory 266764 kb
Host smart-08834dd4-d091-4c65-8557-769207bdfabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983386220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1983386220
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2947690600
Short name T79
Test name
Test status
Simulation time 38141565913 ps
CPU time 127.66 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:04:08 PM PDT 24
Peak memory 266672 kb
Host smart-326750ea-c80a-41d7-908a-cf7b21acc4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947690600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2947690600
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1690138115
Short name T166
Test name
Test status
Simulation time 16498922493 ps
CPU time 191.94 seconds
Started Jul 03 06:01:53 PM PDT 24
Finished Jul 03 06:05:05 PM PDT 24
Peak memory 257604 kb
Host smart-296825ee-cb43-4007-aa4d-5a1ff8983ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690138115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1690138115
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1445653629
Short name T197
Test name
Test status
Simulation time 30646465386 ps
CPU time 256.35 seconds
Started Jul 03 06:02:49 PM PDT 24
Finished Jul 03 06:07:05 PM PDT 24
Peak memory 251344 kb
Host smart-b4affee8-3dbd-457a-8e11-a38432747151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445653629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1445653629
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4200902911
Short name T54
Test name
Test status
Simulation time 16386173074 ps
CPU time 68.19 seconds
Started Jul 03 06:03:59 PM PDT 24
Finished Jul 03 06:05:08 PM PDT 24
Peak memory 254452 kb
Host smart-0b3244d7-c2c8-444b-b2bf-eebb8e03a784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200902911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4200902911
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.64685172
Short name T248
Test name
Test status
Simulation time 64658260777 ps
CPU time 212.87 seconds
Started Jul 03 06:02:10 PM PDT 24
Finished Jul 03 06:05:44 PM PDT 24
Peak memory 263356 kb
Host smart-fee0c94a-951c-4bcf-86b0-270ea412e973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64685172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.64685172
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1039505135
Short name T66
Test name
Test status
Simulation time 44486992 ps
CPU time 0.72 seconds
Started Jul 03 06:00:52 PM PDT 24
Finished Jul 03 06:00:53 PM PDT 24
Peak memory 206392 kb
Host smart-b2f6efce-8be2-41ad-91bd-552866c5fb8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039505135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
039505135
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.445456479
Short name T32
Test name
Test status
Simulation time 234156845044 ps
CPU time 592.52 seconds
Started Jul 03 06:02:39 PM PDT 24
Finished Jul 03 06:12:32 PM PDT 24
Peak memory 273964 kb
Host smart-cfbd21cb-d0dc-44cf-934e-bc1d9df577bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445456479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.445456479
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1021624985
Short name T118
Test name
Test status
Simulation time 199493562 ps
CPU time 13.61 seconds
Started Jul 03 06:05:56 PM PDT 24
Finished Jul 03 06:06:10 PM PDT 24
Peak memory 222896 kb
Host smart-1df16db5-3787-47c1-99a1-870dcb51c595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021624985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1021624985
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1136985998
Short name T1090
Test name
Test status
Simulation time 233988106 ps
CPU time 4.52 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:06 PM PDT 24
Peak memory 215836 kb
Host smart-f0e1c6c0-cbbb-4f93-b2e1-cb025cb24668
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136985998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
136985998
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.494801917
Short name T269
Test name
Test status
Simulation time 23823105318 ps
CPU time 41.83 seconds
Started Jul 03 06:01:54 PM PDT 24
Finished Jul 03 06:02:36 PM PDT 24
Peak memory 237456 kb
Host smart-6253f01a-fcef-4d67-a983-003186ef4c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494801917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.494801917
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1503568349
Short name T207
Test name
Test status
Simulation time 3901796028 ps
CPU time 48.44 seconds
Started Jul 03 06:01:52 PM PDT 24
Finished Jul 03 06:02:41 PM PDT 24
Peak memory 252324 kb
Host smart-b28c38bf-d055-4c84-b0e1-066a4abc7064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503568349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1503568349
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1943364644
Short name T254
Test name
Test status
Simulation time 12325662340 ps
CPU time 166.39 seconds
Started Jul 03 06:02:47 PM PDT 24
Finished Jul 03 06:05:33 PM PDT 24
Peak memory 271100 kb
Host smart-8b3d02c1-57df-48fc-87be-d861b0bc1490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943364644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1943364644
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2192583581
Short name T262
Test name
Test status
Simulation time 77512635338 ps
CPU time 404.6 seconds
Started Jul 03 06:03:12 PM PDT 24
Finished Jul 03 06:09:57 PM PDT 24
Peak memory 285184 kb
Host smart-738ca1b9-9f3c-4c22-afed-a5219130e825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192583581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2192583581
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1225754799
Short name T878
Test name
Test status
Simulation time 139866355416 ps
CPU time 190.8 seconds
Started Jul 03 06:01:13 PM PDT 24
Finished Jul 03 06:04:24 PM PDT 24
Peak memory 271584 kb
Host smart-f02b9568-fbf0-4b7d-b998-e73374b075c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225754799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1225754799
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2217015323
Short name T252
Test name
Test status
Simulation time 97986200103 ps
CPU time 172.33 seconds
Started Jul 03 06:01:28 PM PDT 24
Finished Jul 03 06:04:21 PM PDT 24
Peak memory 255708 kb
Host smart-3a936c88-a11a-4e1d-bec3-1ad5badb1f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217015323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2217015323
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.56018337
Short name T285
Test name
Test status
Simulation time 93637893696 ps
CPU time 186.47 seconds
Started Jul 03 06:01:40 PM PDT 24
Finished Jul 03 06:04:47 PM PDT 24
Peak memory 242268 kb
Host smart-67c337e7-5a4f-44ae-b620-c90b752e4458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56018337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.56018337
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3518291134
Short name T107
Test name
Test status
Simulation time 161733899 ps
CPU time 2.58 seconds
Started Jul 03 06:05:46 PM PDT 24
Finished Jul 03 06:05:48 PM PDT 24
Peak memory 215748 kb
Host smart-17430b8f-a4d0-48c3-be41-35066ecc9054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518291134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
518291134
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2347096457
Short name T259
Test name
Test status
Simulation time 15192649554 ps
CPU time 13.2 seconds
Started Jul 03 06:03:09 PM PDT 24
Finished Jul 03 06:03:23 PM PDT 24
Peak memory 234000 kb
Host smart-5513bc37-0d58-45ea-9ec8-f357a24ef5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347096457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2347096457
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3433593124
Short name T26
Test name
Test status
Simulation time 20054888996 ps
CPU time 159.88 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:06:01 PM PDT 24
Peak memory 274424 kb
Host smart-bfe105d6-e854-410f-bf48-0c158439a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433593124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3433593124
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1208484115
Short name T175
Test name
Test status
Simulation time 314184473 ps
CPU time 19.78 seconds
Started Jul 03 06:06:05 PM PDT 24
Finished Jul 03 06:06:25 PM PDT 24
Peak memory 215668 kb
Host smart-53c1f467-c639-4993-a562-3433e5afd322
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208484115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1208484115
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.444625723
Short name T172
Test name
Test status
Simulation time 11256771725 ps
CPU time 20.54 seconds
Started Jul 03 06:06:08 PM PDT 24
Finished Jul 03 06:06:29 PM PDT 24
Peak memory 215676 kb
Host smart-35cb3ec3-c838-4273-b885-00cffe3a520a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444625723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.444625723
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1131285755
Short name T178
Test name
Test status
Simulation time 752400176 ps
CPU time 6.12 seconds
Started Jul 03 06:00:52 PM PDT 24
Finished Jul 03 06:00:59 PM PDT 24
Peak memory 225492 kb
Host smart-92b18e86-3fb3-4c4c-ac3a-4c1a10eadc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131285755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1131285755
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2055945885
Short name T859
Test name
Test status
Simulation time 94804853392 ps
CPU time 129.82 seconds
Started Jul 03 06:01:32 PM PDT 24
Finished Jul 03 06:03:42 PM PDT 24
Peak memory 251344 kb
Host smart-3e130dcd-6e9b-491b-8fd3-f464af3d247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055945885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2055945885
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.110565150
Short name T429
Test name
Test status
Simulation time 3506231375 ps
CPU time 71.05 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:02:49 PM PDT 24
Peak memory 258016 kb
Host smart-a03c1159-379c-4067-9b5d-8b6113378b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110565150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.110565150
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.347183417
Short name T897
Test name
Test status
Simulation time 736555083 ps
CPU time 8.13 seconds
Started Jul 03 06:01:59 PM PDT 24
Finished Jul 03 06:02:07 PM PDT 24
Peak memory 241836 kb
Host smart-96e5a5db-570b-4a4a-aa0f-c6675fa9406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347183417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.347183417
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1611077326
Short name T861
Test name
Test status
Simulation time 180253648012 ps
CPU time 306.64 seconds
Started Jul 03 06:01:02 PM PDT 24
Finished Jul 03 06:06:09 PM PDT 24
Peak memory 257512 kb
Host smart-7ae2cb97-5416-4781-a6b1-aadffb2da193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611077326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1611077326
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2443135207
Short name T87
Test name
Test status
Simulation time 3281855545 ps
CPU time 18.22 seconds
Started Jul 03 06:04:20 PM PDT 24
Finished Jul 03 06:04:39 PM PDT 24
Peak memory 241296 kb
Host smart-cc3f328e-04d3-4aae-8d82-a7492c0fe59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443135207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2443135207
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3534708555
Short name T109
Test name
Test status
Simulation time 3408372495 ps
CPU time 12.74 seconds
Started Jul 03 06:06:17 PM PDT 24
Finished Jul 03 06:06:30 PM PDT 24
Peak memory 215524 kb
Host smart-69eb92cd-6b67-4ae5-8ed4-958bf41c2097
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534708555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3534708555
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.114658336
Short name T3
Test name
Test status
Simulation time 34650320 ps
CPU time 0.88 seconds
Started Jul 03 06:00:51 PM PDT 24
Finished Jul 03 06:00:52 PM PDT 24
Peak memory 207528 kb
Host smart-0f6b1e18-b5b0-4620-984b-7b8ae9d09687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114658336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.114658336
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3781129188
Short name T159
Test name
Test status
Simulation time 115830292 ps
CPU time 2.85 seconds
Started Jul 03 06:00:52 PM PDT 24
Finished Jul 03 06:00:56 PM PDT 24
Peak memory 225572 kb
Host smart-53e68efa-f745-4bcc-94a6-16571d7f2d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781129188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3781129188
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2130276691
Short name T1130
Test name
Test status
Simulation time 2846936015 ps
CPU time 15.44 seconds
Started Jul 03 06:05:34 PM PDT 24
Finished Jul 03 06:05:50 PM PDT 24
Peak memory 207368 kb
Host smart-dfd55d02-244f-4924-88a6-2e7061a54598
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130276691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2130276691
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4042209129
Short name T1089
Test name
Test status
Simulation time 1246976651 ps
CPU time 12.18 seconds
Started Jul 03 06:05:35 PM PDT 24
Finished Jul 03 06:05:47 PM PDT 24
Peak memory 207396 kb
Host smart-d1ec9678-7ab2-4463-b4fc-9051b2b9d3d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042209129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4042209129
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3480001892
Short name T86
Test name
Test status
Simulation time 72115669 ps
CPU time 0.99 seconds
Started Jul 03 06:05:38 PM PDT 24
Finished Jul 03 06:05:40 PM PDT 24
Peak memory 207088 kb
Host smart-ac9c8e67-ab6e-4648-87a9-326a57be0cd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480001892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3480001892
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1206956567
Short name T1087
Test name
Test status
Simulation time 157781827 ps
CPU time 2.55 seconds
Started Jul 03 06:05:35 PM PDT 24
Finished Jul 03 06:05:38 PM PDT 24
Peak memory 216680 kb
Host smart-bd1a1cd7-8d3a-4b30-bb8b-f851d8e20151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206956567 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1206956567
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3220485523
Short name T1081
Test name
Test status
Simulation time 849904033 ps
CPU time 1.48 seconds
Started Jul 03 06:05:37 PM PDT 24
Finished Jul 03 06:05:40 PM PDT 24
Peak memory 207360 kb
Host smart-ec336904-4a3a-43dd-9a82-d4748f43357e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220485523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
220485523
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2735194630
Short name T1094
Test name
Test status
Simulation time 15572930 ps
CPU time 0.74 seconds
Started Jul 03 06:05:34 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 203992 kb
Host smart-d26545c2-91ae-45cf-af7d-594a9483a057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735194630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
735194630
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3105913258
Short name T128
Test name
Test status
Simulation time 75072380 ps
CPU time 2.22 seconds
Started Jul 03 06:05:37 PM PDT 24
Finished Jul 03 06:05:40 PM PDT 24
Peak memory 215548 kb
Host smart-10b59fb7-8fc2-4c8d-ac34-33c9494c78dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105913258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3105913258
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3945295304
Short name T1064
Test name
Test status
Simulation time 10935220 ps
CPU time 0.66 seconds
Started Jul 03 06:05:34 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 203924 kb
Host smart-f5e2f58a-2930-4f6a-9c27-6cf5cdec31c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945295304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3945295304
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3575590668
Short name T1110
Test name
Test status
Simulation time 234389964 ps
CPU time 2.8 seconds
Started Jul 03 06:05:35 PM PDT 24
Finished Jul 03 06:05:39 PM PDT 24
Peak memory 215464 kb
Host smart-19bb6e46-20a4-4111-90a5-9d219af20733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575590668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3575590668
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1831368032
Short name T110
Test name
Test status
Simulation time 176418808 ps
CPU time 3.06 seconds
Started Jul 03 06:05:36 PM PDT 24
Finished Jul 03 06:05:40 PM PDT 24
Peak memory 216648 kb
Host smart-121fe682-a146-4d79-88ca-7d98361146e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831368032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
831368032
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2142099186
Short name T1088
Test name
Test status
Simulation time 197503838 ps
CPU time 6.96 seconds
Started Jul 03 06:05:34 PM PDT 24
Finished Jul 03 06:05:42 PM PDT 24
Peak memory 216152 kb
Host smart-96100c5d-2719-4c0f-a645-60a3e692bef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142099186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2142099186
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.656275981
Short name T1148
Test name
Test status
Simulation time 3555134956 ps
CPU time 8.92 seconds
Started Jul 03 06:05:43 PM PDT 24
Finished Jul 03 06:05:53 PM PDT 24
Peak memory 215552 kb
Host smart-8cf25459-0db7-4115-afbd-8912dca31141
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656275981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.656275981
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1266236728
Short name T1149
Test name
Test status
Simulation time 1874863649 ps
CPU time 27.75 seconds
Started Jul 03 06:05:39 PM PDT 24
Finished Jul 03 06:06:08 PM PDT 24
Peak memory 207400 kb
Host smart-14ea43bb-79f2-443d-8d0b-f206a3d15114
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266236728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1266236728
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2557003532
Short name T83
Test name
Test status
Simulation time 14031513 ps
CPU time 0.95 seconds
Started Jul 03 06:05:36 PM PDT 24
Finished Jul 03 06:05:37 PM PDT 24
Peak memory 207068 kb
Host smart-b3a81bc0-43ed-46dc-85e5-8c8ddfc79436
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557003532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2557003532
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.377973749
Short name T1098
Test name
Test status
Simulation time 189260222 ps
CPU time 3.28 seconds
Started Jul 03 06:05:37 PM PDT 24
Finished Jul 03 06:05:41 PM PDT 24
Peak memory 216648 kb
Host smart-33df843e-58b6-4f10-ae83-a0ba896a7b02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377973749 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.377973749
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.592220095
Short name T122
Test name
Test status
Simulation time 136865193 ps
CPU time 2.4 seconds
Started Jul 03 06:05:38 PM PDT 24
Finished Jul 03 06:05:41 PM PDT 24
Peak memory 215540 kb
Host smart-f1aef7fc-ce00-44d4-8a32-077fba77c713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592220095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.592220095
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2794805865
Short name T1043
Test name
Test status
Simulation time 50428173 ps
CPU time 0.78 seconds
Started Jul 03 06:05:38 PM PDT 24
Finished Jul 03 06:05:39 PM PDT 24
Peak memory 203860 kb
Host smart-796dec1c-fcbd-4c9b-847a-b740c5278314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794805865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
794805865
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1340004326
Short name T126
Test name
Test status
Simulation time 69868323 ps
CPU time 1.38 seconds
Started Jul 03 06:05:37 PM PDT 24
Finished Jul 03 06:05:39 PM PDT 24
Peak memory 215512 kb
Host smart-94e81020-449d-4c73-802b-9dee416f296d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340004326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1340004326
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1944112391
Short name T1109
Test name
Test status
Simulation time 10932379 ps
CPU time 0.67 seconds
Started Jul 03 06:05:35 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 204264 kb
Host smart-7923265a-1e67-4fbb-ba7b-542d13e67a8c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944112391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1944112391
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3985346075
Short name T1123
Test name
Test status
Simulation time 43590238 ps
CPU time 2.71 seconds
Started Jul 03 06:05:39 PM PDT 24
Finished Jul 03 06:05:42 PM PDT 24
Peak memory 215552 kb
Host smart-33328d03-f99e-4e06-9539-041ebd816c20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985346075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3985346075
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.607384479
Short name T171
Test name
Test status
Simulation time 878654838 ps
CPU time 3.32 seconds
Started Jul 03 06:05:35 PM PDT 24
Finished Jul 03 06:05:39 PM PDT 24
Peak memory 215644 kb
Host smart-57d46ab7-6fa2-419c-bcd5-bbe7ba5d81c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607384479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.607384479
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.110268951
Short name T1141
Test name
Test status
Simulation time 345926193 ps
CPU time 8.05 seconds
Started Jul 03 06:05:40 PM PDT 24
Finished Jul 03 06:05:49 PM PDT 24
Peak memory 215604 kb
Host smart-4bf1e111-8c19-4bbb-81cc-61e5b045f301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110268951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.110268951
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1741504133
Short name T116
Test name
Test status
Simulation time 37181766 ps
CPU time 2.4 seconds
Started Jul 03 06:06:00 PM PDT 24
Finished Jul 03 06:06:03 PM PDT 24
Peak memory 216620 kb
Host smart-d8c82583-e7da-4efe-a9fc-272b85644721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741504133 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1741504133
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1645282523
Short name T1121
Test name
Test status
Simulation time 34061696 ps
CPU time 2.04 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:05 PM PDT 24
Peak memory 215512 kb
Host smart-8981dc29-1fef-4faf-8a24-b0338756beb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645282523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1645282523
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.780293802
Short name T1112
Test name
Test status
Simulation time 41941681 ps
CPU time 0.71 seconds
Started Jul 03 06:06:00 PM PDT 24
Finished Jul 03 06:06:01 PM PDT 24
Peak memory 203876 kb
Host smart-12cd7826-2505-489f-9003-d30d1adc2a95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780293802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.780293802
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1241384356
Short name T169
Test name
Test status
Simulation time 584629134 ps
CPU time 3.54 seconds
Started Jul 03 06:06:01 PM PDT 24
Finished Jul 03 06:06:05 PM PDT 24
Peak memory 215512 kb
Host smart-f9d14e3c-aa3f-4fd9-b489-e1e6bee7d28f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241384356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1241384356
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3207215468
Short name T106
Test name
Test status
Simulation time 43635018 ps
CPU time 2.68 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:05 PM PDT 24
Peak memory 215676 kb
Host smart-90de3085-f9d4-434e-a6bb-f68fd5f04ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207215468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3207215468
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3462564290
Short name T1134
Test name
Test status
Simulation time 576766421 ps
CPU time 15.69 seconds
Started Jul 03 06:06:00 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 216088 kb
Host smart-1773d54b-bed1-4676-a18e-f6e639d7f74d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462564290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3462564290
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2681521494
Short name T1096
Test name
Test status
Simulation time 42239590 ps
CPU time 3 seconds
Started Jul 03 06:06:09 PM PDT 24
Finished Jul 03 06:06:12 PM PDT 24
Peak memory 217140 kb
Host smart-97356e88-ac4d-474d-970f-f31b6348a97f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681521494 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2681521494
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1980315344
Short name T1125
Test name
Test status
Simulation time 97378619 ps
CPU time 2.73 seconds
Started Jul 03 06:06:00 PM PDT 24
Finished Jul 03 06:06:03 PM PDT 24
Peak memory 215520 kb
Host smart-c3bd61b9-7354-49f5-9dd2-c5c66532252b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980315344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1980315344
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2003256835
Short name T1085
Test name
Test status
Simulation time 53358910 ps
CPU time 0.74 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:03 PM PDT 24
Peak memory 203940 kb
Host smart-a39d1bfe-d1ea-41a6-8b8d-d919da9ddb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003256835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2003256835
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.39762828
Short name T1127
Test name
Test status
Simulation time 62006259 ps
CPU time 1.94 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:04 PM PDT 24
Peak memory 207280 kb
Host smart-c6351fc8-e05c-453a-a17a-3a69db059f37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39762828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sp
i_device_same_csr_outstanding.39762828
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1375029988
Short name T97
Test name
Test status
Simulation time 146770561 ps
CPU time 3.86 seconds
Started Jul 03 06:06:00 PM PDT 24
Finished Jul 03 06:06:04 PM PDT 24
Peak memory 215788 kb
Host smart-ad57ac91-d561-42d9-99b5-abbf6a8eb66f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375029988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1375029988
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3538021747
Short name T1063
Test name
Test status
Simulation time 2181528890 ps
CPU time 6.97 seconds
Started Jul 03 06:06:04 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 215444 kb
Host smart-3d018819-9c17-49a6-96eb-71ffd1d73e58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538021747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3538021747
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2344512642
Short name T1082
Test name
Test status
Simulation time 57593800 ps
CPU time 4.21 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:07 PM PDT 24
Peak memory 218268 kb
Host smart-5673fb3e-1736-43f6-8026-6b8b147aac75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344512642 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2344512642
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2201064021
Short name T161
Test name
Test status
Simulation time 84384905 ps
CPU time 2.06 seconds
Started Jul 03 06:06:04 PM PDT 24
Finished Jul 03 06:06:07 PM PDT 24
Peak memory 215548 kb
Host smart-a9661393-58b5-4318-abfa-097856fa988d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201064021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2201064021
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.949279213
Short name T1074
Test name
Test status
Simulation time 55532426 ps
CPU time 0.74 seconds
Started Jul 03 06:06:03 PM PDT 24
Finished Jul 03 06:06:04 PM PDT 24
Peak memory 203896 kb
Host smart-19275695-ccb5-4fb2-93d5-c271094d3ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949279213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.949279213
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.366422048
Short name T1120
Test name
Test status
Simulation time 139346429 ps
CPU time 3.12 seconds
Started Jul 03 06:06:03 PM PDT 24
Finished Jul 03 06:06:06 PM PDT 24
Peak memory 215532 kb
Host smart-4d2df300-deea-4f1f-82e3-2b64aa08facd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366422048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.366422048
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2389489435
Short name T111
Test name
Test status
Simulation time 120991678 ps
CPU time 2.19 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:05 PM PDT 24
Peak memory 215684 kb
Host smart-d2e21a49-4ad9-4519-a0e1-7992a99f50f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389489435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2389489435
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2677948634
Short name T1080
Test name
Test status
Simulation time 690740991 ps
CPU time 15.76 seconds
Started Jul 03 06:06:05 PM PDT 24
Finished Jul 03 06:06:21 PM PDT 24
Peak memory 223600 kb
Host smart-df357b74-9257-451d-85bb-46035e991b03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677948634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2677948634
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1031815121
Short name T1107
Test name
Test status
Simulation time 282204154 ps
CPU time 1.72 seconds
Started Jul 03 06:06:17 PM PDT 24
Finished Jul 03 06:06:19 PM PDT 24
Peak memory 215628 kb
Host smart-df16574a-69d1-4981-95bf-220f57e258fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031815121 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1031815121
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1418146755
Short name T130
Test name
Test status
Simulation time 308708545 ps
CPU time 2.56 seconds
Started Jul 03 06:06:03 PM PDT 24
Finished Jul 03 06:06:06 PM PDT 24
Peak memory 215508 kb
Host smart-c4ec54ac-7024-43a7-a200-dc3ed165c6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418146755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1418146755
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.653379710
Short name T1039
Test name
Test status
Simulation time 33386426 ps
CPU time 0.7 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:03 PM PDT 24
Peak memory 204248 kb
Host smart-431274ab-31bc-4011-8ec0-dbd7de90652b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653379710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.653379710
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3224815148
Short name T1070
Test name
Test status
Simulation time 169056550 ps
CPU time 2.65 seconds
Started Jul 03 06:06:15 PM PDT 24
Finished Jul 03 06:06:18 PM PDT 24
Peak memory 215540 kb
Host smart-3821d65e-1359-4a7a-98ca-23d1cbea053a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224815148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3224815148
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1437054103
Short name T115
Test name
Test status
Simulation time 109176042 ps
CPU time 1.84 seconds
Started Jul 03 06:06:04 PM PDT 24
Finished Jul 03 06:06:06 PM PDT 24
Peak memory 215804 kb
Host smart-a8d51f29-f85c-469e-b724-ed8285f3723e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437054103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1437054103
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.449579395
Short name T176
Test name
Test status
Simulation time 302484316 ps
CPU time 18.91 seconds
Started Jul 03 06:06:06 PM PDT 24
Finished Jul 03 06:06:25 PM PDT 24
Peak memory 215472 kb
Host smart-998292ec-0325-480e-b992-9939388e490c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449579395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.449579395
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2359579353
Short name T1071
Test name
Test status
Simulation time 58932794 ps
CPU time 3.69 seconds
Started Jul 03 06:06:04 PM PDT 24
Finished Jul 03 06:06:08 PM PDT 24
Peak memory 218496 kb
Host smart-0a455491-4c01-4c2c-b95e-29fd63a195a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359579353 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2359579353
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2073848178
Short name T121
Test name
Test status
Simulation time 146878519 ps
CPU time 1.95 seconds
Started Jul 03 06:06:18 PM PDT 24
Finished Jul 03 06:06:20 PM PDT 24
Peak memory 215552 kb
Host smart-8ff8744a-0ead-4d9d-8232-8ce7e5ff1f04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073848178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2073848178
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3845169635
Short name T1103
Test name
Test status
Simulation time 15072764 ps
CPU time 0.74 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:03 PM PDT 24
Peak memory 204036 kb
Host smart-a7d0370b-fcfc-4d69-a7c3-6662300379e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845169635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3845169635
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3644468548
Short name T1113
Test name
Test status
Simulation time 145517309 ps
CPU time 4.14 seconds
Started Jul 03 06:06:03 PM PDT 24
Finished Jul 03 06:06:08 PM PDT 24
Peak memory 215540 kb
Host smart-f25b13cf-70ef-413c-b978-8c868bbbd8a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644468548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3644468548
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1038091040
Short name T96
Test name
Test status
Simulation time 78627959 ps
CPU time 2.08 seconds
Started Jul 03 06:06:03 PM PDT 24
Finished Jul 03 06:06:06 PM PDT 24
Peak memory 215796 kb
Host smart-61b9ff44-d728-4f75-b459-1a0861487764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038091040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1038091040
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3375437108
Short name T1115
Test name
Test status
Simulation time 102677087 ps
CPU time 6.38 seconds
Started Jul 03 06:06:06 PM PDT 24
Finished Jul 03 06:06:12 PM PDT 24
Peak memory 215556 kb
Host smart-0021efb3-9945-41de-bd86-f1e9843ca52b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375437108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3375437108
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2521471559
Short name T1067
Test name
Test status
Simulation time 52313902 ps
CPU time 1.75 seconds
Started Jul 03 06:06:07 PM PDT 24
Finished Jul 03 06:06:09 PM PDT 24
Peak memory 215416 kb
Host smart-4450d059-21b5-4815-9e99-713e425a6a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521471559 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2521471559
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1834236483
Short name T1079
Test name
Test status
Simulation time 17627394 ps
CPU time 1.24 seconds
Started Jul 03 06:06:07 PM PDT 24
Finished Jul 03 06:06:08 PM PDT 24
Peak memory 215448 kb
Host smart-e9f4395b-693f-4a2b-9978-cac46ca1002d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834236483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1834236483
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.888279652
Short name T1054
Test name
Test status
Simulation time 41692642 ps
CPU time 0.71 seconds
Started Jul 03 06:06:17 PM PDT 24
Finished Jul 03 06:06:18 PM PDT 24
Peak memory 204000 kb
Host smart-5bff58b9-3b2d-4d8f-a61c-10b1aba8853b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888279652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.888279652
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3779057739
Short name T1150
Test name
Test status
Simulation time 89095639 ps
CPU time 2.13 seconds
Started Jul 03 06:06:06 PM PDT 24
Finished Jul 03 06:06:09 PM PDT 24
Peak memory 207332 kb
Host smart-4f0ce9a6-38a3-4444-96a0-c2f14c9469d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779057739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3779057739
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2539288465
Short name T113
Test name
Test status
Simulation time 63684374 ps
CPU time 1.9 seconds
Started Jul 03 06:06:03 PM PDT 24
Finished Jul 03 06:06:05 PM PDT 24
Peak memory 215704 kb
Host smart-0b355ba1-8394-4605-aa3e-d2f9854303a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539288465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2539288465
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.252479154
Short name T98
Test name
Test status
Simulation time 1541474784 ps
CPU time 7.6 seconds
Started Jul 03 06:06:18 PM PDT 24
Finished Jul 03 06:06:26 PM PDT 24
Peak memory 215712 kb
Host smart-29231cb2-6b53-47b6-8bb8-f4f437bb3024
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252479154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.252479154
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3856452971
Short name T162
Test name
Test status
Simulation time 413221655 ps
CPU time 2.85 seconds
Started Jul 03 06:06:08 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 217412 kb
Host smart-3c4c4611-9a24-4b48-bc30-80717ec18576
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856452971 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3856452971
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.509380532
Short name T123
Test name
Test status
Simulation time 345757940 ps
CPU time 2.66 seconds
Started Jul 03 06:06:09 PM PDT 24
Finished Jul 03 06:06:13 PM PDT 24
Peak memory 215536 kb
Host smart-c7e04423-c1aa-4220-92e8-bb8c9a41c763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509380532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.509380532
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2862874399
Short name T1092
Test name
Test status
Simulation time 99769286 ps
CPU time 0.76 seconds
Started Jul 03 06:06:07 PM PDT 24
Finished Jul 03 06:06:08 PM PDT 24
Peak memory 204272 kb
Host smart-3ba59305-f0ff-403c-8017-a76e40bae70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862874399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2862874399
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1146234005
Short name T146
Test name
Test status
Simulation time 344852025 ps
CPU time 1.7 seconds
Started Jul 03 06:06:07 PM PDT 24
Finished Jul 03 06:06:09 PM PDT 24
Peak memory 215424 kb
Host smart-39ffe9cb-9595-48ba-a81d-41f3c7991639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146234005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1146234005
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3176694367
Short name T1131
Test name
Test status
Simulation time 164169919 ps
CPU time 3.74 seconds
Started Jul 03 06:06:06 PM PDT 24
Finished Jul 03 06:06:10 PM PDT 24
Peak memory 215808 kb
Host smart-89db8f44-c2d4-44d1-8320-d0cf5295cdda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176694367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3176694367
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2628951493
Short name T108
Test name
Test status
Simulation time 373326997 ps
CPU time 2.39 seconds
Started Jul 03 06:06:08 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 217680 kb
Host smart-aa7b2f98-a431-485a-b598-739285d42eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628951493 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2628951493
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1235453837
Short name T1151
Test name
Test status
Simulation time 32999542 ps
CPU time 1.34 seconds
Started Jul 03 06:06:06 PM PDT 24
Finished Jul 03 06:06:08 PM PDT 24
Peak memory 207268 kb
Host smart-cb20bee2-b6bc-489e-b8a8-42d0f15aedfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235453837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1235453837
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2181562441
Short name T1050
Test name
Test status
Simulation time 91379627 ps
CPU time 0.73 seconds
Started Jul 03 06:06:08 PM PDT 24
Finished Jul 03 06:06:09 PM PDT 24
Peak memory 203924 kb
Host smart-8683dc53-e956-4777-93f0-1787c222ac8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181562441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2181562441
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2123362925
Short name T1055
Test name
Test status
Simulation time 66109909 ps
CPU time 3.9 seconds
Started Jul 03 06:06:08 PM PDT 24
Finished Jul 03 06:06:12 PM PDT 24
Peak memory 215552 kb
Host smart-258cf794-fc57-4609-bd37-3f31e1d96b01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123362925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2123362925
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3244285442
Short name T1114
Test name
Test status
Simulation time 190363560 ps
CPU time 1.99 seconds
Started Jul 03 06:06:09 PM PDT 24
Finished Jul 03 06:06:12 PM PDT 24
Peak memory 215736 kb
Host smart-dce91649-c00c-42e2-83d5-db5647cc4f8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244285442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3244285442
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.789832367
Short name T117
Test name
Test status
Simulation time 236204371 ps
CPU time 4.34 seconds
Started Jul 03 06:06:10 PM PDT 24
Finished Jul 03 06:06:15 PM PDT 24
Peak memory 217872 kb
Host smart-dd5ab714-99e5-4e43-9e20-740b1bf1db0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789832367 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.789832367
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.124800416
Short name T1097
Test name
Test status
Simulation time 55005044 ps
CPU time 1.23 seconds
Started Jul 03 06:06:12 PM PDT 24
Finished Jul 03 06:06:13 PM PDT 24
Peak memory 207332 kb
Host smart-9952e1a9-48d7-46ff-968f-8d1ce371345b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124800416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.124800416
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4075630410
Short name T1042
Test name
Test status
Simulation time 20640592 ps
CPU time 0.76 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:15 PM PDT 24
Peak memory 204052 kb
Host smart-55d512c0-fd7d-4e75-bb4f-f5365767a213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075630410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4075630410
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3140986226
Short name T1086
Test name
Test status
Simulation time 464573333 ps
CPU time 4.46 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:19 PM PDT 24
Peak memory 215592 kb
Host smart-50c94cf3-9101-4473-9b45-5cbe0745578c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140986226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3140986226
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2470504271
Short name T94
Test name
Test status
Simulation time 779288435 ps
CPU time 4.79 seconds
Started Jul 03 06:06:17 PM PDT 24
Finished Jul 03 06:06:22 PM PDT 24
Peak memory 215708 kb
Host smart-04cbf9de-d13d-417f-b651-b2a830dd32df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470504271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2470504271
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2343417425
Short name T1101
Test name
Test status
Simulation time 321738864 ps
CPU time 4.02 seconds
Started Jul 03 06:06:09 PM PDT 24
Finished Jul 03 06:06:13 PM PDT 24
Peak memory 217696 kb
Host smart-8134986b-c926-4efd-9f9e-d708e20c36a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343417425 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2343417425
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3148872561
Short name T1061
Test name
Test status
Simulation time 219451013 ps
CPU time 1.48 seconds
Started Jul 03 06:06:09 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 207356 kb
Host smart-c801d869-0bd9-4133-af73-aa46711e39ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148872561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3148872561
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2097775664
Short name T1062
Test name
Test status
Simulation time 73364815 ps
CPU time 0.75 seconds
Started Jul 03 06:06:10 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 203976 kb
Host smart-94f0730f-fed1-4268-b89c-89122a5cc8d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097775664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2097775664
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4114765083
Short name T1047
Test name
Test status
Simulation time 158350071 ps
CPU time 2.57 seconds
Started Jul 03 06:06:18 PM PDT 24
Finished Jul 03 06:06:21 PM PDT 24
Peak memory 215468 kb
Host smart-1cbc45ca-ea96-4ef1-8ed3-a1d7b52c3dc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114765083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4114765083
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1532577542
Short name T112
Test name
Test status
Simulation time 167406659 ps
CPU time 1.74 seconds
Started Jul 03 06:06:18 PM PDT 24
Finished Jul 03 06:06:20 PM PDT 24
Peak memory 215708 kb
Host smart-ce603745-9af7-4418-b472-274e29c27aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532577542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1532577542
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2371130623
Short name T1140
Test name
Test status
Simulation time 1189224689 ps
CPU time 18.07 seconds
Started Jul 03 06:06:18 PM PDT 24
Finished Jul 03 06:06:36 PM PDT 24
Peak memory 215640 kb
Host smart-07f6999c-4392-4f6f-9082-6cdc9bee567e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371130623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2371130623
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2188192823
Short name T1053
Test name
Test status
Simulation time 108452263 ps
CPU time 7.31 seconds
Started Jul 03 06:05:42 PM PDT 24
Finished Jul 03 06:05:50 PM PDT 24
Peak memory 215528 kb
Host smart-a1d66907-f02d-428d-8597-6e530c054c80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188192823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2188192823
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1836188005
Short name T1091
Test name
Test status
Simulation time 740562173 ps
CPU time 35.1 seconds
Started Jul 03 06:05:42 PM PDT 24
Finished Jul 03 06:06:17 PM PDT 24
Peak memory 207312 kb
Host smart-9e512015-800d-41bb-94f5-e3ac766186d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836188005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1836188005
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3111466779
Short name T84
Test name
Test status
Simulation time 33204276 ps
CPU time 1.18 seconds
Started Jul 03 06:05:41 PM PDT 24
Finished Jul 03 06:05:43 PM PDT 24
Peak memory 207272 kb
Host smart-2c33bfb2-cf8c-43b1-82f7-8e57b6f36762
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111466779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3111466779
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3804050438
Short name T1126
Test name
Test status
Simulation time 172292395 ps
CPU time 3.29 seconds
Started Jul 03 06:05:42 PM PDT 24
Finished Jul 03 06:05:46 PM PDT 24
Peak memory 217800 kb
Host smart-3079c5bc-ecb7-4e52-aafb-0139e65631a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804050438 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3804050438
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1315363768
Short name T125
Test name
Test status
Simulation time 444164787 ps
CPU time 2.86 seconds
Started Jul 03 06:05:42 PM PDT 24
Finished Jul 03 06:05:45 PM PDT 24
Peak memory 215496 kb
Host smart-307706e1-169e-4480-9f7d-cb90825ab6ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315363768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
315363768
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1432562696
Short name T1065
Test name
Test status
Simulation time 27330218 ps
CPU time 0.75 seconds
Started Jul 03 06:05:37 PM PDT 24
Finished Jul 03 06:05:38 PM PDT 24
Peak memory 204300 kb
Host smart-4a7169f6-1544-437b-b788-90b8d51ed653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432562696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
432562696
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.497958527
Short name T1093
Test name
Test status
Simulation time 98726895 ps
CPU time 2 seconds
Started Jul 03 06:05:37 PM PDT 24
Finished Jul 03 06:05:40 PM PDT 24
Peak memory 215520 kb
Host smart-83ac1d79-3c94-4576-b96a-8873404f5616
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497958527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.497958527
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4115868375
Short name T1100
Test name
Test status
Simulation time 16231366 ps
CPU time 0.68 seconds
Started Jul 03 06:05:37 PM PDT 24
Finished Jul 03 06:05:38 PM PDT 24
Peak memory 203932 kb
Host smart-033f8a93-5e9c-4c13-a46b-fd29d288f805
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115868375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4115868375
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.811836516
Short name T145
Test name
Test status
Simulation time 42154116 ps
CPU time 1.86 seconds
Started Jul 03 06:05:41 PM PDT 24
Finished Jul 03 06:05:44 PM PDT 24
Peak memory 215604 kb
Host smart-cf7905ad-ac01-49a5-9d04-c976cadf48f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811836516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.811836516
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.447956910
Short name T1132
Test name
Test status
Simulation time 39566064 ps
CPU time 0.75 seconds
Started Jul 03 06:06:09 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 204048 kb
Host smart-b84f115c-0d87-4d19-9de3-0553947f13aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447956910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.447956910
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.729370082
Short name T1068
Test name
Test status
Simulation time 19236035 ps
CPU time 0.7 seconds
Started Jul 03 06:06:10 PM PDT 24
Finished Jul 03 06:06:12 PM PDT 24
Peak memory 204048 kb
Host smart-a3cdd658-ad95-4281-946e-3886883ea66e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729370082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.729370082
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2785697101
Short name T1069
Test name
Test status
Simulation time 14138128 ps
CPU time 0.69 seconds
Started Jul 03 06:06:17 PM PDT 24
Finished Jul 03 06:06:18 PM PDT 24
Peak memory 203944 kb
Host smart-2c009ac6-f362-4efc-ac56-240d5b9ecfe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785697101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2785697101
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4039058029
Short name T1083
Test name
Test status
Simulation time 44297662 ps
CPU time 0.76 seconds
Started Jul 03 06:06:13 PM PDT 24
Finished Jul 03 06:06:14 PM PDT 24
Peak memory 204276 kb
Host smart-b04cce37-e50b-4a8c-b2e1-ba0a612927ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039058029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4039058029
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3398357053
Short name T1105
Test name
Test status
Simulation time 18033398 ps
CPU time 0.73 seconds
Started Jul 03 06:06:10 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 203992 kb
Host smart-f541c170-80b2-40c0-acf3-957e98ca7d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398357053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3398357053
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.293442761
Short name T1073
Test name
Test status
Simulation time 28884179 ps
CPU time 0.69 seconds
Started Jul 03 06:06:11 PM PDT 24
Finished Jul 03 06:06:12 PM PDT 24
Peak memory 203916 kb
Host smart-05bddb66-62d5-4888-9b7b-8865a0067f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293442761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.293442761
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3185179061
Short name T1041
Test name
Test status
Simulation time 14088678 ps
CPU time 0.73 seconds
Started Jul 03 06:06:10 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 204308 kb
Host smart-9f5a8a56-433f-41ef-8610-a63ee6f3ba58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185179061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3185179061
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4218234238
Short name T1135
Test name
Test status
Simulation time 14866296 ps
CPU time 0.71 seconds
Started Jul 03 06:06:09 PM PDT 24
Finished Jul 03 06:06:10 PM PDT 24
Peak memory 203920 kb
Host smart-10694806-ffa6-41ba-a2a3-3193863fd488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218234238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4218234238
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3095008896
Short name T1138
Test name
Test status
Simulation time 18866586 ps
CPU time 0.74 seconds
Started Jul 03 06:06:13 PM PDT 24
Finished Jul 03 06:06:14 PM PDT 24
Peak memory 203992 kb
Host smart-4886ba7f-d814-4d47-bbc1-ba9e3faac3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095008896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3095008896
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2522956291
Short name T1144
Test name
Test status
Simulation time 21437224 ps
CPU time 0.73 seconds
Started Jul 03 06:06:10 PM PDT 24
Finished Jul 03 06:06:11 PM PDT 24
Peak memory 203916 kb
Host smart-a92ed228-c963-43ee-9e9c-8a06c3200bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522956291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2522956291
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1955975792
Short name T1117
Test name
Test status
Simulation time 2075758669 ps
CPU time 23.08 seconds
Started Jul 03 06:05:44 PM PDT 24
Finished Jul 03 06:06:07 PM PDT 24
Peak memory 215548 kb
Host smart-118785ce-d2a0-4abf-80f3-20faaa2a72cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955975792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1955975792
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1805007304
Short name T1128
Test name
Test status
Simulation time 1809640964 ps
CPU time 38.26 seconds
Started Jul 03 06:05:43 PM PDT 24
Finished Jul 03 06:06:22 PM PDT 24
Peak memory 207236 kb
Host smart-ea89da0e-622b-4b79-9ebe-f124982c9021
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805007304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1805007304
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2328842355
Short name T1118
Test name
Test status
Simulation time 13692317 ps
CPU time 0.98 seconds
Started Jul 03 06:05:45 PM PDT 24
Finished Jul 03 06:05:46 PM PDT 24
Peak memory 207068 kb
Host smart-ad1d2581-9895-4922-a81b-ae66c09433d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328842355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2328842355
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2366832789
Short name T95
Test name
Test status
Simulation time 103525120 ps
CPU time 1.71 seconds
Started Jul 03 06:05:45 PM PDT 24
Finished Jul 03 06:05:47 PM PDT 24
Peak memory 215560 kb
Host smart-5c6373ab-f6df-4d43-8f3d-658f4bb64abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366832789 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2366832789
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.781790377
Short name T1119
Test name
Test status
Simulation time 331278812 ps
CPU time 2.44 seconds
Started Jul 03 06:05:44 PM PDT 24
Finished Jul 03 06:05:47 PM PDT 24
Peak memory 215480 kb
Host smart-46b13f88-f9e1-4663-9643-51dec17815c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781790377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.781790377
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4120412298
Short name T1072
Test name
Test status
Simulation time 19590464 ps
CPU time 0.7 seconds
Started Jul 03 06:05:43 PM PDT 24
Finished Jul 03 06:05:44 PM PDT 24
Peak memory 204240 kb
Host smart-1c7c04dd-6147-4d10-95d6-3cc26e14210b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120412298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
120412298
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3402983083
Short name T129
Test name
Test status
Simulation time 117370891 ps
CPU time 2.38 seconds
Started Jul 03 06:05:41 PM PDT 24
Finished Jul 03 06:05:44 PM PDT 24
Peak memory 215564 kb
Host smart-e58fd50b-2fc5-4002-9ffc-ca82dd48e069
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402983083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3402983083
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3062487813
Short name T1036
Test name
Test status
Simulation time 10508960 ps
CPU time 0.64 seconds
Started Jul 03 06:05:39 PM PDT 24
Finished Jul 03 06:05:40 PM PDT 24
Peak memory 203888 kb
Host smart-d1244665-b58f-4fcc-9c4b-26add115e904
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062487813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3062487813
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3874244645
Short name T147
Test name
Test status
Simulation time 423179946 ps
CPU time 2.74 seconds
Started Jul 03 06:05:45 PM PDT 24
Finished Jul 03 06:05:48 PM PDT 24
Peak memory 215464 kb
Host smart-6d696b0d-bf11-465e-8f46-dd7d3144a465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874244645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3874244645
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1611291822
Short name T1145
Test name
Test status
Simulation time 383130761 ps
CPU time 3.13 seconds
Started Jul 03 06:05:42 PM PDT 24
Finished Jul 03 06:05:45 PM PDT 24
Peak memory 215720 kb
Host smart-621c132c-17c3-4eaa-b705-a56f856b8db4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611291822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
611291822
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3871899762
Short name T120
Test name
Test status
Simulation time 594621597 ps
CPU time 8.51 seconds
Started Jul 03 06:05:40 PM PDT 24
Finished Jul 03 06:05:49 PM PDT 24
Peak memory 215536 kb
Host smart-5999e364-aa1e-4b1a-9440-580488267668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871899762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3871899762
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3481718530
Short name T1046
Test name
Test status
Simulation time 54408991 ps
CPU time 0.8 seconds
Started Jul 03 06:06:12 PM PDT 24
Finished Jul 03 06:06:13 PM PDT 24
Peak memory 204020 kb
Host smart-60c26d78-8c6f-4074-9f63-76ce20bde9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481718530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3481718530
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3605488057
Short name T1058
Test name
Test status
Simulation time 100752884 ps
CPU time 0.77 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:15 PM PDT 24
Peak memory 204004 kb
Host smart-bb93b908-cdcd-4b5a-bb38-2fba717610c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605488057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3605488057
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2393099821
Short name T1051
Test name
Test status
Simulation time 35937619 ps
CPU time 0.75 seconds
Started Jul 03 06:06:19 PM PDT 24
Finished Jul 03 06:06:20 PM PDT 24
Peak memory 204012 kb
Host smart-36434214-cfcb-4583-b04b-5bf97cca89eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393099821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2393099821
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2327538588
Short name T1044
Test name
Test status
Simulation time 11093294 ps
CPU time 0.75 seconds
Started Jul 03 06:06:12 PM PDT 24
Finished Jul 03 06:06:13 PM PDT 24
Peak memory 204324 kb
Host smart-6d51cefe-1d5e-4520-8156-382d24eb58fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327538588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2327538588
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3623110604
Short name T1142
Test name
Test status
Simulation time 46360754 ps
CPU time 0.73 seconds
Started Jul 03 06:06:15 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 203940 kb
Host smart-c01c33cf-06ab-44a8-81f2-0529f9ddd42a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623110604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3623110604
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1723126703
Short name T1095
Test name
Test status
Simulation time 23803602 ps
CPU time 0.74 seconds
Started Jul 03 06:06:13 PM PDT 24
Finished Jul 03 06:06:14 PM PDT 24
Peak memory 204044 kb
Host smart-108e6beb-0e2a-4c3c-81ec-11293d19de7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723126703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1723126703
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3269141993
Short name T1059
Test name
Test status
Simulation time 14076012 ps
CPU time 0.7 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:15 PM PDT 24
Peak memory 203948 kb
Host smart-81a86a2c-806e-46d1-a22b-c43b8c1c86ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269141993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3269141993
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3636962334
Short name T1116
Test name
Test status
Simulation time 14097287 ps
CPU time 0.73 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 203868 kb
Host smart-c1b9b7a0-d5d5-486d-994b-6c41a3975d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636962334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3636962334
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1920961180
Short name T1056
Test name
Test status
Simulation time 17736548 ps
CPU time 0.74 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:15 PM PDT 24
Peak memory 203992 kb
Host smart-f7232786-ce4e-41fa-8e15-489fec456eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920961180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1920961180
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1292411985
Short name T1037
Test name
Test status
Simulation time 15188666 ps
CPU time 0.72 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:15 PM PDT 24
Peak memory 203916 kb
Host smart-18992a59-6da6-4de3-b532-10f55707a13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292411985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1292411985
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.370772574
Short name T1129
Test name
Test status
Simulation time 373736463 ps
CPU time 8.52 seconds
Started Jul 03 06:05:49 PM PDT 24
Finished Jul 03 06:05:58 PM PDT 24
Peak memory 215440 kb
Host smart-05f6ed29-bfde-4b1e-9e63-7fbc03a3ae46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370772574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.370772574
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4044702648
Short name T1108
Test name
Test status
Simulation time 3607949912 ps
CPU time 35.28 seconds
Started Jul 03 06:05:48 PM PDT 24
Finished Jul 03 06:06:24 PM PDT 24
Peak memory 207292 kb
Host smart-97b50d4b-1839-4205-beed-2db3576cba32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044702648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.4044702648
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3990047823
Short name T114
Test name
Test status
Simulation time 318137180 ps
CPU time 3.27 seconds
Started Jul 03 06:05:52 PM PDT 24
Finished Jul 03 06:05:56 PM PDT 24
Peak memory 217172 kb
Host smart-da4c4939-6c50-4248-93a2-6f0a11bc30a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990047823 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3990047823
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.951684759
Short name T132
Test name
Test status
Simulation time 172754562 ps
CPU time 2.6 seconds
Started Jul 03 06:05:50 PM PDT 24
Finished Jul 03 06:05:52 PM PDT 24
Peak memory 215552 kb
Host smart-d57a3b3f-9b74-4e5b-8edc-b90e81b61e8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951684759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.951684759
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3492679181
Short name T1057
Test name
Test status
Simulation time 21098919 ps
CPU time 0.82 seconds
Started Jul 03 06:05:48 PM PDT 24
Finished Jul 03 06:05:49 PM PDT 24
Peak memory 203944 kb
Host smart-c6097ff0-49b1-4eaf-87d4-44113a80239a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492679181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
492679181
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4030026485
Short name T124
Test name
Test status
Simulation time 41351283 ps
CPU time 1.43 seconds
Started Jul 03 06:05:48 PM PDT 24
Finished Jul 03 06:05:50 PM PDT 24
Peak memory 215512 kb
Host smart-d1c82867-aa58-4f22-bd1e-f95507d5bdf9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030026485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4030026485
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2804446731
Short name T1045
Test name
Test status
Simulation time 16011052 ps
CPU time 0.74 seconds
Started Jul 03 06:05:48 PM PDT 24
Finished Jul 03 06:05:50 PM PDT 24
Peak memory 204256 kb
Host smart-5a01bd23-185e-4b4f-a875-193f29ee265c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804446731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2804446731
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1947460422
Short name T1139
Test name
Test status
Simulation time 193603953 ps
CPU time 4.08 seconds
Started Jul 03 06:05:49 PM PDT 24
Finished Jul 03 06:05:53 PM PDT 24
Peak memory 215452 kb
Host smart-5813df99-8105-4a4d-b5c1-a76e925b55e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947460422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1947460422
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4175986805
Short name T1147
Test name
Test status
Simulation time 82469634 ps
CPU time 3.12 seconds
Started Jul 03 06:05:45 PM PDT 24
Finished Jul 03 06:05:49 PM PDT 24
Peak memory 215748 kb
Host smart-9f7e13b5-37ec-459e-9a48-313f57c1f17e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175986805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
175986805
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2026747643
Short name T174
Test name
Test status
Simulation time 11169191027 ps
CPU time 15.42 seconds
Started Jul 03 06:05:44 PM PDT 24
Finished Jul 03 06:06:00 PM PDT 24
Peak memory 215928 kb
Host smart-53026910-9174-4e3c-b059-9e80d4c172a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026747643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2026747643
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2712068260
Short name T1099
Test name
Test status
Simulation time 13771002 ps
CPU time 0.69 seconds
Started Jul 03 06:06:13 PM PDT 24
Finished Jul 03 06:06:14 PM PDT 24
Peak memory 203924 kb
Host smart-f99ded9f-8a25-4e73-bdb5-0d6b713cad5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712068260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2712068260
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1342556366
Short name T1038
Test name
Test status
Simulation time 20086178 ps
CPU time 0.73 seconds
Started Jul 03 06:06:15 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 203916 kb
Host smart-9ed33659-b33b-4348-b9f9-c1abf3f1a971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342556366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1342556366
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3563912733
Short name T1136
Test name
Test status
Simulation time 37935584 ps
CPU time 0.69 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 204316 kb
Host smart-047ef8dd-e905-4ca4-9547-67047f526736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563912733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3563912733
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3482266367
Short name T1040
Test name
Test status
Simulation time 14819715 ps
CPU time 0.74 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 203896 kb
Host smart-75b4570b-8ca7-4baa-b4a9-05917e43607d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482266367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3482266367
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.122589002
Short name T1049
Test name
Test status
Simulation time 40466575 ps
CPU time 0.7 seconds
Started Jul 03 06:06:15 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 203904 kb
Host smart-4142b820-c1ca-4a9e-a01b-19f5caecc8c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122589002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.122589002
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2938076051
Short name T1084
Test name
Test status
Simulation time 54947704 ps
CPU time 0.77 seconds
Started Jul 03 06:06:15 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 203932 kb
Host smart-d1ae0c6e-cd0f-46ec-aa33-13318c0379c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938076051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2938076051
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2477477934
Short name T1048
Test name
Test status
Simulation time 69606552 ps
CPU time 0.75 seconds
Started Jul 03 06:06:13 PM PDT 24
Finished Jul 03 06:06:14 PM PDT 24
Peak memory 204012 kb
Host smart-9ae72e21-4b5a-4339-937a-80d729027f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477477934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2477477934
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2123442993
Short name T1102
Test name
Test status
Simulation time 19258666 ps
CPU time 0.72 seconds
Started Jul 03 06:06:15 PM PDT 24
Finished Jul 03 06:06:16 PM PDT 24
Peak memory 204236 kb
Host smart-b8890f59-784b-4540-9cae-9302affde0eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123442993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2123442993
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3640967914
Short name T1124
Test name
Test status
Simulation time 17177684 ps
CPU time 0.72 seconds
Started Jul 03 06:06:13 PM PDT 24
Finished Jul 03 06:06:14 PM PDT 24
Peak memory 204004 kb
Host smart-d1dddfd0-b015-46c4-8bb6-108917f014c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640967914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3640967914
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2568330059
Short name T1052
Test name
Test status
Simulation time 24849625 ps
CPU time 0.7 seconds
Started Jul 03 06:06:14 PM PDT 24
Finished Jul 03 06:06:15 PM PDT 24
Peak memory 204336 kb
Host smart-7326a8a9-b630-41e6-a5e1-32d7dc186a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568330059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2568330059
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1800052360
Short name T105
Test name
Test status
Simulation time 25535955 ps
CPU time 1.8 seconds
Started Jul 03 06:05:53 PM PDT 24
Finished Jul 03 06:05:55 PM PDT 24
Peak memory 216616 kb
Host smart-2b3ae738-2bb9-4144-a505-80167d619d8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800052360 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1800052360
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3179459918
Short name T131
Test name
Test status
Simulation time 126298865 ps
CPU time 2.93 seconds
Started Jul 03 06:05:50 PM PDT 24
Finished Jul 03 06:05:54 PM PDT 24
Peak memory 215520 kb
Host smart-b82b7250-8ca5-4183-af02-de960ebae2ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179459918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
179459918
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4170084936
Short name T1133
Test name
Test status
Simulation time 281368888 ps
CPU time 0.76 seconds
Started Jul 03 06:05:51 PM PDT 24
Finished Jul 03 06:05:52 PM PDT 24
Peak memory 204036 kb
Host smart-d87333a9-0c8d-4142-8355-0154d2694b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170084936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
170084936
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1103780746
Short name T164
Test name
Test status
Simulation time 125615786 ps
CPU time 2.9 seconds
Started Jul 03 06:05:53 PM PDT 24
Finished Jul 03 06:05:56 PM PDT 24
Peak memory 215428 kb
Host smart-25acfbd8-cbc6-4c52-840d-a8a132989f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103780746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1103780746
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2613941303
Short name T103
Test name
Test status
Simulation time 35937889 ps
CPU time 2.11 seconds
Started Jul 03 06:05:52 PM PDT 24
Finished Jul 03 06:05:55 PM PDT 24
Peak memory 215672 kb
Host smart-ef5a9d57-888e-43b7-845e-74a8d1749bee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613941303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
613941303
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1454018866
Short name T100
Test name
Test status
Simulation time 844434994 ps
CPU time 19.6 seconds
Started Jul 03 06:05:53 PM PDT 24
Finished Jul 03 06:06:13 PM PDT 24
Peak memory 215680 kb
Host smart-0bde0568-ad9e-4bba-86e4-0dd50cd61f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454018866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1454018866
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3606227001
Short name T1066
Test name
Test status
Simulation time 82930202 ps
CPU time 1.66 seconds
Started Jul 03 06:05:57 PM PDT 24
Finished Jul 03 06:05:59 PM PDT 24
Peak memory 215632 kb
Host smart-0c034603-d307-48dd-92af-5d95b10661d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606227001 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3606227001
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3885925711
Short name T133
Test name
Test status
Simulation time 51269658 ps
CPU time 1.96 seconds
Started Jul 03 06:05:51 PM PDT 24
Finished Jul 03 06:05:54 PM PDT 24
Peak memory 207364 kb
Host smart-3b828c34-00c2-4bce-a11d-7938056d00b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885925711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
885925711
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3796903107
Short name T1146
Test name
Test status
Simulation time 90653810 ps
CPU time 0.69 seconds
Started Jul 03 06:05:53 PM PDT 24
Finished Jul 03 06:05:54 PM PDT 24
Peak memory 203896 kb
Host smart-ad7ddd89-6cec-451e-bd9f-0b01d1a418e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796903107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
796903107
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2000280081
Short name T163
Test name
Test status
Simulation time 152628939 ps
CPU time 3.15 seconds
Started Jul 03 06:05:52 PM PDT 24
Finished Jul 03 06:05:56 PM PDT 24
Peak memory 215552 kb
Host smart-4209788c-b03b-4e6c-b92a-3d0e7ac7fa24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000280081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2000280081
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1012051409
Short name T173
Test name
Test status
Simulation time 781400276 ps
CPU time 13.86 seconds
Started Jul 03 06:05:51 PM PDT 24
Finished Jul 03 06:06:05 PM PDT 24
Peak memory 216024 kb
Host smart-8f62cc68-0e97-4672-8375-a7a74ac5fd6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012051409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1012051409
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3653745989
Short name T1075
Test name
Test status
Simulation time 123268942 ps
CPU time 3.49 seconds
Started Jul 03 06:05:55 PM PDT 24
Finished Jul 03 06:05:59 PM PDT 24
Peak memory 218544 kb
Host smart-ce297171-87ab-4f85-babf-03a9a5dfc7c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653745989 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3653745989
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1186716988
Short name T1106
Test name
Test status
Simulation time 975146836 ps
CPU time 2.96 seconds
Started Jul 03 06:05:55 PM PDT 24
Finished Jul 03 06:05:58 PM PDT 24
Peak memory 207320 kb
Host smart-57810ed8-b406-4165-88cc-5b50984da87c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186716988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
186716988
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1363143422
Short name T1076
Test name
Test status
Simulation time 50242543 ps
CPU time 0.74 seconds
Started Jul 03 06:05:55 PM PDT 24
Finished Jul 03 06:05:56 PM PDT 24
Peak memory 204324 kb
Host smart-02bf2ec6-07de-490b-8341-22e048c4a492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363143422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
363143422
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3387913469
Short name T165
Test name
Test status
Simulation time 179654094 ps
CPU time 3.97 seconds
Started Jul 03 06:05:54 PM PDT 24
Finished Jul 03 06:05:59 PM PDT 24
Peak memory 215492 kb
Host smart-d7dab191-244c-483a-a970-cc59e066cae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387913469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3387913469
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.596439423
Short name T104
Test name
Test status
Simulation time 99598174 ps
CPU time 1.74 seconds
Started Jul 03 06:05:57 PM PDT 24
Finished Jul 03 06:05:59 PM PDT 24
Peak memory 215788 kb
Host smart-370599b8-6c71-4af6-91c5-f11675a64851
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596439423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.596439423
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2981132259
Short name T119
Test name
Test status
Simulation time 296472064 ps
CPU time 19.24 seconds
Started Jul 03 06:05:55 PM PDT 24
Finished Jul 03 06:06:15 PM PDT 24
Peak memory 215552 kb
Host smart-3ba9ce3a-beb0-4012-ad7b-1616f26e7624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981132259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2981132259
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2849202891
Short name T1104
Test name
Test status
Simulation time 371207711 ps
CPU time 3.71 seconds
Started Jul 03 06:06:03 PM PDT 24
Finished Jul 03 06:06:07 PM PDT 24
Peak memory 217176 kb
Host smart-1c9b113e-63f8-4bfa-806a-8b5ba99bb3dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849202891 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2849202891
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1269265481
Short name T1122
Test name
Test status
Simulation time 38288488 ps
CPU time 2.56 seconds
Started Jul 03 06:06:00 PM PDT 24
Finished Jul 03 06:06:03 PM PDT 24
Peak memory 215484 kb
Host smart-a68a28aa-66d1-4fe4-99e2-13be79a5ad8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269265481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
269265481
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2323405860
Short name T1137
Test name
Test status
Simulation time 13922120 ps
CPU time 0.7 seconds
Started Jul 03 06:06:04 PM PDT 24
Finished Jul 03 06:06:05 PM PDT 24
Peak memory 203824 kb
Host smart-2b44f8d5-4eb7-4740-bc73-07cfe84bd63d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323405860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
323405860
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.655792125
Short name T1078
Test name
Test status
Simulation time 403680597 ps
CPU time 3.17 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:05 PM PDT 24
Peak memory 215596 kb
Host smart-c01e5ddc-1cf7-49eb-897b-41be403ece80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655792125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.655792125
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3102168129
Short name T102
Test name
Test status
Simulation time 124870643 ps
CPU time 3.09 seconds
Started Jul 03 06:05:56 PM PDT 24
Finished Jul 03 06:06:00 PM PDT 24
Peak memory 215644 kb
Host smart-542404c2-ff9c-4d2f-9fd8-82d8436f2a5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102168129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
102168129
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2878595522
Short name T1077
Test name
Test status
Simulation time 311665913 ps
CPU time 3.63 seconds
Started Jul 03 06:05:58 PM PDT 24
Finished Jul 03 06:06:02 PM PDT 24
Peak memory 217144 kb
Host smart-0cef698c-edf9-44f1-ba55-2cc1b3aab1d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878595522 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2878595522
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3824730405
Short name T127
Test name
Test status
Simulation time 200641779 ps
CPU time 2.72 seconds
Started Jul 03 06:05:59 PM PDT 24
Finished Jul 03 06:06:02 PM PDT 24
Peak memory 215496 kb
Host smart-714fd2a5-7705-406f-bd72-e23dc130ec2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824730405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
824730405
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.964547048
Short name T1060
Test name
Test status
Simulation time 15509087 ps
CPU time 0.7 seconds
Started Jul 03 06:06:02 PM PDT 24
Finished Jul 03 06:06:03 PM PDT 24
Peak memory 203904 kb
Host smart-f79eb7f8-edf3-4bb2-a08e-2e142f21d4ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964547048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.964547048
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.12895787
Short name T1111
Test name
Test status
Simulation time 451602737 ps
CPU time 2.93 seconds
Started Jul 03 06:06:03 PM PDT 24
Finished Jul 03 06:06:07 PM PDT 24
Peak memory 215412 kb
Host smart-372827a4-c483-4b62-be2e-a82a2e62f31d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12895787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi
_device_same_csr_outstanding.12895787
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2730605654
Short name T1143
Test name
Test status
Simulation time 2822150907 ps
CPU time 17.73 seconds
Started Jul 03 06:05:59 PM PDT 24
Finished Jul 03 06:06:17 PM PDT 24
Peak memory 215612 kb
Host smart-832fd258-cca7-4266-a40e-331624375653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730605654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2730605654
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3428682778
Short name T755
Test name
Test status
Simulation time 20033903 ps
CPU time 0.7 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:00:47 PM PDT 24
Peak memory 205848 kb
Host smart-af1a0fa2-6c75-4bd0-8f7c-71aaa9a58bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428682778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
428682778
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4154491939
Short name T783
Test name
Test status
Simulation time 1133539381 ps
CPU time 10.22 seconds
Started Jul 03 06:00:48 PM PDT 24
Finished Jul 03 06:00:59 PM PDT 24
Peak memory 225540 kb
Host smart-99df37f1-0aea-4a81-89cf-faaa12f2241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154491939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4154491939
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3591505705
Short name T393
Test name
Test status
Simulation time 19123789 ps
CPU time 0.78 seconds
Started Jul 03 06:00:47 PM PDT 24
Finished Jul 03 06:00:48 PM PDT 24
Peak memory 206832 kb
Host smart-d3a2878b-5030-4dcc-9813-0be47b346d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591505705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3591505705
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2473228934
Short name T707
Test name
Test status
Simulation time 44370961188 ps
CPU time 144.63 seconds
Started Jul 03 06:00:45 PM PDT 24
Finished Jul 03 06:03:10 PM PDT 24
Peak memory 250652 kb
Host smart-0cd62925-2edd-4beb-9733-1587cfdedaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473228934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2473228934
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2362398750
Short name T822
Test name
Test status
Simulation time 6702977784 ps
CPU time 47.39 seconds
Started Jul 03 06:00:51 PM PDT 24
Finished Jul 03 06:01:39 PM PDT 24
Peak memory 250436 kb
Host smart-80c04cbd-940f-4657-b8f9-f222b81f65a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362398750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2362398750
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1911187457
Short name T253
Test name
Test status
Simulation time 60422720099 ps
CPU time 114.66 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:02:41 PM PDT 24
Peak memory 253364 kb
Host smart-53d5c84e-097a-47ff-b361-0ab8425e2375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911187457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1911187457
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.441443833
Short name T547
Test name
Test status
Simulation time 2373178666 ps
CPU time 12.61 seconds
Started Jul 03 06:00:48 PM PDT 24
Finished Jul 03 06:01:01 PM PDT 24
Peak memory 225728 kb
Host smart-12018290-3aac-46cd-831e-8cce7243947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441443833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.441443833
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2369900938
Short name T12
Test name
Test status
Simulation time 41137921813 ps
CPU time 271.2 seconds
Started Jul 03 06:00:47 PM PDT 24
Finished Jul 03 06:05:19 PM PDT 24
Peak memory 252304 kb
Host smart-e6a3738d-aee7-41ab-89f0-cc44f2aaca17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369900938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2369900938
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1595692395
Short name T959
Test name
Test status
Simulation time 692664801 ps
CPU time 7.08 seconds
Started Jul 03 06:00:48 PM PDT 24
Finished Jul 03 06:00:55 PM PDT 24
Peak memory 233748 kb
Host smart-26f5fe7d-6bc9-4c15-861d-9f077fb603c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595692395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1595692395
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3770119177
Short name T640
Test name
Test status
Simulation time 3437651623 ps
CPU time 20.43 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:01:07 PM PDT 24
Peak memory 241092 kb
Host smart-25751f62-2355-4d3f-8380-7f435596054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770119177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3770119177
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.162397443
Short name T987
Test name
Test status
Simulation time 15351649 ps
CPU time 1.07 seconds
Started Jul 03 06:00:43 PM PDT 24
Finished Jul 03 06:00:44 PM PDT 24
Peak memory 217688 kb
Host smart-6b9e4cfb-5955-4fc8-bc1b-1349541751fa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162397443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.162397443
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.543702942
Short name T237
Test name
Test status
Simulation time 596733308 ps
CPU time 11.32 seconds
Started Jul 03 06:00:49 PM PDT 24
Finished Jul 03 06:01:00 PM PDT 24
Peak memory 241288 kb
Host smart-70e62ac4-b4bf-4408-9e2c-98475af4e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543702942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
543702942
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2541417475
Short name T464
Test name
Test status
Simulation time 699264842 ps
CPU time 3.36 seconds
Started Jul 03 06:00:45 PM PDT 24
Finished Jul 03 06:00:49 PM PDT 24
Peak memory 233772 kb
Host smart-d341d18a-e757-413f-879e-c697d91dbf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541417475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2541417475
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3357272327
Short name T328
Test name
Test status
Simulation time 1140262655 ps
CPU time 5.6 seconds
Started Jul 03 06:00:48 PM PDT 24
Finished Jul 03 06:00:53 PM PDT 24
Peak memory 223012 kb
Host smart-a4e7a6fd-2303-4c8d-89d8-85a152e888bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3357272327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3357272327
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2159524827
Short name T70
Test name
Test status
Simulation time 353852021 ps
CPU time 1.07 seconds
Started Jul 03 06:00:50 PM PDT 24
Finished Jul 03 06:00:52 PM PDT 24
Peak memory 236336 kb
Host smart-d2fcaaa4-d624-4038-8b61-59e875bc67e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159524827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2159524827
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3116939639
Short name T550
Test name
Test status
Simulation time 144796024005 ps
CPU time 254.35 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:05:01 PM PDT 24
Peak memory 264532 kb
Host smart-d049a993-86f9-4338-9357-83f78a11937f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116939639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3116939639
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4125961020
Short name T281
Test name
Test status
Simulation time 637061135 ps
CPU time 2.73 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:00:49 PM PDT 24
Peak memory 217360 kb
Host smart-9e875124-f7d1-4f9f-a19f-875cee1d03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125961020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4125961020
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.942256352
Short name T482
Test name
Test status
Simulation time 1525668329 ps
CPU time 8.71 seconds
Started Jul 03 06:00:43 PM PDT 24
Finished Jul 03 06:00:53 PM PDT 24
Peak memory 217324 kb
Host smart-5f0e78ae-d3c3-4776-8cf9-12af84728643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942256352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.942256352
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1757897819
Short name T540
Test name
Test status
Simulation time 145379481 ps
CPU time 7.86 seconds
Started Jul 03 06:00:44 PM PDT 24
Finished Jul 03 06:00:53 PM PDT 24
Peak memory 217352 kb
Host smart-18fca741-e811-4b44-9af9-c9181cccbe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757897819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1757897819
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3978929287
Short name T405
Test name
Test status
Simulation time 372335273 ps
CPU time 0.97 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:00:47 PM PDT 24
Peak memory 207956 kb
Host smart-a7dc53f5-3c30-4781-a456-25323dca2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978929287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3978929287
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3629592264
Short name T693
Test name
Test status
Simulation time 2476543894 ps
CPU time 10.43 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:00:56 PM PDT 24
Peak memory 233804 kb
Host smart-da80f274-2b64-4082-a8e9-3f6e744070a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629592264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3629592264
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3019945487
Short name T807
Test name
Test status
Simulation time 8866161855 ps
CPU time 53.25 seconds
Started Jul 03 06:00:59 PM PDT 24
Finished Jul 03 06:01:53 PM PDT 24
Peak memory 225696 kb
Host smart-f3937610-a779-4923-8eca-82c497a91119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019945487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3019945487
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2918302299
Short name T261
Test name
Test status
Simulation time 172288726648 ps
CPU time 344.18 seconds
Started Jul 03 06:00:50 PM PDT 24
Finished Jul 03 06:06:35 PM PDT 24
Peak memory 257264 kb
Host smart-638fa225-467e-481b-a02e-1c611bd2f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918302299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2918302299
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2558777786
Short name T633
Test name
Test status
Simulation time 24209984434 ps
CPU time 239.67 seconds
Started Jul 03 06:00:52 PM PDT 24
Finished Jul 03 06:04:52 PM PDT 24
Peak memory 255024 kb
Host smart-ea556fc1-18b9-4ab1-81a5-d9ee7080db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558777786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2558777786
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1510679497
Short name T244
Test name
Test status
Simulation time 13676930495 ps
CPU time 126.33 seconds
Started Jul 03 06:00:52 PM PDT 24
Finished Jul 03 06:02:59 PM PDT 24
Peak memory 269320 kb
Host smart-1d9b3bf3-406a-4d54-9a1d-fc9e0181390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510679497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1510679497
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3360175850
Short name T980
Test name
Test status
Simulation time 1382332876 ps
CPU time 17.21 seconds
Started Jul 03 06:00:51 PM PDT 24
Finished Jul 03 06:01:09 PM PDT 24
Peak memory 225584 kb
Host smart-c2dbeb61-b2b4-4b5c-89ea-0909a60c5a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360175850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3360175850
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1718692973
Short name T544
Test name
Test status
Simulation time 709558127 ps
CPU time 6.96 seconds
Started Jul 03 06:00:50 PM PDT 24
Finished Jul 03 06:00:58 PM PDT 24
Peak memory 233884 kb
Host smart-5d17d171-84fa-4661-afdb-8a2fe208c878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718692973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1718692973
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.991137918
Short name T968
Test name
Test status
Simulation time 34197151 ps
CPU time 1.04 seconds
Started Jul 03 06:00:51 PM PDT 24
Finished Jul 03 06:00:52 PM PDT 24
Peak memory 217668 kb
Host smart-4149f7ff-c314-40b7-91f5-8bb1ae08bf00
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991137918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.991137918
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2444564425
Short name T443
Test name
Test status
Simulation time 7917201005 ps
CPU time 13.39 seconds
Started Jul 03 06:00:52 PM PDT 24
Finished Jul 03 06:01:06 PM PDT 24
Peak memory 237384 kb
Host smart-a42ca00a-ddd2-483e-abbf-fbb42892d521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444564425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2444564425
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.911027443
Short name T689
Test name
Test status
Simulation time 5640971820 ps
CPU time 9.11 seconds
Started Jul 03 06:00:58 PM PDT 24
Finished Jul 03 06:01:08 PM PDT 24
Peak memory 234852 kb
Host smart-2645d28d-a5f1-49ae-9354-f77d14d28f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911027443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.911027443
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2316257608
Short name T1007
Test name
Test status
Simulation time 374079039 ps
CPU time 6.19 seconds
Started Jul 03 06:00:53 PM PDT 24
Finished Jul 03 06:00:59 PM PDT 24
Peak memory 223600 kb
Host smart-b76db0c7-c6e4-4ab0-af6e-05a0a5d5d6cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2316257608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2316257608
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3595584542
Short name T432
Test name
Test status
Simulation time 106528658 ps
CPU time 1.07 seconds
Started Jul 03 06:00:53 PM PDT 24
Finished Jul 03 06:00:54 PM PDT 24
Peak memory 208540 kb
Host smart-807a3df0-1ab2-44a4-878b-a42d957701cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595584542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3595584542
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2696541966
Short name T407
Test name
Test status
Simulation time 1343554963 ps
CPU time 8.03 seconds
Started Jul 03 06:00:51 PM PDT 24
Finished Jul 03 06:00:59 PM PDT 24
Peak memory 217388 kb
Host smart-849feba2-fb20-4016-88c1-258535bb4f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696541966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2696541966
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4154818705
Short name T415
Test name
Test status
Simulation time 8642666490 ps
CPU time 9.13 seconds
Started Jul 03 06:00:58 PM PDT 24
Finished Jul 03 06:01:07 PM PDT 24
Peak memory 217480 kb
Host smart-e97b59b6-ea50-40aa-86d3-00a908e03d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154818705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4154818705
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2008553838
Short name T374
Test name
Test status
Simulation time 30702217 ps
CPU time 1.04 seconds
Started Jul 03 06:00:53 PM PDT 24
Finished Jul 03 06:00:54 PM PDT 24
Peak memory 208488 kb
Host smart-606e4dc1-4971-4a99-80f2-ae3decbd11b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008553838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2008553838
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3946707673
Short name T838
Test name
Test status
Simulation time 58768275 ps
CPU time 0.75 seconds
Started Jul 03 06:00:50 PM PDT 24
Finished Jul 03 06:00:52 PM PDT 24
Peak memory 206992 kb
Host smart-33edd397-416b-4157-96a0-30d1fb50925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946707673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3946707673
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.592205507
Short name T217
Test name
Test status
Simulation time 5055934553 ps
CPU time 17.88 seconds
Started Jul 03 06:00:51 PM PDT 24
Finished Jul 03 06:01:09 PM PDT 24
Peak memory 225680 kb
Host smart-66499cc2-5533-4030-8888-18b9c40c2b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592205507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.592205507
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.70688835
Short name T65
Test name
Test status
Simulation time 14029378 ps
CPU time 0.73 seconds
Started Jul 03 06:01:29 PM PDT 24
Finished Jul 03 06:01:30 PM PDT 24
Peak memory 205780 kb
Host smart-109db2b6-868d-4033-8864-8c4685c4f667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70688835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.70688835
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.959448015
Short name T703
Test name
Test status
Simulation time 217105631 ps
CPU time 3.52 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:29 PM PDT 24
Peak memory 225572 kb
Host smart-e043d19c-daa4-45fa-abfc-789738e8fbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959448015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.959448015
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1540132122
Short name T60
Test name
Test status
Simulation time 22478128 ps
CPU time 0.81 seconds
Started Jul 03 06:01:27 PM PDT 24
Finished Jul 03 06:01:28 PM PDT 24
Peak memory 207508 kb
Host smart-fef11586-af94-4e0a-a333-87cdd3708b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540132122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1540132122
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1476596711
Short name T849
Test name
Test status
Simulation time 47598265223 ps
CPU time 341.36 seconds
Started Jul 03 06:01:28 PM PDT 24
Finished Jul 03 06:07:10 PM PDT 24
Peak memory 254612 kb
Host smart-4703c116-ff71-4160-821a-552d34f2bad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476596711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1476596711
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3530207765
Short name T211
Test name
Test status
Simulation time 25170985162 ps
CPU time 170.21 seconds
Started Jul 03 06:01:27 PM PDT 24
Finished Jul 03 06:04:18 PM PDT 24
Peak memory 253456 kb
Host smart-4fdc4945-b581-49d9-9973-5af72829bb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530207765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3530207765
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1055575684
Short name T654
Test name
Test status
Simulation time 1114187063251 ps
CPU time 539.49 seconds
Started Jul 03 06:01:30 PM PDT 24
Finished Jul 03 06:10:30 PM PDT 24
Peak memory 255220 kb
Host smart-093ee186-6a93-4e0a-b37c-9de5ba165b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055575684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1055575684
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3587121414
Short name T967
Test name
Test status
Simulation time 4583624616 ps
CPU time 25.14 seconds
Started Jul 03 06:01:28 PM PDT 24
Finished Jul 03 06:01:54 PM PDT 24
Peak memory 233956 kb
Host smart-fee1fcd7-ac6b-47a8-9c78-e68bfd6b513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587121414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3587121414
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2308343072
Short name T504
Test name
Test status
Simulation time 3035392918 ps
CPU time 27.31 seconds
Started Jul 03 06:01:24 PM PDT 24
Finished Jul 03 06:01:52 PM PDT 24
Peak memory 233860 kb
Host smart-31831005-fe3c-4b90-99b8-4846659ccc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308343072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2308343072
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4285726040
Short name T700
Test name
Test status
Simulation time 8393404150 ps
CPU time 23.43 seconds
Started Jul 03 06:01:26 PM PDT 24
Finished Jul 03 06:01:50 PM PDT 24
Peak memory 225692 kb
Host smart-8d13d882-f4f4-40c1-9ad8-ac6430468532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285726040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4285726040
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.4078245327
Short name T973
Test name
Test status
Simulation time 43284825 ps
CPU time 1.04 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 217672 kb
Host smart-59194128-f176-4afa-b8a3-300604ef71f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078245327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.4078245327
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1523109612
Short name T59
Test name
Test status
Simulation time 121048090 ps
CPU time 2.04 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:27 PM PDT 24
Peak memory 224944 kb
Host smart-77884fcf-b934-42f3-8b39-8cf896d9868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523109612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1523109612
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4247922272
Short name T340
Test name
Test status
Simulation time 1584453369 ps
CPU time 7.52 seconds
Started Jul 03 06:01:24 PM PDT 24
Finished Jul 03 06:01:32 PM PDT 24
Peak memory 233704 kb
Host smart-3eb9cf2d-19b0-4949-851b-45bc01395d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247922272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4247922272
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1630392909
Short name T148
Test name
Test status
Simulation time 492077523 ps
CPU time 7.9 seconds
Started Jul 03 06:01:28 PM PDT 24
Finished Jul 03 06:01:37 PM PDT 24
Peak memory 222532 kb
Host smart-804c1c67-c309-49d1-9725-2e037224ff4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1630392909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1630392909
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3397357218
Short name T906
Test name
Test status
Simulation time 12626206318 ps
CPU time 37.76 seconds
Started Jul 03 06:01:30 PM PDT 24
Finished Jul 03 06:02:08 PM PDT 24
Peak memory 240144 kb
Host smart-52435e9e-2bae-4c15-a88f-f4d20da4be58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397357218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3397357218
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.891228961
Short name T778
Test name
Test status
Simulation time 39116701201 ps
CPU time 25.92 seconds
Started Jul 03 06:01:22 PM PDT 24
Finished Jul 03 06:01:48 PM PDT 24
Peak memory 217496 kb
Host smart-4ed6e510-fb9e-425e-a15b-518bd79f036d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891228961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.891228961
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.422198058
Short name T850
Test name
Test status
Simulation time 388406454 ps
CPU time 2.5 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:28 PM PDT 24
Peak memory 217376 kb
Host smart-cfa2e7fa-b5ee-40f5-bceb-b9ddeb122cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422198058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.422198058
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1058845783
Short name T280
Test name
Test status
Simulation time 142106576 ps
CPU time 2.53 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:28 PM PDT 24
Peak memory 217420 kb
Host smart-373af377-caed-4450-8b15-893eec3a320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058845783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1058845783
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1721401525
Short name T721
Test name
Test status
Simulation time 249849838 ps
CPU time 0.91 seconds
Started Jul 03 06:01:26 PM PDT 24
Finished Jul 03 06:01:27 PM PDT 24
Peak memory 206996 kb
Host smart-67336e56-afb9-48b1-bb8d-f199eb770933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721401525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1721401525
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2176529998
Short name T940
Test name
Test status
Simulation time 7424416155 ps
CPU time 21.43 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:47 PM PDT 24
Peak memory 225704 kb
Host smart-c7e12aa6-cbfd-4736-b288-4bb9d3059fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176529998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2176529998
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.625581947
Short name T343
Test name
Test status
Simulation time 38453990 ps
CPU time 0.75 seconds
Started Jul 03 06:01:40 PM PDT 24
Finished Jul 03 06:01:41 PM PDT 24
Peak memory 206712 kb
Host smart-d8668f50-8240-40cc-ac72-0a15298ad224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625581947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.625581947
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2230213843
Short name T560
Test name
Test status
Simulation time 434087319 ps
CPU time 2.37 seconds
Started Jul 03 06:01:30 PM PDT 24
Finished Jul 03 06:01:33 PM PDT 24
Peak memory 225624 kb
Host smart-98e9e3bb-4d66-4010-bbd3-b529d4b24afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230213843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2230213843
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.140339194
Short name T461
Test name
Test status
Simulation time 56903026 ps
CPU time 0.85 seconds
Started Jul 03 06:01:31 PM PDT 24
Finished Jul 03 06:01:32 PM PDT 24
Peak memory 206500 kb
Host smart-3578b3cb-e814-46d6-96c4-697bfbd9f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140339194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.140339194
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.230797397
Short name T521
Test name
Test status
Simulation time 1835607927 ps
CPU time 32.01 seconds
Started Jul 03 06:01:34 PM PDT 24
Finished Jul 03 06:02:06 PM PDT 24
Peak memory 242256 kb
Host smart-2407f80c-2b58-47b7-8c2a-d30cb6ebfa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230797397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.230797397
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2121592559
Short name T187
Test name
Test status
Simulation time 2418477284 ps
CPU time 49.83 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:02:27 PM PDT 24
Peak memory 236372 kb
Host smart-caf98e9b-d172-4d91-a8a6-77b3be98d83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121592559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2121592559
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4029824753
Short name T256
Test name
Test status
Simulation time 39732349268 ps
CPU time 125.4 seconds
Started Jul 03 06:01:39 PM PDT 24
Finished Jul 03 06:03:45 PM PDT 24
Peak memory 266656 kb
Host smart-38bff48c-df85-402c-8b3e-1b6bb068ad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029824753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4029824753
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4001052618
Short name T424
Test name
Test status
Simulation time 165071399 ps
CPU time 5.69 seconds
Started Jul 03 06:01:32 PM PDT 24
Finished Jul 03 06:01:38 PM PDT 24
Peak memory 235484 kb
Host smart-b6fb27ea-8745-4eb0-ab1f-2301ba34a32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001052618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4001052618
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3464803733
Short name T942
Test name
Test status
Simulation time 136531064 ps
CPU time 4.38 seconds
Started Jul 03 06:01:33 PM PDT 24
Finished Jul 03 06:01:38 PM PDT 24
Peak memory 225584 kb
Host smart-118706d7-15e2-4c98-a686-6b6ade7e6c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464803733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3464803733
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3724361288
Short name T784
Test name
Test status
Simulation time 86231081 ps
CPU time 2.96 seconds
Started Jul 03 06:01:31 PM PDT 24
Finished Jul 03 06:01:35 PM PDT 24
Peak memory 225552 kb
Host smart-99a93c97-4c2d-435a-8452-56cb03409838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724361288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3724361288
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1023132785
Short name T824
Test name
Test status
Simulation time 52684100 ps
CPU time 0.99 seconds
Started Jul 03 06:01:28 PM PDT 24
Finished Jul 03 06:01:29 PM PDT 24
Peak memory 217596 kb
Host smart-4a3cb9b2-3ce9-4bcd-9f8d-8ab10a31d3be
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023132785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1023132785
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2350915070
Short name T480
Test name
Test status
Simulation time 32116943 ps
CPU time 2.12 seconds
Started Jul 03 06:01:28 PM PDT 24
Finished Jul 03 06:01:31 PM PDT 24
Peak memory 224752 kb
Host smart-b5071531-30aa-4cf3-8c6d-30b03c347813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350915070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2350915070
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3554761732
Short name T193
Test name
Test status
Simulation time 26193164149 ps
CPU time 19.25 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:45 PM PDT 24
Peak memory 234944 kb
Host smart-c136d848-7a60-47be-ac93-3c942eaec5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554761732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3554761732
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3291584826
Short name T999
Test name
Test status
Simulation time 236870780 ps
CPU time 5.48 seconds
Started Jul 03 06:01:36 PM PDT 24
Finished Jul 03 06:01:42 PM PDT 24
Peak memory 223116 kb
Host smart-8dbade3b-3076-4793-a3d8-d876584cfff9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3291584826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3291584826
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3264418960
Short name T311
Test name
Test status
Simulation time 139867935 ps
CPU time 1.18 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:01:38 PM PDT 24
Peak memory 207752 kb
Host smart-8348c229-51e0-43fd-af36-a59ecd05280e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264418960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3264418960
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2233793749
Short name T690
Test name
Test status
Simulation time 60367224243 ps
CPU time 33.02 seconds
Started Jul 03 06:01:30 PM PDT 24
Finished Jul 03 06:02:03 PM PDT 24
Peak memory 217504 kb
Host smart-742f659d-c295-4d92-b25e-a17209597b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233793749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2233793749
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1173079132
Short name T1030
Test name
Test status
Simulation time 2945633519 ps
CPU time 2.86 seconds
Started Jul 03 06:01:27 PM PDT 24
Finished Jul 03 06:01:31 PM PDT 24
Peak memory 217500 kb
Host smart-95a9b95a-ce57-4e33-b233-cbfcec225054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173079132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1173079132
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4198262955
Short name T619
Test name
Test status
Simulation time 152647077 ps
CPU time 1.6 seconds
Started Jul 03 06:01:29 PM PDT 24
Finished Jul 03 06:01:31 PM PDT 24
Peak memory 217416 kb
Host smart-319d1008-185a-42e8-9851-73a1a2912de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198262955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4198262955
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1387541447
Short name T876
Test name
Test status
Simulation time 79948523 ps
CPU time 0.84 seconds
Started Jul 03 06:01:27 PM PDT 24
Finished Jul 03 06:01:29 PM PDT 24
Peak memory 207024 kb
Host smart-f64a1a09-1fcd-4f1f-b691-80ccef4b8bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387541447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1387541447
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3920568795
Short name T223
Test name
Test status
Simulation time 4369793927 ps
CPU time 15.51 seconds
Started Jul 03 06:01:32 PM PDT 24
Finished Jul 03 06:01:48 PM PDT 24
Peak memory 233836 kb
Host smart-75e35ca7-5c25-42d5-b050-ee3be440ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920568795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3920568795
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2327513055
Short name T798
Test name
Test status
Simulation time 11259016 ps
CPU time 0.73 seconds
Started Jul 03 06:01:41 PM PDT 24
Finished Jul 03 06:01:42 PM PDT 24
Peak memory 206336 kb
Host smart-ae75f840-d385-4d44-835e-931583db66ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327513055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2327513055
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1054503740
Short name T898
Test name
Test status
Simulation time 4690773851 ps
CPU time 12.39 seconds
Started Jul 03 06:01:38 PM PDT 24
Finished Jul 03 06:01:51 PM PDT 24
Peak memory 233900 kb
Host smart-97950bd5-6738-44ed-9a97-0fd3944b9d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054503740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1054503740
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2574710374
Short name T155
Test name
Test status
Simulation time 88817397 ps
CPU time 0.81 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:01:38 PM PDT 24
Peak memory 207516 kb
Host smart-3b20d656-760c-4104-aa1c-0c9ddeaaf58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574710374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2574710374
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2153438866
Short name T58
Test name
Test status
Simulation time 3870267826 ps
CPU time 80.52 seconds
Started Jul 03 06:01:39 PM PDT 24
Finished Jul 03 06:03:00 PM PDT 24
Peak memory 255648 kb
Host smart-2f042009-b002-4d33-b0ac-5af110a38685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153438866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2153438866
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1203975077
Short name T88
Test name
Test status
Simulation time 2137670768 ps
CPU time 41.31 seconds
Started Jul 03 06:01:40 PM PDT 24
Finished Jul 03 06:02:22 PM PDT 24
Peak memory 251584 kb
Host smart-a23ed053-8141-4351-9c7b-de3310ee4100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203975077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1203975077
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.855922374
Short name T975
Test name
Test status
Simulation time 252151874 ps
CPU time 3.06 seconds
Started Jul 03 06:01:39 PM PDT 24
Finished Jul 03 06:01:43 PM PDT 24
Peak memory 233780 kb
Host smart-06238e23-7238-4812-bd57-3d68a2d37914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855922374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.855922374
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1327880648
Short name T36
Test name
Test status
Simulation time 35572803317 ps
CPU time 252.65 seconds
Started Jul 03 06:01:41 PM PDT 24
Finished Jul 03 06:05:54 PM PDT 24
Peak memory 256724 kb
Host smart-6c88def1-760b-4771-97f5-87102e5c024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327880648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1327880648
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3979838799
Short name T977
Test name
Test status
Simulation time 6899080502 ps
CPU time 15.71 seconds
Started Jul 03 06:01:35 PM PDT 24
Finished Jul 03 06:01:51 PM PDT 24
Peak memory 233864 kb
Host smart-190ca5a6-4255-43c4-822b-5e37aa7600c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979838799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3979838799
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3865909154
Short name T398
Test name
Test status
Simulation time 21212214508 ps
CPU time 65.68 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:02:43 PM PDT 24
Peak memory 249740 kb
Host smart-75adf776-3fff-4781-956d-45c10bb2aacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865909154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3865909154
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3107306743
Short name T526
Test name
Test status
Simulation time 8981663818 ps
CPU time 24.5 seconds
Started Jul 03 06:01:38 PM PDT 24
Finished Jul 03 06:02:03 PM PDT 24
Peak memory 233916 kb
Host smart-87d4db14-3a3d-458f-9ce7-cb4fd45d3889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107306743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3107306743
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2185489555
Short name T911
Test name
Test status
Simulation time 731663763 ps
CPU time 3.7 seconds
Started Jul 03 06:01:38 PM PDT 24
Finished Jul 03 06:01:42 PM PDT 24
Peak memory 233816 kb
Host smart-14ec1071-2180-4839-801b-b65f2c022ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185489555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2185489555
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.366380005
Short name T355
Test name
Test status
Simulation time 434383132 ps
CPU time 7.48 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:01:45 PM PDT 24
Peak memory 223888 kb
Host smart-86915aa5-54df-4da8-b3fa-3e24e16ff96a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=366380005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.366380005
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2676764920
Short name T816
Test name
Test status
Simulation time 1879234825 ps
CPU time 10.92 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:01:48 PM PDT 24
Peak memory 217420 kb
Host smart-b299f933-a079-49ab-a0f1-b1af4fb8f717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676764920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2676764920
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2877333249
Short name T299
Test name
Test status
Simulation time 4434292458 ps
CPU time 2.37 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:01:40 PM PDT 24
Peak memory 209092 kb
Host smart-b2b7a611-554d-4baf-a216-c612d4563c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877333249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2877333249
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1737954555
Short name T884
Test name
Test status
Simulation time 466004628 ps
CPU time 3.02 seconds
Started Jul 03 06:01:36 PM PDT 24
Finished Jul 03 06:01:39 PM PDT 24
Peak memory 217264 kb
Host smart-c5373589-faf8-466b-8e93-5dab46d10359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737954555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1737954555
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2784155186
Short name T667
Test name
Test status
Simulation time 274225200 ps
CPU time 1.03 seconds
Started Jul 03 06:01:37 PM PDT 24
Finished Jul 03 06:01:38 PM PDT 24
Peak memory 207972 kb
Host smart-835c8df1-9bea-4d1a-9c82-ca5bc5b9e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784155186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2784155186
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2258471608
Short name T746
Test name
Test status
Simulation time 442968985 ps
CPU time 3.05 seconds
Started Jul 03 06:01:36 PM PDT 24
Finished Jul 03 06:01:39 PM PDT 24
Peak memory 233844 kb
Host smart-5f595ac9-c478-4a13-bbb5-f322c23ac991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258471608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2258471608
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2105869272
Short name T317
Test name
Test status
Simulation time 12791793 ps
CPU time 0.71 seconds
Started Jul 03 06:01:48 PM PDT 24
Finished Jul 03 06:01:49 PM PDT 24
Peak memory 206336 kb
Host smart-f85ed5ba-f42b-4731-ae33-4286ab7f6bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105869272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2105869272
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1169400452
Short name T970
Test name
Test status
Simulation time 1987312726 ps
CPU time 14.97 seconds
Started Jul 03 06:01:44 PM PDT 24
Finished Jul 03 06:01:59 PM PDT 24
Peak memory 225500 kb
Host smart-bd19baed-0620-4f08-b114-ff11f9a1e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169400452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1169400452
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2868181072
Short name T78
Test name
Test status
Simulation time 57761712 ps
CPU time 0.74 seconds
Started Jul 03 06:01:39 PM PDT 24
Finished Jul 03 06:01:40 PM PDT 24
Peak memory 206840 kb
Host smart-f8bc2091-d08c-4cf9-bd8b-bd20e92d0c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868181072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2868181072
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.55008212
Short name T188
Test name
Test status
Simulation time 99898895626 ps
CPU time 212.8 seconds
Started Jul 03 06:01:49 PM PDT 24
Finished Jul 03 06:05:22 PM PDT 24
Peak memory 271944 kb
Host smart-4e759e77-d0a2-48e2-acb9-ec1c22c09a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55008212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.55008212
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3543290806
Short name T862
Test name
Test status
Simulation time 7433321711 ps
CPU time 15.8 seconds
Started Jul 03 06:01:45 PM PDT 24
Finished Jul 03 06:02:01 PM PDT 24
Peak memory 238844 kb
Host smart-5d7cb022-6ca8-4564-b3d8-1fd17efa3847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543290806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3543290806
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3925116697
Short name T191
Test name
Test status
Simulation time 26597536672 ps
CPU time 233.88 seconds
Started Jul 03 06:01:45 PM PDT 24
Finished Jul 03 06:05:40 PM PDT 24
Peak memory 256772 kb
Host smart-a9f9e2a3-df05-45fb-b53a-3f6127dc95f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925116697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3925116697
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.710658330
Short name T765
Test name
Test status
Simulation time 189062039 ps
CPU time 3.59 seconds
Started Jul 03 06:01:49 PM PDT 24
Finished Jul 03 06:01:53 PM PDT 24
Peak memory 233708 kb
Host smart-a6af19f4-8958-411f-8f1a-16ab7f22038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710658330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.710658330
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1910023221
Short name T537
Test name
Test status
Simulation time 2867714768 ps
CPU time 21.89 seconds
Started Jul 03 06:01:49 PM PDT 24
Finished Jul 03 06:02:11 PM PDT 24
Peak memory 242028 kb
Host smart-ba2ca6af-7bfe-4ccd-b6ca-20f16c2ccd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910023221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1910023221
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2019038810
Short name T845
Test name
Test status
Simulation time 1724036973 ps
CPU time 15.87 seconds
Started Jul 03 06:01:45 PM PDT 24
Finished Jul 03 06:02:01 PM PDT 24
Peak memory 233788 kb
Host smart-7c2f1e4f-947c-416a-b3d3-e376eced7c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019038810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2019038810
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3265371229
Short name T637
Test name
Test status
Simulation time 2290124945 ps
CPU time 18.43 seconds
Started Jul 03 06:01:42 PM PDT 24
Finished Jul 03 06:02:01 PM PDT 24
Peak memory 225660 kb
Host smart-5f2c1c7d-5436-47d3-bfc8-fac744696cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265371229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3265371229
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.963213380
Short name T34
Test name
Test status
Simulation time 41298219 ps
CPU time 1.07 seconds
Started Jul 03 06:01:40 PM PDT 24
Finished Jul 03 06:01:41 PM PDT 24
Peak memory 217680 kb
Host smart-dcc61743-94d3-4c92-925a-b1078616ee63
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963213380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.963213380
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1894054415
Short name T156
Test name
Test status
Simulation time 59517793 ps
CPU time 2.1 seconds
Started Jul 03 06:01:44 PM PDT 24
Finished Jul 03 06:01:46 PM PDT 24
Peak memory 225168 kb
Host smart-bf5a0776-8e27-4819-857e-e8cf80a62520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894054415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1894054415
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1725337446
Short name T695
Test name
Test status
Simulation time 23721568995 ps
CPU time 20.18 seconds
Started Jul 03 06:01:42 PM PDT 24
Finished Jul 03 06:02:03 PM PDT 24
Peak memory 250028 kb
Host smart-8c8ebb97-4c0d-4214-94af-f7c25fbcda55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725337446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1725337446
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2956929970
Short name T814
Test name
Test status
Simulation time 1213700445 ps
CPU time 5.59 seconds
Started Jul 03 06:01:46 PM PDT 24
Finished Jul 03 06:01:51 PM PDT 24
Peak memory 224076 kb
Host smart-424cca91-9cf4-420c-8ec0-a7ae55c56e00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2956929970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2956929970
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2931834258
Short name T21
Test name
Test status
Simulation time 48495151165 ps
CPU time 135.89 seconds
Started Jul 03 06:01:46 PM PDT 24
Finished Jul 03 06:04:02 PM PDT 24
Peak memory 251416 kb
Host smart-896c4dc2-440a-4cd1-af7b-868af81f59a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931834258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2931834258
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3672861981
Short name T672
Test name
Test status
Simulation time 2931036674 ps
CPU time 29.13 seconds
Started Jul 03 06:01:43 PM PDT 24
Finished Jul 03 06:02:13 PM PDT 24
Peak memory 217432 kb
Host smart-8e2c0a24-257e-4d6b-804f-0707eb8d87b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672861981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3672861981
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2025431886
Short name T453
Test name
Test status
Simulation time 472700972 ps
CPU time 1.85 seconds
Started Jul 03 06:01:40 PM PDT 24
Finished Jul 03 06:01:42 PM PDT 24
Peak memory 217188 kb
Host smart-b7f457b2-ed73-4bab-8ea7-29f96dc301f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025431886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2025431886
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3364810247
Short name T314
Test name
Test status
Simulation time 213578527 ps
CPU time 1.98 seconds
Started Jul 03 06:01:43 PM PDT 24
Finished Jul 03 06:01:45 PM PDT 24
Peak memory 217376 kb
Host smart-2c2e1f60-3e8d-4bea-8403-bbc8b73d054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364810247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3364810247
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2523427255
Short name T590
Test name
Test status
Simulation time 441485355 ps
CPU time 0.91 seconds
Started Jul 03 06:01:46 PM PDT 24
Finished Jul 03 06:01:48 PM PDT 24
Peak memory 207020 kb
Host smart-df5c35d0-2f11-4bbd-8586-23febe57bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523427255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2523427255
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.146593202
Short name T736
Test name
Test status
Simulation time 28118209967 ps
CPU time 46.53 seconds
Started Jul 03 06:01:45 PM PDT 24
Finished Jul 03 06:02:32 PM PDT 24
Peak memory 250428 kb
Host smart-97c5eb41-252c-412f-b8aa-e9b7c6011b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146593202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.146593202
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4036521848
Short name T963
Test name
Test status
Simulation time 38293495 ps
CPU time 0.71 seconds
Started Jul 03 06:01:56 PM PDT 24
Finished Jul 03 06:01:58 PM PDT 24
Peak memory 205836 kb
Host smart-3da73856-b53e-4d33-a0a8-09ed541f347e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036521848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4036521848
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3495376175
Short name T575
Test name
Test status
Simulation time 992618936 ps
CPU time 4.61 seconds
Started Jul 03 06:01:54 PM PDT 24
Finished Jul 03 06:01:59 PM PDT 24
Peak memory 233788 kb
Host smart-b55d56eb-ccb2-490c-bb48-efc696e8a66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495376175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3495376175
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3901900668
Short name T899
Test name
Test status
Simulation time 46395948 ps
CPU time 0.82 seconds
Started Jul 03 06:01:50 PM PDT 24
Finished Jul 03 06:01:52 PM PDT 24
Peak memory 207500 kb
Host smart-554b5d87-b0ea-4622-b45b-3d8328614f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901900668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3901900668
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2838826465
Short name T243
Test name
Test status
Simulation time 61053732267 ps
CPU time 438.68 seconds
Started Jul 03 06:01:54 PM PDT 24
Finished Jul 03 06:09:13 PM PDT 24
Peak memory 258496 kb
Host smart-62768ca4-0483-46b2-96cc-c00dbdfef542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838826465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2838826465
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1631472753
Short name T950
Test name
Test status
Simulation time 2991682970 ps
CPU time 72.2 seconds
Started Jul 03 06:01:51 PM PDT 24
Finished Jul 03 06:03:03 PM PDT 24
Peak memory 255104 kb
Host smart-bef700b1-9398-45dc-a2d5-6501090d48ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631472753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1631472753
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2791517494
Short name T883
Test name
Test status
Simulation time 3349033042 ps
CPU time 30.19 seconds
Started Jul 03 06:01:54 PM PDT 24
Finished Jul 03 06:02:24 PM PDT 24
Peak memory 225732 kb
Host smart-3457f932-0f3b-4b02-a9b9-213c2e19ce9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791517494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2791517494
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2697520230
Short name T900
Test name
Test status
Simulation time 85068152 ps
CPU time 2.36 seconds
Started Jul 03 06:01:53 PM PDT 24
Finished Jul 03 06:01:56 PM PDT 24
Peak memory 225580 kb
Host smart-d1949ee5-8fc1-49f7-b2fd-451de76fb8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697520230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2697520230
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3310754172
Short name T776
Test name
Test status
Simulation time 210748961 ps
CPU time 1.05 seconds
Started Jul 03 06:01:50 PM PDT 24
Finished Jul 03 06:01:52 PM PDT 24
Peak memory 217636 kb
Host smart-73fdc25d-10f2-4a1d-9fe3-96fd9fa2a157
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310754172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3310754172
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2079423010
Short name T557
Test name
Test status
Simulation time 401102632 ps
CPU time 6.84 seconds
Started Jul 03 06:01:48 PM PDT 24
Finished Jul 03 06:01:55 PM PDT 24
Peak memory 234744 kb
Host smart-d47e5695-4f2d-4bb8-bc66-43c605a184cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079423010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2079423010
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1361226970
Short name T817
Test name
Test status
Simulation time 4663663402 ps
CPU time 16.33 seconds
Started Jul 03 06:01:46 PM PDT 24
Finished Jul 03 06:02:03 PM PDT 24
Peak memory 241268 kb
Host smart-2fcf6c48-378b-4489-a512-63d573dad14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361226970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1361226970
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2477114402
Short name T791
Test name
Test status
Simulation time 428597339 ps
CPU time 5.69 seconds
Started Jul 03 06:01:57 PM PDT 24
Finished Jul 03 06:02:03 PM PDT 24
Peak memory 223444 kb
Host smart-f8b60d77-48dc-4dcf-a1d7-fb70dda5bd2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2477114402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2477114402
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.571742382
Short name T282
Test name
Test status
Simulation time 1998679478 ps
CPU time 19.67 seconds
Started Jul 03 06:01:47 PM PDT 24
Finished Jul 03 06:02:07 PM PDT 24
Peak memory 217380 kb
Host smart-a4a59775-4f41-413a-84c2-92b81806238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571742382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.571742382
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2178734877
Short name T751
Test name
Test status
Simulation time 1317334623 ps
CPU time 3.45 seconds
Started Jul 03 06:01:49 PM PDT 24
Finished Jul 03 06:01:53 PM PDT 24
Peak memory 217280 kb
Host smart-8f46986a-7f0f-487d-a53f-c7863ebb39aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178734877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2178734877
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4033047203
Short name T307
Test name
Test status
Simulation time 3044933921 ps
CPU time 12.87 seconds
Started Jul 03 06:01:48 PM PDT 24
Finished Jul 03 06:02:01 PM PDT 24
Peak memory 217524 kb
Host smart-79f76bbe-1452-4914-9bc8-75579025b236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033047203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4033047203
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1969416464
Short name T434
Test name
Test status
Simulation time 371688972 ps
CPU time 0.95 seconds
Started Jul 03 06:01:47 PM PDT 24
Finished Jul 03 06:01:48 PM PDT 24
Peak memory 206996 kb
Host smart-5a41aa0d-9fd2-4333-8313-c1e16cd3eb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969416464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1969416464
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3755606970
Short name T47
Test name
Test status
Simulation time 10123639327 ps
CPU time 9.1 seconds
Started Jul 03 06:01:53 PM PDT 24
Finished Jul 03 06:02:02 PM PDT 24
Peak memory 225764 kb
Host smart-f4b0a7f4-1fd6-490a-bf39-2f7ae9fc6a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755606970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3755606970
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.927790014
Short name T391
Test name
Test status
Simulation time 199974110 ps
CPU time 0.71 seconds
Started Jul 03 06:01:56 PM PDT 24
Finished Jul 03 06:01:58 PM PDT 24
Peak memory 206748 kb
Host smart-9f004f98-3b49-4719-a8ef-f69882757160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927790014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.927790014
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.578351703
Short name T978
Test name
Test status
Simulation time 8963783619 ps
CPU time 19.4 seconds
Started Jul 03 06:02:07 PM PDT 24
Finished Jul 03 06:02:27 PM PDT 24
Peak memory 233908 kb
Host smart-1fc7047e-d7f0-4d7f-8c59-f9c69eef60a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578351703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.578351703
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.792973675
Short name T769
Test name
Test status
Simulation time 28958494 ps
CPU time 0.8 seconds
Started Jul 03 06:01:58 PM PDT 24
Finished Jul 03 06:01:59 PM PDT 24
Peak memory 207864 kb
Host smart-17d2d876-40ee-43a2-8e07-d3c070e8d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792973675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.792973675
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2774932312
Short name T236
Test name
Test status
Simulation time 2683231658 ps
CPU time 13.05 seconds
Started Jul 03 06:01:58 PM PDT 24
Finished Jul 03 06:02:11 PM PDT 24
Peak memory 235256 kb
Host smart-308c75ba-f25f-439a-9806-d7f5a10e4c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774932312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2774932312
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2581372507
Short name T478
Test name
Test status
Simulation time 40678858687 ps
CPU time 173.7 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:05:02 PM PDT 24
Peak memory 250408 kb
Host smart-91388346-29b4-4abd-a5b6-14bd5c893f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581372507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2581372507
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3650178073
Short name T542
Test name
Test status
Simulation time 3047580094 ps
CPU time 68.85 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:03:24 PM PDT 24
Peak memory 257592 kb
Host smart-c5af8374-47c2-4f40-96ce-45dfb20a43bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650178073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3650178073
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1522815147
Short name T683
Test name
Test status
Simulation time 1711472703 ps
CPU time 14.2 seconds
Started Jul 03 06:01:55 PM PDT 24
Finished Jul 03 06:02:09 PM PDT 24
Peak memory 234568 kb
Host smart-940c3320-c00a-4ede-a0fd-4134f5782ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522815147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1522815147
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1265243507
Short name T376
Test name
Test status
Simulation time 18836327407 ps
CPU time 14.47 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:02:23 PM PDT 24
Peak memory 242096 kb
Host smart-e544e5ea-8c7e-483d-aa51-25d489be0d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265243507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1265243507
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1191896933
Short name T530
Test name
Test status
Simulation time 138599580 ps
CPU time 4.25 seconds
Started Jul 03 06:01:55 PM PDT 24
Finished Jul 03 06:02:00 PM PDT 24
Peak memory 225564 kb
Host smart-095b474e-6572-43d5-a1f9-71878103fbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191896933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1191896933
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4249993321
Short name T720
Test name
Test status
Simulation time 25702692425 ps
CPU time 67.01 seconds
Started Jul 03 06:01:57 PM PDT 24
Finished Jul 03 06:03:04 PM PDT 24
Peak memory 233860 kb
Host smart-d2d9ccf0-f6ed-4676-9605-7546c6fa7386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249993321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4249993321
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1482166631
Short name T860
Test name
Test status
Simulation time 15163368 ps
CPU time 1.06 seconds
Started Jul 03 06:01:55 PM PDT 24
Finished Jul 03 06:01:57 PM PDT 24
Peak memory 217692 kb
Host smart-68724989-6e17-436c-b2fa-d262dc2d9211
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482166631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1482166631
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.458269956
Short name T965
Test name
Test status
Simulation time 2347937982 ps
CPU time 3.73 seconds
Started Jul 03 06:01:56 PM PDT 24
Finished Jul 03 06:02:00 PM PDT 24
Peak memory 225596 kb
Host smart-e13fd3fc-6416-4270-8da9-6f8fb8085e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458269956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.458269956
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3156874548
Short name T92
Test name
Test status
Simulation time 10298038675 ps
CPU time 28.29 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:29 PM PDT 24
Peak memory 233948 kb
Host smart-437959c5-33ab-4a17-9591-2f79f550cb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156874548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3156874548
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.87116600
Short name T632
Test name
Test status
Simulation time 135321404 ps
CPU time 3.98 seconds
Started Jul 03 06:01:53 PM PDT 24
Finished Jul 03 06:01:58 PM PDT 24
Peak memory 223604 kb
Host smart-5777e06c-16e2-41e7-bcba-fdee07843179
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=87116600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direc
t.87116600
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.764609691
Short name T890
Test name
Test status
Simulation time 3596188278 ps
CPU time 26.93 seconds
Started Jul 03 06:02:01 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 220912 kb
Host smart-19098e8c-b0b6-4eea-be88-acb4ca83b518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764609691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.764609691
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2063573842
Short name T382
Test name
Test status
Simulation time 5531064136 ps
CPU time 2.93 seconds
Started Jul 03 06:01:57 PM PDT 24
Finished Jul 03 06:02:00 PM PDT 24
Peak memory 217328 kb
Host smart-642bc3bf-6182-4b02-abf0-1851ce27ae5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063573842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2063573842
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1882602249
Short name T399
Test name
Test status
Simulation time 203765330 ps
CPU time 3.29 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:05 PM PDT 24
Peak memory 217328 kb
Host smart-bfb1f338-9c42-4391-9f20-1aacdd73c496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882602249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1882602249
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3369112156
Short name T428
Test name
Test status
Simulation time 88746600 ps
CPU time 0.98 seconds
Started Jul 03 06:01:56 PM PDT 24
Finished Jul 03 06:01:57 PM PDT 24
Peak memory 207984 kb
Host smart-422d52d8-4a25-45a4-9870-13eaa8bc4167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369112156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3369112156
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1340410366
Short name T349
Test name
Test status
Simulation time 490465839 ps
CPU time 2.7 seconds
Started Jul 03 06:01:56 PM PDT 24
Finished Jul 03 06:01:59 PM PDT 24
Peak memory 225540 kb
Host smart-c1dfff24-017f-4d58-b2ca-85ec3e094991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340410366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1340410366
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3860570910
Short name T1017
Test name
Test status
Simulation time 48997840 ps
CPU time 0.7 seconds
Started Jul 03 06:02:12 PM PDT 24
Finished Jul 03 06:02:13 PM PDT 24
Peak memory 206416 kb
Host smart-6c31836b-f296-45fc-80ea-062ac4f48e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860570910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3860570910
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2939401810
Short name T777
Test name
Test status
Simulation time 116420265 ps
CPU time 2.71 seconds
Started Jul 03 06:02:12 PM PDT 24
Finished Jul 03 06:02:15 PM PDT 24
Peak memory 233524 kb
Host smart-ba934538-ac0d-4445-ada5-e4b0fb1facd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939401810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2939401810
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1099127587
Short name T418
Test name
Test status
Simulation time 28451174 ps
CPU time 0.75 seconds
Started Jul 03 06:01:55 PM PDT 24
Finished Jul 03 06:01:56 PM PDT 24
Peak memory 206820 kb
Host smart-63ed05a3-a810-47c0-b0e5-8eb6f62110b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099127587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1099127587
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.833728719
Short name T48
Test name
Test status
Simulation time 24359362299 ps
CPU time 61.68 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:03:16 PM PDT 24
Peak memory 265724 kb
Host smart-6eb3642b-2f8d-4b06-bf03-c1696b58b1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833728719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.833728719
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3030205450
Short name T136
Test name
Test status
Simulation time 15621336635 ps
CPU time 134.16 seconds
Started Jul 03 06:02:02 PM PDT 24
Finished Jul 03 06:04:16 PM PDT 24
Peak memory 254552 kb
Host smart-b637e7b6-ed39-48fb-9cc1-7fb98fe4734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030205450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3030205450
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.477420635
Short name T960
Test name
Test status
Simulation time 3616918688 ps
CPU time 22.34 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:23 PM PDT 24
Peak memory 242232 kb
Host smart-d2e8b9ce-f3de-4c9e-a3e5-fdbb85f23b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477420635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.477420635
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.817734210
Short name T273
Test name
Test status
Simulation time 5273315849 ps
CPU time 20.71 seconds
Started Jul 03 06:02:03 PM PDT 24
Finished Jul 03 06:02:24 PM PDT 24
Peak memory 237380 kb
Host smart-4b0c0dc6-b493-483c-aada-2c768c0ba175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817734210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.817734210
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2346385813
Short name T487
Test name
Test status
Simulation time 9856465665 ps
CPU time 82.77 seconds
Started Jul 03 06:02:12 PM PDT 24
Finished Jul 03 06:03:35 PM PDT 24
Peak memory 250752 kb
Host smart-9fbd5064-566c-4b80-b657-5ceb3f8125f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346385813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2346385813
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1829351003
Short name T939
Test name
Test status
Simulation time 381180097 ps
CPU time 6.82 seconds
Started Jul 03 06:02:09 PM PDT 24
Finished Jul 03 06:02:16 PM PDT 24
Peak memory 233820 kb
Host smart-91cca4a8-3c1d-4897-85f0-96a850333f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829351003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1829351003
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1493574497
Short name T300
Test name
Test status
Simulation time 2817719418 ps
CPU time 26.21 seconds
Started Jul 03 06:02:03 PM PDT 24
Finished Jul 03 06:02:29 PM PDT 24
Peak memory 232488 kb
Host smart-e8b7408f-b381-4d96-a851-664a667213d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493574497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1493574497
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.206383805
Short name T828
Test name
Test status
Simulation time 57073608 ps
CPU time 1.04 seconds
Started Jul 03 06:01:59 PM PDT 24
Finished Jul 03 06:02:01 PM PDT 24
Peak memory 218916 kb
Host smart-d2ae5b5c-09ea-400f-82f6-ea93cc61686e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206383805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.206383805
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.878833304
Short name T642
Test name
Test status
Simulation time 101503655 ps
CPU time 2.32 seconds
Started Jul 03 06:02:01 PM PDT 24
Finished Jul 03 06:02:04 PM PDT 24
Peak memory 224200 kb
Host smart-aa3e5f06-3b15-49ac-94f9-e19216d8bc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878833304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.878833304
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1515822376
Short name T601
Test name
Test status
Simulation time 11590772571 ps
CPU time 16.65 seconds
Started Jul 03 06:02:13 PM PDT 24
Finished Jul 03 06:02:30 PM PDT 24
Peak memory 233856 kb
Host smart-1a4d7ab6-748d-41e6-a157-83d73f363861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515822376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1515822376
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1560064476
Short name T326
Test name
Test status
Simulation time 3831367764 ps
CPU time 8.52 seconds
Started Jul 03 06:01:57 PM PDT 24
Finished Jul 03 06:02:06 PM PDT 24
Peak memory 223204 kb
Host smart-9b6a1ab7-7544-4d34-aa95-e795241c04b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1560064476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1560064476
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1993138654
Short name T938
Test name
Test status
Simulation time 11170214066 ps
CPU time 165.83 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:04:47 PM PDT 24
Peak memory 258620 kb
Host smart-bc3aaf96-e379-4d78-86a0-744e246d5b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993138654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1993138654
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.796459032
Short name T387
Test name
Test status
Simulation time 5955044785 ps
CPU time 17.71 seconds
Started Jul 03 06:01:56 PM PDT 24
Finished Jul 03 06:02:14 PM PDT 24
Peak memory 217780 kb
Host smart-9c8ecc24-8ef4-4e03-bb29-766a8e5ce575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796459032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.796459032
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3552268437
Short name T986
Test name
Test status
Simulation time 1260545713 ps
CPU time 5.11 seconds
Started Jul 03 06:02:07 PM PDT 24
Finished Jul 03 06:02:13 PM PDT 24
Peak memory 217332 kb
Host smart-35355c9e-102e-48ac-b2f8-3f2acb85298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552268437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3552268437
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3376560126
Short name T832
Test name
Test status
Simulation time 18994380 ps
CPU time 1.06 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:02:10 PM PDT 24
Peak memory 217184 kb
Host smart-fe975150-cff5-406b-b599-0206e72f8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376560126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3376560126
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3923219001
Short name T893
Test name
Test status
Simulation time 250563641 ps
CPU time 0.84 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:02:09 PM PDT 24
Peak memory 206976 kb
Host smart-3e5a685c-bae3-43f5-b635-6112df0bc705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923219001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3923219001
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4048761865
Short name T937
Test name
Test status
Simulation time 8831097364 ps
CPU time 14.8 seconds
Started Jul 03 06:02:13 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 238816 kb
Host smart-a2f2fa56-dab3-4c48-8e2d-bbcf5d65668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048761865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4048761865
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3747767051
Short name T806
Test name
Test status
Simulation time 38708627 ps
CPU time 0.72 seconds
Started Jul 03 06:02:05 PM PDT 24
Finished Jul 03 06:02:07 PM PDT 24
Peak memory 205808 kb
Host smart-47659538-7d6c-4484-bdb3-566c777d882e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747767051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3747767051
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3442030920
Short name T745
Test name
Test status
Simulation time 719337763 ps
CPU time 5.75 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:06 PM PDT 24
Peak memory 233740 kb
Host smart-4e7e094a-af53-4bc5-bd66-2ac4da7a147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442030920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3442030920
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2198025595
Short name T836
Test name
Test status
Simulation time 138887104 ps
CPU time 0.81 seconds
Started Jul 03 06:02:02 PM PDT 24
Finished Jul 03 06:02:04 PM PDT 24
Peak memory 207596 kb
Host smart-468e0bde-238d-47db-bdc2-ebd935d0363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198025595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2198025595
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2299025559
Short name T190
Test name
Test status
Simulation time 88143380004 ps
CPU time 615.79 seconds
Started Jul 03 06:01:59 PM PDT 24
Finished Jul 03 06:12:16 PM PDT 24
Peak memory 266592 kb
Host smart-e41229f3-3544-4e91-923c-061127747ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299025559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2299025559
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3428518308
Short name T413
Test name
Test status
Simulation time 2221275066 ps
CPU time 65.21 seconds
Started Jul 03 06:01:59 PM PDT 24
Finished Jul 03 06:03:05 PM PDT 24
Peak memory 258576 kb
Host smart-1a4edcdc-65db-4413-a05d-4e66675e69fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428518308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3428518308
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.59586569
Short name T455
Test name
Test status
Simulation time 4724498737 ps
CPU time 80.01 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:03:21 PM PDT 24
Peak memory 253628 kb
Host smart-542a7786-5fa6-417c-b818-3c82c13784d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59586569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.59586569
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1389620698
Short name T362
Test name
Test status
Simulation time 83867713 ps
CPU time 2.17 seconds
Started Jul 03 06:01:58 PM PDT 24
Finished Jul 03 06:02:00 PM PDT 24
Peak memory 233516 kb
Host smart-6b838ed0-7d6a-4c19-a55f-f53273293227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389620698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1389620698
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.634842953
Short name T513
Test name
Test status
Simulation time 2392259281 ps
CPU time 17.59 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:18 PM PDT 24
Peak memory 233916 kb
Host smart-10cd2ad7-4255-4b21-924f-471df6bfd090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634842953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.634842953
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2691265340
Short name T578
Test name
Test status
Simulation time 355278248 ps
CPU time 1.06 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:02 PM PDT 24
Peak memory 217724 kb
Host smart-b0e00b39-de13-43d0-9272-3ba4d386545c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691265340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2691265340
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.661621191
Short name T936
Test name
Test status
Simulation time 376408265 ps
CPU time 4.37 seconds
Started Jul 03 06:02:02 PM PDT 24
Finished Jul 03 06:02:06 PM PDT 24
Peak memory 225584 kb
Host smart-bdd84478-638e-496c-8bba-18dd835390db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661621191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.661621191
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2829005632
Short name T565
Test name
Test status
Simulation time 366082615 ps
CPU time 2.14 seconds
Started Jul 03 06:02:01 PM PDT 24
Finished Jul 03 06:02:04 PM PDT 24
Peak memory 224940 kb
Host smart-e5baabde-c051-4717-9cec-07245798c7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829005632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2829005632
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.380151825
Short name T341
Test name
Test status
Simulation time 700418976 ps
CPU time 3.88 seconds
Started Jul 03 06:01:59 PM PDT 24
Finished Jul 03 06:02:03 PM PDT 24
Peak memory 220824 kb
Host smart-5d48c194-f887-4efe-a7b2-2e4074115a89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=380151825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.380151825
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3859445146
Short name T29
Test name
Test status
Simulation time 4574489560 ps
CPU time 56.39 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:57 PM PDT 24
Peak memory 238684 kb
Host smart-fa08e2f3-8e4b-4f98-a84e-7598c72b7fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859445146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3859445146
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1830549017
Short name T439
Test name
Test status
Simulation time 10358527831 ps
CPU time 27.54 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 217512 kb
Host smart-10a79f69-bff9-4f8a-aef5-f7f8719abefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830549017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1830549017
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1491301677
Short name T853
Test name
Test status
Simulation time 15878068242 ps
CPU time 24.29 seconds
Started Jul 03 06:02:02 PM PDT 24
Finished Jul 03 06:02:27 PM PDT 24
Peak memory 217516 kb
Host smart-c682766b-a9c2-43cd-b968-b2fe5f69f4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491301677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1491301677
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.501182527
Short name T678
Test name
Test status
Simulation time 21130819 ps
CPU time 0.92 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:02 PM PDT 24
Peak memory 208032 kb
Host smart-8a85022f-0079-4519-b37e-9bc2128f884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501182527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.501182527
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2352748995
Short name T400
Test name
Test status
Simulation time 517047583 ps
CPU time 0.85 seconds
Started Jul 03 06:02:00 PM PDT 24
Finished Jul 03 06:02:01 PM PDT 24
Peak memory 206968 kb
Host smart-3d82ebd8-9267-4228-a6cc-135e4971732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352748995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2352748995
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1168932315
Short name T490
Test name
Test status
Simulation time 15787966295 ps
CPU time 13.75 seconds
Started Jul 03 06:01:59 PM PDT 24
Finished Jul 03 06:02:13 PM PDT 24
Peak memory 225644 kb
Host smart-a14192d2-d0c1-4175-b72d-2adfc31ed44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168932315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1168932315
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2361840445
Short name T442
Test name
Test status
Simulation time 46864173 ps
CPU time 0.71 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:07 PM PDT 24
Peak memory 206728 kb
Host smart-495a4906-466d-402b-9b50-ae1888392c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361840445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2361840445
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4145082308
Short name T748
Test name
Test status
Simulation time 272204504 ps
CPU time 5.67 seconds
Started Jul 03 06:02:04 PM PDT 24
Finished Jul 03 06:02:10 PM PDT 24
Peak memory 225576 kb
Host smart-a6627d91-d1c6-4425-9535-94f330aad767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145082308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4145082308
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2505253005
Short name T4
Test name
Test status
Simulation time 12576287 ps
CPU time 0.73 seconds
Started Jul 03 06:02:09 PM PDT 24
Finished Jul 03 06:02:10 PM PDT 24
Peak memory 206488 kb
Host smart-7947cb71-0cd8-4b3c-b182-1ec3bd7350c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505253005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2505253005
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1974752451
Short name T218
Test name
Test status
Simulation time 19021314388 ps
CPU time 140.68 seconds
Started Jul 03 06:02:02 PM PDT 24
Finished Jul 03 06:04:23 PM PDT 24
Peak memory 250368 kb
Host smart-c7c34f25-151e-4914-bbfc-909b5e4f4337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974752451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1974752451
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.856903542
Short name T730
Test name
Test status
Simulation time 31339630048 ps
CPU time 304.93 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:07:12 PM PDT 24
Peak memory 257032 kb
Host smart-85f87b9f-3341-4429-80a8-38e529231e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856903542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.856903542
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.294964279
Short name T821
Test name
Test status
Simulation time 3374950014 ps
CPU time 64.7 seconds
Started Jul 03 06:02:04 PM PDT 24
Finished Jul 03 06:03:09 PM PDT 24
Peak memory 253812 kb
Host smart-25281c2a-3c01-43c7-b8da-b185f5ea0f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294964279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.294964279
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1037271570
Short name T288
Test name
Test status
Simulation time 159574274 ps
CPU time 5.22 seconds
Started Jul 03 06:02:04 PM PDT 24
Finished Jul 03 06:02:09 PM PDT 24
Peak memory 225608 kb
Host smart-5e5cd632-63b1-43c0-9c07-91a956c25476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037271570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1037271570
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2880026688
Short name T37
Test name
Test status
Simulation time 116033661805 ps
CPU time 432.8 seconds
Started Jul 03 06:02:05 PM PDT 24
Finished Jul 03 06:09:18 PM PDT 24
Peak memory 266268 kb
Host smart-a0dee7e0-6109-4ad4-8213-f0dd24362bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880026688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2880026688
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.313277771
Short name T981
Test name
Test status
Simulation time 784927480 ps
CPU time 5.01 seconds
Started Jul 03 06:02:07 PM PDT 24
Finished Jul 03 06:02:12 PM PDT 24
Peak memory 225612 kb
Host smart-92ea1a04-921e-4f18-afea-3647f7d1e337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313277771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.313277771
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3194592710
Short name T447
Test name
Test status
Simulation time 18737870894 ps
CPU time 38.08 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:44 PM PDT 24
Peak memory 233928 kb
Host smart-e487a58a-7da9-4fa1-a437-9661a8610b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194592710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3194592710
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.720718992
Short name T494
Test name
Test status
Simulation time 26346454 ps
CPU time 1.03 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:08 PM PDT 24
Peak memory 217676 kb
Host smart-33baf31e-587c-4bd3-9a22-17db23e6b36f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720718992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.720718992
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1697303407
Short name T45
Test name
Test status
Simulation time 1211793908 ps
CPU time 6.4 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:13 PM PDT 24
Peak memory 225568 kb
Host smart-b9d57e71-9c56-473d-ab9e-40228940adc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697303407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1697303407
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.257528030
Short name T371
Test name
Test status
Simulation time 3330966524 ps
CPU time 10.11 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:17 PM PDT 24
Peak memory 225752 kb
Host smart-9e907bbe-593a-4fa4-b9e2-25b724b59021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257528030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.257528030
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3850179330
Short name T448
Test name
Test status
Simulation time 228314992 ps
CPU time 5.49 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:11 PM PDT 24
Peak memory 220324 kb
Host smart-7c5d6838-d5c8-490f-9909-8bbb4c4e9b86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3850179330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3850179330
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1730341529
Short name T839
Test name
Test status
Simulation time 1968999318 ps
CPU time 29.36 seconds
Started Jul 03 06:02:05 PM PDT 24
Finished Jul 03 06:02:35 PM PDT 24
Peak memory 242060 kb
Host smart-17240272-e9d6-4278-a27c-f01e3a9472b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730341529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1730341529
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2173987817
Short name T602
Test name
Test status
Simulation time 9375882647 ps
CPU time 23.17 seconds
Started Jul 03 06:02:05 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 217468 kb
Host smart-2b8c2a00-e97a-4bb3-8b87-45f62fb5c36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173987817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2173987817
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1394311707
Short name T301
Test name
Test status
Simulation time 19233839641 ps
CPU time 14.07 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:02:22 PM PDT 24
Peak memory 217556 kb
Host smart-83a34c19-b1e7-400c-9342-8bdc4ffe0861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394311707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1394311707
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3740914373
Short name T356
Test name
Test status
Simulation time 154173207 ps
CPU time 2.36 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:09 PM PDT 24
Peak memory 217396 kb
Host smart-8ff0cbd0-55cf-421a-89b4-f840ba13e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740914373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3740914373
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2271563799
Short name T321
Test name
Test status
Simulation time 39092946 ps
CPU time 0.75 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:07 PM PDT 24
Peak memory 207016 kb
Host smart-2978a606-1ca9-4e22-a763-ff50ae1452c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271563799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2271563799
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2001939786
Short name T905
Test name
Test status
Simulation time 4820296014 ps
CPU time 16.01 seconds
Started Jul 03 06:02:05 PM PDT 24
Finished Jul 03 06:02:22 PM PDT 24
Peak memory 233932 kb
Host smart-7d9a6af0-6771-4c67-974f-0bb664617dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001939786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2001939786
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.79044941
Short name T406
Test name
Test status
Simulation time 11345379 ps
CPU time 0.72 seconds
Started Jul 03 06:02:13 PM PDT 24
Finished Jul 03 06:02:14 PM PDT 24
Peak memory 206416 kb
Host smart-920cf880-9660-4575-bdb5-56dc16d57ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79044941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.79044941
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1093090347
Short name T795
Test name
Test status
Simulation time 283415627 ps
CPU time 2.25 seconds
Started Jul 03 06:02:07 PM PDT 24
Finished Jul 03 06:02:10 PM PDT 24
Peak memory 225160 kb
Host smart-e0b8b147-86b2-4bcf-b95c-a898cbb0c94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093090347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1093090347
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3536114926
Short name T157
Test name
Test status
Simulation time 19797273 ps
CPU time 0.77 seconds
Started Jul 03 06:02:05 PM PDT 24
Finished Jul 03 06:02:06 PM PDT 24
Peak memory 207568 kb
Host smart-f9156a8a-5c15-4548-bddd-c1a7521ebd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536114926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3536114926
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2958055499
Short name T385
Test name
Test status
Simulation time 14827549 ps
CPU time 0.78 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:02:10 PM PDT 24
Peak memory 216944 kb
Host smart-80054a1c-6d1d-4ea9-96f8-cc4c1b845377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958055499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2958055499
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3882049603
Short name T607
Test name
Test status
Simulation time 702398853412 ps
CPU time 353.23 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:08:01 PM PDT 24
Peak memory 250420 kb
Host smart-577743f4-9d34-4c61-a258-83741d3d8a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882049603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3882049603
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1620853513
Short name T268
Test name
Test status
Simulation time 12736255514 ps
CPU time 54.46 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:03:03 PM PDT 24
Peak memory 242056 kb
Host smart-369b92a2-b283-47d5-bd22-7c7e90304c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620853513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1620853513
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1436978259
Short name T220
Test name
Test status
Simulation time 3622938169 ps
CPU time 15.32 seconds
Started Jul 03 06:02:11 PM PDT 24
Finished Jul 03 06:02:27 PM PDT 24
Peak memory 237180 kb
Host smart-361724a5-b40f-4da4-a0d9-271364b5dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436978259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1436978259
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1179505700
Short name T396
Test name
Test status
Simulation time 3562299983 ps
CPU time 18.24 seconds
Started Jul 03 06:02:08 PM PDT 24
Finished Jul 03 06:02:27 PM PDT 24
Peak memory 233912 kb
Host smart-d4cefc2e-6bff-4da1-9063-1b243fb6b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179505700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1179505700
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2298394830
Short name T452
Test name
Test status
Simulation time 10620122114 ps
CPU time 7.44 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:14 PM PDT 24
Peak memory 237144 kb
Host smart-51716c4a-1222-469d-8288-532f60e33495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298394830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2298394830
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2197949032
Short name T972
Test name
Test status
Simulation time 16238750 ps
CPU time 1.07 seconds
Started Jul 03 06:02:07 PM PDT 24
Finished Jul 03 06:02:08 PM PDT 24
Peak memory 218984 kb
Host smart-aa813dd7-c188-498e-bc08-5ef0c052ee95
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197949032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2197949032
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3028183643
Short name T234
Test name
Test status
Simulation time 3422047186 ps
CPU time 4.56 seconds
Started Jul 03 06:02:09 PM PDT 24
Finished Jul 03 06:02:14 PM PDT 24
Peak memory 233852 kb
Host smart-1ec01135-3473-403f-a5ed-c2b596afd009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028183643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3028183643
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1231757183
Short name T902
Test name
Test status
Simulation time 3763567370 ps
CPU time 13.8 seconds
Started Jul 03 06:02:07 PM PDT 24
Finished Jul 03 06:02:21 PM PDT 24
Peak memory 233920 kb
Host smart-c0c2fc35-aa6f-4524-a735-8caa6d267181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231757183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1231757183
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1487885589
Short name T1001
Test name
Test status
Simulation time 228600417 ps
CPU time 2.96 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:10 PM PDT 24
Peak memory 219796 kb
Host smart-848888b5-6fde-45b5-b21e-1bcd15ee7d0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1487885589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1487885589
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.526383183
Short name T19
Test name
Test status
Simulation time 184098814891 ps
CPU time 331.1 seconds
Started Jul 03 06:02:11 PM PDT 24
Finished Jul 03 06:07:43 PM PDT 24
Peak memory 256480 kb
Host smart-f642989f-7ddc-47de-8fed-a6cca678a3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526383183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.526383183
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1610774283
Short name T332
Test name
Test status
Simulation time 31911993 ps
CPU time 0.73 seconds
Started Jul 03 06:02:05 PM PDT 24
Finished Jul 03 06:02:06 PM PDT 24
Peak memory 206632 kb
Host smart-5c031103-c0a4-44dc-9996-f384c582096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610774283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1610774283
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.210018560
Short name T305
Test name
Test status
Simulation time 1106785529 ps
CPU time 6.04 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:13 PM PDT 24
Peak memory 217312 kb
Host smart-d4925608-6bb2-4233-b762-68838a368cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210018560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.210018560
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1910444059
Short name T606
Test name
Test status
Simulation time 22708027 ps
CPU time 0.99 seconds
Started Jul 03 06:02:05 PM PDT 24
Finished Jul 03 06:02:06 PM PDT 24
Peak memory 208076 kb
Host smart-d0e31901-2602-4d38-bc3b-a3cef635d0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910444059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1910444059
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2761785350
Short name T926
Test name
Test status
Simulation time 89169205 ps
CPU time 0.73 seconds
Started Jul 03 06:02:03 PM PDT 24
Finished Jul 03 06:02:04 PM PDT 24
Peak memory 206912 kb
Host smart-fb0170c0-3124-4ed6-9683-8e965acd4233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761785350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2761785350
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.980870492
Short name T377
Test name
Test status
Simulation time 331379262 ps
CPU time 4.87 seconds
Started Jul 03 06:02:06 PM PDT 24
Finished Jul 03 06:02:12 PM PDT 24
Peak memory 241756 kb
Host smart-029ba30b-3778-48cf-84e3-6fd61aefc590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980870492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.980870492
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3509721555
Short name T401
Test name
Test status
Simulation time 31613865 ps
CPU time 0.68 seconds
Started Jul 03 06:00:54 PM PDT 24
Finished Jul 03 06:00:55 PM PDT 24
Peak memory 205812 kb
Host smart-77b7e5a0-c36a-43f6-94f6-6e1efae9a81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509721555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
509721555
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4102013221
Short name T740
Test name
Test status
Simulation time 762575520 ps
CPU time 5.05 seconds
Started Jul 03 06:00:55 PM PDT 24
Finished Jul 03 06:01:00 PM PDT 24
Peak memory 225564 kb
Host smart-0db6a5dd-548c-452f-98f4-6676cfacba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102013221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4102013221
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1400668567
Short name T809
Test name
Test status
Simulation time 85087872 ps
CPU time 0.78 seconds
Started Jul 03 06:00:48 PM PDT 24
Finished Jul 03 06:00:49 PM PDT 24
Peak memory 206540 kb
Host smart-fe6886fa-362c-42b6-bd06-891b2de1cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400668567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1400668567
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3977785894
Short name T39
Test name
Test status
Simulation time 162975951227 ps
CPU time 292.5 seconds
Started Jul 03 06:01:00 PM PDT 24
Finished Jul 03 06:05:53 PM PDT 24
Peak memory 257340 kb
Host smart-74e24cae-6718-41d3-b1de-cb14eaef3522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977785894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3977785894
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.578596879
Short name T198
Test name
Test status
Simulation time 30087420013 ps
CPU time 40.07 seconds
Started Jul 03 06:00:57 PM PDT 24
Finished Jul 03 06:01:38 PM PDT 24
Peak memory 242212 kb
Host smart-4735b138-33b5-4017-a358-0d58f71b86e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578596879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.578596879
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1801332565
Short name T13
Test name
Test status
Simulation time 2100900067 ps
CPU time 26.21 seconds
Started Jul 03 06:00:54 PM PDT 24
Finished Jul 03 06:01:20 PM PDT 24
Peak memory 242084 kb
Host smart-c67b057f-1cf4-48aa-a8f0-620da557fe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801332565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1801332565
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.929609922
Short name T430
Test name
Test status
Simulation time 850215198 ps
CPU time 11.95 seconds
Started Jul 03 06:00:57 PM PDT 24
Finished Jul 03 06:01:09 PM PDT 24
Peak memory 235288 kb
Host smart-4d2b847f-e687-4e88-a7d5-84ab92b5c2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929609922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.929609922
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2035837100
Short name T263
Test name
Test status
Simulation time 92508491147 ps
CPU time 105.12 seconds
Started Jul 03 06:00:57 PM PDT 24
Finished Jul 03 06:02:43 PM PDT 24
Peak memory 258320 kb
Host smart-bfe4051c-fdec-4b6a-886a-59edfba05f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035837100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2035837100
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.832557514
Short name T787
Test name
Test status
Simulation time 157609116 ps
CPU time 2.24 seconds
Started Jul 03 06:00:56 PM PDT 24
Finished Jul 03 06:00:59 PM PDT 24
Peak memory 233520 kb
Host smart-5aaca206-c2d6-46a8-a86c-70667b29147a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832557514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.832557514
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.695006476
Short name T222
Test name
Test status
Simulation time 294569798 ps
CPU time 3.92 seconds
Started Jul 03 06:00:53 PM PDT 24
Finished Jul 03 06:00:57 PM PDT 24
Peak memory 233988 kb
Host smart-d088eae0-5b71-4fe4-8077-59d24562a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695006476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.695006476
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.684259870
Short name T661
Test name
Test status
Simulation time 171838460 ps
CPU time 1.08 seconds
Started Jul 03 06:00:53 PM PDT 24
Finished Jul 03 06:00:54 PM PDT 24
Peak memory 217668 kb
Host smart-a60aef3c-757b-4e44-97a0-e42a0bf4bb01
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684259870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.684259870
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1509995885
Short name T892
Test name
Test status
Simulation time 7890767662 ps
CPU time 13.37 seconds
Started Jul 03 06:00:59 PM PDT 24
Finished Jul 03 06:01:13 PM PDT 24
Peak memory 241292 kb
Host smart-14574281-f8fc-42ab-a0fc-e325f0d3d721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509995885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1509995885
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2826893471
Short name T333
Test name
Test status
Simulation time 1064207887 ps
CPU time 3.64 seconds
Started Jul 03 06:00:54 PM PDT 24
Finished Jul 03 06:00:58 PM PDT 24
Peak memory 225528 kb
Host smart-087629eb-fba1-4864-bd77-8a36514ef5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826893471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2826893471
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2394040504
Short name T752
Test name
Test status
Simulation time 1116260623 ps
CPU time 3.58 seconds
Started Jul 03 06:01:00 PM PDT 24
Finished Jul 03 06:01:03 PM PDT 24
Peak memory 220296 kb
Host smart-9ccefc1e-442a-498e-ab99-dcdc9e53aa18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2394040504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2394040504
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3139693207
Short name T69
Test name
Test status
Simulation time 276311264 ps
CPU time 1.2 seconds
Started Jul 03 06:00:57 PM PDT 24
Finished Jul 03 06:00:59 PM PDT 24
Peak memory 236808 kb
Host smart-1f611132-4d1c-46b2-aa7a-8ec5fb8238ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139693207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3139693207
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2374481095
Short name T286
Test name
Test status
Simulation time 132151287 ps
CPU time 0.97 seconds
Started Jul 03 06:01:02 PM PDT 24
Finished Jul 03 06:01:03 PM PDT 24
Peak memory 207728 kb
Host smart-b9aa5d5d-c108-4bec-8288-328b1ad79c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374481095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2374481095
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3108482517
Short name T563
Test name
Test status
Simulation time 3421550829 ps
CPU time 7.49 seconds
Started Jul 03 06:00:56 PM PDT 24
Finished Jul 03 06:01:04 PM PDT 24
Peak memory 219336 kb
Host smart-4766d481-a3f0-4f72-aca9-b0bfa1c7fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108482517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3108482517
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3036910430
Short name T394
Test name
Test status
Simulation time 11135583 ps
CPU time 0.72 seconds
Started Jul 03 06:00:58 PM PDT 24
Finished Jul 03 06:00:59 PM PDT 24
Peak memory 206544 kb
Host smart-630b3104-c2ee-4b91-81b8-3e719c8c37f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036910430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3036910430
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2263019633
Short name T539
Test name
Test status
Simulation time 439816464 ps
CPU time 2.52 seconds
Started Jul 03 06:00:55 PM PDT 24
Finished Jul 03 06:00:58 PM PDT 24
Peak memory 217364 kb
Host smart-b827e2da-b950-4c83-86bf-cc15686304e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263019633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2263019633
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2679489917
Short name T808
Test name
Test status
Simulation time 196022909 ps
CPU time 0.9 seconds
Started Jul 03 06:00:53 PM PDT 24
Finished Jul 03 06:00:54 PM PDT 24
Peak memory 207192 kb
Host smart-36fb5d4a-0adf-4932-bf1b-1ca3778fd810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679489917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2679489917
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3490947326
Short name T392
Test name
Test status
Simulation time 2372322872 ps
CPU time 10.02 seconds
Started Jul 03 06:00:54 PM PDT 24
Finished Jul 03 06:01:04 PM PDT 24
Peak memory 233956 kb
Host smart-e0cb6cbf-e899-4973-969e-4637b26349c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490947326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3490947326
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3077491381
Short name T1018
Test name
Test status
Simulation time 64491834 ps
CPU time 0.71 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:02:17 PM PDT 24
Peak memory 206316 kb
Host smart-6c3d860c-306b-4f18-97d1-bc4be6ebdc7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077491381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3077491381
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.713391292
Short name T741
Test name
Test status
Simulation time 321029159 ps
CPU time 4.85 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:02:21 PM PDT 24
Peak memory 233788 kb
Host smart-1df421fd-8c71-4404-9334-aa1631508abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713391292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.713391292
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3647424216
Short name T414
Test name
Test status
Simulation time 19296407 ps
CPU time 0.77 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:02:15 PM PDT 24
Peak memory 207548 kb
Host smart-0d39e1d2-92a9-439e-a60b-d7658a830070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647424216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3647424216
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1832615240
Short name T195
Test name
Test status
Simulation time 2156399384 ps
CPU time 27.84 seconds
Started Jul 03 06:02:20 PM PDT 24
Finished Jul 03 06:02:48 PM PDT 24
Peak memory 237572 kb
Host smart-40aec8bf-22c4-4e37-9a57-c82babe1b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832615240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1832615240
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3771495193
Short name T395
Test name
Test status
Simulation time 16604227179 ps
CPU time 183.77 seconds
Started Jul 03 06:02:20 PM PDT 24
Finished Jul 03 06:05:24 PM PDT 24
Peak memory 258324 kb
Host smart-92c10871-4b52-4ac2-b78e-3f4011969e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771495193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3771495193
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3118646212
Short name T1002
Test name
Test status
Simulation time 1305608887 ps
CPU time 20.97 seconds
Started Jul 03 06:02:11 PM PDT 24
Finished Jul 03 06:02:32 PM PDT 24
Peak memory 235680 kb
Host smart-fb84f46f-cc48-42b2-8241-b18752ae9d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118646212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3118646212
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3229412191
Short name T49
Test name
Test status
Simulation time 215990176919 ps
CPU time 380.52 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:08:35 PM PDT 24
Peak memory 266600 kb
Host smart-01e0aa5d-0af8-4e4b-b278-8423a5e115dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229412191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3229412191
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4124195566
Short name T788
Test name
Test status
Simulation time 19795442094 ps
CPU time 34.29 seconds
Started Jul 03 06:02:12 PM PDT 24
Finished Jul 03 06:02:47 PM PDT 24
Peak memory 225756 kb
Host smart-5c4980d8-83ab-48fe-84df-60868dd64ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124195566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4124195566
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4286147254
Short name T636
Test name
Test status
Simulation time 188719381 ps
CPU time 2.86 seconds
Started Jul 03 06:02:12 PM PDT 24
Finished Jul 03 06:02:16 PM PDT 24
Peak memory 225472 kb
Host smart-ee7e6d4e-b2a7-40ef-a4c2-4568ec5b5467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286147254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4286147254
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1090127197
Short name T485
Test name
Test status
Simulation time 11591816525 ps
CPU time 16.77 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:02:31 PM PDT 24
Peak memory 225744 kb
Host smart-b7b996f2-1dc1-4ffe-91ac-600690b045bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090127197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1090127197
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1800931779
Short name T761
Test name
Test status
Simulation time 625740984 ps
CPU time 11.02 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:02:27 PM PDT 24
Peak memory 252420 kb
Host smart-64047155-e7de-4eb0-9497-e31b18d73593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800931779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1800931779
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1166036434
Short name T588
Test name
Test status
Simulation time 1689833004 ps
CPU time 17.67 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:02:32 PM PDT 24
Peak memory 220216 kb
Host smart-e2549ecf-fe46-46ab-bd86-cbe99da1a12c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1166036434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1166036434
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3675888732
Short name T600
Test name
Test status
Simulation time 21862531337 ps
CPU time 151.76 seconds
Started Jul 03 06:02:20 PM PDT 24
Finished Jul 03 06:04:52 PM PDT 24
Peak memory 274940 kb
Host smart-f546818e-0c66-4937-9506-5fdf41b29992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675888732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3675888732
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3954547449
Short name T408
Test name
Test status
Simulation time 10817763020 ps
CPU time 14.07 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 217396 kb
Host smart-6bbbabdd-5ae0-4bc2-a1df-16ba6e3ee57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954547449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3954547449
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.168935999
Short name T315
Test name
Test status
Simulation time 16107060160 ps
CPU time 10.19 seconds
Started Jul 03 06:02:11 PM PDT 24
Finished Jul 03 06:02:22 PM PDT 24
Peak memory 217500 kb
Host smart-0905c14a-5297-42fb-8c49-4c1d0354fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168935999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.168935999
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.260789356
Short name T303
Test name
Test status
Simulation time 1049442053 ps
CPU time 1.19 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:02:16 PM PDT 24
Peak memory 208832 kb
Host smart-3d8e9176-5073-49ff-9c94-1170dcfe3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260789356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.260789356
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3697582169
Short name T446
Test name
Test status
Simulation time 74607857 ps
CPU time 0.79 seconds
Started Jul 03 06:02:13 PM PDT 24
Finished Jul 03 06:02:14 PM PDT 24
Peak memory 206996 kb
Host smart-d4ede32f-833d-40df-8927-cce57889123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697582169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3697582169
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2121408336
Short name T582
Test name
Test status
Simulation time 15003843812 ps
CPU time 16.92 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:02:33 PM PDT 24
Peak memory 233912 kb
Host smart-a9233fe6-d325-4aae-96c6-aa943cc57acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121408336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2121408336
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3504505359
Short name T660
Test name
Test status
Simulation time 17089870 ps
CPU time 0.71 seconds
Started Jul 03 06:02:24 PM PDT 24
Finished Jul 03 06:02:25 PM PDT 24
Peak memory 206404 kb
Host smart-b0844f46-3326-49c3-af25-088cd760e1e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504505359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3504505359
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3997129237
Short name T983
Test name
Test status
Simulation time 1215475981 ps
CPU time 2.26 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:02:19 PM PDT 24
Peak memory 225564 kb
Host smart-368a8188-8c06-43ad-a1f4-c22a0f45a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997129237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3997129237
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3123224244
Short name T137
Test name
Test status
Simulation time 63415698 ps
CPU time 0.83 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:02:17 PM PDT 24
Peak memory 207860 kb
Host smart-645b781d-2741-4fb3-ba2e-a2b28de15359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123224244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3123224244
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1542262373
Short name T258
Test name
Test status
Simulation time 25920482974 ps
CPU time 210.48 seconds
Started Jul 03 06:02:20 PM PDT 24
Finished Jul 03 06:05:51 PM PDT 24
Peak memory 257068 kb
Host smart-247038fc-c013-4fcf-9b40-e7dca2055db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542262373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1542262373
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1355534261
Short name T833
Test name
Test status
Simulation time 4006567851 ps
CPU time 59.64 seconds
Started Jul 03 06:02:21 PM PDT 24
Finished Jul 03 06:03:20 PM PDT 24
Peak memory 250568 kb
Host smart-a72a4818-3b9a-4934-9d3d-a9d86068d5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355534261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1355534261
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.774609130
Short name T803
Test name
Test status
Simulation time 15178261881 ps
CPU time 142.92 seconds
Started Jul 03 06:02:20 PM PDT 24
Finished Jul 03 06:04:43 PM PDT 24
Peak memory 250316 kb
Host smart-bf7e6659-24cb-4528-a3c8-b8d1da095182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774609130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.774609130
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2748536801
Short name T274
Test name
Test status
Simulation time 13864114148 ps
CPU time 13 seconds
Started Jul 03 06:02:22 PM PDT 24
Finished Jul 03 06:02:35 PM PDT 24
Peak memory 250360 kb
Host smart-8f80d455-5d44-4297-b435-ac823771b3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748536801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2748536801
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.465416
Short name T212
Test name
Test status
Simulation time 12315464410 ps
CPU time 106.95 seconds
Started Jul 03 06:02:19 PM PDT 24
Finished Jul 03 06:04:06 PM PDT 24
Peak memory 253724 kb
Host smart-7a4b6f64-2175-4e2a-b7c2-73bcf13d7025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.465416
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2450851169
Short name T185
Test name
Test status
Simulation time 9414063225 ps
CPU time 8.51 seconds
Started Jul 03 06:02:21 PM PDT 24
Finished Jul 03 06:02:29 PM PDT 24
Peak memory 225708 kb
Host smart-005bd16b-ac5d-4407-a433-eb8f58d19a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450851169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2450851169
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2653319615
Short name T502
Test name
Test status
Simulation time 6996669752 ps
CPU time 25.14 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:02:40 PM PDT 24
Peak memory 225760 kb
Host smart-89de1511-7d50-4d02-be90-71d9f86ebd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653319615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2653319615
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.359861061
Short name T796
Test name
Test status
Simulation time 4713293312 ps
CPU time 15.27 seconds
Started Jul 03 06:02:15 PM PDT 24
Finished Jul 03 06:02:31 PM PDT 24
Peak memory 233940 kb
Host smart-3d261d11-7532-4b82-8004-50b0f04494f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359861061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.359861061
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2748693592
Short name T810
Test name
Test status
Simulation time 22261472368 ps
CPU time 12.22 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 237280 kb
Host smart-35f4931d-4843-4118-be47-2c907cd658a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748693592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2748693592
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2276642775
Short name T476
Test name
Test status
Simulation time 895820016 ps
CPU time 4.6 seconds
Started Jul 03 06:02:18 PM PDT 24
Finished Jul 03 06:02:23 PM PDT 24
Peak memory 224084 kb
Host smart-4fefbca2-33cf-46e9-8454-44d318ea8e69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2276642775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2276642775
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.91555703
Short name T555
Test name
Test status
Simulation time 403568484 ps
CPU time 1.11 seconds
Started Jul 03 06:02:21 PM PDT 24
Finished Jul 03 06:02:23 PM PDT 24
Peak memory 208544 kb
Host smart-f6dc676e-da03-45f3-a053-3777e06f79d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91555703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress
_all.91555703
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1855908855
Short name T649
Test name
Test status
Simulation time 33138092408 ps
CPU time 46.85 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:03:03 PM PDT 24
Peak memory 217564 kb
Host smart-6b858ced-5158-4b1a-86fb-e26f14fbcec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855908855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1855908855
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2122493524
Short name T2
Test name
Test status
Simulation time 12108977 ps
CPU time 0.7 seconds
Started Jul 03 06:02:16 PM PDT 24
Finished Jul 03 06:02:17 PM PDT 24
Peak memory 206656 kb
Host smart-26e1228b-7159-41aa-9232-1d6e0f7fad46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122493524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2122493524
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2795338356
Short name T868
Test name
Test status
Simulation time 306109243 ps
CPU time 3.76 seconds
Started Jul 03 06:02:14 PM PDT 24
Finished Jul 03 06:02:19 PM PDT 24
Peak memory 217448 kb
Host smart-83ee670d-bc3b-471e-ba6a-d3e3e1e2abf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795338356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2795338356
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3950978230
Short name T325
Test name
Test status
Simulation time 143898298 ps
CPU time 0.83 seconds
Started Jul 03 06:02:15 PM PDT 24
Finished Jul 03 06:02:16 PM PDT 24
Peak memory 206952 kb
Host smart-3fe747fc-2ab4-4e29-a32c-47c538493849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950978230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3950978230
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1220046375
Short name T73
Test name
Test status
Simulation time 3881156514 ps
CPU time 15.92 seconds
Started Jul 03 06:02:17 PM PDT 24
Finished Jul 03 06:02:33 PM PDT 24
Peak memory 249932 kb
Host smart-024f644e-1a7e-4a4a-829b-f6f46e4a0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220046375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1220046375
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4101880521
Short name T456
Test name
Test status
Simulation time 25836619 ps
CPU time 0.74 seconds
Started Jul 03 06:02:26 PM PDT 24
Finished Jul 03 06:02:26 PM PDT 24
Peak memory 205812 kb
Host smart-d0291586-f452-400e-a90c-57eb2adcf754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101880521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4101880521
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1450585875
Short name T294
Test name
Test status
Simulation time 950286855 ps
CPU time 5.65 seconds
Started Jul 03 06:02:27 PM PDT 24
Finished Jul 03 06:02:33 PM PDT 24
Peak memory 225432 kb
Host smart-8da1142f-0f08-4325-a4ac-d58564ec58b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450585875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1450585875
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3480939389
Short name T984
Test name
Test status
Simulation time 96644891 ps
CPU time 0.78 seconds
Started Jul 03 06:02:26 PM PDT 24
Finished Jul 03 06:02:27 PM PDT 24
Peak memory 207548 kb
Host smart-28d8fb50-bfee-4a46-9b96-0e2c7122fee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480939389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3480939389
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3341749172
Short name T431
Test name
Test status
Simulation time 29043486703 ps
CPU time 27.62 seconds
Started Jul 03 06:02:26 PM PDT 24
Finished Jul 03 06:02:54 PM PDT 24
Peak memory 250304 kb
Host smart-b38ef743-3579-4dc4-aad6-ea2894525f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341749172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3341749172
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1405978668
Short name T143
Test name
Test status
Simulation time 15104330396 ps
CPU time 144.18 seconds
Started Jul 03 06:02:28 PM PDT 24
Finished Jul 03 06:04:53 PM PDT 24
Peak memory 261876 kb
Host smart-874cfb89-1efb-4966-b2ca-67a79b71c4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405978668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1405978668
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3179319366
Short name T634
Test name
Test status
Simulation time 6357597988 ps
CPU time 90.96 seconds
Started Jul 03 06:02:25 PM PDT 24
Finished Jul 03 06:03:57 PM PDT 24
Peak memory 266832 kb
Host smart-68e928ef-a935-4b2d-8e33-618d5ed25836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179319366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3179319366
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2032423353
Short name T1015
Test name
Test status
Simulation time 119233969 ps
CPU time 3.18 seconds
Started Jul 03 06:02:27 PM PDT 24
Finished Jul 03 06:02:31 PM PDT 24
Peak memory 236808 kb
Host smart-e28aa2fa-f6be-4c8f-8bc0-85e09f512866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032423353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2032423353
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.650180964
Short name T580
Test name
Test status
Simulation time 1910406670 ps
CPU time 17.18 seconds
Started Jul 03 06:02:26 PM PDT 24
Finished Jul 03 06:02:44 PM PDT 24
Peak memory 225556 kb
Host smart-012423db-c69b-4b78-91b1-8f5b876ba7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650180964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.650180964
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.594628781
Short name T734
Test name
Test status
Simulation time 168098187 ps
CPU time 5.21 seconds
Started Jul 03 06:02:23 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 233812 kb
Host smart-f7d53d34-1eb3-47cb-bc4e-b81599b39927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594628781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.594628781
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.8734805
Short name T664
Test name
Test status
Simulation time 4930604259 ps
CPU time 40.84 seconds
Started Jul 03 06:02:21 PM PDT 24
Finished Jul 03 06:03:02 PM PDT 24
Peak memory 233860 kb
Host smart-d09ba49d-cf70-4cba-987c-62884c914a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8734805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.8734805
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.940294507
Short name T691
Test name
Test status
Simulation time 2165105949 ps
CPU time 7.01 seconds
Started Jul 03 06:02:29 PM PDT 24
Finished Jul 03 06:02:36 PM PDT 24
Peak memory 240460 kb
Host smart-f3c53d49-9832-4e24-bae9-909ea1617d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940294507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.940294507
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2114238660
Short name T445
Test name
Test status
Simulation time 724392586 ps
CPU time 6.4 seconds
Started Jul 03 06:02:21 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 233840 kb
Host smart-7fb68e2b-0fe0-49bf-9655-095869713299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114238660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2114238660
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4153041
Short name T364
Test name
Test status
Simulation time 448056725 ps
CPU time 7.74 seconds
Started Jul 03 06:02:26 PM PDT 24
Finished Jul 03 06:02:34 PM PDT 24
Peak memory 223088 kb
Host smart-5de454ae-f1f7-4f1d-b4cf-c9c94168fc0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4153041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.4153041
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4210241495
Short name T384
Test name
Test status
Simulation time 11580490455 ps
CPU time 32.41 seconds
Started Jul 03 06:02:24 PM PDT 24
Finished Jul 03 06:02:57 PM PDT 24
Peak memory 221908 kb
Host smart-a66b404b-ae30-4801-94e9-a4b15fc68167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210241495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4210241495
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4218965588
Short name T594
Test name
Test status
Simulation time 3613551846 ps
CPU time 11.98 seconds
Started Jul 03 06:02:24 PM PDT 24
Finished Jul 03 06:02:36 PM PDT 24
Peak memory 217476 kb
Host smart-d6136b35-5989-4f9d-b52b-b93f7019afdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218965588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4218965588
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.602558408
Short name T422
Test name
Test status
Simulation time 295886114 ps
CPU time 0.89 seconds
Started Jul 03 06:02:21 PM PDT 24
Finished Jul 03 06:02:22 PM PDT 24
Peak memory 208568 kb
Host smart-7d447073-5d9d-40f4-b370-8e5dc1deba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602558408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.602558408
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.125318173
Short name T468
Test name
Test status
Simulation time 31560006 ps
CPU time 0.76 seconds
Started Jul 03 06:02:24 PM PDT 24
Finished Jul 03 06:02:25 PM PDT 24
Peak memory 207324 kb
Host smart-cab49284-97cf-4f83-87a3-a701dfafc105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125318173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.125318173
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1144576630
Short name T831
Test name
Test status
Simulation time 1879684419 ps
CPU time 8.84 seconds
Started Jul 03 06:02:26 PM PDT 24
Finished Jul 03 06:02:35 PM PDT 24
Peak memory 233748 kb
Host smart-b97f54ea-f261-48cd-a1b0-f4ada4c5dee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144576630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1144576630
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.219115218
Short name T64
Test name
Test status
Simulation time 22170701 ps
CPU time 0.72 seconds
Started Jul 03 06:02:34 PM PDT 24
Finished Jul 03 06:02:35 PM PDT 24
Peak memory 205824 kb
Host smart-15af6773-fb8b-46b5-9e75-9b31c0e95628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219115218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.219115218
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1538247302
Short name T553
Test name
Test status
Simulation time 9124494508 ps
CPU time 9.78 seconds
Started Jul 03 06:02:34 PM PDT 24
Finished Jul 03 06:02:44 PM PDT 24
Peak memory 225736 kb
Host smart-5b9ab195-6a15-4621-9311-52a4373c29ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538247302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1538247302
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3332724783
Short name T403
Test name
Test status
Simulation time 89899044 ps
CPU time 0.82 seconds
Started Jul 03 06:02:27 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 207568 kb
Host smart-434fa010-82b0-4c62-b583-382ae0fe0177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332724783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3332724783
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2355311879
Short name T912
Test name
Test status
Simulation time 138876212235 ps
CPU time 126.3 seconds
Started Jul 03 06:02:39 PM PDT 24
Finished Jul 03 06:04:46 PM PDT 24
Peak memory 257528 kb
Host smart-c4691dcc-a5ab-4547-a26b-e23daa6dc5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355311879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2355311879
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2232643232
Short name T210
Test name
Test status
Simulation time 274778752209 ps
CPU time 596.81 seconds
Started Jul 03 06:02:33 PM PDT 24
Finished Jul 03 06:12:30 PM PDT 24
Peak memory 269216 kb
Host smart-ea0bbfab-4c2d-48a0-ad7d-cdbf3b733ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232643232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2232643232
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4031738664
Short name T641
Test name
Test status
Simulation time 19116150947 ps
CPU time 139.72 seconds
Started Jul 03 06:02:33 PM PDT 24
Finished Jul 03 06:04:53 PM PDT 24
Peak memory 250472 kb
Host smart-7253ebb2-02d4-497b-ab99-626fa1352112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031738664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4031738664
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2443870134
Short name T272
Test name
Test status
Simulation time 612861017 ps
CPU time 10.49 seconds
Started Jul 03 06:02:35 PM PDT 24
Finished Jul 03 06:02:45 PM PDT 24
Peak memory 234356 kb
Host smart-f50014a7-b851-4862-8a90-65a2199c116f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443870134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2443870134
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.27225803
Short name T568
Test name
Test status
Simulation time 3664082591 ps
CPU time 50.9 seconds
Started Jul 03 06:02:39 PM PDT 24
Finished Jul 03 06:03:30 PM PDT 24
Peak memory 242148 kb
Host smart-c3ca6742-c61d-4c62-bc58-e322f925f2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27225803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.27225803
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1534787843
Short name T985
Test name
Test status
Simulation time 893891241 ps
CPU time 5.6 seconds
Started Jul 03 06:02:30 PM PDT 24
Finished Jul 03 06:02:36 PM PDT 24
Peak memory 220676 kb
Host smart-7011cf1e-2a8e-42fb-b5d2-348af3822929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534787843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1534787843
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1291505605
Short name T239
Test name
Test status
Simulation time 14506124689 ps
CPU time 60.13 seconds
Started Jul 03 06:02:32 PM PDT 24
Finished Jul 03 06:03:32 PM PDT 24
Peak memory 233844 kb
Host smart-a34a7b23-2407-42a5-bf26-91f2400ce131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291505605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1291505605
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.123145806
Short name T354
Test name
Test status
Simulation time 571623562 ps
CPU time 8.56 seconds
Started Jul 03 06:02:31 PM PDT 24
Finished Jul 03 06:02:40 PM PDT 24
Peak memory 233748 kb
Host smart-6efb1d11-c610-4785-be64-4b694bcc2457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123145806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.123145806
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1190526679
Short name T462
Test name
Test status
Simulation time 5972613627 ps
CPU time 4.6 seconds
Started Jul 03 06:02:29 PM PDT 24
Finished Jul 03 06:02:34 PM PDT 24
Peak memory 233960 kb
Host smart-238fa193-3953-49b8-bf99-09623a719bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190526679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1190526679
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.349355676
Short name T801
Test name
Test status
Simulation time 327006809 ps
CPU time 6.8 seconds
Started Jul 03 06:02:37 PM PDT 24
Finished Jul 03 06:02:44 PM PDT 24
Peak memory 224100 kb
Host smart-453bad90-1989-4837-9aeb-edb38872836a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=349355676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.349355676
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.992524510
Short name T141
Test name
Test status
Simulation time 31820441399 ps
CPU time 292.55 seconds
Started Jul 03 06:02:33 PM PDT 24
Finished Jul 03 06:07:26 PM PDT 24
Peak memory 255148 kb
Host smart-0d4d122f-1d06-4255-ad79-a0822af0bf4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992524510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.992524510
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.560522826
Short name T512
Test name
Test status
Simulation time 4044424568 ps
CPU time 23.86 seconds
Started Jul 03 06:02:30 PM PDT 24
Finished Jul 03 06:02:55 PM PDT 24
Peak memory 217488 kb
Host smart-1ba8f8ba-f63c-4b25-90ea-6f1e3528f305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560522826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.560522826
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3188513907
Short name T735
Test name
Test status
Simulation time 2205321917 ps
CPU time 5.58 seconds
Started Jul 03 06:02:29 PM PDT 24
Finished Jul 03 06:02:35 PM PDT 24
Peak memory 217492 kb
Host smart-7780e673-82d7-4576-9bfe-0f1f18c369fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188513907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3188513907
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1981943269
Short name T459
Test name
Test status
Simulation time 49110371 ps
CPU time 1.19 seconds
Started Jul 03 06:02:32 PM PDT 24
Finished Jul 03 06:02:33 PM PDT 24
Peak memory 208992 kb
Host smart-80b60619-5e94-4185-8312-bb4fead82dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981943269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1981943269
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2062337022
Short name T312
Test name
Test status
Simulation time 137734860 ps
CPU time 0.84 seconds
Started Jul 03 06:02:30 PM PDT 24
Finished Jul 03 06:02:31 PM PDT 24
Peak memory 207308 kb
Host smart-1cd324c6-55a4-418b-9465-5788e73b4277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062337022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2062337022
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.4236729954
Short name T794
Test name
Test status
Simulation time 4992226337 ps
CPU time 13.63 seconds
Started Jul 03 06:02:34 PM PDT 24
Finished Jul 03 06:02:47 PM PDT 24
Peak memory 225708 kb
Host smart-2fa04d02-3920-4856-bced-8cf8f5633d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236729954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4236729954
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2203971236
Short name T535
Test name
Test status
Simulation time 12921186 ps
CPU time 0.7 seconds
Started Jul 03 06:02:39 PM PDT 24
Finished Jul 03 06:02:40 PM PDT 24
Peak memory 205772 kb
Host smart-05e622cb-1f0b-432a-94f1-8c6e1d9d7cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203971236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2203971236
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2087943465
Short name T894
Test name
Test status
Simulation time 4041638666 ps
CPU time 12.75 seconds
Started Jul 03 06:02:40 PM PDT 24
Finished Jul 03 06:02:53 PM PDT 24
Peak memory 225740 kb
Host smart-53e8ee8e-6fa8-42b9-87f0-c55173d6ad76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087943465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2087943465
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2326238805
Short name T409
Test name
Test status
Simulation time 17033446 ps
CPU time 0.77 seconds
Started Jul 03 06:02:36 PM PDT 24
Finished Jul 03 06:02:37 PM PDT 24
Peak memory 206512 kb
Host smart-9d43b99b-4786-4980-92a8-1748f8c0ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326238805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2326238805
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1427910762
Short name T520
Test name
Test status
Simulation time 6078061114 ps
CPU time 26.43 seconds
Started Jul 03 06:02:37 PM PDT 24
Finished Jul 03 06:03:04 PM PDT 24
Peak memory 225680 kb
Host smart-89c65e28-708b-4c76-9708-0095e64d0a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427910762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1427910762
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3657359
Short name T1012
Test name
Test status
Simulation time 326193959 ps
CPU time 3.66 seconds
Started Jul 03 06:02:36 PM PDT 24
Finished Jul 03 06:02:40 PM PDT 24
Peak memory 233780 kb
Host smart-c0b91f00-27a8-4f4e-afa9-77e8062d6c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3657359
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.246579877
Short name T706
Test name
Test status
Simulation time 27296899480 ps
CPU time 50.67 seconds
Started Jul 03 06:02:38 PM PDT 24
Finished Jul 03 06:03:29 PM PDT 24
Peak memory 250300 kb
Host smart-ee0a04cb-c0d9-4d08-ada9-1fdfe74980b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246579877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.246579877
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3789773918
Short name T466
Test name
Test status
Simulation time 997213884 ps
CPU time 5.72 seconds
Started Jul 03 06:02:38 PM PDT 24
Finished Jul 03 06:02:44 PM PDT 24
Peak memory 219888 kb
Host smart-aa382b2c-928b-4077-9326-25aa39dd3959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789773918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3789773918
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1720944568
Short name T536
Test name
Test status
Simulation time 21762088002 ps
CPU time 92.28 seconds
Started Jul 03 06:02:36 PM PDT 24
Finished Jul 03 06:04:09 PM PDT 24
Peak memory 233908 kb
Host smart-cd9c84e7-74fe-4d2f-8779-489c760406fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720944568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1720944568
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1303817983
Short name T710
Test name
Test status
Simulation time 6146822654 ps
CPU time 15.64 seconds
Started Jul 03 06:02:38 PM PDT 24
Finished Jul 03 06:02:54 PM PDT 24
Peak memory 225668 kb
Host smart-34bf5d47-ca08-4c83-bea9-64f1237f704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303817983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1303817983
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3544414293
Short name T467
Test name
Test status
Simulation time 15565032166 ps
CPU time 18.29 seconds
Started Jul 03 06:02:39 PM PDT 24
Finished Jul 03 06:02:57 PM PDT 24
Peak memory 241608 kb
Host smart-93dbfad0-6725-4d64-9057-bfd9c6aad555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544414293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3544414293
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2700942342
Short name T345
Test name
Test status
Simulation time 723675307 ps
CPU time 4.24 seconds
Started Jul 03 06:02:41 PM PDT 24
Finished Jul 03 06:02:45 PM PDT 24
Peak memory 220428 kb
Host smart-010d9e5c-7b89-4681-9ef6-1a85e10d8bf2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2700942342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2700942342
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2430404963
Short name T194
Test name
Test status
Simulation time 110221980080 ps
CPU time 433.81 seconds
Started Jul 03 06:02:38 PM PDT 24
Finished Jul 03 06:09:52 PM PDT 24
Peak memory 266772 kb
Host smart-e84e2237-4f34-4feb-8c92-f9586dc4064d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430404963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2430404963
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.227271327
Short name T524
Test name
Test status
Simulation time 17382532235 ps
CPU time 29.65 seconds
Started Jul 03 06:02:39 PM PDT 24
Finished Jul 03 06:03:09 PM PDT 24
Peak memory 219240 kb
Host smart-31e7dcef-d55e-4bef-8289-0e11d6beb1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227271327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.227271327
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3554783736
Short name T969
Test name
Test status
Simulation time 354777742 ps
CPU time 2.12 seconds
Started Jul 03 06:02:38 PM PDT 24
Finished Jul 03 06:02:40 PM PDT 24
Peak memory 217156 kb
Host smart-b40286a4-cbb3-472a-8550-8df1ba0b3587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554783736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3554783736
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2417900307
Short name T613
Test name
Test status
Simulation time 375841254 ps
CPU time 2.45 seconds
Started Jul 03 06:02:35 PM PDT 24
Finished Jul 03 06:02:37 PM PDT 24
Peak memory 217392 kb
Host smart-ca92c31f-893d-4ff5-b57e-9eb5bed1e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417900307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2417900307
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3567092307
Short name T835
Test name
Test status
Simulation time 441982259 ps
CPU time 0.85 seconds
Started Jul 03 06:02:38 PM PDT 24
Finished Jul 03 06:02:39 PM PDT 24
Peak memory 206924 kb
Host smart-d8acdac8-5563-4d89-97c2-494c71384f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567092307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3567092307
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4031675482
Short name T579
Test name
Test status
Simulation time 795842488 ps
CPU time 7.74 seconds
Started Jul 03 06:02:39 PM PDT 24
Finished Jul 03 06:02:47 PM PDT 24
Peak memory 225464 kb
Host smart-a802c7fb-836e-4f3a-89af-1564ab892bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031675482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4031675482
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.183964626
Short name T848
Test name
Test status
Simulation time 10278087 ps
CPU time 0.75 seconds
Started Jul 03 06:02:47 PM PDT 24
Finished Jul 03 06:02:48 PM PDT 24
Peak memory 206280 kb
Host smart-f6907b8c-856b-4567-80be-259b8af375dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183964626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.183964626
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1722385046
Short name T548
Test name
Test status
Simulation time 181110429 ps
CPU time 2.87 seconds
Started Jul 03 06:02:42 PM PDT 24
Finished Jul 03 06:02:45 PM PDT 24
Peak memory 233752 kb
Host smart-526d559a-d2bf-4117-9659-4603602eb868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722385046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1722385046
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2789519261
Short name T696
Test name
Test status
Simulation time 15477349 ps
CPU time 0.76 seconds
Started Jul 03 06:02:38 PM PDT 24
Finished Jul 03 06:02:39 PM PDT 24
Peak memory 206820 kb
Host smart-29801fcf-0c0e-47b4-8c03-78129b972765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789519261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2789519261
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1427771961
Short name T209
Test name
Test status
Simulation time 34428022704 ps
CPU time 249.97 seconds
Started Jul 03 06:02:47 PM PDT 24
Finished Jul 03 06:06:58 PM PDT 24
Peak memory 250284 kb
Host smart-8e34f4fe-bdf6-484b-9d86-3735a07f578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427771961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1427771961
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2713485919
Short name T993
Test name
Test status
Simulation time 25419696625 ps
CPU time 86.77 seconds
Started Jul 03 06:02:42 PM PDT 24
Finished Jul 03 06:04:09 PM PDT 24
Peak memory 254044 kb
Host smart-2f324305-6bc3-46c5-b06c-f8e6cf730405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713485919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2713485919
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.382219334
Short name T825
Test name
Test status
Simulation time 29718832756 ps
CPU time 122.85 seconds
Started Jul 03 06:02:43 PM PDT 24
Finished Jul 03 06:04:47 PM PDT 24
Peak memory 268576 kb
Host smart-7fa80ad1-ebd7-4ac9-8bff-0aea79e11e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382219334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.382219334
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2822492951
Short name T43
Test name
Test status
Simulation time 689462780 ps
CPU time 7.46 seconds
Started Jul 03 06:02:42 PM PDT 24
Finished Jul 03 06:02:50 PM PDT 24
Peak memory 250180 kb
Host smart-3c084ec9-6150-4ce5-a410-dc24c2b260bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822492951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2822492951
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2957702421
Short name T397
Test name
Test status
Simulation time 18200287 ps
CPU time 0.77 seconds
Started Jul 03 06:02:42 PM PDT 24
Finished Jul 03 06:02:43 PM PDT 24
Peak memory 216828 kb
Host smart-a150fece-430e-45e2-9415-5b0ab30955d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957702421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2957702421
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2927462506
Short name T724
Test name
Test status
Simulation time 1165078328 ps
CPU time 6.43 seconds
Started Jul 03 06:02:44 PM PDT 24
Finished Jul 03 06:02:51 PM PDT 24
Peak memory 233772 kb
Host smart-8a7eedf2-165d-4ccb-b17d-ead94de422d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927462506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2927462506
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1408542291
Short name T793
Test name
Test status
Simulation time 30598745641 ps
CPU time 66.15 seconds
Started Jul 03 06:02:40 PM PDT 24
Finished Jul 03 06:03:47 PM PDT 24
Peak memory 233900 kb
Host smart-8ed9d8db-4fef-4735-9416-5834652a8d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408542291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1408542291
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1853377657
Short name T324
Test name
Test status
Simulation time 14032078653 ps
CPU time 36.32 seconds
Started Jul 03 06:02:43 PM PDT 24
Finished Jul 03 06:03:19 PM PDT 24
Peak memory 233836 kb
Host smart-35dfbd0a-f313-454e-a003-a157b26e6065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853377657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1853377657
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3854342012
Short name T681
Test name
Test status
Simulation time 338479681 ps
CPU time 2.43 seconds
Started Jul 03 06:02:41 PM PDT 24
Finished Jul 03 06:02:44 PM PDT 24
Peak memory 233760 kb
Host smart-80719ef0-e358-4490-a0a4-242beb768df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854342012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3854342012
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4289267411
Short name T781
Test name
Test status
Simulation time 1201121808 ps
CPU time 6.42 seconds
Started Jul 03 06:02:43 PM PDT 24
Finished Jul 03 06:02:49 PM PDT 24
Peak memory 220312 kb
Host smart-37009590-e4c8-4c3b-a078-362b63ad47d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4289267411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4289267411
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3539036673
Short name T717
Test name
Test status
Simulation time 15955714070 ps
CPU time 115.27 seconds
Started Jul 03 06:02:43 PM PDT 24
Finished Jul 03 06:04:38 PM PDT 24
Peak memory 250300 kb
Host smart-c26d1043-85e3-471c-9aef-eb7765777ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539036673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3539036673
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2282642322
Short name T283
Test name
Test status
Simulation time 6249092240 ps
CPU time 16.33 seconds
Started Jul 03 06:02:37 PM PDT 24
Finished Jul 03 06:02:53 PM PDT 24
Peak memory 217468 kb
Host smart-db3860b5-35b4-4113-af47-d0b4e0112d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282642322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2282642322
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2603891096
Short name T870
Test name
Test status
Simulation time 1562582884 ps
CPU time 4.2 seconds
Started Jul 03 06:02:38 PM PDT 24
Finished Jul 03 06:02:43 PM PDT 24
Peak memory 217380 kb
Host smart-7cbca6b1-f7a5-4f8b-b38e-eb106b3632b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603891096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2603891096
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3912334245
Short name T57
Test name
Test status
Simulation time 181900270 ps
CPU time 2.56 seconds
Started Jul 03 06:02:36 PM PDT 24
Finished Jul 03 06:02:39 PM PDT 24
Peak memory 217416 kb
Host smart-eb9e44ca-7f83-4ba2-9fee-7772292a4bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912334245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3912334245
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2260145024
Short name T658
Test name
Test status
Simulation time 13576212 ps
CPU time 0.71 seconds
Started Jul 03 06:02:37 PM PDT 24
Finished Jul 03 06:02:38 PM PDT 24
Peak memory 206608 kb
Host smart-648bf4dd-4627-4db9-8335-e755057addbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260145024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2260145024
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1747782880
Short name T196
Test name
Test status
Simulation time 29669234275 ps
CPU time 22.37 seconds
Started Jul 03 06:02:41 PM PDT 24
Finished Jul 03 06:03:04 PM PDT 24
Peak memory 233948 kb
Host smart-4dcb0ebb-e899-4dab-9c77-847f4790af29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747782880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1747782880
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1796718185
Short name T470
Test name
Test status
Simulation time 24962774 ps
CPU time 0.72 seconds
Started Jul 03 06:02:45 PM PDT 24
Finished Jul 03 06:02:46 PM PDT 24
Peak memory 206364 kb
Host smart-233f4831-7a00-4484-94b4-b864286c86b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796718185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1796718185
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4132858874
Short name T319
Test name
Test status
Simulation time 11048161283 ps
CPU time 26.21 seconds
Started Jul 03 06:02:45 PM PDT 24
Finished Jul 03 06:03:12 PM PDT 24
Peak memory 225716 kb
Host smart-3aecefe3-3360-45c0-8a0f-68487c494bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132858874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4132858874
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.685332390
Short name T292
Test name
Test status
Simulation time 53017581 ps
CPU time 0.75 seconds
Started Jul 03 06:02:40 PM PDT 24
Finished Jul 03 06:02:41 PM PDT 24
Peak memory 207448 kb
Host smart-dd37f1c3-537a-428f-9f86-adba0fb54bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685332390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.685332390
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2213637021
Short name T726
Test name
Test status
Simulation time 46987021088 ps
CPU time 32.84 seconds
Started Jul 03 06:02:48 PM PDT 24
Finished Jul 03 06:03:21 PM PDT 24
Peak memory 220844 kb
Host smart-bbc389fa-349f-46a9-a7ce-1c9de3454c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213637021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2213637021
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2089704393
Short name T789
Test name
Test status
Simulation time 2178051588 ps
CPU time 51.74 seconds
Started Jul 03 06:02:46 PM PDT 24
Finished Jul 03 06:03:38 PM PDT 24
Peak memory 258592 kb
Host smart-32f04d81-ddb9-4df2-8922-1a5e15beddd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089704393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2089704393
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3274353731
Short name T757
Test name
Test status
Simulation time 13589848148 ps
CPU time 60.73 seconds
Started Jul 03 06:02:45 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 225672 kb
Host smart-940e3592-ac94-4b99-ab6b-080275e879b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274353731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3274353731
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.453833424
Short name T516
Test name
Test status
Simulation time 5720594293 ps
CPU time 69.26 seconds
Started Jul 03 06:02:45 PM PDT 24
Finished Jul 03 06:03:55 PM PDT 24
Peak memory 258416 kb
Host smart-6a0922ae-ab51-4f46-ae66-89370d2f6730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453833424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.453833424
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3308120118
Short name T567
Test name
Test status
Simulation time 884387570 ps
CPU time 4.3 seconds
Started Jul 03 06:02:43 PM PDT 24
Finished Jul 03 06:02:47 PM PDT 24
Peak memory 233752 kb
Host smart-ae0c10af-6d51-4e80-bae4-56f9606ffeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308120118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3308120118
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.50021267
Short name T242
Test name
Test status
Simulation time 4089685505 ps
CPU time 16.81 seconds
Started Jul 03 06:02:41 PM PDT 24
Finished Jul 03 06:02:58 PM PDT 24
Peak memory 233912 kb
Host smart-e5adbf36-7ba3-42df-b240-b65936197768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50021267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.50021267
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.245609896
Short name T265
Test name
Test status
Simulation time 5287085478 ps
CPU time 16.28 seconds
Started Jul 03 06:02:43 PM PDT 24
Finished Jul 03 06:03:00 PM PDT 24
Peak memory 242008 kb
Host smart-29dac776-a37f-42cb-941c-054b2b7b6976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245609896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.245609896
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.249655544
Short name T423
Test name
Test status
Simulation time 74459308 ps
CPU time 2.19 seconds
Started Jul 03 06:02:41 PM PDT 24
Finished Jul 03 06:02:43 PM PDT 24
Peak memory 225140 kb
Host smart-a9d82266-c586-4bfa-becb-d5ba63f8be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249655544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.249655544
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3304887870
Short name T586
Test name
Test status
Simulation time 1067113605 ps
CPU time 7.94 seconds
Started Jul 03 06:02:45 PM PDT 24
Finished Jul 03 06:02:54 PM PDT 24
Peak memory 221432 kb
Host smart-a97b8e30-7a3d-4ca4-9ac6-825de8a98586
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3304887870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3304887870
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3073121818
Short name T907
Test name
Test status
Simulation time 68247563673 ps
CPU time 208.21 seconds
Started Jul 03 06:02:44 PM PDT 24
Finished Jul 03 06:06:12 PM PDT 24
Peak memory 265732 kb
Host smart-5fd4bc1b-9ea4-4c50-82e2-32fd7de82464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073121818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3073121818
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.64398326
Short name T750
Test name
Test status
Simulation time 2749433563 ps
CPU time 19.08 seconds
Started Jul 03 06:02:44 PM PDT 24
Finished Jul 03 06:03:04 PM PDT 24
Peak memory 217800 kb
Host smart-fceb5d85-fcb4-4a6b-9b99-97ed6c0edc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64398326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.64398326
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4198754393
Short name T611
Test name
Test status
Simulation time 21347558865 ps
CPU time 17.05 seconds
Started Jul 03 06:02:42 PM PDT 24
Finished Jul 03 06:02:59 PM PDT 24
Peak memory 217516 kb
Host smart-f9883055-eb5f-40e3-84ac-0689179f155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198754393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4198754393
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4203816271
Short name T949
Test name
Test status
Simulation time 236966599 ps
CPU time 3.59 seconds
Started Jul 03 06:02:44 PM PDT 24
Finished Jul 03 06:02:48 PM PDT 24
Peak memory 217376 kb
Host smart-d5552208-ca78-4b51-9b62-223287e38fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203816271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4203816271
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2944497500
Short name T475
Test name
Test status
Simulation time 90302890 ps
CPU time 0.88 seconds
Started Jul 03 06:02:47 PM PDT 24
Finished Jul 03 06:02:48 PM PDT 24
Peak memory 206964 kb
Host smart-ff81e3da-5708-4b9c-b0d0-3f2d82442040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944497500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2944497500
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3650102008
Short name T510
Test name
Test status
Simulation time 705460927 ps
CPU time 8.41 seconds
Started Jul 03 06:02:46 PM PDT 24
Finished Jul 03 06:02:55 PM PDT 24
Peak memory 233656 kb
Host smart-c531fb51-424e-431c-8823-825444e4def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650102008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3650102008
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.34820659
Short name T820
Test name
Test status
Simulation time 29854773 ps
CPU time 0.74 seconds
Started Jul 03 06:02:53 PM PDT 24
Finished Jul 03 06:02:55 PM PDT 24
Peak memory 206352 kb
Host smart-066d4c20-ba11-4f34-8c5f-3c11e323e0b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34820659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.34820659
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2746061064
Short name T704
Test name
Test status
Simulation time 2564185561 ps
CPU time 4.75 seconds
Started Jul 03 06:02:53 PM PDT 24
Finished Jul 03 06:02:58 PM PDT 24
Peak memory 225724 kb
Host smart-85a9a519-81e3-4152-9422-1afb21e4bf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746061064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2746061064
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4091773833
Short name T797
Test name
Test status
Simulation time 19928076 ps
CPU time 0.76 seconds
Started Jul 03 06:02:45 PM PDT 24
Finished Jul 03 06:02:46 PM PDT 24
Peak memory 207848 kb
Host smart-fcdcbff8-5f78-4bec-bade-2c3dd5c77358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091773833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4091773833
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4075273176
Short name T966
Test name
Test status
Simulation time 1737812808 ps
CPU time 16.47 seconds
Started Jul 03 06:02:52 PM PDT 24
Finished Jul 03 06:03:08 PM PDT 24
Peak memory 236384 kb
Host smart-ee7467ef-91c3-4b2f-ae3d-c504727b6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075273176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4075273176
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2424142974
Short name T134
Test name
Test status
Simulation time 8907910274 ps
CPU time 70.56 seconds
Started Jul 03 06:02:49 PM PDT 24
Finished Jul 03 06:03:59 PM PDT 24
Peak memory 254972 kb
Host smart-8a9592dd-9b56-430f-8acf-b3c938732e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424142974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2424142974
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1346272699
Short name T874
Test name
Test status
Simulation time 29258507864 ps
CPU time 171.65 seconds
Started Jul 03 06:02:46 PM PDT 24
Finished Jul 03 06:05:38 PM PDT 24
Peak memory 268032 kb
Host smart-bb8ef4b0-45fc-4581-baca-4c302be6533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346272699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1346272699
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2953350244
Short name T644
Test name
Test status
Simulation time 15187606361 ps
CPU time 22.52 seconds
Started Jul 03 06:02:53 PM PDT 24
Finished Jul 03 06:03:16 PM PDT 24
Peak memory 233932 kb
Host smart-53378f08-ee71-4b0a-bd73-368cac73be53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953350244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2953350244
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4100234934
Short name T247
Test name
Test status
Simulation time 866914307 ps
CPU time 9.82 seconds
Started Jul 03 06:02:49 PM PDT 24
Finished Jul 03 06:02:59 PM PDT 24
Peak memory 225508 kb
Host smart-d6c201cc-1892-468f-be0e-5cff964f24a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100234934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4100234934
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3128527902
Short name T562
Test name
Test status
Simulation time 2676186909 ps
CPU time 10.3 seconds
Started Jul 03 06:02:51 PM PDT 24
Finished Jul 03 06:03:01 PM PDT 24
Peak memory 233944 kb
Host smart-05fc6d07-cfe4-45c5-8813-59233a9b1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128527902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3128527902
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4163605754
Short name T945
Test name
Test status
Simulation time 607512923 ps
CPU time 7.56 seconds
Started Jul 03 06:02:52 PM PDT 24
Finished Jul 03 06:03:00 PM PDT 24
Peak memory 233832 kb
Host smart-df9c938b-aa21-4c54-b0eb-12a8778ba539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163605754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4163605754
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2555742380
Short name T224
Test name
Test status
Simulation time 490227614 ps
CPU time 5.37 seconds
Started Jul 03 06:02:51 PM PDT 24
Finished Jul 03 06:02:57 PM PDT 24
Peak memory 233808 kb
Host smart-60f916c5-d90d-4915-9a3f-98849516a1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555742380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2555742380
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2306599176
Short name T318
Test name
Test status
Simulation time 637868686 ps
CPU time 8.87 seconds
Started Jul 03 06:02:52 PM PDT 24
Finished Jul 03 06:03:01 PM PDT 24
Peak memory 223056 kb
Host smart-9312ba53-36cd-40a9-8e1f-4b93b70ab472
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2306599176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2306599176
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1668069334
Short name T770
Test name
Test status
Simulation time 41716441300 ps
CPU time 364.91 seconds
Started Jul 03 06:02:48 PM PDT 24
Finished Jul 03 06:08:54 PM PDT 24
Peak memory 266760 kb
Host smart-4697deb6-3035-484c-a752-da82dcf9d781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668069334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1668069334
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1325075411
Short name T834
Test name
Test status
Simulation time 1810880598 ps
CPU time 19.17 seconds
Started Jul 03 06:02:45 PM PDT 24
Finished Jul 03 06:03:04 PM PDT 24
Peak memory 217376 kb
Host smart-9f90418b-82c7-4ec4-b74f-d0f5c58ee3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325075411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1325075411
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3862799139
Short name T507
Test name
Test status
Simulation time 637612567 ps
CPU time 4.13 seconds
Started Jul 03 06:02:44 PM PDT 24
Finished Jul 03 06:02:48 PM PDT 24
Peak memory 217372 kb
Host smart-cf861f9f-a67f-424c-9950-20a55cd9f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862799139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3862799139
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2930889216
Short name T628
Test name
Test status
Simulation time 730868152 ps
CPU time 4.31 seconds
Started Jul 03 06:02:49 PM PDT 24
Finished Jul 03 06:02:53 PM PDT 24
Peak memory 217364 kb
Host smart-0e3e21ee-4284-4729-9b26-e78b1fbc8a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930889216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2930889216
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1496733495
Short name T713
Test name
Test status
Simulation time 110072465 ps
CPU time 0.83 seconds
Started Jul 03 06:02:47 PM PDT 24
Finished Jul 03 06:02:48 PM PDT 24
Peak memory 207044 kb
Host smart-4c74f814-7fb1-4484-9449-54568a17a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496733495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1496733495
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3100566480
Short name T589
Test name
Test status
Simulation time 861160954 ps
CPU time 7.22 seconds
Started Jul 03 06:02:53 PM PDT 24
Finished Jul 03 06:03:01 PM PDT 24
Peak memory 233748 kb
Host smart-d986ef38-efe4-4051-a51a-24390e709749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100566480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3100566480
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2445740371
Short name T624
Test name
Test status
Simulation time 14622067 ps
CPU time 0.69 seconds
Started Jul 03 06:02:59 PM PDT 24
Finished Jul 03 06:03:00 PM PDT 24
Peak memory 206780 kb
Host smart-d1199f87-bc98-44f3-b663-d83c60986679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445740371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2445740371
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3627955420
Short name T1
Test name
Test status
Simulation time 161107468 ps
CPU time 2.76 seconds
Started Jul 03 06:02:54 PM PDT 24
Finished Jul 03 06:02:57 PM PDT 24
Peak memory 233848 kb
Host smart-488f0e05-7c81-4fa3-8344-1cd4a28ba3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627955420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3627955420
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3691792793
Short name T705
Test name
Test status
Simulation time 18811677 ps
CPU time 0.77 seconds
Started Jul 03 06:02:49 PM PDT 24
Finished Jul 03 06:02:50 PM PDT 24
Peak memory 206476 kb
Host smart-da31313c-1f23-4872-a84b-84a6768a1a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691792793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3691792793
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1912335863
Short name T572
Test name
Test status
Simulation time 2728201702 ps
CPU time 35.54 seconds
Started Jul 03 06:02:58 PM PDT 24
Finished Jul 03 06:03:34 PM PDT 24
Peak memory 250316 kb
Host smart-754e3f42-13ab-44b4-abb1-4b2145e17c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912335863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1912335863
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.553683758
Short name T663
Test name
Test status
Simulation time 20689124221 ps
CPU time 28.17 seconds
Started Jul 03 06:02:56 PM PDT 24
Finished Jul 03 06:03:25 PM PDT 24
Peak memory 218896 kb
Host smart-ccdb9ea7-2663-4c03-8147-226aa29f473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553683758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.553683758
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.232878004
Short name T245
Test name
Test status
Simulation time 77944378212 ps
CPU time 270.51 seconds
Started Jul 03 06:02:58 PM PDT 24
Finished Jul 03 06:07:29 PM PDT 24
Peak memory 257536 kb
Host smart-88cc94b2-2893-493e-9e7a-bb363fa8bb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232878004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.232878004
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2293071221
Short name T1027
Test name
Test status
Simulation time 926316589 ps
CPU time 14.4 seconds
Started Jul 03 06:03:00 PM PDT 24
Finished Jul 03 06:03:15 PM PDT 24
Peak memory 225596 kb
Host smart-35474728-374f-432f-8966-921e533e064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293071221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2293071221
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1994875120
Short name T177
Test name
Test status
Simulation time 20573921007 ps
CPU time 162.35 seconds
Started Jul 03 06:02:58 PM PDT 24
Finished Jul 03 06:05:41 PM PDT 24
Peak memory 251380 kb
Host smart-24a6e271-0129-4b6d-9329-4ca1655e474b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994875120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1994875120
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1156291825
Short name T881
Test name
Test status
Simulation time 85799303 ps
CPU time 2.38 seconds
Started Jul 03 06:02:53 PM PDT 24
Finished Jul 03 06:02:56 PM PDT 24
Peak memory 225496 kb
Host smart-1e147f29-68a3-4d9b-a7f3-17e6b13d4474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156291825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1156291825
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1217516918
Short name T549
Test name
Test status
Simulation time 3016953797 ps
CPU time 7.04 seconds
Started Jul 03 06:02:54 PM PDT 24
Finished Jul 03 06:03:02 PM PDT 24
Peak memory 233904 kb
Host smart-0ae70db7-07a0-473a-931f-f4ecf54443df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217516918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1217516918
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3685900597
Short name T411
Test name
Test status
Simulation time 46042976 ps
CPU time 2.37 seconds
Started Jul 03 06:02:54 PM PDT 24
Finished Jul 03 06:02:57 PM PDT 24
Peak memory 233848 kb
Host smart-bae24f0b-3804-4cb5-b37c-c6d1f16e15d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685900597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3685900597
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.233646216
Short name T416
Test name
Test status
Simulation time 11492535061 ps
CPU time 7.06 seconds
Started Jul 03 06:02:52 PM PDT 24
Finished Jul 03 06:02:59 PM PDT 24
Peak memory 233812 kb
Host smart-9d3232d5-6871-48e7-bf10-a95dd3768110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233646216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.233646216
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.640264345
Short name T962
Test name
Test status
Simulation time 6248755376 ps
CPU time 12.78 seconds
Started Jul 03 06:02:57 PM PDT 24
Finished Jul 03 06:03:10 PM PDT 24
Peak memory 221096 kb
Host smart-761d1104-3ce7-439b-8615-ead8dce0557d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=640264345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.640264345
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2945066737
Short name T538
Test name
Test status
Simulation time 171628845583 ps
CPU time 459.57 seconds
Started Jul 03 06:02:58 PM PDT 24
Finished Jul 03 06:10:38 PM PDT 24
Peak memory 264832 kb
Host smart-8e61cdaa-ce40-4913-b3a9-dde0bc3dd626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945066737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2945066737
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3608022829
Short name T665
Test name
Test status
Simulation time 3100409389 ps
CPU time 15.8 seconds
Started Jul 03 06:02:49 PM PDT 24
Finished Jul 03 06:03:05 PM PDT 24
Peak memory 217796 kb
Host smart-f7aa0150-fc0b-4d0e-8fb9-807a5992a749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608022829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3608022829
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1167238347
Short name T491
Test name
Test status
Simulation time 9704544409 ps
CPU time 13.37 seconds
Started Jul 03 06:02:52 PM PDT 24
Finished Jul 03 06:03:06 PM PDT 24
Peak memory 217512 kb
Host smart-60b5b54f-d270-430d-82dc-d3c796814ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167238347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1167238347
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.942198057
Short name T675
Test name
Test status
Simulation time 349649682 ps
CPU time 1.32 seconds
Started Jul 03 06:02:55 PM PDT 24
Finished Jul 03 06:02:57 PM PDT 24
Peak memory 209092 kb
Host smart-e9b619b3-b2f5-480a-b4d5-00a657806d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942198057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.942198057
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.540758742
Short name T715
Test name
Test status
Simulation time 67356279 ps
CPU time 0.85 seconds
Started Jul 03 06:02:54 PM PDT 24
Finished Jul 03 06:02:56 PM PDT 24
Peak memory 206952 kb
Host smart-c29a75f5-1619-44f6-9fae-b2835e2daca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540758742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.540758742
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2522717768
Short name T444
Test name
Test status
Simulation time 679652130 ps
CPU time 2.45 seconds
Started Jul 03 06:02:52 PM PDT 24
Finished Jul 03 06:02:54 PM PDT 24
Peak memory 224204 kb
Host smart-ae58f4af-3613-414c-8338-a1bde3f8ec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522717768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2522717768
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3573143320
Short name T910
Test name
Test status
Simulation time 38436671 ps
CPU time 0.74 seconds
Started Jul 03 06:03:06 PM PDT 24
Finished Jul 03 06:03:07 PM PDT 24
Peak memory 205856 kb
Host smart-f3fc9bc2-c953-4b66-a3eb-16c2963a58f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573143320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3573143320
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.824226811
Short name T964
Test name
Test status
Simulation time 136310580 ps
CPU time 2.89 seconds
Started Jul 03 06:03:02 PM PDT 24
Finished Jul 03 06:03:05 PM PDT 24
Peak memory 225548 kb
Host smart-4129f7c8-f76a-4b9a-8118-adc342096c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824226811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.824226811
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.382050051
Short name T826
Test name
Test status
Simulation time 13411182 ps
CPU time 0.71 seconds
Started Jul 03 06:02:57 PM PDT 24
Finished Jul 03 06:02:58 PM PDT 24
Peak memory 207496 kb
Host smart-13e05ed3-7ceb-4068-9cfb-212269ae6ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382050051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.382050051
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4282283337
Short name T823
Test name
Test status
Simulation time 7459692124 ps
CPU time 130.41 seconds
Started Jul 03 06:03:04 PM PDT 24
Finished Jul 03 06:05:14 PM PDT 24
Peak memory 266640 kb
Host smart-654c6b8a-7dcc-4134-9531-2a5430dcadb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282283337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4282283337
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3079455815
Short name T381
Test name
Test status
Simulation time 22911997595 ps
CPU time 30.93 seconds
Started Jul 03 06:02:58 PM PDT 24
Finished Jul 03 06:03:29 PM PDT 24
Peak memory 237300 kb
Host smart-9bcfd240-82bf-4766-810e-76fd7e2973c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079455815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3079455815
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.389231536
Short name T214
Test name
Test status
Simulation time 54900070043 ps
CPU time 228.81 seconds
Started Jul 03 06:03:07 PM PDT 24
Finished Jul 03 06:06:56 PM PDT 24
Peak memory 250412 kb
Host smart-e111bde3-802f-42ee-bdd7-fe24ce0d6bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389231536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.389231536
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.376485436
Short name T864
Test name
Test status
Simulation time 168953542 ps
CPU time 3.63 seconds
Started Jul 03 06:03:02 PM PDT 24
Finished Jul 03 06:03:06 PM PDT 24
Peak memory 233800 kb
Host smart-337d9d7a-c78e-4781-af2a-b51f6abd7ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376485436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.376485436
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.4185636602
Short name T8
Test name
Test status
Simulation time 3948786709 ps
CPU time 21.93 seconds
Started Jul 03 06:03:04 PM PDT 24
Finished Jul 03 06:03:26 PM PDT 24
Peak memory 242148 kb
Host smart-7108640a-f754-478b-bdc3-cc4938435ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185636602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.4185636602
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3144058892
Short name T541
Test name
Test status
Simulation time 1246459192 ps
CPU time 6.11 seconds
Started Jul 03 06:03:06 PM PDT 24
Finished Jul 03 06:03:13 PM PDT 24
Peak memory 229296 kb
Host smart-52242407-aa90-4ab5-a7d3-4b1501a317b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144058892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3144058892
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1389280349
Short name T486
Test name
Test status
Simulation time 2179392735 ps
CPU time 8.13 seconds
Started Jul 03 06:03:02 PM PDT 24
Finished Jul 03 06:03:11 PM PDT 24
Peak memory 233984 kb
Host smart-e28fc858-18c9-44d6-b940-addb5f4375da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389280349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1389280349
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.341129790
Short name T625
Test name
Test status
Simulation time 491649280 ps
CPU time 3.95 seconds
Started Jul 03 06:03:00 PM PDT 24
Finished Jul 03 06:03:04 PM PDT 24
Peak memory 225548 kb
Host smart-cb39b40e-f8ed-4d30-882c-b34cfd4a467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341129790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.341129790
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2926546928
Short name T674
Test name
Test status
Simulation time 870607869 ps
CPU time 7.71 seconds
Started Jul 03 06:03:00 PM PDT 24
Finished Jul 03 06:03:08 PM PDT 24
Peak memory 225660 kb
Host smart-76c9b1ac-1a68-46b6-b7c5-1999a8dc8b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926546928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2926546928
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1855693944
Short name T771
Test name
Test status
Simulation time 1084957471 ps
CPU time 12.19 seconds
Started Jul 03 06:03:07 PM PDT 24
Finished Jul 03 06:03:20 PM PDT 24
Peak memory 223296 kb
Host smart-31f3d7ec-e577-4b94-bc34-82ecee2d61c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1855693944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1855693944
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3637321493
Short name T754
Test name
Test status
Simulation time 34723741 ps
CPU time 0.98 seconds
Started Jul 03 06:03:02 PM PDT 24
Finished Jul 03 06:03:04 PM PDT 24
Peak memory 208784 kb
Host smart-b91d0745-3511-4029-badc-2ba9e742b452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637321493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3637321493
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4076755638
Short name T1033
Test name
Test status
Simulation time 2841918747 ps
CPU time 12.97 seconds
Started Jul 03 06:02:56 PM PDT 24
Finished Jul 03 06:03:09 PM PDT 24
Peak memory 217564 kb
Host smart-57f8a8a1-8c6b-4a19-a8cc-0c90e2235b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076755638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4076755638
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1607720044
Short name T946
Test name
Test status
Simulation time 4191167670 ps
CPU time 12.68 seconds
Started Jul 03 06:02:55 PM PDT 24
Finished Jul 03 06:03:08 PM PDT 24
Peak memory 217524 kb
Host smart-94754f90-6113-469f-ae9c-9272ad8a76b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607720044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1607720044
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2648700413
Short name T716
Test name
Test status
Simulation time 169347292 ps
CPU time 4.48 seconds
Started Jul 03 06:03:01 PM PDT 24
Finished Jul 03 06:03:06 PM PDT 24
Peak memory 217308 kb
Host smart-202b5735-73f8-4207-a282-ddd13f4cea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648700413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2648700413
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2647365494
Short name T790
Test name
Test status
Simulation time 143181126 ps
CPU time 1.07 seconds
Started Jul 03 06:02:55 PM PDT 24
Finished Jul 03 06:02:56 PM PDT 24
Peak memory 207500 kb
Host smart-bfdeded2-f29e-454a-a5c2-823a4e9cd4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647365494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2647365494
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1777007375
Short name T595
Test name
Test status
Simulation time 3785663373 ps
CPU time 7.95 seconds
Started Jul 03 06:03:01 PM PDT 24
Finished Jul 03 06:03:09 PM PDT 24
Peak memory 242000 kb
Host smart-8dd1fd31-2279-4ef1-825f-32cf92f1b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777007375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1777007375
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2047555447
Short name T509
Test name
Test status
Simulation time 15088039 ps
CPU time 0.72 seconds
Started Jul 03 06:01:05 PM PDT 24
Finished Jul 03 06:01:06 PM PDT 24
Peak memory 205816 kb
Host smart-dd32fcc2-8ff0-49b4-b183-3eaf67148c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047555447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
047555447
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3204838424
Short name T994
Test name
Test status
Simulation time 2895507051 ps
CPU time 4.57 seconds
Started Jul 03 06:01:03 PM PDT 24
Finished Jul 03 06:01:08 PM PDT 24
Peak memory 233908 kb
Host smart-0c33599b-fdf3-4a3f-9832-154f1eeedd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204838424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3204838424
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2700727027
Short name T976
Test name
Test status
Simulation time 20967995 ps
CPU time 0.77 seconds
Started Jul 03 06:01:00 PM PDT 24
Finished Jul 03 06:01:01 PM PDT 24
Peak memory 206452 kb
Host smart-586deab4-0b0e-4970-ab5a-ec01708e6175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700727027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2700727027
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3618143506
Short name T473
Test name
Test status
Simulation time 27932458045 ps
CPU time 59.65 seconds
Started Jul 03 06:01:06 PM PDT 24
Finished Jul 03 06:02:06 PM PDT 24
Peak memory 242200 kb
Host smart-24b19afa-c3b7-4f4a-8b95-87f80d1b4807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618143506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3618143506
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.600158958
Short name T238
Test name
Test status
Simulation time 26034107289 ps
CPU time 156 seconds
Started Jul 03 06:01:04 PM PDT 24
Finished Jul 03 06:03:41 PM PDT 24
Peak memory 267476 kb
Host smart-e56add25-5560-4202-88b2-497a187ffdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600158958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
600158958
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2143868341
Short name T271
Test name
Test status
Simulation time 51623462 ps
CPU time 3.78 seconds
Started Jul 03 06:01:01 PM PDT 24
Finished Jul 03 06:01:06 PM PDT 24
Peak memory 233752 kb
Host smart-14ebbe4b-566e-4500-ad58-6349b3360ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143868341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2143868341
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1428121240
Short name T917
Test name
Test status
Simulation time 17370924704 ps
CPU time 119.11 seconds
Started Jul 03 06:01:01 PM PDT 24
Finished Jul 03 06:03:01 PM PDT 24
Peak memory 263244 kb
Host smart-2330400b-7964-4f6b-ae50-4be9351fc2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428121240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1428121240
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2113589335
Short name T6
Test name
Test status
Simulation time 2902401797 ps
CPU time 16.99 seconds
Started Jul 03 06:01:03 PM PDT 24
Finished Jul 03 06:01:20 PM PDT 24
Peak memory 233952 kb
Host smart-37986ba0-0b6c-4d73-b966-742dadc845ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113589335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2113589335
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1739686389
Short name T916
Test name
Test status
Simulation time 3591962984 ps
CPU time 11.3 seconds
Started Jul 03 06:01:02 PM PDT 24
Finished Jul 03 06:01:13 PM PDT 24
Peak memory 242060 kb
Host smart-a6b36e36-41e0-4bc6-b07e-61ec3d4a5cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739686389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1739686389
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.623998611
Short name T35
Test name
Test status
Simulation time 34723817 ps
CPU time 1.06 seconds
Started Jul 03 06:01:03 PM PDT 24
Finished Jul 03 06:01:05 PM PDT 24
Peak memory 217692 kb
Host smart-19f5ef89-192e-454d-835d-f73e8fe98f33
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623998611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.623998611
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3855540515
Short name T546
Test name
Test status
Simulation time 3105183645 ps
CPU time 4.8 seconds
Started Jul 03 06:01:02 PM PDT 24
Finished Jul 03 06:01:07 PM PDT 24
Peak memory 225724 kb
Host smart-d84d9364-1151-475c-9fa0-5f2821f06a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855540515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3855540515
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1560156365
Short name T203
Test name
Test status
Simulation time 4748019380 ps
CPU time 10.84 seconds
Started Jul 03 06:00:57 PM PDT 24
Finished Jul 03 06:01:08 PM PDT 24
Peak memory 241704 kb
Host smart-0fd1f022-f813-4ec6-bd1c-2ff0eea37c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560156365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1560156365
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4004014639
Short name T338
Test name
Test status
Simulation time 4085268939 ps
CPU time 10.88 seconds
Started Jul 03 06:01:03 PM PDT 24
Finished Jul 03 06:01:14 PM PDT 24
Peak memory 223764 kb
Host smart-a0a76d52-405e-4289-a93b-ede90ac8e911
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4004014639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4004014639
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1057849959
Short name T72
Test name
Test status
Simulation time 45732477 ps
CPU time 0.97 seconds
Started Jul 03 06:01:03 PM PDT 24
Finished Jul 03 06:01:04 PM PDT 24
Peak memory 236412 kb
Host smart-5b97ab89-66a9-4648-954e-9c5b2db9f7cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057849959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1057849959
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.320314156
Short name T843
Test name
Test status
Simulation time 43120167330 ps
CPU time 194.9 seconds
Started Jul 03 06:01:04 PM PDT 24
Finished Jul 03 06:04:19 PM PDT 24
Peak memory 258608 kb
Host smart-9a2fbc64-5c98-49af-9896-09afb76e39c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320314156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.320314156
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3472873417
Short name T451
Test name
Test status
Simulation time 13025738 ps
CPU time 0.74 seconds
Started Jul 03 06:01:02 PM PDT 24
Finished Jul 03 06:01:03 PM PDT 24
Peak memory 206672 kb
Host smart-a2d9733c-84a3-4787-8b0d-165a71892bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472873417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3472873417
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.379612427
Short name T576
Test name
Test status
Simulation time 3117647020 ps
CPU time 5.55 seconds
Started Jul 03 06:01:00 PM PDT 24
Finished Jul 03 06:01:06 PM PDT 24
Peak memory 217552 kb
Host smart-a5c6c72b-b65c-4200-a770-912fd7ad4981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379612427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.379612427
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3337586917
Short name T914
Test name
Test status
Simulation time 12881882 ps
CPU time 0.68 seconds
Started Jul 03 06:00:59 PM PDT 24
Finished Jul 03 06:01:00 PM PDT 24
Peak memory 206584 kb
Host smart-c7a145bb-b1bf-498c-916c-2920f8dd9c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337586917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3337586917
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2926828920
Short name T465
Test name
Test status
Simulation time 24567764 ps
CPU time 0.85 seconds
Started Jul 03 06:00:58 PM PDT 24
Finished Jul 03 06:00:59 PM PDT 24
Peak memory 206992 kb
Host smart-c66faffc-7a77-4fcd-9d5c-f378fc3664e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926828920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2926828920
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.344321803
Short name T192
Test name
Test status
Simulation time 28111962717 ps
CPU time 16.78 seconds
Started Jul 03 06:01:06 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 234916 kb
Host smart-3f6d0a2f-c7d6-45e7-a127-94383e83531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344321803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.344321803
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3210684470
Short name T80
Test name
Test status
Simulation time 19328816 ps
CPU time 0.78 seconds
Started Jul 03 06:03:08 PM PDT 24
Finished Jul 03 06:03:10 PM PDT 24
Peak memory 205816 kb
Host smart-b0abef8d-877f-4028-b2a3-c705578ef29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210684470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3210684470
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2143739227
Short name T779
Test name
Test status
Simulation time 802321375 ps
CPU time 3.11 seconds
Started Jul 03 06:03:04 PM PDT 24
Finished Jul 03 06:03:08 PM PDT 24
Peak memory 225504 kb
Host smart-1f1151b0-70bd-4cee-a6fe-942bc9ee907c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143739227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2143739227
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2759577601
Short name T1000
Test name
Test status
Simulation time 46220773 ps
CPU time 0.81 seconds
Started Jul 03 06:03:03 PM PDT 24
Finished Jul 03 06:03:04 PM PDT 24
Peak memory 207848 kb
Host smart-d0c8a94b-c946-42df-ac7f-71d7c5254372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759577601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2759577601
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4146633051
Short name T712
Test name
Test status
Simulation time 10418560058 ps
CPU time 40.39 seconds
Started Jul 03 06:03:08 PM PDT 24
Finished Jul 03 06:03:49 PM PDT 24
Peak memory 251332 kb
Host smart-0dab1d14-62ef-404c-ab02-74967fb7e8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146633051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4146633051
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1925855384
Short name T604
Test name
Test status
Simulation time 14247506617 ps
CPU time 84.25 seconds
Started Jul 03 06:03:04 PM PDT 24
Finished Jul 03 06:04:28 PM PDT 24
Peak memory 262456 kb
Host smart-a176846a-b857-4ae3-ad03-f236d2de1df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925855384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1925855384
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2975645371
Short name T276
Test name
Test status
Simulation time 29909957637 ps
CPU time 71.09 seconds
Started Jul 03 06:03:08 PM PDT 24
Finished Jul 03 06:04:19 PM PDT 24
Peak memory 240888 kb
Host smart-f95cac5a-7ea8-45ed-b7d9-ed0ad5d78919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975645371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2975645371
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2874056852
Short name T702
Test name
Test status
Simulation time 264023440 ps
CPU time 2.73 seconds
Started Jul 03 06:03:05 PM PDT 24
Finished Jul 03 06:03:08 PM PDT 24
Peak memory 233776 kb
Host smart-47750e91-d662-456b-8be7-9d5c145db812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874056852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2874056852
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1832386812
Short name T653
Test name
Test status
Simulation time 10099274391 ps
CPU time 12.41 seconds
Started Jul 03 06:03:04 PM PDT 24
Finished Jul 03 06:03:16 PM PDT 24
Peak memory 225652 kb
Host smart-3c82f1f4-2956-4cb6-a8f8-5841c2a20e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832386812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1832386812
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2727730670
Short name T498
Test name
Test status
Simulation time 4349433155 ps
CPU time 33.65 seconds
Started Jul 03 06:03:09 PM PDT 24
Finished Jul 03 06:03:43 PM PDT 24
Peak memory 236960 kb
Host smart-e2906aa0-4888-41e3-9271-0a0499b7a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727730670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2727730670
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1707023868
Short name T186
Test name
Test status
Simulation time 2608075297 ps
CPU time 8.45 seconds
Started Jul 03 06:03:08 PM PDT 24
Finished Jul 03 06:03:17 PM PDT 24
Peak memory 233940 kb
Host smart-9b34c5ef-c941-4cbd-8cc8-48f388de103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707023868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1707023868
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1130012631
Short name T505
Test name
Test status
Simulation time 3046325139 ps
CPU time 10.71 seconds
Started Jul 03 06:03:05 PM PDT 24
Finished Jul 03 06:03:16 PM PDT 24
Peak memory 233924 kb
Host smart-0d7117f6-d162-4922-b180-ea67786f9426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130012631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1130012631
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1938832267
Short name T327
Test name
Test status
Simulation time 172321560 ps
CPU time 5.18 seconds
Started Jul 03 06:03:08 PM PDT 24
Finished Jul 03 06:03:14 PM PDT 24
Peak memory 224052 kb
Host smart-0c3a50c8-efb1-499f-a9c1-2d62e33f39a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1938832267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1938832267
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1346900766
Short name T167
Test name
Test status
Simulation time 128040083246 ps
CPU time 393.01 seconds
Started Jul 03 06:03:07 PM PDT 24
Finished Jul 03 06:09:40 PM PDT 24
Peak memory 268712 kb
Host smart-7dcb7580-854f-4ed6-9914-6b8a5a847d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346900766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1346900766
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.249972926
Short name T919
Test name
Test status
Simulation time 12571849117 ps
CPU time 12.51 seconds
Started Jul 03 06:03:02 PM PDT 24
Finished Jul 03 06:03:15 PM PDT 24
Peak memory 217592 kb
Host smart-a547243c-c87b-4a52-8763-b15c007b2a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249972926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.249972926
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1717317520
Short name T435
Test name
Test status
Simulation time 2634874000 ps
CPU time 6.55 seconds
Started Jul 03 06:03:02 PM PDT 24
Finished Jul 03 06:03:09 PM PDT 24
Peak memory 217452 kb
Host smart-5ddfb302-ce0d-4041-b0d4-c17317f88974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717317520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1717317520
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.393836357
Short name T291
Test name
Test status
Simulation time 204333905 ps
CPU time 1.93 seconds
Started Jul 03 06:03:00 PM PDT 24
Finished Jul 03 06:03:03 PM PDT 24
Peak memory 217376 kb
Host smart-5a60fdc5-33ce-4813-84a9-cffd015e0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393836357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.393836357
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2067010275
Short name T10
Test name
Test status
Simulation time 58199585 ps
CPU time 0.92 seconds
Started Jul 03 06:03:02 PM PDT 24
Finished Jul 03 06:03:03 PM PDT 24
Peak memory 206964 kb
Host smart-08434b2d-7aa8-40fc-b695-8df15eedfeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067010275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2067010275
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1814807397
Short name T792
Test name
Test status
Simulation time 773402101 ps
CPU time 5.03 seconds
Started Jul 03 06:03:08 PM PDT 24
Finished Jul 03 06:03:14 PM PDT 24
Peak memory 233776 kb
Host smart-61abed4c-cac2-41fe-bf6f-32dd5ce6fa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814807397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1814807397
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.488556307
Short name T337
Test name
Test status
Simulation time 13300584 ps
CPU time 0.72 seconds
Started Jul 03 06:03:13 PM PDT 24
Finished Jul 03 06:03:14 PM PDT 24
Peak memory 205804 kb
Host smart-e709578c-67cb-4c2d-96f4-a2b309412379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488556307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.488556307
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4209193564
Short name T231
Test name
Test status
Simulation time 24062478582 ps
CPU time 24.91 seconds
Started Jul 03 06:03:10 PM PDT 24
Finished Jul 03 06:03:35 PM PDT 24
Peak memory 225720 kb
Host smart-257e9e35-3194-4213-a7ad-d1028f744169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209193564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4209193564
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2567078647
Short name T331
Test name
Test status
Simulation time 56933126 ps
CPU time 0.78 seconds
Started Jul 03 06:03:09 PM PDT 24
Finished Jul 03 06:03:10 PM PDT 24
Peak memory 207848 kb
Host smart-4d3bcc96-3da4-482f-a880-62ef540189a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567078647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2567078647
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3875544839
Short name T918
Test name
Test status
Simulation time 9945087813 ps
CPU time 85.96 seconds
Started Jul 03 06:03:13 PM PDT 24
Finished Jul 03 06:04:39 PM PDT 24
Peak memory 257240 kb
Host smart-6594148b-f4a2-4be3-835a-d4d251716877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875544839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3875544839
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1364873160
Short name T278
Test name
Test status
Simulation time 3331788012 ps
CPU time 19.21 seconds
Started Jul 03 06:03:14 PM PDT 24
Finished Jul 03 06:03:33 PM PDT 24
Peak memory 218748 kb
Host smart-33a31394-98f7-402c-a54e-009cacd018b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364873160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1364873160
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2647167251
Short name T871
Test name
Test status
Simulation time 18110047866 ps
CPU time 158.92 seconds
Started Jul 03 06:03:12 PM PDT 24
Finished Jul 03 06:05:51 PM PDT 24
Peak memory 251652 kb
Host smart-88630261-b2db-4375-b85f-bab5949c5ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647167251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2647167251
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3751780800
Short name T270
Test name
Test status
Simulation time 1775534922 ps
CPU time 27.27 seconds
Started Jul 03 06:03:10 PM PDT 24
Finished Jul 03 06:03:37 PM PDT 24
Peak memory 242956 kb
Host smart-78ef7789-f46c-4efe-8d65-2e14aebd5c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751780800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3751780800
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2724812121
Short name T596
Test name
Test status
Simulation time 7721589399 ps
CPU time 71.94 seconds
Started Jul 03 06:03:10 PM PDT 24
Finished Jul 03 06:04:22 PM PDT 24
Peak memory 242300 kb
Host smart-2f4c076c-6038-4bb8-8662-fcc3a3f5697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724812121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2724812121
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2295340267
Short name T287
Test name
Test status
Simulation time 104209736 ps
CPU time 1.92 seconds
Started Jul 03 06:03:07 PM PDT 24
Finished Jul 03 06:03:09 PM PDT 24
Peak memory 224260 kb
Host smart-83107170-f788-42d2-be3b-85aaf61a8b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295340267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2295340267
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.920348777
Short name T930
Test name
Test status
Simulation time 6215749104 ps
CPU time 20.76 seconds
Started Jul 03 06:03:10 PM PDT 24
Finished Jul 03 06:03:31 PM PDT 24
Peak memory 241520 kb
Host smart-e1185bd6-2f45-4e24-a7fb-3662da3a39db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920348777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.920348777
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.935150923
Short name T1004
Test name
Test status
Simulation time 206453912 ps
CPU time 4.53 seconds
Started Jul 03 06:03:10 PM PDT 24
Finished Jul 03 06:03:15 PM PDT 24
Peak memory 233796 kb
Host smart-871dc5ed-2524-403d-864f-87fbf4b0baad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935150923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.935150923
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4167917321
Short name T851
Test name
Test status
Simulation time 13991594863 ps
CPU time 9.36 seconds
Started Jul 03 06:03:14 PM PDT 24
Finished Jul 03 06:03:24 PM PDT 24
Peak memory 224192 kb
Host smart-0a414444-44af-4f7a-a8cd-3b8f4aa1ecbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4167917321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4167917321
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3228097873
Short name T597
Test name
Test status
Simulation time 1310152805 ps
CPU time 10.61 seconds
Started Jul 03 06:03:07 PM PDT 24
Finished Jul 03 06:03:18 PM PDT 24
Peak memory 217436 kb
Host smart-bd25b2d2-1c85-4f02-9017-88067c6607aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228097873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3228097873
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.266330266
Short name T718
Test name
Test status
Simulation time 1966697883 ps
CPU time 7.59 seconds
Started Jul 03 06:03:10 PM PDT 24
Finished Jul 03 06:03:18 PM PDT 24
Peak memory 217372 kb
Host smart-7682ae5e-118f-4271-b104-d2a3358bee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266330266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.266330266
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.206214494
Short name T379
Test name
Test status
Simulation time 188981082 ps
CPU time 6.62 seconds
Started Jul 03 06:03:10 PM PDT 24
Finished Jul 03 06:03:17 PM PDT 24
Peak memory 217356 kb
Host smart-41f55ca1-c7bf-4aad-a54c-beca1ecac73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206214494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.206214494
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3915230322
Short name T375
Test name
Test status
Simulation time 127996863 ps
CPU time 0.91 seconds
Started Jul 03 06:03:08 PM PDT 24
Finished Jul 03 06:03:10 PM PDT 24
Peak memory 206992 kb
Host smart-ae1a028c-b8d3-423a-8253-ea476861a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915230322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3915230322
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3793270409
Short name T440
Test name
Test status
Simulation time 462081015 ps
CPU time 4.99 seconds
Started Jul 03 06:03:07 PM PDT 24
Finished Jul 03 06:03:13 PM PDT 24
Peak memory 230348 kb
Host smart-45bc74dd-0ed7-45ec-bddd-a7745ef2db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793270409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3793270409
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2307751858
Short name T581
Test name
Test status
Simulation time 13433783 ps
CPU time 0.82 seconds
Started Jul 03 06:03:19 PM PDT 24
Finished Jul 03 06:03:20 PM PDT 24
Peak memory 205812 kb
Host smart-45cbfbcc-62d2-458c-b7bb-df11e66a27d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307751858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2307751858
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1968905576
Short name T179
Test name
Test status
Simulation time 64478106 ps
CPU time 2.86 seconds
Started Jul 03 06:03:18 PM PDT 24
Finished Jul 03 06:03:21 PM PDT 24
Peak memory 225600 kb
Host smart-892442c5-4fbf-4497-a965-dbb338014e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968905576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1968905576
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2527252367
Short name T441
Test name
Test status
Simulation time 79528387 ps
CPU time 0.76 seconds
Started Jul 03 06:03:13 PM PDT 24
Finished Jul 03 06:03:14 PM PDT 24
Peak memory 207528 kb
Host smart-83cc73c8-6089-47f1-96fe-cf7759316fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527252367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2527252367
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2847931203
Short name T662
Test name
Test status
Simulation time 6417122997 ps
CPU time 53.63 seconds
Started Jul 03 06:03:15 PM PDT 24
Finished Jul 03 06:04:09 PM PDT 24
Peak memory 240000 kb
Host smart-a95dfa8a-547b-44b5-be3a-0e278da683ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847931203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2847931203
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2900505391
Short name T804
Test name
Test status
Simulation time 1021282305 ps
CPU time 14.46 seconds
Started Jul 03 06:03:15 PM PDT 24
Finished Jul 03 06:03:30 PM PDT 24
Peak memory 225632 kb
Host smart-1d8cd14b-83a1-4f5b-8927-678e8bd16019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900505391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2900505391
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.754214536
Short name T350
Test name
Test status
Simulation time 80905211084 ps
CPU time 131.05 seconds
Started Jul 03 06:03:18 PM PDT 24
Finished Jul 03 06:05:30 PM PDT 24
Peak memory 253456 kb
Host smart-dc180d53-1018-43d3-b693-a6daacaf1fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754214536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.754214536
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3432654210
Short name T615
Test name
Test status
Simulation time 2312539793 ps
CPU time 13.22 seconds
Started Jul 03 06:03:18 PM PDT 24
Finished Jul 03 06:03:31 PM PDT 24
Peak memory 233884 kb
Host smart-0f2938d9-b0b3-4359-bd85-e42f9b918683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432654210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3432654210
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.12729944
Short name T614
Test name
Test status
Simulation time 599871734 ps
CPU time 9.77 seconds
Started Jul 03 06:03:18 PM PDT 24
Finished Jul 03 06:03:28 PM PDT 24
Peak memory 233824 kb
Host smart-b5469d6e-096d-4f80-bbde-e2fae137c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12729944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.12729944
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1522013905
Short name T805
Test name
Test status
Simulation time 1596647555 ps
CPU time 3.38 seconds
Started Jul 03 06:03:18 PM PDT 24
Finished Jul 03 06:03:21 PM PDT 24
Peak memory 233808 kb
Host smart-dbce0154-0852-48e4-a716-2ea6b0ef403e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522013905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1522013905
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3325571554
Short name T701
Test name
Test status
Simulation time 35735005110 ps
CPU time 22.65 seconds
Started Jul 03 06:03:18 PM PDT 24
Finished Jul 03 06:03:41 PM PDT 24
Peak memory 225732 kb
Host smart-3929d645-a87b-43fb-ba3c-17c666901cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325571554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3325571554
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3926913436
Short name T1010
Test name
Test status
Simulation time 2910872702 ps
CPU time 16.15 seconds
Started Jul 03 06:03:20 PM PDT 24
Finished Jul 03 06:03:37 PM PDT 24
Peak memory 221868 kb
Host smart-6f0a2c01-678f-48f5-baad-377b3522545f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3926913436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3926913436
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1051807943
Short name T257
Test name
Test status
Simulation time 30505640524 ps
CPU time 137.4 seconds
Started Jul 03 06:03:16 PM PDT 24
Finished Jul 03 06:05:33 PM PDT 24
Peak memory 274024 kb
Host smart-19fb5358-d7a2-4eef-ad5a-45184311c21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051807943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1051807943
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1174483604
Short name T564
Test name
Test status
Simulation time 3137620224 ps
CPU time 16.36 seconds
Started Jul 03 06:03:13 PM PDT 24
Finished Jul 03 06:03:30 PM PDT 24
Peak memory 217656 kb
Host smart-d03e139d-e6b9-41ab-b29d-0509c13530ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174483604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1174483604
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1894912983
Short name T436
Test name
Test status
Simulation time 86173262 ps
CPU time 1.23 seconds
Started Jul 03 06:03:13 PM PDT 24
Finished Jul 03 06:03:14 PM PDT 24
Peak memory 207960 kb
Host smart-5ac60fcb-d4ef-494b-8f6f-0bacaa29fc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894912983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1894912983
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.851519743
Short name T627
Test name
Test status
Simulation time 47332774 ps
CPU time 1.43 seconds
Started Jul 03 06:03:12 PM PDT 24
Finished Jul 03 06:03:13 PM PDT 24
Peak memory 217340 kb
Host smart-673a6b86-4ffe-4553-aa4b-4e10267aab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851519743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.851519743
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2187520523
Short name T370
Test name
Test status
Simulation time 272187727 ps
CPU time 0.98 seconds
Started Jul 03 06:03:14 PM PDT 24
Finished Jul 03 06:03:15 PM PDT 24
Peak memory 208032 kb
Host smart-6e4c6770-a90f-44d7-a294-b7de997d243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187520523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2187520523
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3991264649
Short name T901
Test name
Test status
Simulation time 10245556367 ps
CPU time 9.84 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:03:32 PM PDT 24
Peak memory 225692 kb
Host smart-23675254-cc6c-4286-a0ed-2999126cbcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991264649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3991264649
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3254107649
Short name T888
Test name
Test status
Simulation time 48408320 ps
CPU time 0.76 seconds
Started Jul 03 06:03:22 PM PDT 24
Finished Jul 03 06:03:23 PM PDT 24
Peak memory 206360 kb
Host smart-34162caa-92d5-4222-905e-580ae4d8f5e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254107649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3254107649
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3599417937
Short name T351
Test name
Test status
Simulation time 2309587982 ps
CPU time 6.26 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:03:28 PM PDT 24
Peak memory 225724 kb
Host smart-a4ee5c0b-e5d9-4038-99d3-149e2ca34af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599417937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3599417937
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2598338419
Short name T737
Test name
Test status
Simulation time 22319556 ps
CPU time 0.78 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:03:22 PM PDT 24
Peak memory 207544 kb
Host smart-91aae175-1221-4c5f-b6a0-700d3cdff89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598338419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2598338419
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3379744295
Short name T1028
Test name
Test status
Simulation time 6291758598 ps
CPU time 65.1 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:04:27 PM PDT 24
Peak memory 254736 kb
Host smart-eb7d7024-3662-4032-9f43-7d071d20d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379744295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3379744295
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.602072713
Short name T277
Test name
Test status
Simulation time 8343437529 ps
CPU time 37.9 seconds
Started Jul 03 06:03:22 PM PDT 24
Finished Jul 03 06:04:01 PM PDT 24
Peak memory 218844 kb
Host smart-4936bd92-bad5-47d0-a3ed-df764d6ee886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602072713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.602072713
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1597151934
Short name T650
Test name
Test status
Simulation time 47262036257 ps
CPU time 387.48 seconds
Started Jul 03 06:03:25 PM PDT 24
Finished Jul 03 06:09:52 PM PDT 24
Peak memory 252636 kb
Host smart-3d64e786-900b-40aa-9442-936bd36c574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597151934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1597151934
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1168396474
Short name T931
Test name
Test status
Simulation time 700739050 ps
CPU time 15.26 seconds
Started Jul 03 06:03:20 PM PDT 24
Finished Jul 03 06:03:36 PM PDT 24
Peak memory 233668 kb
Host smart-2408f647-0aac-4996-a778-d814e79b0a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168396474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1168396474
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.344883624
Short name T558
Test name
Test status
Simulation time 4358313551 ps
CPU time 18.97 seconds
Started Jul 03 06:03:20 PM PDT 24
Finished Jul 03 06:03:40 PM PDT 24
Peak memory 225728 kb
Host smart-f2dfb039-6ce9-4efc-a5a9-55aabc6528ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344883624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.344883624
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.477191213
Short name T692
Test name
Test status
Simulation time 94339640 ps
CPU time 2.19 seconds
Started Jul 03 06:03:20 PM PDT 24
Finished Jul 03 06:03:23 PM PDT 24
Peak memory 223996 kb
Host smart-cf909c1e-6b09-4b34-a9a6-d29e5d1d6735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477191213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.477191213
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2238031147
Short name T1029
Test name
Test status
Simulation time 413914860 ps
CPU time 10.43 seconds
Started Jul 03 06:03:22 PM PDT 24
Finished Jul 03 06:03:32 PM PDT 24
Peak memory 234144 kb
Host smart-eca25bb0-9734-48fa-9fde-18b5d0c56094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238031147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2238031147
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2473510957
Short name T506
Test name
Test status
Simulation time 32802974 ps
CPU time 2.52 seconds
Started Jul 03 06:03:20 PM PDT 24
Finished Jul 03 06:03:24 PM PDT 24
Peak memory 233572 kb
Host smart-9e7f4e7b-891c-410e-9ca8-bbd9ef8b130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473510957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2473510957
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2398514503
Short name T677
Test name
Test status
Simulation time 438405689 ps
CPU time 7.91 seconds
Started Jul 03 06:03:19 PM PDT 24
Finished Jul 03 06:03:27 PM PDT 24
Peak memory 233800 kb
Host smart-b327d904-58b1-47c7-898b-f2b71ecb7cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398514503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2398514503
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2306123009
Short name T373
Test name
Test status
Simulation time 1174359198 ps
CPU time 4.65 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:03:26 PM PDT 24
Peak memory 224088 kb
Host smart-966099fe-24ad-4ac0-9a91-46c7eb9ac6ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2306123009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2306123009
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2101792902
Short name T249
Test name
Test status
Simulation time 284079659577 ps
CPU time 919.45 seconds
Started Jul 03 06:03:22 PM PDT 24
Finished Jul 03 06:18:42 PM PDT 24
Peak memory 306524 kb
Host smart-c1683e97-ed53-4184-8fa4-c3cea1aecf8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101792902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2101792902
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2516619476
Short name T499
Test name
Test status
Simulation time 4427133166 ps
CPU time 30.32 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:03:52 PM PDT 24
Peak memory 217544 kb
Host smart-080781e6-74be-4d63-a937-4400e2bf242d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516619476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2516619476
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1260925341
Short name T551
Test name
Test status
Simulation time 4410575275 ps
CPU time 11.02 seconds
Started Jul 03 06:03:18 PM PDT 24
Finished Jul 03 06:03:29 PM PDT 24
Peak memory 217492 kb
Host smart-0fdd4893-25c6-4328-b1bf-55582c173df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260925341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1260925341
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2327587209
Short name T304
Test name
Test status
Simulation time 331882815 ps
CPU time 1.06 seconds
Started Jul 03 06:03:19 PM PDT 24
Finished Jul 03 06:03:21 PM PDT 24
Peak memory 208028 kb
Host smart-9eaa558f-5ff9-4bed-8d56-a6822b9f4caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327587209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2327587209
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3919434837
Short name T361
Test name
Test status
Simulation time 21369270 ps
CPU time 0.77 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:03:22 PM PDT 24
Peak memory 206940 kb
Host smart-824be62e-fbfc-499f-bd60-b731adfbe164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919434837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3919434837
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2853968951
Short name T15
Test name
Test status
Simulation time 71580684 ps
CPU time 2.2 seconds
Started Jul 03 06:03:21 PM PDT 24
Finished Jul 03 06:03:24 PM PDT 24
Peak memory 225400 kb
Host smart-ced61d41-4de3-4c09-afec-47683c0c8d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853968951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2853968951
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.922684892
Short name T708
Test name
Test status
Simulation time 23414195 ps
CPU time 0.76 seconds
Started Jul 03 06:03:27 PM PDT 24
Finished Jul 03 06:03:28 PM PDT 24
Peak memory 206684 kb
Host smart-78005d8d-9ac0-4abc-9e15-b711e5eb29ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922684892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.922684892
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4154866455
Short name T339
Test name
Test status
Simulation time 2065954069 ps
CPU time 16.56 seconds
Started Jul 03 06:03:28 PM PDT 24
Finished Jul 03 06:03:45 PM PDT 24
Peak memory 225548 kb
Host smart-1c1fff74-8a4c-4a6b-ba39-2cf487a270f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154866455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4154866455
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.263836289
Short name T885
Test name
Test status
Simulation time 21774721 ps
CPU time 0.8 seconds
Started Jul 03 06:03:26 PM PDT 24
Finished Jul 03 06:03:28 PM PDT 24
Peak memory 207544 kb
Host smart-b1f89f94-cc39-44a5-9f71-4eb57ef3e68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263836289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.263836289
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2434754259
Short name T1013
Test name
Test status
Simulation time 82433818218 ps
CPU time 158.43 seconds
Started Jul 03 06:03:28 PM PDT 24
Finished Jul 03 06:06:07 PM PDT 24
Peak memory 253600 kb
Host smart-4c71ab9e-878b-4ef3-8e34-e6db77ad46b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434754259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2434754259
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3984180419
Short name T219
Test name
Test status
Simulation time 24773064822 ps
CPU time 43.9 seconds
Started Jul 03 06:03:28 PM PDT 24
Finished Jul 03 06:04:13 PM PDT 24
Peak memory 250492 kb
Host smart-05e6d411-0646-4cea-a42c-617ec02f7291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984180419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3984180419
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.782155777
Short name T785
Test name
Test status
Simulation time 20960445182 ps
CPU time 96.42 seconds
Started Jul 03 06:03:28 PM PDT 24
Finished Jul 03 06:05:05 PM PDT 24
Peak memory 242196 kb
Host smart-97534754-7815-41aa-bf12-13aeb6d9cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782155777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.782155777
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1691542999
Short name T481
Test name
Test status
Simulation time 135852538 ps
CPU time 3.79 seconds
Started Jul 03 06:03:28 PM PDT 24
Finished Jul 03 06:03:33 PM PDT 24
Peak memory 225584 kb
Host smart-0d6bee38-f5f1-41ac-b9ef-7640e4371756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691542999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1691542999
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.676350849
Short name T747
Test name
Test status
Simulation time 4237700534 ps
CPU time 46.06 seconds
Started Jul 03 06:03:27 PM PDT 24
Finished Jul 03 06:04:14 PM PDT 24
Peak memory 250320 kb
Host smart-5746cd4f-c286-47c7-986f-fd9694920941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676350849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.676350849
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4062196372
Short name T369
Test name
Test status
Simulation time 4878551720 ps
CPU time 10.22 seconds
Started Jul 03 06:03:26 PM PDT 24
Finished Jul 03 06:03:36 PM PDT 24
Peak memory 233972 kb
Host smart-e2a0ae12-e870-4ae5-b48e-1911ef671739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062196372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4062196372
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1596352157
Short name T867
Test name
Test status
Simulation time 17307847501 ps
CPU time 57.12 seconds
Started Jul 03 06:03:27 PM PDT 24
Finished Jul 03 06:04:24 PM PDT 24
Peak memory 240152 kb
Host smart-1455f4b9-b69d-451b-bfac-f88f518c05ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596352157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1596352157
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2541852896
Short name T497
Test name
Test status
Simulation time 206302591 ps
CPU time 2.27 seconds
Started Jul 03 06:03:24 PM PDT 24
Finished Jul 03 06:03:26 PM PDT 24
Peak memory 225600 kb
Host smart-7410ad7f-dcaa-4a39-a4e2-6825039d9faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541852896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2541852896
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2705440791
Short name T979
Test name
Test status
Simulation time 699035737 ps
CPU time 4.46 seconds
Started Jul 03 06:03:22 PM PDT 24
Finished Jul 03 06:03:27 PM PDT 24
Peak memory 225548 kb
Host smart-140985c6-8d1c-410a-a330-20cd31350a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705440791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2705440791
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.404047201
Short name T534
Test name
Test status
Simulation time 1980535575 ps
CPU time 9.11 seconds
Started Jul 03 06:03:26 PM PDT 24
Finished Jul 03 06:03:36 PM PDT 24
Peak memory 219868 kb
Host smart-d5b009a3-0ab0-4105-b692-8d28ebbf7ecf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=404047201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.404047201
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3674374590
Short name T533
Test name
Test status
Simulation time 2426663102 ps
CPU time 7.83 seconds
Started Jul 03 06:03:23 PM PDT 24
Finished Jul 03 06:03:31 PM PDT 24
Peak memory 217496 kb
Host smart-5203efc6-7f30-4201-811b-29cbb3951090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674374590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3674374590
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4126836584
Short name T474
Test name
Test status
Simulation time 8611595831 ps
CPU time 7.91 seconds
Started Jul 03 06:03:23 PM PDT 24
Finished Jul 03 06:03:31 PM PDT 24
Peak memory 217468 kb
Host smart-722e548e-07ce-4541-b37b-528a9a8d93eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126836584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4126836584
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2919730040
Short name T289
Test name
Test status
Simulation time 487608504 ps
CPU time 1.74 seconds
Started Jul 03 06:03:25 PM PDT 24
Finished Jul 03 06:03:26 PM PDT 24
Peak memory 217396 kb
Host smart-693b09db-733a-4fbd-a036-d0d40c19c879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919730040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2919730040
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3857205242
Short name T463
Test name
Test status
Simulation time 148964077 ps
CPU time 0.8 seconds
Started Jul 03 06:03:24 PM PDT 24
Finished Jul 03 06:03:25 PM PDT 24
Peak memory 206952 kb
Host smart-5ec1c1c6-a22d-4051-b181-294c8716d01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857205242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3857205242
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3856605504
Short name T14
Test name
Test status
Simulation time 951968001 ps
CPU time 5.89 seconds
Started Jul 03 06:03:27 PM PDT 24
Finished Jul 03 06:03:34 PM PDT 24
Peak memory 233752 kb
Host smart-238c1b1a-86a1-4b6b-b201-372a26eb3607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856605504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3856605504
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4284318090
Short name T552
Test name
Test status
Simulation time 11832280 ps
CPU time 0.72 seconds
Started Jul 03 06:03:36 PM PDT 24
Finished Jul 03 06:03:38 PM PDT 24
Peak memory 206748 kb
Host smart-08a1f4a8-2da2-44aa-95de-3bc8f36324f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284318090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4284318090
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1964722689
Short name T1022
Test name
Test status
Simulation time 229152273 ps
CPU time 3.32 seconds
Started Jul 03 06:03:33 PM PDT 24
Finished Jul 03 06:03:37 PM PDT 24
Peak memory 225532 kb
Host smart-de97ae4c-7599-4b11-907c-a4d5fa358e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964722689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1964722689
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1335867110
Short name T372
Test name
Test status
Simulation time 39178141 ps
CPU time 0.79 seconds
Started Jul 03 06:03:27 PM PDT 24
Finished Jul 03 06:03:28 PM PDT 24
Peak memory 207504 kb
Host smart-a95e3b32-3013-4dac-9ee7-f888f4b1ac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335867110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1335867110
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2988018960
Short name T255
Test name
Test status
Simulation time 5941386572 ps
CPU time 34.09 seconds
Started Jul 03 06:03:32 PM PDT 24
Finished Jul 03 06:04:06 PM PDT 24
Peak memory 250312 kb
Host smart-9f3979b0-c07b-4d27-a679-67381d355180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988018960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2988018960
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2187388091
Short name T829
Test name
Test status
Simulation time 2191962530 ps
CPU time 40.64 seconds
Started Jul 03 06:03:32 PM PDT 24
Finished Jul 03 06:04:13 PM PDT 24
Peak memory 256252 kb
Host smart-4d7e1fff-4df3-43f0-b986-de2fab5650ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187388091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2187388091
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1894157654
Short name T685
Test name
Test status
Simulation time 21322842969 ps
CPU time 169.74 seconds
Started Jul 03 06:03:32 PM PDT 24
Finished Jul 03 06:06:22 PM PDT 24
Peak memory 256800 kb
Host smart-b4f22011-cfc8-4bf2-b75f-c5a8e2fe8602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894157654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1894157654
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.975361091
Short name T519
Test name
Test status
Simulation time 269628212 ps
CPU time 4.53 seconds
Started Jul 03 06:03:32 PM PDT 24
Finished Jul 03 06:03:37 PM PDT 24
Peak memory 225624 kb
Host smart-74cfe7b5-74bf-4ae5-905a-cd6e2ce9a5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975361091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.975361091
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.178804121
Short name T358
Test name
Test status
Simulation time 230029854 ps
CPU time 4.74 seconds
Started Jul 03 06:03:32 PM PDT 24
Finished Jul 03 06:03:37 PM PDT 24
Peak memory 235472 kb
Host smart-45ffb6e7-8d11-4e2e-b0e1-9ad966b90057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178804121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.178804121
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4011881170
Short name T158
Test name
Test status
Simulation time 161517427 ps
CPU time 3.54 seconds
Started Jul 03 06:03:31 PM PDT 24
Finished Jul 03 06:03:35 PM PDT 24
Peak memory 233748 kb
Host smart-7b27216e-ed93-41fb-803b-8180853ac47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011881170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4011881170
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1277668050
Short name T230
Test name
Test status
Simulation time 801652779 ps
CPU time 14.16 seconds
Started Jul 03 06:03:31 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 233772 kb
Host smart-de93adb6-0bb2-402c-a432-462e695e57ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277668050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1277668050
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3800253195
Short name T450
Test name
Test status
Simulation time 14410065460 ps
CPU time 21.07 seconds
Started Jul 03 06:03:30 PM PDT 24
Finished Jul 03 06:03:52 PM PDT 24
Peak memory 233936 kb
Host smart-a17e672c-2513-44b9-bda1-5538e75a3cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800253195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3800253195
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.384994132
Short name T206
Test name
Test status
Simulation time 6238022262 ps
CPU time 7.16 seconds
Started Jul 03 06:03:33 PM PDT 24
Finished Jul 03 06:03:40 PM PDT 24
Peak memory 225696 kb
Host smart-c74dc3b7-fde7-4b72-8565-9ecb0f2e64d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384994132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.384994132
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1820438178
Short name T844
Test name
Test status
Simulation time 1344893970 ps
CPU time 7.08 seconds
Started Jul 03 06:03:34 PM PDT 24
Finished Jul 03 06:03:41 PM PDT 24
Peak memory 223444 kb
Host smart-90697b0e-8de9-4c10-b7f1-bbd4aeab58a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1820438178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1820438178
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3413955039
Short name T56
Test name
Test status
Simulation time 41832910467 ps
CPU time 376.93 seconds
Started Jul 03 06:03:31 PM PDT 24
Finished Jul 03 06:09:49 PM PDT 24
Peak memory 250376 kb
Host smart-f9f499f6-63ed-4ca1-82d5-46f72a73a3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413955039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3413955039
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.657246522
Short name T725
Test name
Test status
Simulation time 4406169273 ps
CPU time 21.11 seconds
Started Jul 03 06:03:33 PM PDT 24
Finished Jul 03 06:03:55 PM PDT 24
Peak memory 217556 kb
Host smart-a118ee00-fab7-4949-abb6-ab8a66426e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657246522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.657246522
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1737808269
Short name T923
Test name
Test status
Simulation time 48353636784 ps
CPU time 12.49 seconds
Started Jul 03 06:03:28 PM PDT 24
Finished Jul 03 06:03:41 PM PDT 24
Peak memory 217472 kb
Host smart-b8c2919b-c29a-4a9a-851a-f7818a851cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737808269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1737808269
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2232524170
Short name T668
Test name
Test status
Simulation time 209188173 ps
CPU time 1.25 seconds
Started Jul 03 06:03:31 PM PDT 24
Finished Jul 03 06:03:33 PM PDT 24
Peak memory 209184 kb
Host smart-b527d618-5a0c-4387-931e-ca3ce2c2d20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232524170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2232524170
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2621082065
Short name T529
Test name
Test status
Simulation time 45956561 ps
CPU time 0.81 seconds
Started Jul 03 06:03:32 PM PDT 24
Finished Jul 03 06:03:34 PM PDT 24
Peak memory 206992 kb
Host smart-f3a08d88-2d93-4c8e-95ef-c2842b126b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621082065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2621082065
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4271806263
Short name T386
Test name
Test status
Simulation time 1217049160 ps
CPU time 9.38 seconds
Started Jul 03 06:03:32 PM PDT 24
Finished Jul 03 06:03:41 PM PDT 24
Peak memory 240116 kb
Host smart-54c8fc49-1ce1-47fb-93dd-13454209de4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271806263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4271806263
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4068871267
Short name T585
Test name
Test status
Simulation time 38881591 ps
CPU time 0.72 seconds
Started Jul 03 06:03:42 PM PDT 24
Finished Jul 03 06:03:43 PM PDT 24
Peak memory 205812 kb
Host smart-a08831b5-7126-4552-b3e3-966ae2b769d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068871267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4068871267
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4271150124
Short name T298
Test name
Test status
Simulation time 72378974 ps
CPU time 2.23 seconds
Started Jul 03 06:03:37 PM PDT 24
Finished Jul 03 06:03:39 PM PDT 24
Peak memory 224920 kb
Host smart-3fec8284-17d4-459e-abe6-244e7bc23f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271150124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4271150124
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1740863597
Short name T523
Test name
Test status
Simulation time 74516645 ps
CPU time 0.8 seconds
Started Jul 03 06:03:38 PM PDT 24
Finished Jul 03 06:03:39 PM PDT 24
Peak memory 207528 kb
Host smart-fd947777-aaf8-403b-845d-d4656dbe1b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740863597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1740863597
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1875917750
Short name T989
Test name
Test status
Simulation time 278314548025 ps
CPU time 515.28 seconds
Started Jul 03 06:03:37 PM PDT 24
Finished Jul 03 06:12:13 PM PDT 24
Peak memory 266688 kb
Host smart-e5a602a9-b835-424b-85e2-60dbe2ddd7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875917750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1875917750
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2604629402
Short name T508
Test name
Test status
Simulation time 34677127 ps
CPU time 0.82 seconds
Started Jul 03 06:03:38 PM PDT 24
Finished Jul 03 06:03:39 PM PDT 24
Peak memory 218956 kb
Host smart-11fc0082-3197-4837-ab79-356adcf1afff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604629402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2604629402
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.227496642
Short name T50
Test name
Test status
Simulation time 223623491143 ps
CPU time 439.44 seconds
Started Jul 03 06:03:40 PM PDT 24
Finished Jul 03 06:11:00 PM PDT 24
Peak memory 255436 kb
Host smart-8a93b100-eba5-4db0-bb0e-e33972d12cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227496642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.227496642
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.337371701
Short name T275
Test name
Test status
Simulation time 2536382044 ps
CPU time 15.79 seconds
Started Jul 03 06:03:37 PM PDT 24
Finished Jul 03 06:03:53 PM PDT 24
Peak memory 225740 kb
Host smart-5298cbc0-693d-4bb8-9241-17ac076e73e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337371701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.337371701
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1293379718
Short name T780
Test name
Test status
Simulation time 3755007123 ps
CPU time 31.63 seconds
Started Jul 03 06:03:35 PM PDT 24
Finished Jul 03 06:04:07 PM PDT 24
Peak memory 239256 kb
Host smart-852e3d38-a76e-4e9e-ae9f-a9ff51f638f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293379718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1293379718
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.910000492
Short name T216
Test name
Test status
Simulation time 678315016 ps
CPU time 3.69 seconds
Started Jul 03 06:03:34 PM PDT 24
Finished Jul 03 06:03:38 PM PDT 24
Peak memory 225572 kb
Host smart-2c723a09-3eb4-4941-9205-43f745d2faf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910000492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.910000492
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4115622580
Short name T138
Test name
Test status
Simulation time 604914639 ps
CPU time 15.18 seconds
Started Jul 03 06:03:37 PM PDT 24
Finished Jul 03 06:03:53 PM PDT 24
Peak memory 225564 kb
Host smart-8b7cc811-a3e3-40bb-9b29-0ef9576b36fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115622580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4115622580
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2305894915
Short name T16
Test name
Test status
Simulation time 30992500 ps
CPU time 2.45 seconds
Started Jul 03 06:03:34 PM PDT 24
Finished Jul 03 06:03:37 PM PDT 24
Peak memory 233792 kb
Host smart-5f4e087e-d0ef-4395-a967-5b9efe0cdc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305894915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2305894915
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1145340889
Short name T635
Test name
Test status
Simulation time 8839331752 ps
CPU time 14.66 seconds
Started Jul 03 06:03:35 PM PDT 24
Finished Jul 03 06:03:50 PM PDT 24
Peak memory 233916 kb
Host smart-fbac375d-d928-481e-83ae-e0d875eb8ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145340889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1145340889
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4237654477
Short name T150
Test name
Test status
Simulation time 702137918 ps
CPU time 5.85 seconds
Started Jul 03 06:03:35 PM PDT 24
Finished Jul 03 06:03:42 PM PDT 24
Peak memory 223244 kb
Host smart-2f2d7336-5f46-445e-b0af-a7e4e39b8413
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4237654477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4237654477
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.806073795
Short name T363
Test name
Test status
Simulation time 75202121527 ps
CPU time 162.95 seconds
Started Jul 03 06:03:42 PM PDT 24
Finished Jul 03 06:06:26 PM PDT 24
Peak memory 250384 kb
Host smart-a3aa4831-f889-4523-afed-ffa03702674c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806073795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.806073795
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3825982514
Short name T433
Test name
Test status
Simulation time 18356760681 ps
CPU time 24.45 seconds
Started Jul 03 06:03:34 PM PDT 24
Finished Jul 03 06:03:59 PM PDT 24
Peak memory 217384 kb
Host smart-bb06150f-dc16-44af-a1c6-f1b621467b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825982514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3825982514
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1534354767
Short name T591
Test name
Test status
Simulation time 10449339 ps
CPU time 0.71 seconds
Started Jul 03 06:03:36 PM PDT 24
Finished Jul 03 06:03:37 PM PDT 24
Peak memory 206620 kb
Host smart-ad49f06b-6941-4888-97b9-b72c52daf042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534354767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1534354767
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.654852763
Short name T766
Test name
Test status
Simulation time 501257596 ps
CPU time 3.23 seconds
Started Jul 03 06:03:34 PM PDT 24
Finished Jul 03 06:03:38 PM PDT 24
Peak memory 217328 kb
Host smart-ddf04ce9-d740-4f0e-90d4-037812d95e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654852763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.654852763
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3399771758
Short name T719
Test name
Test status
Simulation time 57417525 ps
CPU time 0.85 seconds
Started Jul 03 06:03:37 PM PDT 24
Finished Jul 03 06:03:39 PM PDT 24
Peak memory 206952 kb
Host smart-451e661f-ba2a-4967-8f26-366766f87d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399771758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3399771758
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4241825881
Short name T545
Test name
Test status
Simulation time 766358474 ps
CPU time 5.73 seconds
Started Jul 03 06:03:36 PM PDT 24
Finished Jul 03 06:03:41 PM PDT 24
Peak memory 233804 kb
Host smart-139fc532-47f2-4401-a31c-153dc853aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241825881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4241825881
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1090322340
Short name T574
Test name
Test status
Simulation time 39692867 ps
CPU time 0.75 seconds
Started Jul 03 06:03:45 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 206408 kb
Host smart-cb64d74a-6e85-4664-aeef-f102063a6bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090322340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1090322340
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1269162240
Short name T763
Test name
Test status
Simulation time 32580412 ps
CPU time 2.78 seconds
Started Jul 03 06:03:42 PM PDT 24
Finished Jul 03 06:03:45 PM PDT 24
Peak memory 233752 kb
Host smart-f46fd7b3-0a18-4fd2-9f31-e8f280edddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269162240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1269162240
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1972637693
Short name T866
Test name
Test status
Simulation time 21478206 ps
CPU time 0.8 seconds
Started Jul 03 06:03:38 PM PDT 24
Finished Jul 03 06:03:39 PM PDT 24
Peak memory 207884 kb
Host smart-dec8c719-9ca8-4fe6-bbfa-a7a2805d8dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972637693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1972637693
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2903379610
Short name T183
Test name
Test status
Simulation time 189622442649 ps
CPU time 395.05 seconds
Started Jul 03 06:03:38 PM PDT 24
Finished Jul 03 06:10:14 PM PDT 24
Peak memory 273048 kb
Host smart-9e1d900d-7624-413d-96d7-4f8328a1c8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903379610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2903379610
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1754900653
Short name T517
Test name
Test status
Simulation time 53639315943 ps
CPU time 251.9 seconds
Started Jul 03 06:03:39 PM PDT 24
Finished Jul 03 06:07:51 PM PDT 24
Peak memory 251472 kb
Host smart-97929bf5-b6f8-47eb-a7c4-025a6336f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754900653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1754900653
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1544624997
Short name T180
Test name
Test status
Simulation time 43288136625 ps
CPU time 175.39 seconds
Started Jul 03 06:03:37 PM PDT 24
Finished Jul 03 06:06:33 PM PDT 24
Peak memory 252100 kb
Host smart-108df80e-6f7f-45b0-bc01-74ab0d92e942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544624997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1544624997
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.792179888
Short name T1021
Test name
Test status
Simulation time 6161903626 ps
CPU time 24.09 seconds
Started Jul 03 06:03:40 PM PDT 24
Finished Jul 03 06:04:05 PM PDT 24
Peak memory 250348 kb
Host smart-4e705a1b-d968-42a0-aac2-273048ebe60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792179888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.792179888
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3700832558
Short name T631
Test name
Test status
Simulation time 801994646 ps
CPU time 1.03 seconds
Started Jul 03 06:03:41 PM PDT 24
Finished Jul 03 06:03:42 PM PDT 24
Peak memory 217184 kb
Host smart-a8e1a4b7-cd19-452b-948f-50040d162951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700832558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3700832558
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2726570647
Short name T160
Test name
Test status
Simulation time 623188048 ps
CPU time 3.84 seconds
Started Jul 03 06:03:41 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 233728 kb
Host smart-1697a456-255b-4d72-a502-4f1908ba61a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726570647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2726570647
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2981930792
Short name T956
Test name
Test status
Simulation time 104720848 ps
CPU time 2.28 seconds
Started Jul 03 06:03:38 PM PDT 24
Finished Jul 03 06:03:40 PM PDT 24
Peak memory 224884 kb
Host smart-f15a6aeb-1042-4280-b6fe-123f45d02442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981930792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2981930792
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3817206855
Short name T587
Test name
Test status
Simulation time 139862341 ps
CPU time 2.15 seconds
Started Jul 03 06:03:43 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 225544 kb
Host smart-e68176f1-81ef-4490-baea-5501c4698202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817206855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3817206855
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1966194790
Short name T383
Test name
Test status
Simulation time 833141343 ps
CPU time 2.98 seconds
Started Jul 03 06:03:43 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 233684 kb
Host smart-c85d20f4-1c06-46af-af6e-ee00718aa808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966194790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1966194790
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1498378451
Short name T40
Test name
Test status
Simulation time 2257521342 ps
CPU time 12.3 seconds
Started Jul 03 06:03:42 PM PDT 24
Finished Jul 03 06:03:55 PM PDT 24
Peak memory 220548 kb
Host smart-e966657e-59fa-4c81-8a18-e69c81113f72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1498378451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1498378451
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2923047882
Short name T365
Test name
Test status
Simulation time 1462648824 ps
CPU time 11.05 seconds
Started Jul 03 06:03:42 PM PDT 24
Finished Jul 03 06:03:53 PM PDT 24
Peak memory 217400 kb
Host smart-699b6de3-4a35-451c-bed2-28cd08df4175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923047882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2923047882
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2692465463
Short name T566
Test name
Test status
Simulation time 6310777275 ps
CPU time 6.73 seconds
Started Jul 03 06:03:38 PM PDT 24
Finished Jul 03 06:03:45 PM PDT 24
Peak memory 217508 kb
Host smart-5fae2bd2-5308-4c98-a2b9-5376f2004532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692465463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2692465463
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1471486171
Short name T378
Test name
Test status
Simulation time 41996092 ps
CPU time 1.38 seconds
Started Jul 03 06:03:39 PM PDT 24
Finished Jul 03 06:03:41 PM PDT 24
Peak memory 217348 kb
Host smart-bd1c6cdd-6981-4f06-8343-728f195dcada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471486171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1471486171
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2861265080
Short name T89
Test name
Test status
Simulation time 99439016 ps
CPU time 0.9 seconds
Started Jul 03 06:03:41 PM PDT 24
Finished Jul 03 06:03:42 PM PDT 24
Peak memory 206968 kb
Host smart-66c84470-6e2c-42c6-89c3-77b2753cf8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861265080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2861265080
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1577972393
Short name T225
Test name
Test status
Simulation time 36027576728 ps
CPU time 24.39 seconds
Started Jul 03 06:03:42 PM PDT 24
Finished Jul 03 06:04:07 PM PDT 24
Peak memory 242088 kb
Host smart-b9e66803-d18a-48eb-8f29-83364f88a3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577972393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1577972393
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3126704451
Short name T786
Test name
Test status
Simulation time 21612295 ps
CPU time 0.74 seconds
Started Jul 03 06:03:47 PM PDT 24
Finished Jul 03 06:03:48 PM PDT 24
Peak memory 205792 kb
Host smart-fd09af0c-961d-4312-a015-bc2b9b6b45e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126704451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3126704451
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.816553490
Short name T773
Test name
Test status
Simulation time 144033912 ps
CPU time 3 seconds
Started Jul 03 06:03:42 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 225540 kb
Host smart-c27befb5-7ae3-4ca7-a89f-c6ccd50ae8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816553490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.816553490
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1933755719
Short name T492
Test name
Test status
Simulation time 13683568 ps
CPU time 0.79 seconds
Started Jul 03 06:03:45 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 207532 kb
Host smart-ba5ae4b6-9d7b-4ad9-a9cc-bc37db4f5041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933755719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1933755719
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3183485431
Short name T915
Test name
Test status
Simulation time 170454698430 ps
CPU time 347.26 seconds
Started Jul 03 06:03:45 PM PDT 24
Finished Jul 03 06:09:33 PM PDT 24
Peak memory 274800 kb
Host smart-62b44571-8273-4a7f-8737-19eeb0d54e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183485431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3183485431
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3473721574
Short name T344
Test name
Test status
Simulation time 17877349052 ps
CPU time 149.68 seconds
Started Jul 03 06:03:43 PM PDT 24
Finished Jul 03 06:06:13 PM PDT 24
Peak memory 250480 kb
Host smart-eb7449d6-7b57-4b46-875b-ad0bedf8f3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473721574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3473721574
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1750977836
Short name T205
Test name
Test status
Simulation time 2252077484 ps
CPU time 45.77 seconds
Started Jul 03 06:03:47 PM PDT 24
Finished Jul 03 06:04:33 PM PDT 24
Peak memory 239516 kb
Host smart-2e04390f-3ca3-4f71-9913-1d6a48cabbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750977836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1750977836
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.575929608
Short name T688
Test name
Test status
Simulation time 1126009544 ps
CPU time 7.13 seconds
Started Jul 03 06:03:45 PM PDT 24
Finished Jul 03 06:03:52 PM PDT 24
Peak memory 233856 kb
Host smart-b4c82ce5-c0eb-40dd-a440-c65e0b56f9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575929608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.575929608
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2144442593
Short name T322
Test name
Test status
Simulation time 36616184560 ps
CPU time 247.98 seconds
Started Jul 03 06:03:45 PM PDT 24
Finished Jul 03 06:07:53 PM PDT 24
Peak memory 250304 kb
Host smart-cede3fc6-cdd2-4f3c-a9e8-5b490f39e04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144442593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2144442593
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3121374610
Short name T669
Test name
Test status
Simulation time 969418874 ps
CPU time 9.21 seconds
Started Jul 03 06:03:41 PM PDT 24
Finished Jul 03 06:03:51 PM PDT 24
Peak memory 233688 kb
Host smart-2754c727-e440-438a-a469-d78eaedd9a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121374610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3121374610
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2857186100
Short name T802
Test name
Test status
Simulation time 16866399629 ps
CPU time 45.8 seconds
Started Jul 03 06:03:53 PM PDT 24
Finished Jul 03 06:04:40 PM PDT 24
Peak memory 225664 kb
Host smart-e8ecb904-e8b6-48dd-8a65-040e9e182329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857186100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2857186100
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1046369390
Short name T1014
Test name
Test status
Simulation time 155119292 ps
CPU time 2.91 seconds
Started Jul 03 06:03:46 PM PDT 24
Finished Jul 03 06:03:49 PM PDT 24
Peak memory 233744 kb
Host smart-ccd39523-3ece-469b-aef4-70da4c0ed5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046369390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1046369390
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1905798226
Short name T503
Test name
Test status
Simulation time 521821542 ps
CPU time 2.46 seconds
Started Jul 03 06:03:45 PM PDT 24
Finished Jul 03 06:03:48 PM PDT 24
Peak memory 225592 kb
Host smart-e532dd0a-a407-4511-b547-f6cf2f5aa7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905798226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1905798226
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1636012206
Short name T764
Test name
Test status
Simulation time 2664498229 ps
CPU time 7.77 seconds
Started Jul 03 06:03:44 PM PDT 24
Finished Jul 03 06:03:52 PM PDT 24
Peak memory 223536 kb
Host smart-836f5887-282d-47c6-a504-ad57f39c7d10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636012206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1636012206
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3376980256
Short name T933
Test name
Test status
Simulation time 70053362 ps
CPU time 1.27 seconds
Started Jul 03 06:03:48 PM PDT 24
Finished Jul 03 06:03:49 PM PDT 24
Peak memory 207984 kb
Host smart-68b9bd64-4d8a-47e0-bd58-ac5cf0df7b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376980256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3376980256
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1662948015
Short name T477
Test name
Test status
Simulation time 13576598108 ps
CPU time 34.5 seconds
Started Jul 03 06:03:43 PM PDT 24
Finished Jul 03 06:04:18 PM PDT 24
Peak memory 217424 kb
Host smart-fe528488-6e84-4ccf-9384-5f8997fa4fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662948015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1662948015
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1471538167
Short name T620
Test name
Test status
Simulation time 76077591960 ps
CPU time 13.08 seconds
Started Jul 03 06:03:43 PM PDT 24
Finished Jul 03 06:03:57 PM PDT 24
Peak memory 217476 kb
Host smart-3e1d44b2-c443-4169-8a5f-f0d61bccae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471538167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1471538167
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3439376054
Short name T290
Test name
Test status
Simulation time 68045465 ps
CPU time 1.21 seconds
Started Jul 03 06:03:44 PM PDT 24
Finished Jul 03 06:03:45 PM PDT 24
Peak memory 217324 kb
Host smart-251c3bf9-a751-4f6a-8ae9-788683c3e689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439376054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3439376054
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3948074826
Short name T11
Test name
Test status
Simulation time 80278732 ps
CPU time 0.73 seconds
Started Jul 03 06:03:45 PM PDT 24
Finished Jul 03 06:03:46 PM PDT 24
Peak memory 206996 kb
Host smart-c8d527f3-2acb-474c-bd0c-b9393b6c13f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948074826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3948074826
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1427573179
Short name T302
Test name
Test status
Simulation time 497037136 ps
CPU time 5.09 seconds
Started Jul 03 06:03:54 PM PDT 24
Finished Jul 03 06:03:59 PM PDT 24
Peak memory 241292 kb
Host smart-c9b898da-992b-4258-b5b8-932396efec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427573179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1427573179
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1441737824
Short name T877
Test name
Test status
Simulation time 14498654 ps
CPU time 0.71 seconds
Started Jul 03 06:03:53 PM PDT 24
Finished Jul 03 06:03:55 PM PDT 24
Peak memory 205816 kb
Host smart-88507026-6550-4070-90ae-3d5ff29d6361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441737824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1441737824
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3183843668
Short name T742
Test name
Test status
Simulation time 121004425 ps
CPU time 3.25 seconds
Started Jul 03 06:03:50 PM PDT 24
Finished Jul 03 06:03:53 PM PDT 24
Peak memory 233844 kb
Host smart-b3791438-4a61-45e2-82db-2c886bafe4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183843668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3183843668
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3293618300
Short name T909
Test name
Test status
Simulation time 57650443 ps
CPU time 0.78 seconds
Started Jul 03 06:03:54 PM PDT 24
Finished Jul 03 06:03:56 PM PDT 24
Peak memory 207524 kb
Host smart-cf49acf5-2729-4866-80e1-ea9cd2aaeab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293618300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3293618300
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3710961819
Short name T873
Test name
Test status
Simulation time 9561256327 ps
CPU time 50.85 seconds
Started Jul 03 06:03:51 PM PDT 24
Finished Jul 03 06:04:42 PM PDT 24
Peak memory 250332 kb
Host smart-ca8d1e10-a315-4a1d-8404-835af3524cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710961819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3710961819
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1305470166
Short name T438
Test name
Test status
Simulation time 68494174294 ps
CPU time 199.48 seconds
Started Jul 03 06:03:52 PM PDT 24
Finished Jul 03 06:07:12 PM PDT 24
Peak memory 250532 kb
Host smart-b3c252a4-b8d3-4007-a2c0-eae1618e98c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305470166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1305470166
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3280912882
Short name T687
Test name
Test status
Simulation time 18806277649 ps
CPU time 38.83 seconds
Started Jul 03 06:03:51 PM PDT 24
Finished Jul 03 06:04:30 PM PDT 24
Peak memory 257396 kb
Host smart-6b375a5f-011d-4d43-856f-26f32d9e0e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280912882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3280912882
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1005083608
Short name T267
Test name
Test status
Simulation time 439407686 ps
CPU time 8.86 seconds
Started Jul 03 06:03:49 PM PDT 24
Finished Jul 03 06:03:58 PM PDT 24
Peak memory 225612 kb
Host smart-9d5b3f49-61e3-4318-b03c-4af79a32a2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005083608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1005083608
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1739849416
Short name T887
Test name
Test status
Simulation time 15991653226 ps
CPU time 76.29 seconds
Started Jul 03 06:03:53 PM PDT 24
Finished Jul 03 06:05:10 PM PDT 24
Peak memory 250276 kb
Host smart-47b26f1c-8763-402a-9f7a-2a69f8db1afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739849416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1739849416
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1934223773
Short name T471
Test name
Test status
Simulation time 695579102 ps
CPU time 2.92 seconds
Started Jul 03 06:03:55 PM PDT 24
Finished Jul 03 06:03:59 PM PDT 24
Peak memory 233816 kb
Host smart-bfc0ecdb-5a77-467a-86dc-20d8d6594d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934223773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1934223773
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3946619273
Short name T927
Test name
Test status
Simulation time 11186910728 ps
CPU time 17.88 seconds
Started Jul 03 06:03:55 PM PDT 24
Finished Jul 03 06:04:13 PM PDT 24
Peak memory 233900 kb
Host smart-fa31c373-592a-4057-9507-f7bca22a0f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946619273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3946619273
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4262476939
Short name T232
Test name
Test status
Simulation time 4332170579 ps
CPU time 7.26 seconds
Started Jul 03 06:03:47 PM PDT 24
Finished Jul 03 06:03:55 PM PDT 24
Peak memory 225716 kb
Host smart-d1f5d7c2-9887-4000-929a-0be4b2bc7337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262476939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4262476939
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.96627858
Short name T684
Test name
Test status
Simulation time 981971433 ps
CPU time 9.61 seconds
Started Jul 03 06:03:48 PM PDT 24
Finished Jul 03 06:03:58 PM PDT 24
Peak memory 241960 kb
Host smart-3f69e962-a2b7-428d-86e1-c20a65513aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96627858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.96627858
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2376820966
Short name T460
Test name
Test status
Simulation time 4057941189 ps
CPU time 8.88 seconds
Started Jul 03 06:03:53 PM PDT 24
Finished Jul 03 06:04:02 PM PDT 24
Peak memory 224092 kb
Host smart-134c48be-ac99-451b-b217-e36a910eaf9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2376820966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2376820966
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3134249953
Short name T1003
Test name
Test status
Simulation time 5331435856 ps
CPU time 32.69 seconds
Started Jul 03 06:03:54 PM PDT 24
Finished Jul 03 06:04:27 PM PDT 24
Peak memory 242224 kb
Host smart-737f6244-a3c4-481e-bda3-f7be2bc53081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134249953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3134249953
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1757158843
Short name T682
Test name
Test status
Simulation time 2809617701 ps
CPU time 10.48 seconds
Started Jul 03 06:03:49 PM PDT 24
Finished Jul 03 06:04:00 PM PDT 24
Peak memory 217760 kb
Host smart-e483c1f5-710f-48fc-9379-20710d06f8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757158843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1757158843
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4148545631
Short name T711
Test name
Test status
Simulation time 1836056603 ps
CPU time 4.22 seconds
Started Jul 03 06:03:47 PM PDT 24
Finished Jul 03 06:03:51 PM PDT 24
Peak memory 217380 kb
Host smart-7991dad6-fae8-4020-ac4c-1628782c9788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148545631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4148545631
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1942282022
Short name T856
Test name
Test status
Simulation time 15926827 ps
CPU time 0.77 seconds
Started Jul 03 06:03:46 PM PDT 24
Finished Jul 03 06:03:47 PM PDT 24
Peak memory 207028 kb
Host smart-c73631ab-7202-4f06-a407-2da7867a9d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942282022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1942282022
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2604598418
Short name T863
Test name
Test status
Simulation time 84395012 ps
CPU time 0.95 seconds
Started Jul 03 06:03:48 PM PDT 24
Finished Jul 03 06:03:49 PM PDT 24
Peak memory 207472 kb
Host smart-7246915d-7c44-44a6-b332-a8f7bc3a13b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604598418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2604598418
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2890083642
Short name T699
Test name
Test status
Simulation time 350057222 ps
CPU time 4.44 seconds
Started Jul 03 06:03:54 PM PDT 24
Finished Jul 03 06:03:59 PM PDT 24
Peak memory 225596 kb
Host smart-095b7011-f183-4687-a1da-b80d32229337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890083642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2890083642
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1052836846
Short name T61
Test name
Test status
Simulation time 34289178 ps
CPU time 0.7 seconds
Started Jul 03 06:01:16 PM PDT 24
Finished Jul 03 06:01:16 PM PDT 24
Peak memory 206404 kb
Host smart-9ce6120c-b679-45b3-969c-5772f5cb8426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052836846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
052836846
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.708032262
Short name T489
Test name
Test status
Simulation time 2876465983 ps
CPU time 7.43 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:29 PM PDT 24
Peak memory 225636 kb
Host smart-bb7077d1-c110-4d3c-9de9-5f62b4b441e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708032262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.708032262
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1643771536
Short name T360
Test name
Test status
Simulation time 57662370 ps
CPU time 0.79 seconds
Started Jul 03 06:01:06 PM PDT 24
Finished Jul 03 06:01:07 PM PDT 24
Peak memory 207868 kb
Host smart-8990909b-a020-4151-9d02-d7e9af0be25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643771536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1643771536
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2120347107
Short name T846
Test name
Test status
Simulation time 2689246299 ps
CPU time 27.48 seconds
Started Jul 03 06:01:06 PM PDT 24
Finished Jul 03 06:01:34 PM PDT 24
Peak memory 237796 kb
Host smart-eb8a5b0f-9e7b-4769-a73f-94f28f7a80d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120347107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2120347107
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2159690557
Short name T251
Test name
Test status
Simulation time 114666396374 ps
CPU time 70.13 seconds
Started Jul 03 06:01:15 PM PDT 24
Finished Jul 03 06:02:25 PM PDT 24
Peak memory 237888 kb
Host smart-b01fe163-4128-4652-8c84-769a6064d951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159690557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2159690557
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.474644847
Short name T144
Test name
Test status
Simulation time 49529068639 ps
CPU time 76.95 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:02:37 PM PDT 24
Peak memory 250440 kb
Host smart-cdf77a36-ee62-4029-86e7-1140346771dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474644847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
474644847
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.270058529
Short name T336
Test name
Test status
Simulation time 179786567 ps
CPU time 5.02 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 233816 kb
Host smart-173d0241-9f19-431d-9dab-bc5d7dd5b2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270058529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.270058529
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.323848124
Short name T758
Test name
Test status
Simulation time 38757254 ps
CPU time 0.77 seconds
Started Jul 03 06:01:11 PM PDT 24
Finished Jul 03 06:01:12 PM PDT 24
Peak memory 216932 kb
Host smart-456fb94a-a46d-424f-b13d-de5f0e64d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323848124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
323848124
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1247047878
Short name T842
Test name
Test status
Simulation time 218753618 ps
CPU time 3.81 seconds
Started Jul 03 06:01:06 PM PDT 24
Finished Jul 03 06:01:11 PM PDT 24
Peak memory 225512 kb
Host smart-6fa7e9b5-226a-4394-80e3-cd65eaefae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247047878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1247047878
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2642055322
Short name T616
Test name
Test status
Simulation time 1320756172 ps
CPU time 5.33 seconds
Started Jul 03 06:01:04 PM PDT 24
Finished Jul 03 06:01:09 PM PDT 24
Peak memory 233800 kb
Host smart-4cc681d2-87b5-4847-abe5-d5e53a8bbace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642055322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2642055322
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3106534169
Short name T522
Test name
Test status
Simulation time 108051866 ps
CPU time 1.07 seconds
Started Jul 03 06:01:06 PM PDT 24
Finished Jul 03 06:01:08 PM PDT 24
Peak memory 218936 kb
Host smart-928ec12b-3331-4b7b-9ef7-739a40c3ac81
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106534169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3106534169
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3311439712
Short name T857
Test name
Test status
Simulation time 5888452532 ps
CPU time 9.89 seconds
Started Jul 03 06:01:06 PM PDT 24
Finished Jul 03 06:01:16 PM PDT 24
Peak memory 225720 kb
Host smart-65c3802a-13f3-4cff-904e-39efafda24d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311439712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3311439712
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1527134091
Short name T592
Test name
Test status
Simulation time 3987281431 ps
CPU time 14.69 seconds
Started Jul 03 06:01:08 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 241872 kb
Host smart-75a83b59-fd32-4944-890e-333ea86ead11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527134091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1527134091
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2616132688
Short name T149
Test name
Test status
Simulation time 1216262107 ps
CPU time 4.49 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 224296 kb
Host smart-54013dfe-c19c-4453-a1a1-ff2091e63bc8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2616132688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2616132688
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2565993013
Short name T71
Test name
Test status
Simulation time 64309800 ps
CPU time 1.11 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 236804 kb
Host smart-04f59ac6-64df-4c93-947c-150dd3f78ea2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565993013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2565993013
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3999592090
Short name T837
Test name
Test status
Simulation time 56016973 ps
CPU time 0.99 seconds
Started Jul 03 06:01:08 PM PDT 24
Finished Jul 03 06:01:09 PM PDT 24
Peak memory 207656 kb
Host smart-4d2784cc-e698-40f5-acbb-155d43f07a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999592090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3999592090
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3116310669
Short name T760
Test name
Test status
Simulation time 1419985518 ps
CPU time 15.66 seconds
Started Jul 03 06:01:07 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 217356 kb
Host smart-6a395930-4c91-4849-88c7-8bb363295da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116310669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3116310669
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1156610373
Short name T135
Test name
Test status
Simulation time 1890812758 ps
CPU time 2.91 seconds
Started Jul 03 06:01:04 PM PDT 24
Finished Jul 03 06:01:08 PM PDT 24
Peak memory 217192 kb
Host smart-15a5cef6-424d-431c-8ec8-addaf8b90657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156610373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1156610373
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4123426008
Short name T753
Test name
Test status
Simulation time 24739559 ps
CPU time 1.46 seconds
Started Jul 03 06:01:05 PM PDT 24
Finished Jul 03 06:01:06 PM PDT 24
Peak memory 209212 kb
Host smart-92193c4f-d824-451f-a312-8c25b229e298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123426008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4123426008
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2503549817
Short name T495
Test name
Test status
Simulation time 73854326 ps
CPU time 0.88 seconds
Started Jul 03 06:01:10 PM PDT 24
Finished Jul 03 06:01:11 PM PDT 24
Peak memory 206984 kb
Host smart-7fe9ac7c-3f96-40ee-b8dc-0dd92c774c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503549817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2503549817
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3492872713
Short name T961
Test name
Test status
Simulation time 55424925533 ps
CPU time 40.5 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:02:01 PM PDT 24
Peak memory 242004 kb
Host smart-88f86fc9-e0a1-4a5c-9fb8-4c72d0bb4634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492872713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3492872713
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.992856648
Short name T599
Test name
Test status
Simulation time 26282183 ps
CPU time 0.74 seconds
Started Jul 03 06:03:58 PM PDT 24
Finished Jul 03 06:03:59 PM PDT 24
Peak memory 205792 kb
Host smart-5a59b24b-2664-4a2e-a3a2-5a9599ca6b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992856648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.992856648
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2498413717
Short name T847
Test name
Test status
Simulation time 265614166 ps
CPU time 2.76 seconds
Started Jul 03 06:03:59 PM PDT 24
Finished Jul 03 06:04:02 PM PDT 24
Peak memory 225608 kb
Host smart-d04d34ea-850c-4423-a51a-6a03390162c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498413717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2498413717
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.751160600
Short name T774
Test name
Test status
Simulation time 23085552 ps
CPU time 0.74 seconds
Started Jul 03 06:03:53 PM PDT 24
Finished Jul 03 06:03:55 PM PDT 24
Peak memory 206520 kb
Host smart-345ad3f6-69f4-4e61-833a-f2bcc91dbe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751160600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.751160600
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1860953682
Short name T645
Test name
Test status
Simulation time 95775088 ps
CPU time 0.78 seconds
Started Jul 03 06:03:56 PM PDT 24
Finished Jul 03 06:03:57 PM PDT 24
Peak memory 216968 kb
Host smart-ebfce650-e061-4a1b-99b3-643847d45e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860953682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1860953682
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.98244193
Short name T488
Test name
Test status
Simulation time 36523641351 ps
CPU time 81 seconds
Started Jul 03 06:04:00 PM PDT 24
Finished Jul 03 06:05:21 PM PDT 24
Peak memory 233956 kb
Host smart-4a9f269d-9c30-4d28-addd-8fc04288389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98244193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.98244193
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.41040972
Short name T367
Test name
Test status
Simulation time 10785862054 ps
CPU time 29.91 seconds
Started Jul 03 06:03:55 PM PDT 24
Finished Jul 03 06:04:25 PM PDT 24
Peak memory 233836 kb
Host smart-9aee5cb8-fedb-4624-9d8f-480c5cdf6321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41040972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.41040972
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2189708496
Short name T639
Test name
Test status
Simulation time 29847513341 ps
CPU time 56.65 seconds
Started Jul 03 06:03:58 PM PDT 24
Finished Jul 03 06:04:55 PM PDT 24
Peak memory 250272 kb
Host smart-59cdae7d-737a-458b-8933-d16bff43b4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189708496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2189708496
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3705656906
Short name T226
Test name
Test status
Simulation time 752990262 ps
CPU time 3.66 seconds
Started Jul 03 06:03:54 PM PDT 24
Finished Jul 03 06:03:59 PM PDT 24
Peak memory 225544 kb
Host smart-023a823b-4391-45c9-903d-dd8971721c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705656906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3705656906
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3017691312
Short name T841
Test name
Test status
Simulation time 11362867778 ps
CPU time 40.68 seconds
Started Jul 03 06:03:55 PM PDT 24
Finished Jul 03 06:04:36 PM PDT 24
Peak memory 251200 kb
Host smart-3a24f000-cdd1-4e66-9111-bcd49651a98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017691312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3017691312
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3021383367
Short name T875
Test name
Test status
Simulation time 712528576 ps
CPU time 3.85 seconds
Started Jul 03 06:03:56 PM PDT 24
Finished Jul 03 06:04:00 PM PDT 24
Peak memory 225656 kb
Host smart-0d3d6dd8-4a93-46aa-9659-8848c529258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021383367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3021383367
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1332754519
Short name T929
Test name
Test status
Simulation time 8151839099 ps
CPU time 10.34 seconds
Started Jul 03 06:03:57 PM PDT 24
Finished Jul 03 06:04:07 PM PDT 24
Peak memory 238124 kb
Host smart-5d8a79a3-aabc-41e7-80db-0cd02d98a560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332754519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1332754519
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1493718823
Short name T947
Test name
Test status
Simulation time 682313447 ps
CPU time 9.21 seconds
Started Jul 03 06:03:57 PM PDT 24
Finished Jul 03 06:04:06 PM PDT 24
Peak memory 221476 kb
Host smart-733afcca-2cc5-4157-8802-68103b0c9cdc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493718823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1493718823
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3969716464
Short name T472
Test name
Test status
Simulation time 78063631546 ps
CPU time 685.32 seconds
Started Jul 03 06:03:59 PM PDT 24
Finished Jul 03 06:15:25 PM PDT 24
Peak memory 272836 kb
Host smart-747ad2f6-58f5-4a36-bd67-b809cdd2290a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969716464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3969716464
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2736850124
Short name T954
Test name
Test status
Simulation time 4312052660 ps
CPU time 28.24 seconds
Started Jul 03 06:03:53 PM PDT 24
Finished Jul 03 06:04:22 PM PDT 24
Peak memory 217548 kb
Host smart-d4f71a25-0ae7-4c3c-bbce-0eaf93cec171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736850124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2736850124
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.398185534
Short name T310
Test name
Test status
Simulation time 6603427285 ps
CPU time 15.63 seconds
Started Jul 03 06:03:51 PM PDT 24
Finished Jul 03 06:04:07 PM PDT 24
Peak memory 217472 kb
Host smart-9886e14c-db71-454f-b826-d07c66eb6a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398185534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.398185534
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1209452840
Short name T920
Test name
Test status
Simulation time 549221603 ps
CPU time 3.35 seconds
Started Jul 03 06:03:58 PM PDT 24
Finished Jul 03 06:04:02 PM PDT 24
Peak memory 217368 kb
Host smart-4fcf33ac-810f-4de5-8bd9-02b94d8652ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209452840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1209452840
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.636913859
Short name T380
Test name
Test status
Simulation time 95319391 ps
CPU time 0.85 seconds
Started Jul 03 06:03:52 PM PDT 24
Finished Jul 03 06:03:53 PM PDT 24
Peak memory 207036 kb
Host smart-1979fd8e-2cda-4766-a15d-13f14698ddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636913859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.636913859
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1205529387
Short name T229
Test name
Test status
Simulation time 2587988499 ps
CPU time 8.8 seconds
Started Jul 03 06:03:55 PM PDT 24
Finished Jul 03 06:04:05 PM PDT 24
Peak memory 233916 kb
Host smart-999b87b7-ced2-48f3-96b3-62c1e650dd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205529387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1205529387
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3537756112
Short name T559
Test name
Test status
Simulation time 38378009 ps
CPU time 0.74 seconds
Started Jul 03 06:04:05 PM PDT 24
Finished Jul 03 06:04:06 PM PDT 24
Peak memory 205824 kb
Host smart-0cd6bf60-1a42-4791-942a-ec286b00cdc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537756112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3537756112
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1757330776
Short name T657
Test name
Test status
Simulation time 255359220 ps
CPU time 3.65 seconds
Started Jul 03 06:04:01 PM PDT 24
Finished Jul 03 06:04:04 PM PDT 24
Peak memory 233776 kb
Host smart-523b79a1-1fba-4195-9075-f24ee9a633ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757330776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1757330776
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1430493865
Short name T728
Test name
Test status
Simulation time 49319271 ps
CPU time 0.78 seconds
Started Jul 03 06:04:00 PM PDT 24
Finished Jul 03 06:04:02 PM PDT 24
Peak memory 206484 kb
Host smart-2c5244f6-d658-4e3b-839a-39eb422e74c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430493865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1430493865
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3710654944
Short name T686
Test name
Test status
Simulation time 7757491284 ps
CPU time 64.86 seconds
Started Jul 03 06:04:08 PM PDT 24
Finished Jul 03 06:05:13 PM PDT 24
Peak memory 255372 kb
Host smart-603360a8-0563-4970-98fb-9b46e2be51c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710654944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3710654944
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3756529218
Short name T812
Test name
Test status
Simulation time 17811189724 ps
CPU time 202.84 seconds
Started Jul 03 06:04:03 PM PDT 24
Finished Jul 03 06:07:26 PM PDT 24
Peak memory 253928 kb
Host smart-91bce474-f6e5-405c-b507-a6cfec3e4f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756529218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3756529218
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1714487071
Short name T184
Test name
Test status
Simulation time 34579015720 ps
CPU time 330.71 seconds
Started Jul 03 06:04:03 PM PDT 24
Finished Jul 03 06:09:34 PM PDT 24
Peak memory 258564 kb
Host smart-d425fc55-7635-4a53-8c6a-fff8dbead452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714487071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1714487071
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2015669371
Short name T308
Test name
Test status
Simulation time 42625408 ps
CPU time 2.57 seconds
Started Jul 03 06:04:04 PM PDT 24
Finished Jul 03 06:04:06 PM PDT 24
Peak memory 225536 kb
Host smart-18c90904-ac05-4878-a7c4-0e670149689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015669371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2015669371
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.159229785
Short name T652
Test name
Test status
Simulation time 14444356561 ps
CPU time 155.45 seconds
Started Jul 03 06:04:08 PM PDT 24
Finished Jul 03 06:06:43 PM PDT 24
Peak memory 257292 kb
Host smart-795edf08-c5a2-40b6-b6c4-4255cfabeba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159229785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.159229785
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1201491776
Short name T943
Test name
Test status
Simulation time 2071608440 ps
CPU time 10.79 seconds
Started Jul 03 06:04:01 PM PDT 24
Finished Jul 03 06:04:12 PM PDT 24
Peak memory 233768 kb
Host smart-1bfcc926-0e4c-445e-9879-bdc0300cc3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201491776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1201491776
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.680773634
Short name T368
Test name
Test status
Simulation time 1600437832 ps
CPU time 5.51 seconds
Started Jul 03 06:04:02 PM PDT 24
Finished Jul 03 06:04:07 PM PDT 24
Peak memory 233784 kb
Host smart-dd978c3d-9fa0-4602-b2dd-6fbe9f8138d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680773634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.680773634
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3502609902
Short name T233
Test name
Test status
Simulation time 971990903 ps
CPU time 3.69 seconds
Started Jul 03 06:03:58 PM PDT 24
Finished Jul 03 06:04:02 PM PDT 24
Peak memory 225532 kb
Host smart-1aa75dc2-707e-4ffd-9885-d36043db0bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502609902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3502609902
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3428722563
Short name T569
Test name
Test status
Simulation time 2436978118 ps
CPU time 6.85 seconds
Started Jul 03 06:04:00 PM PDT 24
Finished Jul 03 06:04:07 PM PDT 24
Peak memory 225724 kb
Host smart-505abf28-d8d2-4cba-8c58-0b0a7655f52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428722563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3428722563
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2454487463
Short name T680
Test name
Test status
Simulation time 241798289 ps
CPU time 5.69 seconds
Started Jul 03 06:04:07 PM PDT 24
Finished Jul 03 06:04:13 PM PDT 24
Peak memory 224096 kb
Host smart-d84c961e-3816-4e43-a98b-1f925440a27d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454487463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2454487463
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.969067877
Short name T77
Test name
Test status
Simulation time 46048010676 ps
CPU time 358.93 seconds
Started Jul 03 06:04:03 PM PDT 24
Finished Jul 03 06:10:02 PM PDT 24
Peak memory 267652 kb
Host smart-8c65b03d-3863-4b9c-ba7f-573ccbaf3ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969067877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.969067877
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2125959449
Short name T27
Test name
Test status
Simulation time 3493493398 ps
CPU time 35.99 seconds
Started Jul 03 06:04:04 PM PDT 24
Finished Jul 03 06:04:40 PM PDT 24
Peak memory 217736 kb
Host smart-6014c48e-f102-459a-99b7-ea092d6b7256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125959449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2125959449
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.996640447
Short name T997
Test name
Test status
Simulation time 5785662802 ps
CPU time 16.02 seconds
Started Jul 03 06:04:00 PM PDT 24
Finished Jul 03 06:04:16 PM PDT 24
Peak memory 217480 kb
Host smart-aed11260-ded3-4a5d-a9e1-94922f8edcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996640447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.996640447
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2094946626
Short name T28
Test name
Test status
Simulation time 466140106 ps
CPU time 2 seconds
Started Jul 03 06:03:59 PM PDT 24
Finished Jul 03 06:04:01 PM PDT 24
Peak memory 217420 kb
Host smart-4f9584cd-9eea-4df0-99bb-e35a6975806a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094946626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2094946626
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1925063312
Short name T626
Test name
Test status
Simulation time 41344728 ps
CPU time 0.82 seconds
Started Jul 03 06:03:57 PM PDT 24
Finished Jul 03 06:03:58 PM PDT 24
Peak memory 207044 kb
Host smart-5ca5a21f-f1d6-4d3f-b101-92d21304e36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925063312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1925063312
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1926859235
Short name T215
Test name
Test status
Simulation time 8530387802 ps
CPU time 8.81 seconds
Started Jul 03 06:04:00 PM PDT 24
Finished Jul 03 06:04:09 PM PDT 24
Peak memory 225604 kb
Host smart-8bbb82fb-5d65-4098-bfd7-a2127144c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926859235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1926859235
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1244398239
Short name T346
Test name
Test status
Simulation time 23795114 ps
CPU time 0.67 seconds
Started Jul 03 06:04:05 PM PDT 24
Finished Jul 03 06:04:05 PM PDT 24
Peak memory 206596 kb
Host smart-75b7396e-afa2-4548-9abe-238a580fe10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244398239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1244398239
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2160163905
Short name T852
Test name
Test status
Simulation time 114115430 ps
CPU time 2.97 seconds
Started Jul 03 06:04:10 PM PDT 24
Finished Jul 03 06:04:13 PM PDT 24
Peak memory 225592 kb
Host smart-a336d5d6-8022-4f02-b585-fd57a37d29a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160163905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2160163905
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3655759096
Short name T679
Test name
Test status
Simulation time 65306749 ps
CPU time 0.8 seconds
Started Jul 03 06:04:03 PM PDT 24
Finished Jul 03 06:04:04 PM PDT 24
Peak memory 207564 kb
Host smart-f04d94cd-0ddd-4935-a083-b75fb5a7e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655759096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3655759096
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4262354524
Short name T266
Test name
Test status
Simulation time 49408692273 ps
CPU time 98.38 seconds
Started Jul 03 06:04:09 PM PDT 24
Finished Jul 03 06:05:47 PM PDT 24
Peak memory 242068 kb
Host smart-06975b3e-a3d9-4278-8208-92b57ba5a500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262354524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4262354524
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2755413675
Short name T264
Test name
Test status
Simulation time 146765391434 ps
CPU time 364.91 seconds
Started Jul 03 06:04:08 PM PDT 24
Finished Jul 03 06:10:13 PM PDT 24
Peak memory 266368 kb
Host smart-90a4778f-aa3f-42d0-bbfe-883e8e159041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755413675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2755413675
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3654920134
Short name T608
Test name
Test status
Simulation time 10273230342 ps
CPU time 22.77 seconds
Started Jul 03 06:04:09 PM PDT 24
Finished Jul 03 06:04:32 PM PDT 24
Peak memory 238792 kb
Host smart-ed195a54-3b98-4253-84d0-3ff4b4dce027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654920134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3654920134
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1702126452
Short name T74
Test name
Test status
Simulation time 1673336637 ps
CPU time 5.37 seconds
Started Jul 03 06:04:08 PM PDT 24
Finished Jul 03 06:04:14 PM PDT 24
Peak memory 242000 kb
Host smart-2bcbf8ef-5ec8-456f-b6b2-4b3af130daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702126452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1702126452
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.290473459
Short name T458
Test name
Test status
Simulation time 660065351 ps
CPU time 10.26 seconds
Started Jul 03 06:04:01 PM PDT 24
Finished Jul 03 06:04:12 PM PDT 24
Peak memory 233864 kb
Host smart-392456be-f212-4847-a30e-1a3711bc69ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290473459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.290473459
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.586147849
Short name T739
Test name
Test status
Simulation time 1011313009 ps
CPU time 13.9 seconds
Started Jul 03 06:04:05 PM PDT 24
Finished Jul 03 06:04:19 PM PDT 24
Peak memory 233844 kb
Host smart-38460570-114f-4d41-8b4a-90e9bb82b0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586147849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.586147849
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2771197934
Short name T605
Test name
Test status
Simulation time 812726334 ps
CPU time 4.85 seconds
Started Jul 03 06:04:04 PM PDT 24
Finished Jul 03 06:04:09 PM PDT 24
Peak memory 241600 kb
Host smart-3da92b46-2c94-432e-b881-1672c0510663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771197934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2771197934
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.303311927
Short name T666
Test name
Test status
Simulation time 9529708576 ps
CPU time 7.78 seconds
Started Jul 03 06:04:04 PM PDT 24
Finished Jul 03 06:04:12 PM PDT 24
Peak memory 233888 kb
Host smart-8d09d1d1-d73f-4e86-b8bf-802ca0f3b6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303311927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.303311927
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3882429036
Short name T484
Test name
Test status
Simulation time 185126165 ps
CPU time 3.51 seconds
Started Jul 03 06:04:10 PM PDT 24
Finished Jul 03 06:04:14 PM PDT 24
Peak memory 219904 kb
Host smart-315c36da-1dea-4ea9-89ea-ee681e6d17ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3882429036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3882429036
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2116926461
Short name T865
Test name
Test status
Simulation time 17884469381 ps
CPU time 184.64 seconds
Started Jul 03 06:04:09 PM PDT 24
Finished Jul 03 06:07:14 PM PDT 24
Peak memory 250372 kb
Host smart-5b13d7e7-2f32-4ed8-b361-bfd5b4312971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116926461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2116926461
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.564518854
Short name T51
Test name
Test status
Simulation time 1800118731 ps
CPU time 12.32 seconds
Started Jul 03 06:04:02 PM PDT 24
Finished Jul 03 06:04:15 PM PDT 24
Peak memory 217384 kb
Host smart-bdc3b5c4-a57b-45de-964a-874557ba4011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564518854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.564518854
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2155030605
Short name T352
Test name
Test status
Simulation time 7927767800 ps
CPU time 12.86 seconds
Started Jul 03 06:04:02 PM PDT 24
Finished Jul 03 06:04:15 PM PDT 24
Peak memory 217448 kb
Host smart-26ccda62-06ff-494a-9754-10b96ef2cb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155030605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2155030605
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3502956619
Short name T514
Test name
Test status
Simulation time 28561082 ps
CPU time 0.79 seconds
Started Jul 03 06:04:03 PM PDT 24
Finished Jul 03 06:04:04 PM PDT 24
Peak memory 206584 kb
Host smart-09c33efe-a050-4fdf-b910-5393a5a39d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502956619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3502956619
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.216488404
Short name T629
Test name
Test status
Simulation time 104216107 ps
CPU time 0.77 seconds
Started Jul 03 06:04:05 PM PDT 24
Finished Jul 03 06:04:06 PM PDT 24
Peak memory 206960 kb
Host smart-9310a744-7135-4728-8e7d-667f47f2f39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216488404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.216488404
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1233659350
Short name T896
Test name
Test status
Simulation time 37576710 ps
CPU time 2.36 seconds
Started Jul 03 06:04:09 PM PDT 24
Finished Jul 03 06:04:11 PM PDT 24
Peak memory 233472 kb
Host smart-36513242-5769-4059-a955-6fc00010e5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233659350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1233659350
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3263584696
Short name T404
Test name
Test status
Simulation time 28894333 ps
CPU time 0.79 seconds
Started Jul 03 06:04:11 PM PDT 24
Finished Jul 03 06:04:12 PM PDT 24
Peak memory 206328 kb
Host smart-caae8c39-38f9-42d4-b043-8615708a02f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263584696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3263584696
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1212085330
Short name T221
Test name
Test status
Simulation time 1372805644 ps
CPU time 6.12 seconds
Started Jul 03 06:04:08 PM PDT 24
Finished Jul 03 06:04:14 PM PDT 24
Peak memory 225632 kb
Host smart-6cb533df-7a7a-45d3-9fbc-98bf28f25c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212085330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1212085330
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3819180543
Short name T988
Test name
Test status
Simulation time 31756931 ps
CPU time 0.82 seconds
Started Jul 03 06:04:09 PM PDT 24
Finished Jul 03 06:04:10 PM PDT 24
Peak memory 206540 kb
Host smart-b32d6aad-7a8f-4957-9129-9ad06eb69233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819180543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3819180543
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2427091493
Short name T201
Test name
Test status
Simulation time 48807266677 ps
CPU time 277.2 seconds
Started Jul 03 06:04:12 PM PDT 24
Finished Jul 03 06:08:49 PM PDT 24
Peak memory 266880 kb
Host smart-0ce0ebb5-f231-48cc-a273-477363efb9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427091493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2427091493
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1033939594
Short name T932
Test name
Test status
Simulation time 8615037473 ps
CPU time 72.06 seconds
Started Jul 03 06:04:10 PM PDT 24
Finished Jul 03 06:05:22 PM PDT 24
Peak memory 223572 kb
Host smart-480e6277-7ef3-42a4-9c84-f3862ec051b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033939594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1033939594
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2264609775
Short name T140
Test name
Test status
Simulation time 18702841591 ps
CPU time 77.56 seconds
Started Jul 03 06:04:13 PM PDT 24
Finished Jul 03 06:05:31 PM PDT 24
Peak memory 250460 kb
Host smart-c540138f-9bc1-410d-9494-4d0037f4919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264609775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2264609775
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2791186522
Short name T153
Test name
Test status
Simulation time 223017779 ps
CPU time 7.68 seconds
Started Jul 03 06:04:11 PM PDT 24
Finished Jul 03 06:04:19 PM PDT 24
Peak memory 239048 kb
Host smart-d6fc5e0e-5488-4381-a20c-883774e7734b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791186522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2791186522
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3847879577
Short name T951
Test name
Test status
Simulation time 90670770880 ps
CPU time 296.46 seconds
Started Jul 03 06:04:11 PM PDT 24
Finished Jul 03 06:09:08 PM PDT 24
Peak memory 258112 kb
Host smart-764d787e-c35b-4a35-9061-710eb85c8bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847879577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3847879577
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2271225213
Short name T756
Test name
Test status
Simulation time 657727290 ps
CPU time 9.26 seconds
Started Jul 03 06:04:13 PM PDT 24
Finished Jul 03 06:04:22 PM PDT 24
Peak memory 233832 kb
Host smart-3e9f1426-02e0-4ece-9ead-3c8d41b3147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271225213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2271225213
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2196282541
Short name T44
Test name
Test status
Simulation time 55570996725 ps
CPU time 137.21 seconds
Started Jul 03 06:04:12 PM PDT 24
Finished Jul 03 06:06:30 PM PDT 24
Peak memory 233956 kb
Host smart-cde503d8-8cf3-4ffc-af48-6128f860432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196282541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2196282541
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1936991963
Short name T1008
Test name
Test status
Simulation time 98554996 ps
CPU time 2.67 seconds
Started Jul 03 06:04:12 PM PDT 24
Finished Jul 03 06:04:15 PM PDT 24
Peak memory 225628 kb
Host smart-a951e09a-0b19-4fee-a264-133d8f0b065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936991963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1936991963
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1528444819
Short name T570
Test name
Test status
Simulation time 849796829 ps
CPU time 6.85 seconds
Started Jul 03 06:04:12 PM PDT 24
Finished Jul 03 06:04:20 PM PDT 24
Peak memory 225608 kb
Host smart-c204026b-7be7-47a7-9232-478388202015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528444819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1528444819
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.351192689
Short name T353
Test name
Test status
Simulation time 987840875 ps
CPU time 11.57 seconds
Started Jul 03 06:04:11 PM PDT 24
Finished Jul 03 06:04:23 PM PDT 24
Peak memory 219988 kb
Host smart-1aeead63-e5e5-4ff1-9755-f24ccd901b36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=351192689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.351192689
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2389597172
Short name T17
Test name
Test status
Simulation time 169894085 ps
CPU time 0.99 seconds
Started Jul 03 06:04:11 PM PDT 24
Finished Jul 03 06:04:13 PM PDT 24
Peak memory 207488 kb
Host smart-e49ad93e-bd1a-42ef-9471-f54295c6146a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389597172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2389597172
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3551853617
Short name T359
Test name
Test status
Simulation time 6693267930 ps
CPU time 10.46 seconds
Started Jul 03 06:04:07 PM PDT 24
Finished Jul 03 06:04:18 PM PDT 24
Peak memory 217524 kb
Host smart-14abc68b-09fa-4ac6-b222-9d4f32b06ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551853617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3551853617
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2982945790
Short name T449
Test name
Test status
Simulation time 901449168 ps
CPU time 5.55 seconds
Started Jul 03 06:04:09 PM PDT 24
Finished Jul 03 06:04:15 PM PDT 24
Peak memory 217340 kb
Host smart-6ed7bf82-79c1-4a5f-80b0-02eb1d636f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982945790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2982945790
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2175809795
Short name T427
Test name
Test status
Simulation time 11236674 ps
CPU time 0.71 seconds
Started Jul 03 06:04:13 PM PDT 24
Finished Jul 03 06:04:14 PM PDT 24
Peak memory 206600 kb
Host smart-76546f35-3317-4922-a674-ed3b267c58a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175809795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2175809795
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1121926561
Short name T621
Test name
Test status
Simulation time 66407618 ps
CPU time 0.88 seconds
Started Jul 03 06:04:12 PM PDT 24
Finished Jul 03 06:04:13 PM PDT 24
Peak memory 206964 kb
Host smart-a71f8850-9e6d-4834-b837-c83d38b294dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121926561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1121926561
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3409780419
Short name T659
Test name
Test status
Simulation time 10899838203 ps
CPU time 32.48 seconds
Started Jul 03 06:04:11 PM PDT 24
Finished Jul 03 06:04:44 PM PDT 24
Peak memory 225692 kb
Host smart-6c8e8c12-22a8-4df8-88a7-a13995cddb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409780419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3409780419
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.381626295
Short name T991
Test name
Test status
Simulation time 11557833 ps
CPU time 0.72 seconds
Started Jul 03 06:04:16 PM PDT 24
Finished Jul 03 06:04:17 PM PDT 24
Peak memory 205808 kb
Host smart-49d66a0c-2676-495c-babd-bd6c7a3ec760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381626295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.381626295
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3585447221
Short name T573
Test name
Test status
Simulation time 6669507349 ps
CPU time 17.67 seconds
Started Jul 03 06:04:15 PM PDT 24
Finished Jul 03 06:04:33 PM PDT 24
Peak memory 233916 kb
Host smart-355db384-ab1c-49fb-b147-b13a4a76fc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585447221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3585447221
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4129208262
Short name T313
Test name
Test status
Simulation time 15262854 ps
CPU time 0.77 seconds
Started Jul 03 06:04:12 PM PDT 24
Finished Jul 03 06:04:13 PM PDT 24
Peak memory 207788 kb
Host smart-5e7298db-0bfc-4adf-9b55-dc8a62e7eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129208262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4129208262
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1947887437
Short name T241
Test name
Test status
Simulation time 1471627933 ps
CPU time 33.9 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:53 PM PDT 24
Peak memory 250876 kb
Host smart-6d9a0800-8d16-47c8-aa42-7581735d9c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947887437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1947887437
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.717926944
Short name T250
Test name
Test status
Simulation time 41090104685 ps
CPU time 182.51 seconds
Started Jul 03 06:04:16 PM PDT 24
Finished Jul 03 06:07:19 PM PDT 24
Peak memory 253544 kb
Host smart-4423282f-1440-412f-b627-ca4cccd9a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717926944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.717926944
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3697469186
Short name T971
Test name
Test status
Simulation time 96987360793 ps
CPU time 35.04 seconds
Started Jul 03 06:04:14 PM PDT 24
Finished Jul 03 06:04:49 PM PDT 24
Peak memory 218820 kb
Host smart-308bcc4d-51c6-45da-a90b-4797d34875da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697469186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3697469186
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1296243246
Short name T496
Test name
Test status
Simulation time 409179506 ps
CPU time 6.76 seconds
Started Jul 03 06:04:17 PM PDT 24
Finished Jul 03 06:04:24 PM PDT 24
Peak memory 225612 kb
Host smart-af329d69-776a-4914-aae2-bcbb7886db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296243246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1296243246
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3681527428
Short name T782
Test name
Test status
Simulation time 117163093 ps
CPU time 0.8 seconds
Started Jul 03 06:04:15 PM PDT 24
Finished Jul 03 06:04:16 PM PDT 24
Peak memory 217192 kb
Host smart-cb9b3df4-adeb-4ed6-b8e6-2217f5d5d75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681527428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3681527428
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3459425052
Short name T922
Test name
Test status
Simulation time 1862534441 ps
CPU time 14.78 seconds
Started Jul 03 06:04:14 PM PDT 24
Finished Jul 03 06:04:29 PM PDT 24
Peak memory 233748 kb
Host smart-afebe1cf-ff74-45f2-82f5-f6547d926f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459425052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3459425052
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2348577216
Short name T913
Test name
Test status
Simulation time 993564812 ps
CPU time 11.04 seconds
Started Jul 03 06:04:18 PM PDT 24
Finished Jul 03 06:04:29 PM PDT 24
Peak memory 233820 kb
Host smart-476f3f1a-b521-478a-b7bc-f60b729af22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348577216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2348577216
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.116322373
Short name T543
Test name
Test status
Simulation time 848319557 ps
CPU time 4.41 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:23 PM PDT 24
Peak memory 233764 kb
Host smart-6be63396-d0bb-44e4-a609-18daa44f3cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116322373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.116322373
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1608178345
Short name T583
Test name
Test status
Simulation time 6521599185 ps
CPU time 7.52 seconds
Started Jul 03 06:04:15 PM PDT 24
Finished Jul 03 06:04:23 PM PDT 24
Peak memory 225672 kb
Host smart-fc5b994d-308c-422e-b4b3-038ea2eb76bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608178345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1608178345
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1843410395
Short name T518
Test name
Test status
Simulation time 279117770 ps
CPU time 3.37 seconds
Started Jul 03 06:04:18 PM PDT 24
Finished Jul 03 06:04:22 PM PDT 24
Peak memory 219988 kb
Host smart-82b2543c-9cd6-4e96-8ee3-4d2d2f8fa7f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1843410395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1843410395
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4002411266
Short name T744
Test name
Test status
Simulation time 22969816742 ps
CPU time 43.31 seconds
Started Jul 03 06:04:15 PM PDT 24
Finished Jul 03 06:04:58 PM PDT 24
Peak memory 242124 kb
Host smart-a4c35963-f62b-4023-8f99-94a02fd03118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002411266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4002411266
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3172476711
Short name T904
Test name
Test status
Simulation time 16485829973 ps
CPU time 20 seconds
Started Jul 03 06:04:18 PM PDT 24
Finished Jul 03 06:04:38 PM PDT 24
Peak memory 217532 kb
Host smart-7660f56f-e7bc-4992-8458-848fac89e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172476711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3172476711
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1810812965
Short name T855
Test name
Test status
Simulation time 3746888475 ps
CPU time 5.63 seconds
Started Jul 03 06:04:16 PM PDT 24
Finished Jul 03 06:04:22 PM PDT 24
Peak memory 217560 kb
Host smart-2eef5e98-1ec7-4519-a423-1967c80f2b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810812965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1810812965
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2042923683
Short name T1005
Test name
Test status
Simulation time 165920509 ps
CPU time 1.31 seconds
Started Jul 03 06:04:18 PM PDT 24
Finished Jul 03 06:04:20 PM PDT 24
Peak memory 209180 kb
Host smart-aefb87ec-a72a-4fbb-90cc-364914bd6155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042923683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2042923683
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.696204777
Short name T284
Test name
Test status
Simulation time 36234942 ps
CPU time 0.83 seconds
Started Jul 03 06:04:15 PM PDT 24
Finished Jul 03 06:04:16 PM PDT 24
Peak memory 206956 kb
Host smart-17a97088-ffe0-4eba-8f3d-8cf277413627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696204777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.696204777
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.320323355
Short name T889
Test name
Test status
Simulation time 59657234 ps
CPU time 2.57 seconds
Started Jul 03 06:04:14 PM PDT 24
Finished Jul 03 06:04:17 PM PDT 24
Peak memory 233532 kb
Host smart-b25a0a04-82b9-4251-a47d-4d35a2c6e4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320323355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.320323355
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1073577443
Short name T891
Test name
Test status
Simulation time 42046155 ps
CPU time 0.73 seconds
Started Jul 03 06:04:23 PM PDT 24
Finished Jul 03 06:04:24 PM PDT 24
Peak memory 206392 kb
Host smart-0d1f59b6-a970-4ec5-bfb5-e147b85e9af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073577443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1073577443
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1971158055
Short name T227
Test name
Test status
Simulation time 516550027 ps
CPU time 3.61 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:24 PM PDT 24
Peak memory 233804 kb
Host smart-19ffbd62-eeff-491d-9f07-dc7d78a59a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971158055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1971158055
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3055235085
Short name T617
Test name
Test status
Simulation time 134021024 ps
CPU time 0.73 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:20 PM PDT 24
Peak memory 206488 kb
Host smart-33e07d53-3417-4d65-98d6-e03757d705ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055235085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3055235085
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3802539825
Short name T25
Test name
Test status
Simulation time 1045448495 ps
CPU time 3.96 seconds
Started Jul 03 06:04:22 PM PDT 24
Finished Jul 03 06:04:26 PM PDT 24
Peak memory 218676 kb
Host smart-5ba71744-3008-4795-b268-f2ac70716364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802539825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3802539825
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3622652353
Short name T410
Test name
Test status
Simulation time 384951863 ps
CPU time 5.62 seconds
Started Jul 03 06:04:22 PM PDT 24
Finished Jul 03 06:04:27 PM PDT 24
Peak memory 218752 kb
Host smart-eda08c4f-11f6-4037-91eb-692c330ad22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622652353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3622652353
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2164242263
Short name T952
Test name
Test status
Simulation time 4080576901 ps
CPU time 8.17 seconds
Started Jul 03 06:04:20 PM PDT 24
Finished Jul 03 06:04:28 PM PDT 24
Peak memory 233904 kb
Host smart-26535e04-a261-408c-a952-f91abb3e5ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164242263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2164242263
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1421213622
Short name T181
Test name
Test status
Simulation time 77200481289 ps
CPU time 282.49 seconds
Started Jul 03 06:04:20 PM PDT 24
Finished Jul 03 06:09:03 PM PDT 24
Peak memory 263600 kb
Host smart-acf056d1-4ba0-47e7-af98-0e080d1ed3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421213622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1421213622
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1987428563
Short name T671
Test name
Test status
Simulation time 5409431504 ps
CPU time 25.38 seconds
Started Jul 03 06:04:20 PM PDT 24
Finished Jul 03 06:04:46 PM PDT 24
Peak memory 233940 kb
Host smart-b53a7a2f-458d-48a8-8cda-92ef4ca7e155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987428563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1987428563
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3744983946
Short name T743
Test name
Test status
Simulation time 568151295 ps
CPU time 9 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:29 PM PDT 24
Peak memory 241200 kb
Host smart-397d5666-80b4-40d0-bf07-8111e6af601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744983946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3744983946
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1648376831
Short name T419
Test name
Test status
Simulation time 800832851 ps
CPU time 4.73 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:24 PM PDT 24
Peak memory 241600 kb
Host smart-5dcc3410-7f6c-4f57-95d5-ef2837869688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648376831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1648376831
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4193359211
Short name T46
Test name
Test status
Simulation time 4593229190 ps
CPU time 4.24 seconds
Started Jul 03 06:04:21 PM PDT 24
Finished Jul 03 06:04:25 PM PDT 24
Peak memory 233864 kb
Host smart-b7367d76-2285-4e0d-989f-4811e58fd7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193359211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4193359211
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1329339379
Short name T603
Test name
Test status
Simulation time 329003801 ps
CPU time 4.54 seconds
Started Jul 03 06:04:20 PM PDT 24
Finished Jul 03 06:04:25 PM PDT 24
Peak memory 224156 kb
Host smart-e0f457d7-ddef-49e3-90b8-a7478f15f4f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1329339379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1329339379
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2596173933
Short name T55
Test name
Test status
Simulation time 56671950538 ps
CPU time 150.45 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:06:50 PM PDT 24
Peak memory 250376 kb
Host smart-2aa65bf5-0487-4b98-92b7-38312dca1efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596173933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2596173933
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1850337676
Short name T81
Test name
Test status
Simulation time 2339076992 ps
CPU time 17.93 seconds
Started Jul 03 06:04:15 PM PDT 24
Finished Jul 03 06:04:33 PM PDT 24
Peak memory 217500 kb
Host smart-1a46d47d-3d95-442a-b67b-6ce26350c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850337676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1850337676
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1177485934
Short name T293
Test name
Test status
Simulation time 8065825863 ps
CPU time 9.42 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:29 PM PDT 24
Peak memory 217452 kb
Host smart-9080797e-8381-4c80-89cb-e60166870118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177485934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1177485934
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3603227519
Short name T525
Test name
Test status
Simulation time 123115024 ps
CPU time 2.19 seconds
Started Jul 03 06:04:16 PM PDT 24
Finished Jul 03 06:04:18 PM PDT 24
Peak memory 217368 kb
Host smart-46785e67-7090-4d40-b1c0-91ba2f39ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603227519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3603227519
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2863407378
Short name T571
Test name
Test status
Simulation time 117249066 ps
CPU time 0.83 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:21 PM PDT 24
Peak memory 208020 kb
Host smart-96f34bbf-0ad7-4561-a0c3-2a63ccdb56bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863407378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2863407378
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3656368634
Short name T623
Test name
Test status
Simulation time 17226049084 ps
CPU time 23.73 seconds
Started Jul 03 06:04:19 PM PDT 24
Finished Jul 03 06:04:43 PM PDT 24
Peak memory 233888 kb
Host smart-5170fde4-e09e-4fdf-a290-25603a13820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656368634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3656368634
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2039882034
Short name T638
Test name
Test status
Simulation time 41174257 ps
CPU time 0.71 seconds
Started Jul 03 06:04:27 PM PDT 24
Finished Jul 03 06:04:28 PM PDT 24
Peak memory 206316 kb
Host smart-19a5f207-62e1-4d6e-8895-515d7987692c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039882034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2039882034
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1565649040
Short name T347
Test name
Test status
Simulation time 700521514 ps
CPU time 4.03 seconds
Started Jul 03 06:04:23 PM PDT 24
Finished Jul 03 06:04:28 PM PDT 24
Peak memory 225544 kb
Host smart-d1f7b63d-2caf-4254-8979-fa597a2da926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565649040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1565649040
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1437422978
Short name T527
Test name
Test status
Simulation time 25965900 ps
CPU time 0.79 seconds
Started Jul 03 06:04:23 PM PDT 24
Finished Jul 03 06:04:24 PM PDT 24
Peak memory 207876 kb
Host smart-14591c9a-243e-4b4b-b55d-269a65d3bb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437422978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1437422978
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3844341535
Short name T189
Test name
Test status
Simulation time 212970377824 ps
CPU time 393.24 seconds
Started Jul 03 06:04:27 PM PDT 24
Finished Jul 03 06:11:01 PM PDT 24
Peak memory 257240 kb
Host smart-51698ded-450f-4f33-9236-870686c1cbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844341535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3844341535
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1177491827
Short name T1009
Test name
Test status
Simulation time 57368016936 ps
CPU time 70.7 seconds
Started Jul 03 06:04:25 PM PDT 24
Finished Jul 03 06:05:36 PM PDT 24
Peak memory 258528 kb
Host smart-5c246b8d-ca15-420c-a941-26b5d402ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177491827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1177491827
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3224638788
Short name T921
Test name
Test status
Simulation time 38359890972 ps
CPU time 95.84 seconds
Started Jul 03 06:04:25 PM PDT 24
Finished Jul 03 06:06:01 PM PDT 24
Peak memory 239044 kb
Host smart-d16dcec8-51cb-4ea9-b7f5-8b17402fc1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224638788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3224638788
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.381140452
Short name T1031
Test name
Test status
Simulation time 162042430 ps
CPU time 6.55 seconds
Started Jul 03 06:04:23 PM PDT 24
Finished Jul 03 06:04:30 PM PDT 24
Peak memory 225628 kb
Host smart-ae594eba-bf87-441f-9caa-98af9c47ff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381140452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.381140452
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2779931585
Short name T139
Test name
Test status
Simulation time 13735786987 ps
CPU time 97.29 seconds
Started Jul 03 06:04:26 PM PDT 24
Finished Jul 03 06:06:04 PM PDT 24
Peak memory 252416 kb
Host smart-c572244b-643f-4f67-a9a9-c7843822ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779931585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2779931585
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.583323609
Short name T729
Test name
Test status
Simulation time 199211043 ps
CPU time 2.72 seconds
Started Jul 03 06:04:23 PM PDT 24
Finished Jul 03 06:04:26 PM PDT 24
Peak memory 233792 kb
Host smart-7189f46a-9d13-4c1e-9f8b-1ea0106999b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583323609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.583323609
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2779395910
Short name T500
Test name
Test status
Simulation time 2701022325 ps
CPU time 20.03 seconds
Started Jul 03 06:04:25 PM PDT 24
Finished Jul 03 06:04:45 PM PDT 24
Peak memory 240408 kb
Host smart-588d2ec2-5934-4498-b026-87dc992962d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779395910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2779395910
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4172846193
Short name T643
Test name
Test status
Simulation time 321698832 ps
CPU time 5.66 seconds
Started Jul 03 06:04:25 PM PDT 24
Finished Jul 03 06:04:31 PM PDT 24
Peak memory 240752 kb
Host smart-f41ed941-cbe8-4d99-b1c6-36d5b9201757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172846193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.4172846193
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2466500631
Short name T955
Test name
Test status
Simulation time 4538095103 ps
CPU time 8.89 seconds
Started Jul 03 06:04:20 PM PDT 24
Finished Jul 03 06:04:30 PM PDT 24
Peak memory 233900 kb
Host smart-419cf16b-18bc-4f9d-94ec-42b1a46f01d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466500631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2466500631
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1549030724
Short name T154
Test name
Test status
Simulation time 506415823 ps
CPU time 4.74 seconds
Started Jul 03 06:04:28 PM PDT 24
Finished Jul 03 06:04:33 PM PDT 24
Peak memory 223576 kb
Host smart-ef7599fa-86e5-43a9-9831-deb69608ba92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1549030724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1549030724
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3644860041
Short name T709
Test name
Test status
Simulation time 2594760945 ps
CPU time 8.61 seconds
Started Jul 03 06:04:20 PM PDT 24
Finished Jul 03 06:04:29 PM PDT 24
Peak memory 217392 kb
Host smart-deb71fd7-fb64-4f75-9db9-44731e8fc7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644860041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3644860041
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3041317463
Short name T759
Test name
Test status
Simulation time 1034780395 ps
CPU time 3.99 seconds
Started Jul 03 06:04:22 PM PDT 24
Finished Jul 03 06:04:26 PM PDT 24
Peak memory 217304 kb
Host smart-5c62f913-059c-4bd6-92de-71b1d5d11311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041317463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3041317463
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.737895447
Short name T800
Test name
Test status
Simulation time 467086857 ps
CPU time 3.23 seconds
Started Jul 03 06:04:20 PM PDT 24
Finished Jul 03 06:04:23 PM PDT 24
Peak memory 217380 kb
Host smart-2c8c21e3-3634-4d5b-9907-f9149ba13746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737895447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.737895447
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2050936344
Short name T306
Test name
Test status
Simulation time 19397627 ps
CPU time 0.8 seconds
Started Jul 03 06:04:22 PM PDT 24
Finished Jul 03 06:04:23 PM PDT 24
Peak memory 207008 kb
Host smart-c2e132d5-f604-4449-a61c-49b294fd412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050936344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2050936344
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2915955479
Short name T390
Test name
Test status
Simulation time 4119827568 ps
CPU time 17.17 seconds
Started Jul 03 06:04:28 PM PDT 24
Finished Jul 03 06:04:45 PM PDT 24
Peak memory 234000 kb
Host smart-71139fa5-a283-4851-b715-c6c31fc4c1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915955479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2915955479
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2288486979
Short name T469
Test name
Test status
Simulation time 14905619 ps
CPU time 0.72 seconds
Started Jul 03 06:04:31 PM PDT 24
Finished Jul 03 06:04:32 PM PDT 24
Peak memory 206388 kb
Host smart-e41a3e07-4e5c-4af9-9afe-62aec8e162e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288486979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2288486979
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1605062399
Short name T630
Test name
Test status
Simulation time 1190847940 ps
CPU time 6.19 seconds
Started Jul 03 06:04:27 PM PDT 24
Finished Jul 03 06:04:34 PM PDT 24
Peak memory 233732 kb
Host smart-0538f2a4-3bda-44ec-86a1-363feae8fda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605062399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1605062399
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1945272905
Short name T329
Test name
Test status
Simulation time 45992580 ps
CPU time 0.76 seconds
Started Jul 03 06:04:31 PM PDT 24
Finished Jul 03 06:04:32 PM PDT 24
Peak memory 206484 kb
Host smart-f811fac5-2bb9-4bd8-b192-575e4daf75d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945272905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1945272905
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4065978163
Short name T246
Test name
Test status
Simulation time 128524609864 ps
CPU time 332.33 seconds
Started Jul 03 06:04:33 PM PDT 24
Finished Jul 03 06:10:06 PM PDT 24
Peak memory 257452 kb
Host smart-29b77a92-2f3a-4960-9934-bd5c2cf283a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065978163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4065978163
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1600128000
Short name T995
Test name
Test status
Simulation time 17037708587 ps
CPU time 150.19 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:07:06 PM PDT 24
Peak memory 250444 kb
Host smart-a66415bb-5386-4146-a53c-1e4e55c0198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600128000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1600128000
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1351782001
Short name T858
Test name
Test status
Simulation time 7891683109 ps
CPU time 27.14 seconds
Started Jul 03 06:04:33 PM PDT 24
Finished Jul 03 06:05:00 PM PDT 24
Peak memory 235728 kb
Host smart-859caf31-2c7f-4824-aaee-70cb7637180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351782001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1351782001
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.320830228
Short name T42
Test name
Test status
Simulation time 5220751676 ps
CPU time 13.4 seconds
Started Jul 03 06:04:28 PM PDT 24
Finished Jul 03 06:04:42 PM PDT 24
Peak memory 225732 kb
Host smart-42b52c3d-b363-448a-ad29-505308ddfa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320830228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.320830228
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3405350183
Short name T1032
Test name
Test status
Simulation time 24401481658 ps
CPU time 193.11 seconds
Started Jul 03 06:04:32 PM PDT 24
Finished Jul 03 06:07:46 PM PDT 24
Peak memory 258500 kb
Host smart-9388253f-e55a-45c9-b2a8-1dff7f338b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405350183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3405350183
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2518430443
Short name T483
Test name
Test status
Simulation time 917157228 ps
CPU time 11.04 seconds
Started Jul 03 06:04:30 PM PDT 24
Finished Jul 03 06:04:41 PM PDT 24
Peak memory 233832 kb
Host smart-6346c830-1ffb-48bf-99e7-f94d0f35ee7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518430443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2518430443
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1640629372
Short name T928
Test name
Test status
Simulation time 1308156615 ps
CPU time 15.84 seconds
Started Jul 03 06:04:29 PM PDT 24
Finished Jul 03 06:04:45 PM PDT 24
Peak memory 251120 kb
Host smart-dd7f22e7-28f0-471d-876a-400fc09aa70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640629372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1640629372
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.792644802
Short name T648
Test name
Test status
Simulation time 436526601 ps
CPU time 9.37 seconds
Started Jul 03 06:04:31 PM PDT 24
Finished Jul 03 06:04:41 PM PDT 24
Peak memory 233724 kb
Host smart-f64ad86c-b5a8-4952-a42b-7b4b968905ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792644802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.792644802
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.156862049
Short name T651
Test name
Test status
Simulation time 3516977848 ps
CPU time 7.26 seconds
Started Jul 03 06:04:26 PM PDT 24
Finished Jul 03 06:04:34 PM PDT 24
Peak memory 225624 kb
Host smart-ebf01a6a-b79e-4709-94e3-e1b637237089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156862049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.156862049
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2364930235
Short name T1020
Test name
Test status
Simulation time 5015366450 ps
CPU time 12.42 seconds
Started Jul 03 06:04:33 PM PDT 24
Finished Jul 03 06:04:46 PM PDT 24
Peak memory 221912 kb
Host smart-4a17b6ec-031c-4148-8cab-79404072ecae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2364930235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2364930235
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1631068746
Short name T168
Test name
Test status
Simulation time 20211041919 ps
CPU time 80.5 seconds
Started Jul 03 06:04:34 PM PDT 24
Finished Jul 03 06:05:55 PM PDT 24
Peak memory 249608 kb
Host smart-6bf5fb87-86a5-42a8-b596-32a84e3c0ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631068746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1631068746
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3712177447
Short name T869
Test name
Test status
Simulation time 3841340214 ps
CPU time 28.6 seconds
Started Jul 03 06:04:26 PM PDT 24
Finished Jul 03 06:04:55 PM PDT 24
Peak memory 217552 kb
Host smart-60485fe5-6898-4c25-8806-00b317f3b18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712177447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3712177447
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.978571890
Short name T330
Test name
Test status
Simulation time 1105300889 ps
CPU time 3.89 seconds
Started Jul 03 06:04:31 PM PDT 24
Finished Jul 03 06:04:35 PM PDT 24
Peak memory 217188 kb
Host smart-5244a161-a768-4875-a8ae-da54ce8ce93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978571890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.978571890
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.761264580
Short name T935
Test name
Test status
Simulation time 16923613 ps
CPU time 0.95 seconds
Started Jul 03 06:04:26 PM PDT 24
Finished Jul 03 06:04:27 PM PDT 24
Peak memory 208352 kb
Host smart-3cd078a4-a199-4ae6-bac0-a5aefa80db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761264580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.761264580
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3593269739
Short name T818
Test name
Test status
Simulation time 110368348 ps
CPU time 0.92 seconds
Started Jul 03 06:04:28 PM PDT 24
Finished Jul 03 06:04:30 PM PDT 24
Peak memory 208016 kb
Host smart-60bbc0ef-1e72-405f-943c-0c96bcf3ace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593269739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3593269739
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2238549161
Short name T731
Test name
Test status
Simulation time 115680588 ps
CPU time 3.15 seconds
Started Jul 03 06:04:28 PM PDT 24
Finished Jul 03 06:04:31 PM PDT 24
Peak memory 233840 kb
Host smart-42db6b70-c9cc-4294-8d41-fb13c85061f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238549161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2238549161
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3477268890
Short name T879
Test name
Test status
Simulation time 13653853 ps
CPU time 0.71 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:04:36 PM PDT 24
Peak memory 205844 kb
Host smart-1f67c5ab-5fb2-4ff5-bd5e-b70d92bb7e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477268890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3477268890
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3628535328
Short name T908
Test name
Test status
Simulation time 1012927943 ps
CPU time 3.92 seconds
Started Jul 03 06:04:36 PM PDT 24
Finished Jul 03 06:04:40 PM PDT 24
Peak memory 225612 kb
Host smart-56be8f9b-38fc-4b94-ae49-836ec0a12cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628535328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3628535328
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.241116756
Short name T76
Test name
Test status
Simulation time 93407532 ps
CPU time 0.77 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:04:36 PM PDT 24
Peak memory 207500 kb
Host smart-66561f97-162f-4e5e-a3b1-58a5ae6b541c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241116756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.241116756
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3918729323
Short name T958
Test name
Test status
Simulation time 11760344903 ps
CPU time 123.58 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:06:39 PM PDT 24
Peak memory 258380 kb
Host smart-6c51a293-d74f-48e5-83a4-3c201f07b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918729323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3918729323
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2600592260
Short name T213
Test name
Test status
Simulation time 8539280907 ps
CPU time 29.58 seconds
Started Jul 03 06:04:37 PM PDT 24
Finished Jul 03 06:05:06 PM PDT 24
Peak memory 250408 kb
Host smart-011145ac-cac0-482d-a098-bd942b8d9ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600592260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2600592260
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1348336758
Short name T204
Test name
Test status
Simulation time 11571964864 ps
CPU time 89.28 seconds
Started Jul 03 06:04:37 PM PDT 24
Finished Jul 03 06:06:07 PM PDT 24
Peak memory 250248 kb
Host smart-3f93a168-e8c0-4338-92fa-50164360bbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348336758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1348336758
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1256545778
Short name T41
Test name
Test status
Simulation time 3573146355 ps
CPU time 18.84 seconds
Started Jul 03 06:04:36 PM PDT 24
Finished Jul 03 06:04:55 PM PDT 24
Peak memory 253672 kb
Host smart-16617c8d-6cfb-4d74-b67f-9458c9208a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256545778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1256545778
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1878387855
Short name T316
Test name
Test status
Simulation time 21299144895 ps
CPU time 160.18 seconds
Started Jul 03 06:04:34 PM PDT 24
Finished Jul 03 06:07:14 PM PDT 24
Peak memory 258480 kb
Host smart-5551cf55-814d-4dbc-9fd3-351fdb7c11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878387855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1878387855
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.420297038
Short name T656
Test name
Test status
Simulation time 790033835 ps
CPU time 7.23 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:04:43 PM PDT 24
Peak memory 233784 kb
Host smart-922ec10d-4b8b-4eb5-bbbb-64ecc60843ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420297038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.420297038
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3253456212
Short name T1034
Test name
Test status
Simulation time 16420967667 ps
CPU time 46.24 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:05:21 PM PDT 24
Peak memory 250308 kb
Host smart-c86018cf-fc14-4f38-937d-766be2d126e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253456212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3253456212
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3548638863
Short name T957
Test name
Test status
Simulation time 180874810 ps
CPU time 4.7 seconds
Started Jul 03 06:04:32 PM PDT 24
Finished Jul 03 06:04:37 PM PDT 24
Peak memory 233776 kb
Host smart-d2256fb9-d62f-4743-9dcc-f03a9f05013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548638863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3548638863
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.64246061
Short name T974
Test name
Test status
Simulation time 363875332 ps
CPU time 5.01 seconds
Started Jul 03 06:04:36 PM PDT 24
Finished Jul 03 06:04:41 PM PDT 24
Peak memory 233796 kb
Host smart-b4a7b703-c255-4a32-9369-c1a79736c2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64246061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.64246061
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3304648438
Short name T454
Test name
Test status
Simulation time 807174651 ps
CPU time 4.77 seconds
Started Jul 03 06:04:38 PM PDT 24
Finished Jul 03 06:04:43 PM PDT 24
Peak memory 221432 kb
Host smart-7533e220-c305-4b7f-9e6e-556b3eb9d2ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3304648438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3304648438
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2621865162
Short name T296
Test name
Test status
Simulation time 471094143 ps
CPU time 3.32 seconds
Started Jul 03 06:04:36 PM PDT 24
Finished Jul 03 06:04:40 PM PDT 24
Peak memory 217468 kb
Host smart-eef1e06a-bf1c-42be-bff3-9a9a36453436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621865162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2621865162
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3855722249
Short name T934
Test name
Test status
Simulation time 8243406222 ps
CPU time 10.9 seconds
Started Jul 03 06:04:33 PM PDT 24
Finished Jul 03 06:04:44 PM PDT 24
Peak memory 217512 kb
Host smart-994d459a-7fb2-404d-848b-deaa98804ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855722249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3855722249
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3713509126
Short name T714
Test name
Test status
Simulation time 232039226 ps
CPU time 2.15 seconds
Started Jul 03 06:04:33 PM PDT 24
Finished Jul 03 06:04:36 PM PDT 24
Peak memory 217376 kb
Host smart-e748869e-b0e9-4cb1-93d9-acd6e9b245d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713509126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3713509126
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2181264358
Short name T493
Test name
Test status
Simulation time 386242773 ps
CPU time 0.94 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:04:37 PM PDT 24
Peak memory 206976 kb
Host smart-9baffcdd-3432-4e72-9630-eea5b0a11025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181264358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2181264358
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1496554695
Short name T733
Test name
Test status
Simulation time 46589475506 ps
CPU time 30.28 seconds
Started Jul 03 06:04:37 PM PDT 24
Finished Jul 03 06:05:08 PM PDT 24
Peak memory 225704 kb
Host smart-bd321cfe-73dd-4bc8-875f-54ed6ce30202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496554695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1496554695
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2661995162
Short name T421
Test name
Test status
Simulation time 71959576 ps
CPU time 0.73 seconds
Started Jul 03 06:04:46 PM PDT 24
Finished Jul 03 06:04:47 PM PDT 24
Peak memory 206364 kb
Host smart-e1434a19-e43f-498a-9f4f-6067aef35de5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661995162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2661995162
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3754692987
Short name T532
Test name
Test status
Simulation time 115341924 ps
CPU time 3.96 seconds
Started Jul 03 06:04:39 PM PDT 24
Finished Jul 03 06:04:43 PM PDT 24
Peak memory 225528 kb
Host smart-960ae390-cb0c-4f1f-a49a-1bea56af9fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754692987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3754692987
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1968110933
Short name T673
Test name
Test status
Simulation time 40609875 ps
CPU time 0.76 seconds
Started Jul 03 06:04:35 PM PDT 24
Finished Jul 03 06:04:36 PM PDT 24
Peak memory 206492 kb
Host smart-56479945-b3fb-46f3-a360-32ea0c33e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968110933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1968110933
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.607193788
Short name T556
Test name
Test status
Simulation time 948676344 ps
CPU time 18.32 seconds
Started Jul 03 06:04:39 PM PDT 24
Finished Jul 03 06:04:58 PM PDT 24
Peak memory 240144 kb
Host smart-3d46a2e3-e366-421b-9244-e4963acc0559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607193788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.607193788
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.435277601
Short name T772
Test name
Test status
Simulation time 3953506040 ps
CPU time 101.43 seconds
Started Jul 03 06:04:44 PM PDT 24
Finished Jul 03 06:06:25 PM PDT 24
Peak memory 257620 kb
Host smart-0059e4c9-40d6-49ff-b536-3d3e0006d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435277601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.435277601
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4062850582
Short name T309
Test name
Test status
Simulation time 752936534 ps
CPU time 6.16 seconds
Started Jul 03 06:04:41 PM PDT 24
Finished Jul 03 06:04:47 PM PDT 24
Peak memory 234864 kb
Host smart-6f95b52d-64c7-423a-872d-036c328eeb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062850582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4062850582
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3681036013
Short name T767
Test name
Test status
Simulation time 1641980660 ps
CPU time 40.33 seconds
Started Jul 03 06:04:43 PM PDT 24
Finished Jul 03 06:05:23 PM PDT 24
Peak memory 250160 kb
Host smart-8403eada-1973-4035-b952-eed8ad604f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681036013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3681036013
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1382988046
Short name T1035
Test name
Test status
Simulation time 214513526 ps
CPU time 6.51 seconds
Started Jul 03 06:04:39 PM PDT 24
Finished Jul 03 06:04:46 PM PDT 24
Peak memory 233804 kb
Host smart-66a92312-c95e-4e71-b65e-8eb40fa60033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382988046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1382988046
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4211438938
Short name T830
Test name
Test status
Simulation time 59968957 ps
CPU time 2.26 seconds
Started Jul 03 06:04:39 PM PDT 24
Finished Jul 03 06:04:42 PM PDT 24
Peak memory 233500 kb
Host smart-678fddea-713e-4797-9888-5b54460e370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211438938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4211438938
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1414300700
Short name T622
Test name
Test status
Simulation time 424859877 ps
CPU time 3.1 seconds
Started Jul 03 06:04:40 PM PDT 24
Finished Jul 03 06:04:43 PM PDT 24
Peak memory 225532 kb
Host smart-da61bb8b-6488-4252-a6bf-8738ad7c435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414300700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1414300700
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4108992098
Short name T63
Test name
Test status
Simulation time 10790602100 ps
CPU time 10.59 seconds
Started Jul 03 06:04:39 PM PDT 24
Finished Jul 03 06:04:50 PM PDT 24
Peak memory 233896 kb
Host smart-6baf9fbe-c1f8-42cb-925c-6a7e414c801a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108992098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4108992098
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2799772749
Short name T882
Test name
Test status
Simulation time 409932194 ps
CPU time 7.81 seconds
Started Jul 03 06:04:43 PM PDT 24
Finished Jul 03 06:04:51 PM PDT 24
Peak memory 219856 kb
Host smart-2e6d7cfe-3f27-4d93-9676-ee8d739ddf8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2799772749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2799772749
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2167935377
Short name T501
Test name
Test status
Simulation time 21329170921 ps
CPU time 210.04 seconds
Started Jul 03 06:04:42 PM PDT 24
Finished Jul 03 06:08:13 PM PDT 24
Peak memory 250460 kb
Host smart-716f7bb1-9209-4068-a0bc-826d6803c953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167935377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2167935377
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4181815454
Short name T1024
Test name
Test status
Simulation time 467718877 ps
CPU time 2.14 seconds
Started Jul 03 06:04:38 PM PDT 24
Finished Jul 03 06:04:40 PM PDT 24
Peak memory 219332 kb
Host smart-8434408f-b42e-497e-b5fb-74492ed700a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181815454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4181815454
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.564172979
Short name T584
Test name
Test status
Simulation time 1872377573 ps
CPU time 2.09 seconds
Started Jul 03 06:04:43 PM PDT 24
Finished Jul 03 06:04:45 PM PDT 24
Peak memory 208820 kb
Host smart-83cde34d-ad00-4ede-887b-6ee76688dc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564172979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.564172979
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.467904381
Short name T647
Test name
Test status
Simulation time 214880833 ps
CPU time 1.98 seconds
Started Jul 03 06:04:39 PM PDT 24
Finished Jul 03 06:04:41 PM PDT 24
Peak memory 209180 kb
Host smart-edc06a41-a41c-48b4-a261-710934eec0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467904381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.467904381
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.947213767
Short name T323
Test name
Test status
Simulation time 50920989 ps
CPU time 0.82 seconds
Started Jul 03 06:04:38 PM PDT 24
Finished Jul 03 06:04:40 PM PDT 24
Peak memory 207044 kb
Host smart-1887f0a9-f2a9-4c8a-8d6b-2e3c9387506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947213767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.947213767
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.580473282
Short name T854
Test name
Test status
Simulation time 2971696144 ps
CPU time 9.96 seconds
Started Jul 03 06:04:38 PM PDT 24
Finished Jul 03 06:04:48 PM PDT 24
Peak memory 225576 kb
Host smart-d2f0b3a1-9920-4c0d-8e61-c0c84379b7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580473282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.580473282
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3694107974
Short name T62
Test name
Test status
Simulation time 13106801 ps
CPU time 0.7 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 206620 kb
Host smart-fe91123c-c726-48fe-b8cc-5ddeb9b01d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694107974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
694107974
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1852023513
Short name T992
Test name
Test status
Simulation time 37163410 ps
CPU time 2.63 seconds
Started Jul 03 06:01:14 PM PDT 24
Finished Jul 03 06:01:17 PM PDT 24
Peak memory 233752 kb
Host smart-3a1f1173-ab3a-40a2-ba94-2165873f476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852023513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1852023513
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3993948335
Short name T775
Test name
Test status
Simulation time 18298164 ps
CPU time 0.81 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 207868 kb
Host smart-6246a7fd-af18-4cf9-a1d2-75f4a4ff0b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993948335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3993948335
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.357115231
Short name T698
Test name
Test status
Simulation time 33052925 ps
CPU time 0.72 seconds
Started Jul 03 06:01:10 PM PDT 24
Finished Jul 03 06:01:11 PM PDT 24
Peak memory 216972 kb
Host smart-826fbe43-b425-421b-ba7b-4427133c571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357115231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.357115231
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1984077410
Short name T260
Test name
Test status
Simulation time 21742164799 ps
CPU time 262.06 seconds
Started Jul 03 06:01:22 PM PDT 24
Finished Jul 03 06:05:45 PM PDT 24
Peak memory 263152 kb
Host smart-f5b3b9b2-36aa-4001-b4d3-f2f2c753764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984077410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1984077410
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1136120277
Short name T727
Test name
Test status
Simulation time 213362838 ps
CPU time 3.36 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 233816 kb
Host smart-b114a313-5773-44da-b21c-a59e965e696c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136120277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1136120277
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2689097395
Short name T53
Test name
Test status
Simulation time 10903435567 ps
CPU time 30.01 seconds
Started Jul 03 06:01:09 PM PDT 24
Finished Jul 03 06:01:39 PM PDT 24
Peak memory 235868 kb
Host smart-ca17af9f-5725-4d99-82e2-f4d0f84ede78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689097395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2689097395
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.895230783
Short name T723
Test name
Test status
Simulation time 2554257698 ps
CPU time 19.96 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:37 PM PDT 24
Peak memory 233948 kb
Host smart-96aa0903-2f96-4fc3-a1de-7373df48bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895230783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.895230783
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.630500536
Short name T335
Test name
Test status
Simulation time 373884904 ps
CPU time 2.77 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 225564 kb
Host smart-31f290f3-310f-4b9e-aa4d-1ffc8e53bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630500536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.630500536
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.849395418
Short name T612
Test name
Test status
Simulation time 31413544 ps
CPU time 0.97 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:19 PM PDT 24
Peak memory 218956 kb
Host smart-521b7cef-f09f-4c5d-ab18-445eb4ba6e9b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849395418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.849395418
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.343657130
Short name T886
Test name
Test status
Simulation time 25618731497 ps
CPU time 9.72 seconds
Started Jul 03 06:01:08 PM PDT 24
Finished Jul 03 06:01:18 PM PDT 24
Peak memory 233824 kb
Host smart-0b1fe36a-ec14-4c4e-98e2-f1b17e7e5080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343657130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
343657130
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2289566465
Short name T813
Test name
Test status
Simulation time 749217523 ps
CPU time 3.94 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 225624 kb
Host smart-31cac442-4d3b-4165-96d5-1d48c7340628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289566465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2289566465
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1502645998
Short name T152
Test name
Test status
Simulation time 2662823106 ps
CPU time 5.18 seconds
Started Jul 03 06:01:14 PM PDT 24
Finished Jul 03 06:01:19 PM PDT 24
Peak memory 223688 kb
Host smart-d2b64624-2efd-42b7-89d7-cb943202552d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1502645998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1502645998
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.397022224
Short name T279
Test name
Test status
Simulation time 691889799 ps
CPU time 3.23 seconds
Started Jul 03 06:01:07 PM PDT 24
Finished Jul 03 06:01:11 PM PDT 24
Peak memory 217444 kb
Host smart-90dd1886-d31f-43f3-8d4a-c8d7741e38a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397022224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.397022224
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2265663848
Short name T577
Test name
Test status
Simulation time 54095336472 ps
CPU time 15.49 seconds
Started Jul 03 06:01:16 PM PDT 24
Finished Jul 03 06:01:32 PM PDT 24
Peak memory 217460 kb
Host smart-060cc5e5-6777-4563-a25e-78ab5e90ca3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265663848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2265663848
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2385789254
Short name T479
Test name
Test status
Simulation time 38175482 ps
CPU time 0.99 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:19 PM PDT 24
Peak memory 208420 kb
Host smart-9e6a9abe-2e87-489f-86e6-b5422b49dde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385789254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2385789254
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.244460880
Short name T426
Test name
Test status
Simulation time 137401116 ps
CPU time 0.9 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 208044 kb
Host smart-fce1cb2c-b8a4-43bb-877f-c35526b0b5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244460880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.244460880
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2870241161
Short name T799
Test name
Test status
Simulation time 5677753259 ps
CPU time 10.17 seconds
Started Jul 03 06:01:08 PM PDT 24
Finished Jul 03 06:01:19 PM PDT 24
Peak memory 233804 kb
Host smart-8930de2c-17d3-4c3d-8005-95ad59a10524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870241161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2870241161
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1833219341
Short name T75
Test name
Test status
Simulation time 22865480 ps
CPU time 0.71 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 206400 kb
Host smart-b7568dca-f99a-4fde-ba4a-8ba6f6a98962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833219341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
833219341
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2226232174
Short name T840
Test name
Test status
Simulation time 516930058 ps
CPU time 3.49 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 225608 kb
Host smart-f2af1dca-76f7-4d50-8000-a18dd462192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226232174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2226232174
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3692830317
Short name T7
Test name
Test status
Simulation time 101568194 ps
CPU time 0.82 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 207424 kb
Host smart-502b3b51-8945-4ea3-894d-0fb3d7876333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692830317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3692830317
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2641421061
Short name T531
Test name
Test status
Simulation time 5828299660 ps
CPU time 37.56 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:58 PM PDT 24
Peak memory 234864 kb
Host smart-4c017e72-c4cc-4e98-ad6f-0389108d911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641421061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2641421061
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2898262018
Short name T208
Test name
Test status
Simulation time 14238745410 ps
CPU time 145.63 seconds
Started Jul 03 06:01:23 PM PDT 24
Finished Jul 03 06:03:49 PM PDT 24
Peak memory 235400 kb
Host smart-732675ca-e8fc-4706-ac34-2673192e46d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898262018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2898262018
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2143957464
Short name T170
Test name
Test status
Simulation time 60213677056 ps
CPU time 81.26 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:02:43 PM PDT 24
Peak memory 255568 kb
Host smart-f9fc02e7-8482-4086-8fa9-92e8280ad45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143957464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2143957464
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1154723271
Short name T827
Test name
Test status
Simulation time 2111496132 ps
CPU time 17.79 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:39 PM PDT 24
Peak memory 225624 kb
Host smart-2125662c-653c-48b2-b233-a4bc07f0bc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154723271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1154723271
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3930421404
Short name T948
Test name
Test status
Simulation time 33703196459 ps
CPU time 66.63 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:02:28 PM PDT 24
Peak memory 238144 kb
Host smart-f256a490-a74d-4a96-a8c2-01f1af710757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930421404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3930421404
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2893341231
Short name T357
Test name
Test status
Simulation time 708281910 ps
CPU time 8.74 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:30 PM PDT 24
Peak memory 233804 kb
Host smart-aaebdf28-52d7-4ff2-b8fa-55551e568914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893341231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2893341231
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3442461735
Short name T1006
Test name
Test status
Simulation time 22015146697 ps
CPU time 21.14 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:38 PM PDT 24
Peak memory 225720 kb
Host smart-5813af30-f842-49f0-b464-b32f797817a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442461735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3442461735
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1244100636
Short name T1011
Test name
Test status
Simulation time 338775844 ps
CPU time 1.09 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 217576 kb
Host smart-71b6c726-6dd7-4c24-8171-dd366eefddf3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244100636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1244100636
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1291177213
Short name T235
Test name
Test status
Simulation time 353669880 ps
CPU time 3.74 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 225528 kb
Host smart-7480fb87-20f1-4ffb-a3ef-c4d646fe12f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291177213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1291177213
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1959402681
Short name T334
Test name
Test status
Simulation time 2881684323 ps
CPU time 11.42 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:30 PM PDT 24
Peak memory 225736 kb
Host smart-62f87c5f-db61-411f-abae-7e863cb01948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959402681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1959402681
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3383293278
Short name T528
Test name
Test status
Simulation time 1154850481 ps
CPU time 9.68 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:27 PM PDT 24
Peak memory 220240 kb
Host smart-9a275129-f0cf-46b2-95ae-f34c0835b18a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3383293278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3383293278
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1962859240
Short name T20
Test name
Test status
Simulation time 17931082492 ps
CPU time 134.34 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:03:35 PM PDT 24
Peak memory 258944 kb
Host smart-f56b18f4-f989-45b8-a475-96059b708b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962859240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1962859240
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1649428792
Short name T342
Test name
Test status
Simulation time 77060097 ps
CPU time 0.72 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:19 PM PDT 24
Peak memory 206952 kb
Host smart-8a12290a-8211-4b32-b265-7d8c06a8c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649428792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1649428792
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1692787753
Short name T295
Test name
Test status
Simulation time 1091608014 ps
CPU time 6.19 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 217368 kb
Host smart-e9a051a5-b77e-49b4-81f6-1a13d680e2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692787753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1692787753
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1775026875
Short name T694
Test name
Test status
Simulation time 55996590 ps
CPU time 1.27 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 217208 kb
Host smart-319b2b13-2f77-42b5-aedb-2fda3c748641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775026875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1775026875
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.591990358
Short name T697
Test name
Test status
Simulation time 143995084 ps
CPU time 0.83 seconds
Started Jul 03 06:01:10 PM PDT 24
Finished Jul 03 06:01:11 PM PDT 24
Peak memory 208048 kb
Host smart-9e3e5a60-bec3-462c-9d6a-46dbd753d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591990358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.591990358
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1816740235
Short name T815
Test name
Test status
Simulation time 15394867490 ps
CPU time 28.36 seconds
Started Jul 03 06:01:14 PM PDT 24
Finished Jul 03 06:01:42 PM PDT 24
Peak memory 250116 kb
Host smart-c371ed3b-2627-4b48-b8b2-40e41081f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816740235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1816740235
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2524420530
Short name T297
Test name
Test status
Simulation time 47350862 ps
CPU time 0.7 seconds
Started Jul 03 06:01:23 PM PDT 24
Finished Jul 03 06:01:24 PM PDT 24
Peak memory 205812 kb
Host smart-e2c1c987-04a8-4995-8a2e-3c3d38ce77b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524420530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
524420530
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.432263801
Short name T1016
Test name
Test status
Simulation time 754824275 ps
CPU time 3.4 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 233748 kb
Host smart-1847b0ab-7d9b-4ea6-a954-3cbe40fbc735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432263801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.432263801
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1503904420
Short name T593
Test name
Test status
Simulation time 67462371 ps
CPU time 0.79 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 207556 kb
Host smart-679cd442-1d22-40ad-8d0b-0c763f3113ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503904420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1503904420
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3094709706
Short name T554
Test name
Test status
Simulation time 20398539075 ps
CPU time 37.73 seconds
Started Jul 03 06:01:22 PM PDT 24
Finished Jul 03 06:02:00 PM PDT 24
Peak memory 251076 kb
Host smart-619ec4c3-341d-4d85-9fc4-ec5fa6accdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094709706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3094709706
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4120893846
Short name T1023
Test name
Test status
Simulation time 14761592497 ps
CPU time 103.85 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:03:02 PM PDT 24
Peak memory 225872 kb
Host smart-cd29ad6b-db35-4e53-8f7b-a4452f3c954c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120893846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4120893846
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4257082266
Short name T655
Test name
Test status
Simulation time 145428271790 ps
CPU time 89.86 seconds
Started Jul 03 06:01:23 PM PDT 24
Finished Jul 03 06:02:53 PM PDT 24
Peak memory 224520 kb
Host smart-ed2e84fc-d8c9-4998-925a-228b466a2d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257082266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4257082266
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.750098298
Short name T819
Test name
Test status
Simulation time 1496882203 ps
CPU time 30.87 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:50 PM PDT 24
Peak memory 250084 kb
Host smart-c00ab9cb-c230-497a-a1bf-0a3ce0d931e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750098298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
750098298
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.434554752
Short name T749
Test name
Test status
Simulation time 257140571 ps
CPU time 2.86 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:28 PM PDT 24
Peak memory 225568 kb
Host smart-036d8f99-dfe6-415a-972d-be15aea4476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434554752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.434554752
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2847135657
Short name T998
Test name
Test status
Simulation time 2856901008 ps
CPU time 6.34 seconds
Started Jul 03 06:01:23 PM PDT 24
Finished Jul 03 06:01:30 PM PDT 24
Peak memory 225664 kb
Host smart-9894c614-543e-4ed9-badc-64881df048ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847135657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2847135657
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3589253403
Short name T23
Test name
Test status
Simulation time 17026636 ps
CPU time 1.04 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 217656 kb
Host smart-8749333b-b869-451a-970b-5abaf002eeb6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589253403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3589253403
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3731066285
Short name T953
Test name
Test status
Simulation time 8648427760 ps
CPU time 22.83 seconds
Started Jul 03 06:01:12 PM PDT 24
Finished Jul 03 06:01:35 PM PDT 24
Peak memory 225736 kb
Host smart-12c68434-d9b4-4efa-bee1-0a6ec7f13a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731066285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3731066285
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2960131108
Short name T389
Test name
Test status
Simulation time 1966905126 ps
CPU time 3.56 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 233760 kb
Host smart-29e6066a-77e2-4476-87c3-aca5cec349f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960131108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2960131108
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3055852321
Short name T618
Test name
Test status
Simulation time 528061270 ps
CPU time 3.46 seconds
Started Jul 03 06:01:13 PM PDT 24
Finished Jul 03 06:01:17 PM PDT 24
Peak memory 220900 kb
Host smart-95455d7f-6c38-4b3e-9512-5c45aab535e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3055852321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3055852321
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2762455118
Short name T420
Test name
Test status
Simulation time 38562585 ps
CPU time 0.88 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 207568 kb
Host smart-8292db78-12f9-4744-b2fe-7dc4373ed549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762455118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2762455118
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3704525073
Short name T872
Test name
Test status
Simulation time 9402663751 ps
CPU time 20.67 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:43 PM PDT 24
Peak memory 217564 kb
Host smart-cf781eca-852e-47e1-ace2-6fe83846dca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704525073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3704525073
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.419041437
Short name T320
Test name
Test status
Simulation time 3147758371 ps
CPU time 11.17 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:33 PM PDT 24
Peak memory 217388 kb
Host smart-6f077b7e-84ae-4f24-ac09-1a911e5ba850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419041437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.419041437
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2999608366
Short name T903
Test name
Test status
Simulation time 11918998 ps
CPU time 0.74 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 206964 kb
Host smart-aaf950c5-f043-4eea-98d0-cb58348f815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999608366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2999608366
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.467105405
Short name T366
Test name
Test status
Simulation time 68435807 ps
CPU time 0.89 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 208020 kb
Host smart-aa67eb5e-6a62-4bfe-99a7-7c159264f800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467105405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.467105405
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.847691542
Short name T1026
Test name
Test status
Simulation time 7228993504 ps
CPU time 21.39 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:40 PM PDT 24
Peak memory 225616 kb
Host smart-20756d52-e888-4f36-a609-36878d332d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847691542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.847691542
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3223285569
Short name T646
Test name
Test status
Simulation time 40155582 ps
CPU time 0.73 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:01:19 PM PDT 24
Peak memory 205772 kb
Host smart-601f2216-9a9d-43a0-ae22-0df4e988af0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223285569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
223285569
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3430479506
Short name T511
Test name
Test status
Simulation time 2691449904 ps
CPU time 6.02 seconds
Started Jul 03 06:01:23 PM PDT 24
Finished Jul 03 06:01:30 PM PDT 24
Peak memory 225632 kb
Host smart-a65e2139-89af-4213-846b-e052b1abcef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430479506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3430479506
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.492221602
Short name T1025
Test name
Test status
Simulation time 85599878 ps
CPU time 0.75 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 206468 kb
Host smart-ab22a103-196c-455a-9d15-98ef2df7dca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492221602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.492221602
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1711604646
Short name T732
Test name
Test status
Simulation time 1663985459 ps
CPU time 31.37 seconds
Started Jul 03 06:01:16 PM PDT 24
Finished Jul 03 06:01:48 PM PDT 24
Peak memory 240628 kb
Host smart-4794d74a-7199-4a83-bc64-e86e389384f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711604646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1711604646
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3996001172
Short name T457
Test name
Test status
Simulation time 423563341 ps
CPU time 4.71 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:26 PM PDT 24
Peak memory 218720 kb
Host smart-9f6dc85c-8308-4d95-9ef1-6a0ef58d3b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996001172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3996001172
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.75239908
Short name T33
Test name
Test status
Simulation time 2123715115 ps
CPU time 56.02 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:02:18 PM PDT 24
Peak memory 254132 kb
Host smart-adc603ff-5449-4996-bc10-636434be0d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75239908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.75239908
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3733162482
Short name T412
Test name
Test status
Simulation time 258554876 ps
CPU time 3.41 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 233856 kb
Host smart-d8c6b839-7586-41d4-82b3-e025ade97697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733162482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3733162482
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.884065318
Short name T91
Test name
Test status
Simulation time 98175876657 ps
CPU time 109.47 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:03:11 PM PDT 24
Peak memory 250304 kb
Host smart-a415aeb2-05cc-4246-9fe9-655931ce07a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884065318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
884065318
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3571084783
Short name T609
Test name
Test status
Simulation time 581515952 ps
CPU time 7.25 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:27 PM PDT 24
Peak memory 233788 kb
Host smart-4b3e1de2-e7b1-4eda-aca2-b6100c2e446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571084783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3571084783
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1469721394
Short name T182
Test name
Test status
Simulation time 363770096 ps
CPU time 4.12 seconds
Started Jul 03 06:01:16 PM PDT 24
Finished Jul 03 06:01:20 PM PDT 24
Peak memory 225560 kb
Host smart-f68be66c-fba2-4061-b9a4-d261076414e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469721394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1469721394
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.216623705
Short name T437
Test name
Test status
Simulation time 40088662 ps
CPU time 1.11 seconds
Started Jul 03 06:01:23 PM PDT 24
Finished Jul 03 06:01:25 PM PDT 24
Peak memory 217692 kb
Host smart-fb09d3cc-d30b-4891-ad1d-acf0a3736f7b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216623705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.216623705
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.186962358
Short name T93
Test name
Test status
Simulation time 4242795954 ps
CPU time 10.84 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:31 PM PDT 24
Peak memory 252244 kb
Host smart-d9e0e448-a2f8-447d-af0d-22fdde252208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186962358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
186962358
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3882846788
Short name T811
Test name
Test status
Simulation time 35244377721 ps
CPU time 29.21 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:51 PM PDT 24
Peak memory 250212 kb
Host smart-770d9223-a5e9-473b-abbb-8de31383e706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882846788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3882846788
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4280880678
Short name T598
Test name
Test status
Simulation time 1429560810 ps
CPU time 6.17 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:24 PM PDT 24
Peak memory 221352 kb
Host smart-c4a128ba-5c62-4895-a1b1-c41b70ad5780
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4280880678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4280880678
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2791425654
Short name T944
Test name
Test status
Simulation time 32098552861 ps
CPU time 94.96 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:02:56 PM PDT 24
Peak memory 258588 kb
Host smart-0b9923a0-5e77-4305-a5d8-82837940b337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791425654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2791425654
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2959748859
Short name T90
Test name
Test status
Simulation time 2204118953 ps
CPU time 20.53 seconds
Started Jul 03 06:01:24 PM PDT 24
Finished Jul 03 06:01:45 PM PDT 24
Peak memory 220424 kb
Host smart-9112dfb3-63f0-4717-b5a6-0a0ff71f8f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959748859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2959748859
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3518101755
Short name T941
Test name
Test status
Simulation time 2646059105 ps
CPU time 7.31 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:27 PM PDT 24
Peak memory 217456 kb
Host smart-1b19ceac-dc08-486f-9f34-78908b022b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518101755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3518101755
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.512805863
Short name T561
Test name
Test status
Simulation time 115147712 ps
CPU time 2 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:22 PM PDT 24
Peak memory 217388 kb
Host smart-06ab919c-f6e0-40b5-a912-b7962e23066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512805863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.512805863
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.786446504
Short name T388
Test name
Test status
Simulation time 104974516 ps
CPU time 0.9 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:26 PM PDT 24
Peak memory 206992 kb
Host smart-2bfb7808-e5d0-49ec-b7c5-8a8d93726043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786446504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.786446504
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2585868182
Short name T880
Test name
Test status
Simulation time 15291931661 ps
CPU time 12.73 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:35 PM PDT 24
Peak memory 233812 kb
Host smart-f350ee53-d9dc-436a-a770-890dfb60c028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585868182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2585868182
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4223690740
Short name T762
Test name
Test status
Simulation time 14787088 ps
CPU time 0.76 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:23 PM PDT 24
Peak memory 206412 kb
Host smart-7a9a5244-a9df-4768-b55f-2fe096aad260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223690740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
223690740
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1502516037
Short name T676
Test name
Test status
Simulation time 259479713 ps
CPU time 5.8 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:26 PM PDT 24
Peak memory 233764 kb
Host smart-aa0acf1e-1ce5-457b-9b96-71abc2d9eaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502516037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1502516037
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2246065701
Short name T924
Test name
Test status
Simulation time 59660726 ps
CPU time 0.74 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:20 PM PDT 24
Peak memory 206452 kb
Host smart-a29f6772-9593-4f36-8dd3-48d10b206fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246065701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2246065701
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.394828617
Short name T199
Test name
Test status
Simulation time 141420137440 ps
CPU time 239.66 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:05:25 PM PDT 24
Peak memory 257760 kb
Host smart-4e3b34dc-447a-4f9d-ac86-f99c1ec2cd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394828617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.394828617
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2278396531
Short name T52
Test name
Test status
Simulation time 4234227891 ps
CPU time 48.83 seconds
Started Jul 03 06:01:29 PM PDT 24
Finished Jul 03 06:02:18 PM PDT 24
Peak memory 252980 kb
Host smart-a9d08b14-f40c-4ac1-ac80-f6e135ef63d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278396531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2278396531
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2003276278
Short name T738
Test name
Test status
Simulation time 17264509361 ps
CPU time 185.79 seconds
Started Jul 03 06:01:29 PM PDT 24
Finished Jul 03 06:04:35 PM PDT 24
Peak memory 250444 kb
Host smart-5235178f-9ae7-409d-b5a3-34ac29e2639f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003276278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2003276278
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3800157878
Short name T996
Test name
Test status
Simulation time 595506144 ps
CPU time 5.16 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:24 PM PDT 24
Peak memory 238984 kb
Host smart-416dff02-d418-4954-8d62-664781ac4828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800157878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3800157878
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3845105551
Short name T670
Test name
Test status
Simulation time 37260435610 ps
CPU time 129.65 seconds
Started Jul 03 06:01:17 PM PDT 24
Finished Jul 03 06:03:27 PM PDT 24
Peak memory 255252 kb
Host smart-c5d87ed8-63c2-46ce-bec7-51297d3ee56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845105551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3845105551
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3823477981
Short name T348
Test name
Test status
Simulation time 337232604 ps
CPU time 4.13 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:24 PM PDT 24
Peak memory 233776 kb
Host smart-3a7ec428-86b0-4d38-a00d-4fe2cf340e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823477981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3823477981
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1362375458
Short name T982
Test name
Test status
Simulation time 1072798635 ps
CPU time 10.48 seconds
Started Jul 03 06:01:27 PM PDT 24
Finished Jul 03 06:01:39 PM PDT 24
Peak memory 234768 kb
Host smart-c6f72344-3f0e-4c42-a3b3-f2d71086919c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362375458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1362375458
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3228922031
Short name T990
Test name
Test status
Simulation time 67136133 ps
CPU time 1.02 seconds
Started Jul 03 06:01:19 PM PDT 24
Finished Jul 03 06:01:21 PM PDT 24
Peak memory 218948 kb
Host smart-aeebd3f9-4597-4e52-9749-2326b940ea8c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228922031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3228922031
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.937320768
Short name T1019
Test name
Test status
Simulation time 1076102204 ps
CPU time 7.7 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:29 PM PDT 24
Peak memory 233768 kb
Host smart-dcb6ee63-4a7b-472a-9e4d-42330833f501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937320768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
937320768
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1386411373
Short name T768
Test name
Test status
Simulation time 2711616750 ps
CPU time 6.95 seconds
Started Jul 03 06:01:21 PM PDT 24
Finished Jul 03 06:01:29 PM PDT 24
Peak memory 233888 kb
Host smart-5533fa10-a8dd-465d-9470-53c66ca13de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386411373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1386411373
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1642356654
Short name T722
Test name
Test status
Simulation time 280492313 ps
CPU time 4.89 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:26 PM PDT 24
Peak memory 221484 kb
Host smart-201766a3-e055-436c-9c25-ff6be31df267
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1642356654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1642356654
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1120148079
Short name T417
Test name
Test status
Simulation time 32174998 ps
CPU time 0.94 seconds
Started Jul 03 06:01:27 PM PDT 24
Finished Jul 03 06:01:28 PM PDT 24
Peak memory 207696 kb
Host smart-a2fb00a4-ad8e-4cdb-b2bd-80ff19c85242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120148079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1120148079
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1823870200
Short name T925
Test name
Test status
Simulation time 1920468234 ps
CPU time 19.01 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:37 PM PDT 24
Peak memory 219336 kb
Host smart-7f6d056f-f200-4778-8c1a-827b29ff2e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823870200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1823870200
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3988839347
Short name T610
Test name
Test status
Simulation time 1931129155 ps
CPU time 6.33 seconds
Started Jul 03 06:01:20 PM PDT 24
Finished Jul 03 06:01:27 PM PDT 24
Peak memory 217348 kb
Host smart-3acdb6e4-3162-45cf-be3b-4210298da7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988839347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3988839347
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4229825294
Short name T402
Test name
Test status
Simulation time 78422352 ps
CPU time 1.87 seconds
Started Jul 03 06:01:29 PM PDT 24
Finished Jul 03 06:01:31 PM PDT 24
Peak memory 217356 kb
Host smart-7462f34b-3e9b-4491-8c54-799126e00432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229825294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4229825294
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.459416253
Short name T425
Test name
Test status
Simulation time 52880183 ps
CPU time 0.81 seconds
Started Jul 03 06:01:18 PM PDT 24
Finished Jul 03 06:01:20 PM PDT 24
Peak memory 206912 kb
Host smart-b07fc906-f69c-48f0-ae31-24493903ddba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459416253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.459416253
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1158681286
Short name T895
Test name
Test status
Simulation time 455294789 ps
CPU time 4.9 seconds
Started Jul 03 06:01:25 PM PDT 24
Finished Jul 03 06:01:30 PM PDT 24
Peak memory 233808 kb
Host smart-0a11650b-b320-49fb-8e11-a88240cd998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158681286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1158681286
Directory /workspace/9.spi_device_upload/latest
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