Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2846288	1			T2	18719		T3	1		T5	764
all_values[1]	2846288	1			T2	18719		T3	1		T5	764
all_values[2]	2846288	1			T2	18719		T3	1		T5	764
all_values[3]	2846288	1			T2	18719		T3	1		T5	764
all_values[4]	2846288	1			T2	18719		T3	1		T5	764
all_values[5]	2846288	1			T2	18719		T3	1		T5	764
all_values[6]	2846288	1			T2	18719		T3	1		T5	764
all_values[7]	2846288	1			T2	18719		T3	1		T5	764

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22010258

1

T2

149752

T3

8

T5

6112

auto[1]

760046

1

T22

55

T29

48

T30

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22744592

1

T2

149345

T3

8

T5

6112

auto[1]

25712

1

T2

407

T12

8

T28

103

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2670064	1			T2	18527		T3	1		T5	764
all_values[0]	auto[0]	auto[1]	11671	1			T2	192		T12	7		T28	53
all_values[0]	auto[1]	auto[0]	163760	1			T22	5		T29	3		T30	5
all_values[0]	auto[1]	auto[1]	793	1			T22	1		T29	3		T30	1
all_values[1]	auto[0]	auto[0]	2729746	1			T2	18611		T3	1		T5	764
all_values[1]	auto[0]	auto[1]	7575	1			T2	108		T12	1		T28	30
all_values[1]	auto[1]	auto[0]	108545	1			T22	3		T29	3		T30	1
all_values[1]	auto[1]	auto[1]	422	1			T22	3		T29	4		T30	4
all_values[2]	auto[0]	auto[0]	2662773	1			T2	18612		T3	1		T5	764
all_values[2]	auto[0]	auto[1]	2878	1			T2	107		T28	20		T48	7
all_values[2]	auto[1]	auto[0]	180296	1			T22	6		T29	2		T30	5
all_values[2]	auto[1]	auto[1]	341	1			T22	1		T29	2		T32	7
all_values[3]	auto[0]	auto[0]	2795366	1			T2	18719		T3	1		T5	764
all_values[3]	auto[0]	auto[1]	227	1			T22	1		T29	6		T30	4
all_values[3]	auto[1]	auto[0]	50488	1			T22	3		T30	4		T32	4
all_values[3]	auto[1]	auto[1]	207	1			T22	3		T29	3		T30	3
all_values[4]	auto[0]	auto[0]	2778732	1			T2	18719		T3	1		T5	764
all_values[4]	auto[0]	auto[1]	214	1			T22	6		T29	2		T30	1
all_values[4]	auto[1]	auto[0]	67162	1			T22	1		T29	3		T30	5
all_values[4]	auto[1]	auto[1]	180	1			T22	5		T29	4		T30	1
all_values[5]	auto[0]	auto[0]	2794940	1			T2	18719		T3	1		T5	764
all_values[5]	auto[0]	auto[1]	176	1			T22	1		T29	4		T30	2
all_values[5]	auto[1]	auto[0]	50989	1			T22	6		T29	6		T30	3
all_values[5]	auto[1]	auto[1]	183	1			T22	4		T29	1		T30	2
all_values[6]	auto[0]	auto[0]	2773687	1			T2	18719		T3	1		T5	764
all_values[6]	auto[0]	auto[1]	204	1			T22	7		T29	3		T30	2
all_values[6]	auto[1]	auto[0]	72193	1			T22	1		T29	3		T30	2
all_values[6]	auto[1]	auto[1]	204	1			T22	4		T29	3		T30	3
all_values[7]	auto[0]	auto[0]	2781780	1			T2	18719		T3	1		T5	764
all_values[7]	auto[0]	auto[1]	225	1			T22	4		T29	2		T30	3
all_values[7]	auto[1]	auto[0]	64071	1			T22	6		T29	7		T30	1
all_values[7]	auto[1]	auto[1]	212	1			T22	3		T29	1		T30	7