Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35921	1			T2	114		T5	19		T12	392
auto[SpiFlashAddrCfg]	7261	1			T2	59		T3	4		T5	7
auto[SpiFlashAddr3b]	9321	1			T2	42		T3	4		T5	8
auto[SpiFlashAddr4b]	7602	1			T2	33		T5	6		T11	1

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33503

1

T2

130

T3

8

T5

32

auto[1]

26602

1

T2

118

T5

8

T12

366

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32181

1

T2

121

T3

4

T5

23

auto[1]

27924

1

T2

127

T3

4

T5

17

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40683	1			T2	142		T5	23		T12	437
values[1]	1091	1			T2	11		T5	2		T11	1
values[2]	1472	1			T2	5		T12	21		T17	19
values[3]	1396	1			T2	6		T12	7		T16	2
values[4]	1448	1			T2	7		T5	3		T12	10
values[5]	1381	1			T2	11		T12	8		T17	4
values[6]	1445	1			T2	9		T3	4		T12	5
values[7]	1416	1			T2	10		T12	9		T17	14
values[8]	9773	1			T2	47		T3	4		T5	12

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27655

1

T3

8

T16

66

T17

554

auto[1]

32450

1

T2

248

T5

40

T11

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56749

1

T2

225

T3

8

T5

38

write

3356

1

T2

23

T5

2

T12

42

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19115

1

T2

113

T3

8

T5

14

valids[0x1]

40990

1

T2

135

T5

26

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1530	1			T2	7		T5	6		T12	9
internal_process_ops[0x5a]	1598	1			T2	7		T12	13		T17	10
internal_process_ops[0x05]	22056	1			T2	32		T5	5		T12	270
internal_process_ops[0x35]	1611	1			T2	11		T12	17		T17	12
internal_process_ops[0x15]	1532	1			T2	7		T5	1		T12	12
internal_process_ops[0x03]	997	1			T2	3		T5	1		T12	7
internal_process_ops[0x0b]	1022	1			T2	4		T5	1		T11	1
internal_process_ops[0x3b]	989	1			T2	4		T3	4		T5	1
internal_process_ops[0x6b]	935	1			T2	2		T5	2		T12	4
internal_process_ops[0xbb]	985	1			T2	2		T12	5		T17	11
internal_process_ops[0xeb]	1083	1			T2	4		T3	4		T5	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58396

1

T2

239

T3

8

T5

40

auto[1]

1709

1

T2

9

T12

23

T17

10

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57671

1

T2

234

T3

8

T5

38

auto[1]

2434

1

T2

14

T5

2

T12

29

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9273

1

T16

54

T17

175

T18

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5817

1

T17

198

T39

2

T20

24

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1747

1

T3

4

T16

6

T17

21

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1588

1

T17

33

T20

16

T33

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2193

1

T3

4

T16

2

T17

35

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2118

1

T17

24

T39

2

T20

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1784

1

T16

2

T17

26

T41

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1629

1

T17

23

T39

14

T20

18

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

130

1

T41

4

T33

1

T42

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

113

1

T17

1

T20

4

T35

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

78

1

T17

1

T20

7

T33

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

82

1

T39

2

T20

1

T33

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

92

1

T43

2

T167

2

T168

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T17

2

T20

1

T42

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

83

1

T17

3

T42

4

T35

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

78

1

T17

1

T20

1

T45

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T20

2

T42

1

T35

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

101

1

T20

1

T45

2

T169

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T17

2

T20

1

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

85

1

T17

1

T20

1

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T16

2

T17

2

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

64

1

T17

4

T33

1

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

72

1

T17

1

T42

1

T24

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

122

1

T17

1

T20

3

T42

5

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11255

1

T2

77

T5

16

T12

124

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8676

1

T2

32

T5

2

T12

257

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1578

1

T2

18

T5

5

T12

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1558

1

T2

37

T5

2

T12

27

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2123

1

T2

14

T5

5

T12

28

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2017

1

T2

17

T5

3

T12

35

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1777

1

T2

13

T5

5

T11

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1616

1

T2

17

T12

26

T28

11

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

121

1

T5

1

T28

1

T20

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

124

1

T12

6

T28

1

T33

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

116

1

T2

3

T12

4

T20

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

136

1

T2

2

T12

1

T20

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

111

1

T12

3

T33

4

T170

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

134

1

T2

4

T12

4

T20

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

102

1

T12

3

T28

2

T33

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

90

1

T12

4

T28

1

T33

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

140

1

T2

2

T12

7

T20

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

128

1

T2

2

T28

2

T20

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

102

1

T2

6

T12

2

T20

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

119

1

T2

1

T12

7

T28

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

86

1

T28

1

T48

2

T20

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

116

1

T12

1

T28

4

T20

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

108

1

T2

3

T5

1

T33

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T20

1

T33

8

T170

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3402	1			T16	6		T17	53		T40	8
auto[0]	values[0]	valids[0x1]	14434	1			T16	58		T17	353		T18	4
auto[0]	values[1]	valids[0x1]	457	1			T17	9		T33	2		T42	8
auto[0]	values[2]	valids[0x0]	481	1			T17	16		T19	12		T171	2
auto[0]	values[2]	valids[0x1]	280	1			T17	3		T20	4		T33	3
auto[0]	values[3]	valids[0x0]	489	1			T16	2		T17	5		T20	5
auto[0]	values[3]	valids[0x1]	223	1			T17	3		T18	2		T39	2
auto[0]	values[4]	valids[0x0]	480	1			T17	8		T44	6		T20	12
auto[0]	values[4]	valids[0x1]	278	1			T17	6		T18	2		T20	4
auto[0]	values[5]	valids[0x0]	532	1			T17	3		T39	2		T41	4
auto[0]	values[5]	valids[0x1]	218	1			T17	1		T33	2		T42	5
auto[0]	values[6]	valids[0x0]	508	1			T3	4		T17	3		T39	4
auto[0]	values[6]	valids[0x1]	254	1			T17	5		T20	3		T42	3
auto[0]	values[7]	valids[0x0]	481	1			T17	8		T20	4		T85	4
auto[0]	values[7]	valids[0x1]	248	1			T17	6		T20	2		T33	1
auto[0]	values[8]	valids[0x0]	3050	1			T3	4		T17	44		T18	2
auto[0]	values[8]	valids[0x1]	1840	1			T17	28		T18	4		T20	14
auto[1]	values[0]	valids[0x0]	4412	1			T2	51		T5	7		T12	67
auto[1]	values[0]	valids[0x1]	18435	1			T2	91		T5	16		T12	370
auto[1]	values[1]	valids[0x1]	634	1			T2	11		T5	2		T11	1
auto[1]	values[2]	valids[0x0]	430	1			T2	4		T12	13		T28	1
auto[1]	values[2]	valids[0x1]	281	1			T2	1		T12	8		T20	4
auto[1]	values[3]	valids[0x0]	408	1			T2	4		T12	5		T28	2
auto[1]	values[3]	valids[0x1]	276	1			T2	2		T12	2		T28	6
auto[1]	values[4]	valids[0x0]	404	1			T2	4		T5	1		T12	5
auto[1]	values[4]	valids[0x1]	286	1			T2	3		T5	2		T12	5
auto[1]	values[5]	valids[0x0]	386	1			T2	10		T12	6		T20	2
auto[1]	values[5]	valids[0x1]	245	1			T2	1		T12	2		T36	5
auto[1]	values[6]	valids[0x0]	406	1			T2	5		T12	1		T36	2
auto[1]	values[6]	valids[0x1]	277	1			T2	4		T12	4		T28	5
auto[1]	values[7]	valids[0x0]	398	1			T2	6		T12	6		T20	16
auto[1]	values[7]	valids[0x1]	289	1			T2	4		T12	3		T20	2
auto[1]	values[8]	valids[0x0]	2848	1			T2	29		T5	6		T12	44
auto[1]	values[8]	valids[0x1]	2035	1			T2	18		T5	6		T12	29