Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3267997

1

T2

4244

T3

5942

T5

4673

auto[1]

28332

1

T2

28

T5

43

T12

260

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

847707

1

T2

82

T3

5942

T5

91

auto[1]

2448622

1

T2

4190

T5

4625

T12

9717

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	613962	1			T2	956		T3	1320		T5	6
auto[524288:1048575]	353248	1			T2	1031		T3	1224		T12	544
auto[1048576:1572863]	396356	1			T2	293		T3	621		T5	794
auto[1572864:2097151]	359194	1			T2	541		T3	285		T5	2
auto[2097152:2621439]	405387	1			T2	664		T3	770		T11	961
auto[2621440:3145727]	369835	1			T2	3		T3	100		T5	3914
auto[3145728:3670015]	396149	1			T2	2		T3	1622		T12	1040
auto[3670016:4194303]	402198	1			T2	782		T12	2789		T17	6536

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2482874

1

T2

4272

T3

25

T5

4715

auto[1]

813455

1

T3

5917

T5

1

T11

961

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2797841

1

T2

3986

T3

5942

T5

4698

auto[1]

498488

1

T2

286

T5

18

T12

2073

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	175619	1			T2	14		T3	1320		T5	6
auto[0]	auto[0]	auto[0:524287]	auto[1]	348127	1			T2	934		T12	774		T16	16
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	102316	1			T2	6		T3	1224		T12	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	197587	1			T2	1024		T12	264		T28	256
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	84262	1			T2	10		T3	621		T5	26
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	225689	1			T2	265		T5	768		T12	522
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	97381	1			T2	11		T3	285		T5	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	216332	1			T2	529		T12	1034		T17	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	83577	1			T2	4		T3	770		T11	961
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	261151	1			T2	391		T12	1159		T17	6323
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	101260	1			T2	3		T3	100		T5	30
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	199121	1			T5	3823		T12	4		T17	6434
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	103547	1			T2	1		T3	1622		T12	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	240883	1			T12	1025		T17	5166		T28	513
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	86447	1			T2	5		T12	8		T17	15
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	252070	1			T2	768		T12	2757		T17	6472
auto[0]	auto[1]	auto[0:524287]	auto[0]	1358	1			T12	12		T17	1		T20	7
auto[0]	auto[1]	auto[0:524287]	auto[1]	84317	1			T12	1361		T20	5436		T33	4879
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1034	1			T2	1		T12	2		T17	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	48661	1			T12	258		T17	2		T20	515
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	944	1			T2	3		T12	2		T28	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	82273	1			T2	2		T12	1		T28	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	660	1			T12	1		T17	2		T40	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	42042	1			T17	4		T20	385		T33	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	572	1			T2	4		T12	6		T17	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	55935	1			T2	262		T12	321		T17	5978
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	560	1			T5	18		T12	2		T17	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	65727	1			T12	6		T17	512		T20	3206
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	665	1			T2	1		T12	1		T17	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	47480	1			T17	1		T28	1		T20	518
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	3615	1			T2	5		T12	1		T20	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	56785	1			T2	1		T20	1		T33	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	462	1			T2	3		T12	1		T16	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	3373	1			T2	5		T12	22		T16	46
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	341	1			T20	1		T33	2		T42	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2762	1			T20	1		T33	3		T35	75
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	453	1			T2	4		T12	6		T17	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2131	1			T2	6		T12	26		T17	34
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	396	1			T2	1		T12	7		T17	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1669	1			T12	48		T17	7		T20	27
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	449	1			T2	2		T12	2		T17	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2689	1			T12	17		T17	61		T33	43
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	397	1			T5	9		T33	5		T35	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1983	1			T5	34		T33	58		T35	31
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	346	1			T12	1		T17	3		T28	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2592	1			T12	8		T17	32		T28	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	333	1			T12	2		T17	3		T20	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2096	1			T12	21		T17	46		T20	24
auto[1]	auto[1]	auto[0:524287]	auto[0]	105	1			T12	3		T20	1		T170	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	601	1			T12	22		T20	2		T170	11
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	72	1			T12	1		T17	2		T30	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	475	1			T12	15		T17	45		T30	9
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	89	1			T2	2		T12	1		T28	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	515	1			T2	1		T20	10		T22	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	83	1			T17	1		T20	1		T33	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	631	1			T17	1		T20	11		T33	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	103	1			T2	1		T12	3		T17	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	911	1			T12	46		T17	8		T33	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	92	1			T12	2		T20	1		T162	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	695	1			T12	6		T162	9		T189	18
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	94	1			T17	1		T28	1		T20	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	542	1			T17	21		T28	2		T20	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	75	1			T2	1		T20	1		T33	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	777	1			T2	2		T20	2		T33	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1967648	1			T2	3965		T3	25		T5	4655
auto[0]	auto[0]	auto[1]	807721	1			T3	5917		T11	961		T12	10
auto[0]	auto[1]	auto[0]	487590	1			T2	279		T5	18		T12	1969
auto[0]	auto[1]	auto[1]	5038	1			T12	5		T17	3		T40	3
auto[1]	auto[0]	auto[0]	21907	1			T2	21		T5	42		T12	153
auto[1]	auto[0]	auto[1]	565	1			T5	1		T12	8		T16	4
auto[1]	auto[1]	auto[0]	5729	1			T2	7		T12	94		T17	79
auto[1]	auto[1]	auto[1]	131	1			T12	5		T17	1		T20	1