Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2846288	1			T2	18719		T3	1		T5	764
all_pins[1]	2846288	1			T2	18719		T3	1		T5	764
all_pins[2]	2846288	1			T2	18719		T3	1		T5	764
all_pins[3]	2846288	1			T2	18719		T3	1		T5	764
all_pins[4]	2846288	1			T2	18719		T3	1		T5	764
all_pins[5]	2846288	1			T2	18719		T3	1		T5	764
all_pins[6]	2846288	1			T2	18719		T3	1		T5	764
all_pins[7]	2846288	1			T2	18719		T3	1		T5	764

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22695739	1			T2	149752		T3	8		T5	6112
values[0x1]	74565	1			T22	24		T29	21		T30	21
transitions[0x0=>0x1]	73843	1			T22	19		T29	16		T30	17
transitions[0x1=>0x0]	73860	1			T22	19		T29	16		T30	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2845424	1			T2	18719		T3	1		T5	764
all_pins[0]	values[0x1]	864	1			T22	1		T29	3		T30	1
all_pins[0]	transitions[0x0=>0x1]	557	1			T22	1		T29	3		T30	1
all_pins[0]	transitions[0x1=>0x0]	149	1			T22	3		T29	4		T30	4
all_pins[1]	values[0x0]	2845832	1			T2	18719		T3	1		T5	764
all_pins[1]	values[0x1]	456	1			T22	3		T29	4		T30	4
all_pins[1]	transitions[0x0=>0x1]	330	1			T22	3		T29	2		T30	4
all_pins[1]	transitions[0x1=>0x0]	236	1			T22	1		T32	4		T166	1
all_pins[2]	values[0x0]	2845926	1			T2	18719		T3	1		T5	764
all_pins[2]	values[0x1]	362	1			T22	1		T29	2		T32	7
all_pins[2]	transitions[0x0=>0x1]	315	1			T29	1		T32	4		T166	2
all_pins[2]	transitions[0x1=>0x0]	160	1			T22	2		T29	2		T30	3
all_pins[3]	values[0x0]	2846081	1			T2	18719		T3	1		T5	764
all_pins[3]	values[0x1]	207	1			T22	3		T29	3		T30	3
all_pins[3]	transitions[0x0=>0x1]	165	1			T22	1		T29	2		T30	3
all_pins[3]	transitions[0x1=>0x0]	138	1			T22	3		T29	3		T30	1
all_pins[4]	values[0x0]	2846108	1			T2	18719		T3	1		T5	764
all_pins[4]	values[0x1]	180	1			T22	5		T29	4		T30	1
all_pins[4]	transitions[0x0=>0x1]	144	1			T22	5		T29	4		T166	4
all_pins[4]	transitions[0x1=>0x0]	542	1			T22	4		T29	1		T30	1
all_pins[5]	values[0x0]	2845710	1			T2	18719		T3	1		T5	764
all_pins[5]	values[0x1]	578	1			T22	4		T29	1		T30	2
all_pins[5]	transitions[0x0=>0x1]	534	1			T22	3		T29	1		T30	2
all_pins[5]	transitions[0x1=>0x0]	71662	1			T22	3		T29	3		T30	3
all_pins[6]	values[0x0]	2774582	1			T2	18719		T3	1		T5	764
all_pins[6]	values[0x1]	71706	1			T22	4		T29	3		T30	3
all_pins[6]	transitions[0x0=>0x1]	71657	1			T22	4		T29	3		T30	2
all_pins[6]	transitions[0x1=>0x0]	163	1			T22	3		T29	1		T30	6
all_pins[7]	values[0x0]	2846076	1			T2	18719		T3	1		T5	764
all_pins[7]	values[0x1]	212	1			T22	3		T29	1		T30	7
all_pins[7]	transitions[0x0=>0x1]	141	1			T22	2		T30	5		T32	2
all_pins[7]	transitions[0x1=>0x0]	810	1			T29	2		T32	3		T166	4