Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15810

1

T3

8

T16

66

T17

266

auto[1]

11845

1

T17

288

T39

20

T20

85

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3119	1			T17	20		T18	14		T40	8
values[1]	3738	1			T17	79		T44	6		T43	22
values[2]	3590	1			T17	38		T20	43		T42	51
values[3]	3173	1			T16	66		T17	69		T19	18
values[4]	3792	1			T240	6		T20	25		T33	69
values[5]	3515	1			T17	70		T90	14		T84	16
values[6]	3926	1			T17	77		T98	2		T20	20
values[7]	2802	1			T3	8		T17	201		T39	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3770	1			T17	46		T90	14		T43	22
values[1]	4271	1			T17	50		T19	18		T84	16
values[2]	3119	1			T17	29		T40	8		T44	6
values[3]	3060	1			T18	14		T33	45		T85	6
values[4]	3510	1			T3	8		T39	20		T20	40
values[5]	3296	1			T17	127		T240	6		T98	2
values[6]	3394	1			T16	66		T20	45		T241	2
values[7]	3235	1			T17	302		T41	51		T171	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	298	1			T20	16		T206	10		T222	14
auto[0]	values[0]	values[1]	217	1			T42	17		T242	4		T150	11
auto[0]	values[0]	values[2]	258	1			T40	8		T181	11		T234	9
auto[0]	values[0]	values[3]	324	1			T18	14		T33	14		T189	10
auto[0]	values[0]	values[4]	324	1			T42	14		T243	16		T189	14
auto[0]	values[0]	values[5]	138	1			T88	11		T244	13		T192	10
auto[0]	values[0]	values[6]	146	1			T241	2		T221	18		T203	21
auto[0]	values[0]	values[7]	127	1			T17	12		T42	9		T245	10
auto[0]	values[1]	values[0]	278	1			T17	30		T43	22		T42	9
auto[0]	values[1]	values[1]	246	1			T20	7		T189	10		T88	11
auto[0]	values[1]	values[2]	168	1			T44	6		T20	10		T169	13
auto[0]	values[1]	values[3]	304	1			T158	10		T221	13		T181	18
auto[0]	values[1]	values[4]	189	1			T167	18		T246	8		T204	8
auto[0]	values[1]	values[5]	210	1			T203	10		T204	26		T216	13
auto[0]	values[1]	values[6]	369	1			T33	10		T42	8		T189	97
auto[0]	values[1]	values[7]	240	1			T17	14		T45	14		T204	9
auto[0]	values[2]	values[0]	139	1			T46	10		T24	5		T205	13
auto[0]	values[2]	values[1]	389	1			T169	10		T247	6		T183	8
auto[0]	values[2]	values[2]	173	1			T189	10		T248	8		T151	15
auto[0]	values[2]	values[3]	291	1			T42	13		T203	8		T75	79
auto[0]	values[2]	values[4]	279	1			T249	20		T222	10		T183	26
auto[0]	values[2]	values[5]	452	1			T17	31		T20	8		T70	18
auto[0]	values[2]	values[6]	355	1			T20	16		T238	6		T189	12
auto[0]	values[2]	values[7]	95	1			T42	20		T250	2		T183	12
auto[0]	values[3]	values[0]	312	1			T45	15		T205	10		T251	20
auto[0]	values[3]	values[1]	195	1			T19	18		T35	7		T45	9
auto[0]	values[3]	values[2]	146	1			T194	20		T150	8		T186	15
auto[0]	values[3]	values[3]	104	1			T35	12		T46	8		T252	21
auto[0]	values[3]	values[4]	276	1			T20	24		T69	8		T196	3
auto[0]	values[3]	values[5]	143	1			T17	62		T169	12		T205	14
auto[0]	values[3]	values[6]	226	1			T16	66		T75	8		T197	25
auto[0]	values[3]	values[7]	480	1			T33	16		T35	23		T45	12
auto[0]	values[4]	values[0]	442	1			T33	11		T204	12		T197	14
auto[0]	values[4]	values[1]	234	1			T225	8		T183	11		T253	6
auto[0]	values[4]	values[2]	219	1			T45	9		T169	9		T181	16
auto[0]	values[4]	values[3]	194	1			T33	12		T42	17		T254	6
auto[0]	values[4]	values[4]	184	1			T33	17		T75	20		T197	8
auto[0]	values[4]	values[5]	286	1			T240	6		T20	20		T236	4
auto[0]	values[4]	values[6]	250	1			T46	8		T255	2		T88	13
auto[0]	values[4]	values[7]	244	1			T256	14		T189	13		T257	12
auto[0]	values[5]	values[0]	222	1			T90	14		T42	16		T45	13
auto[0]	values[5]	values[1]	351	1			T17	13		T84	16		T42	17
auto[0]	values[5]	values[2]	221	1			T258	6		T46	13		T189	15
auto[0]	values[5]	values[3]	228	1			T85	6		T35	13		T169	6
auto[0]	values[5]	values[4]	318	1			T259	2		T47	13		T206	7
auto[0]	values[5]	values[5]	273	1			T215	14		T260	6		T151	18
auto[0]	values[5]	values[6]	242	1			T20	11		T204	10		T75	20
auto[0]	values[5]	values[7]	200	1			T17	9		T171	4		T261	28
auto[0]	values[6]	values[0]	470	1			T45	10		T46	16		T205	9
auto[0]	values[6]	values[1]	297	1			T35	31		T22	15		T161	8
auto[0]	values[6]	values[2]	256	1			T20	17		T169	13		T75	29
auto[0]	values[6]	values[3]	185	1			T42	11		T211	12		T204	5
auto[0]	values[6]	values[4]	171	1			T35	20		T262	4		T181	15
auto[0]	values[6]	values[5]	260	1			T17	9		T98	2		T206	18
auto[0]	values[6]	values[6]	188	1			T42	13		T203	35		T205	12
auto[0]	values[6]	values[7]	360	1			T17	9		T128	14		T35	45
auto[0]	values[7]	values[0]	209	1			T189	77		T88	10		T169	10
auto[0]	values[7]	values[1]	206	1			T35	48		T211	8		T169	14
auto[0]	values[7]	values[2]	184	1			T17	11		T192	13		T263	15
auto[0]	values[7]	values[3]	112	1			T22	13		T264	16		T205	19
auto[0]	values[7]	values[4]	297	1			T3	8		T196	17		T265	12
auto[0]	values[7]	values[5]	128	1			T88	12		T211	14		T221	13
auto[0]	values[7]	values[6]	220	1			T42	5		T266	2		T267	2
auto[0]	values[7]	values[7]	268	1			T17	66		T41	51		T164	24
auto[1]	values[0]	values[0]	95	1			T20	5		T206	10		T222	6
auto[1]	values[0]	values[1]	198	1			T42	24		T150	9		T192	9
auto[1]	values[0]	values[2]	300	1			T91	12		T181	9		T234	11
auto[1]	values[0]	values[3]	159	1			T33	10		T189	14		T181	42
auto[1]	values[0]	values[4]	134	1			T42	9		T189	6		T88	10
auto[1]	values[0]	values[5]	110	1			T88	9		T244	7		T192	16
auto[1]	values[0]	values[6]	208	1			T221	48		T203	2		T268	3
auto[1]	values[0]	values[7]	83	1			T17	8		T42	11		T194	17
auto[1]	values[1]	values[0]	214	1			T17	16		T42	11		T45	9
auto[1]	values[1]	values[1]	399	1			T20	13		T189	12		T88	9
auto[1]	values[1]	values[2]	73	1			T20	10		T169	7		T198	7
auto[1]	values[1]	values[3]	360	1			T221	7		T181	10		T203	12
auto[1]	values[1]	values[4]	182	1			T204	12		T151	10		T152	9
auto[1]	values[1]	values[5]	98	1			T203	10		T204	4		T216	7
auto[1]	values[1]	values[6]	234	1			T33	10		T42	12		T189	13
auto[1]	values[1]	values[7]	174	1			T17	19		T45	6		T204	20
auto[1]	values[2]	values[0]	152	1			T46	10		T24	15		T205	9
auto[1]	values[2]	values[1]	315	1			T169	10		T183	17		T252	7
auto[1]	values[2]	values[2]	130	1			T189	10		T151	6		T183	14
auto[1]	values[2]	values[3]	178	1			T42	9		T203	12		T75	12
auto[1]	values[2]	values[4]	168	1			T222	10		T183	8		T268	5
auto[1]	values[2]	values[5]	229	1			T17	7		T20	15		T181	7
auto[1]	values[2]	values[6]	128	1			T20	4		T189	8		T75	22
auto[1]	values[2]	values[7]	117	1			T42	9		T183	46		T49	16
auto[1]	values[3]	values[0]	121	1			T45	5		T269	4		T205	10
auto[1]	values[3]	values[1]	219	1			T35	45		T45	11		T46	13
auto[1]	values[3]	values[2]	134	1			T270	18		T271	8		T194	10
auto[1]	values[3]	values[3]	156	1			T35	8		T46	12		T224	24
auto[1]	values[3]	values[4]	200	1			T20	16		T132	6		T196	17
auto[1]	values[3]	values[5]	72	1			T17	7		T169	8		T272	12
auto[1]	values[3]	values[6]	239	1			T75	96		T197	8		T273	22
auto[1]	values[3]	values[7]	150	1			T33	4		T35	17		T45	8
auto[1]	values[4]	values[0]	155	1			T33	9		T204	8		T197	6
auto[1]	values[4]	values[1]	339	1			T183	22		T253	33		T193	11
auto[1]	values[4]	values[2]	247	1			T45	11		T169	11		T181	4
auto[1]	values[4]	values[3]	112	1			T33	9		T42	4		T221	8
auto[1]	values[4]	values[4]	219	1			T33	11		T75	39		T197	12
auto[1]	values[4]	values[5]	494	1			T20	5		T204	19		T150	13
auto[1]	values[4]	values[6]	104	1			T46	12		T88	7		T222	11
auto[1]	values[4]	values[7]	69	1			T189	7		T211	16		T193	7
auto[1]	values[5]	values[0]	267	1			T42	6		T45	7		T24	12
auto[1]	values[5]	values[1]	216	1			T17	37		T42	7		T169	12
auto[1]	values[5]	values[2]	190	1			T46	7		T189	22		T169	10
auto[1]	values[5]	values[3]	102	1			T35	19		T169	14		T222	12
auto[1]	values[5]	values[4]	163	1			T47	7		T206	13		T194	7
auto[1]	values[5]	values[5]	149	1			T151	25		T187	30		T192	11
auto[1]	values[5]	values[6]	192	1			T20	14		T274	6		T204	10
auto[1]	values[5]	values[7]	181	1			T17	11		T253	66		T252	8
auto[1]	values[6]	values[0]	224	1			T45	10		T46	4		T205	11
auto[1]	values[6]	values[1]	307	1			T35	9		T22	9		T203	5
auto[1]	values[6]	values[2]	346	1			T20	3		T275	2		T169	7
auto[1]	values[6]	values[3]	199	1			T42	17		T211	8		T204	15
auto[1]	values[6]	values[4]	228	1			T35	8		T181	57		T75	90
auto[1]	values[6]	values[5]	124	1			T17	11		T206	4		T205	9
auto[1]	values[6]	values[6]	143	1			T42	9		T203	4		T205	8
auto[1]	values[6]	values[7]	168	1			T17	48		T35	15		T88	20
auto[1]	values[7]	values[0]	172	1			T189	33		T88	10		T169	10
auto[1]	values[7]	values[1]	143	1			T35	10		T211	20		T169	6
auto[1]	values[7]	values[2]	74	1			T17	18		T192	10		T263	5
auto[1]	values[7]	values[3]	52	1			T22	8		T205	13		T208	9
auto[1]	values[7]	values[4]	178	1			T39	20		T196	3		T194	11
auto[1]	values[7]	values[5]	130	1			T88	8		T211	12		T221	13
auto[1]	values[7]	values[6]	150	1			T42	15		T186	10		T187	8
auto[1]	values[7]	values[7]	279	1			T17	106		T276	6		T216	9