Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	348	1			T17	15		T19	4		T20	1
auto[ReadAddrCrossIntoMailbox]	264	1			T17	8		T20	5		T33	1
auto[ReadAddrCrossOutOfMailbox]	224	1			T17	6		T19	8		T20	3
auto[ReadAddrCrossAllMailbox]	207	1			T17	8		T19	2		T20	3
auto[ReadAddrOutsideMailbox]	3263	1			T3	8		T17	24		T18	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2075

1

T3

4

T17

25

T18

2

auto[1]

2231

1

T3

4

T17

36

T18

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	723	1			T17	10		T20	11		T33	2
read_ops[0x0b]	719	1			T17	9		T18	2		T19	4
read_ops[0x3b]	718	1			T3	4		T17	9		T39	4
read_ops[0x6b]	656	1			T17	10		T19	2		T20	7
read_ops[0xbb]	692	1			T17	11		T18	2		T19	12
read_ops[0xeb]	798	1			T3	4		T17	12		T44	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T17	1		T42	1		T169	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T221	1		T183	1		T192	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T33	1		T42	1		T169	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T17	1		T20	2		T42	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T17	2		T20	1		T189	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	11	1			T205	1		T192	1		T234	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T20	1		T88	1		T169	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T17	2		T42	1		T35	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T17	2		T20	1		T42	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	252	1			T17	2		T20	6		T33	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T17	1		T42	1		T189	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T17	3		T169	1		T203	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T17	1		T42	1		T221	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T17	1		T211	1		T221	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	11	1			T19	2		T33	1		T206	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T19	2		T211	1		T169	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T33	1		T45	1		T206	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T17	1		T35	1		T221	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	247	1			T17	1		T18	1		T39	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T17	1		T18	1		T39	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T17	1		T33	1		T45	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T17	1		T46	1		T238	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T20	1		T42	1		T45	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T17	1		T42	1		T238	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T229	1		T88	1		T206	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T20	1		T229	1		T88	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T22	1		T206	1		T186	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T35	1		T206	1		T253	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T3	2		T17	3		T39	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T3	2		T17	3		T39	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T17	1		T215	2		T75	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T17	1		T215	2		T88	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T20	1		T229	1		T75	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T17	2		T42	2		T35	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T19	1		T33	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T17	1		T19	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T20	1		T46	1		T229	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T17	1		T45	2		T229	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	227	1			T17	4		T20	4		T42	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T33	3		T42	9		T35	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T17	2		T19	2		T35	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T17	3		T19	2		T35	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T85	2		T181	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T17	1		T85	2		T35	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T17	1		T19	1		T181	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T19	1		T42	2		T88	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T19	1		T20	1		T42	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T19	1		T277	1		T208	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T17	1		T18	1		T19	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	262	1			T17	3		T18	1		T19	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T20	1		T42	1		T215	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T17	1		T42	1		T215	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T17	1		T45	1		T169	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T20	1		T42	2		T189	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T33	1		T211	1		T169	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T17	2		T211	1		T204	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T17	2		T229	2		T88	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	29	1			T17	2		T33	2		T229	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T3	2		T17	1		T44	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	329	1			T3	2		T17	3		T44	2