Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	842	1			T22	14		T29	10		T30	11
all_values[1]	842	1			T22	14		T29	10		T30	11
all_values[2]	842	1			T22	14		T29	10		T30	11
all_values[3]	842	1			T22	14		T29	10		T30	11
all_values[4]	842	1			T22	14		T29	10		T30	11
all_values[5]	842	1			T22	14		T29	10		T30	11
all_values[6]	842	1			T22	14		T29	10		T30	11
all_values[7]	842	1			T22	14		T29	10		T30	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3553

1

T22

62

T29

42

T30

48

auto[1]

3183

1

T22

50

T29

38

T30

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2610

1

T22

49

T29

26

T30

34

auto[1]

4126

1

T22

63

T29

54

T30

54

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3769

1

T22

61

T29

39

T30

51

auto[1]

2967

1

T22

51

T29

41

T30

37

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	180	1			T22	7		T29	4		T30	1
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T30	1		T150	1		T151	1
all_values[0]	auto[0]	auto[1]	auto[0]	140	1			T22	2		T29	1		T30	3
all_values[0]	auto[0]	auto[1]	auto[1]	86	1			T29	1		T32	1		T166	2
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T22	3		T29	3		T30	3
all_values[0]	auto[1]	auto[1]	auto[1]	195	1			T22	2		T29	1		T30	3
all_values[1]	auto[0]	auto[0]	auto[0]	158	1			T22	5		T30	3		T32	2
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T22	1		T29	1		T30	2
all_values[1]	auto[0]	auto[1]	auto[0]	155	1			T22	2		T29	3		T30	1
all_values[1]	auto[0]	auto[1]	auto[1]	84	1			T22	1		T29	2		T30	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T22	1		T32	5		T166	5
all_values[1]	auto[1]	auto[1]	auto[1]	169	1			T22	4		T29	4		T30	4
all_values[2]	auto[0]	auto[0]	auto[0]	159	1			T22	4		T29	2		T30	2
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T22	1		T29	1		T30	2
all_values[2]	auto[0]	auto[1]	auto[0]	138	1			T22	2		T29	1		T30	2
all_values[2]	auto[0]	auto[1]	auto[1]	79	1			T30	1		T32	2		T166	2
all_values[2]	auto[1]	auto[0]	auto[1]	222	1			T22	5		T29	2		T30	3
all_values[2]	auto[1]	auto[1]	auto[1]	166	1			T22	2		T29	4		T30	1
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T22	6		T30	1		T32	2
all_values[3]	auto[0]	auto[0]	auto[1]	92	1			T29	1		T30	3		T32	2
all_values[3]	auto[0]	auto[1]	auto[0]	143	1			T22	3		T30	2		T32	2
all_values[3]	auto[0]	auto[1]	auto[1]	88	1			T30	1		T32	3		T166	1
all_values[3]	auto[1]	auto[0]	auto[1]	206	1			T22	3		T29	6		T30	1
all_values[3]	auto[1]	auto[1]	auto[1]	165	1			T22	2		T29	3		T30	3
all_values[4]	auto[0]	auto[0]	auto[0]	179	1			T22	1		T29	2		T30	5
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T22	1		T29	1		T32	3
all_values[4]	auto[0]	auto[1]	auto[0]	151	1			T22	1		T29	1		T30	3
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T22	1		T29	1		T30	1
all_values[4]	auto[1]	auto[0]	auto[1]	198	1			T22	5		T29	4		T30	2
all_values[4]	auto[1]	auto[1]	auto[1]	152	1			T22	5		T29	1		T32	1
all_values[5]	auto[0]	auto[0]	auto[0]	243	1			T22	3		T29	2		T30	4
all_values[5]	auto[0]	auto[1]	auto[0]	240	1			T22	6		T29	3		T30	3
all_values[5]	auto[1]	auto[0]	auto[1]	195	1			T22	2		T29	4		T30	3
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T22	3		T29	1		T30	1
all_values[6]	auto[0]	auto[0]	auto[0]	161	1			T22	1		T30	4		T32	3
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T22	4		T29	1		T32	1
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T22	1		T29	2		T32	4
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T29	1		T30	2		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	214	1			T22	5		T29	3		T30	4
all_values[6]	auto[1]	auto[1]	auto[1]	170	1			T22	3		T29	3		T30	1
all_values[7]	auto[0]	auto[0]	auto[0]	137	1			T22	2		T29	2		T32	2
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T22	2		T29	1		T30	1
all_values[7]	auto[0]	auto[1]	auto[0]	137	1			T22	3		T29	3		T32	3
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T22	1		T29	2		T30	2
all_values[7]	auto[1]	auto[0]	auto[1]	210	1			T29	2		T30	3		T32	6
all_values[7]	auto[1]	auto[1]	auto[1]	174	1			T22	6		T30	5		T32	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal