Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1714

1

T2

7

T8

4

T9

4

auto[1]

1751

1

T2

15

T8

4

T9

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1840

1

T2

21

T8

8

T12

24

auto[1]

1625

1

T2

1

T9

11

T12

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2727

1

T2

13

T8

6

T9

11

auto[1]

738

1

T2

9

T8

2

T12

10

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	682	1			T2	7		T8	3		T9	1
valid[1]	685	1			T2	2		T8	3		T9	1
valid[2]	686	1			T2	1		T9	4		T12	14
valid[3]	709	1			T2	9		T8	1		T9	1
valid[4]	703	1			T2	3		T8	1		T9	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	122	1			T2	2		T8	1		T12	2
auto[0]	auto[0]	valid[0]	auto[1]	147	1			T12	1		T14	1		T81	2
auto[0]	auto[0]	valid[1]	auto[0]	102	1			T2	1		T8	2		T12	3
auto[0]	auto[0]	valid[1]	auto[1]	165	1			T12	3		T15	1		T81	2
auto[0]	auto[0]	valid[2]	auto[0]	106	1			T12	3		T28	1		T20	2
auto[0]	auto[0]	valid[2]	auto[1]	145	1			T9	1		T12	1		T15	3
auto[0]	auto[0]	valid[3]	auto[0]	114	1			T12	1		T20	2		T33	2
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T2	1		T9	1		T81	5
auto[0]	auto[0]	valid[4]	auto[0]	97	1			T8	1		T20	3		T42	1
auto[0]	auto[0]	valid[4]	auto[1]	181	1			T9	2		T12	2		T25	1
auto[0]	auto[1]	valid[0]	auto[0]	97	1			T2	4		T8	2		T28	1
auto[0]	auto[1]	valid[0]	auto[1]	168	1			T9	1		T12	1		T14	1
auto[0]	auto[1]	valid[1]	auto[0]	111	1			T2	1		T33	2		T320	1
auto[0]	auto[1]	valid[1]	auto[1]	150	1			T9	1		T14	1		T15	1
auto[0]	auto[1]	valid[2]	auto[0]	117	1			T12	4		T48	2		T33	2
auto[0]	auto[1]	valid[2]	auto[1]	185	1			T9	3		T12	2		T81	1
auto[0]	auto[1]	valid[3]	auto[0]	136	1			T2	2		T12	1		T28	2
auto[0]	auto[1]	valid[3]	auto[1]	138	1			T12	2		T81	1		T82	1
auto[0]	auto[1]	valid[4]	auto[0]	100	1			T2	2		T28	1		T20	4
auto[0]	auto[1]	valid[4]	auto[1]	189	1			T9	2		T12	1		T14	1
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T12	1		T20	1		T42	1
auto[1]	auto[0]	valid[1]	auto[0]	83	1			T12	2		T48	2		T20	1
auto[1]	auto[0]	valid[2]	auto[0]	65	1			T12	4		T48	2		T20	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T2	3		T12	1		T20	2
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T48	1		T20	1		T42	1
auto[1]	auto[1]	valid[0]	auto[0]	70	1			T2	1		T17	1		T20	3
auto[1]	auto[1]	valid[1]	auto[0]	74	1			T8	1		T28	2		T20	1
auto[1]	auto[1]	valid[2]	auto[0]	68	1			T2	1		T17	1		T28	1
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T2	3		T8	1		T15	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T2	1		T12	2		T25	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal