Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48406

1

T2

373

T8

146

T12

653

auto[1]

17516

1

T2

75

T9

11

T12

132

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48171

1

T2

291

T8

108

T9

11

auto[1]

17751

1

T2

157

T8

38

T12

268

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33830	1			T2	247		T8	82		T9	11
others[1]	5581	1			T2	30		T8	12		T12	62
others[2]	5674	1			T2	28		T8	10		T12	69
others[3]	6264	1			T2	28		T8	10		T12	77
interest[1]	3565	1			T2	25		T8	9		T12	54
interest[4]	22048	1			T2	155		T8	54		T9	11
interest[64]	11008	1			T2	90		T8	23		T12	129

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15614	1			T2	121		T8	63		T12	195
auto[0]	auto[0]	others[1]	2645	1			T2	18		T8	8		T12	33
auto[0]	auto[0]	others[2]	2635	1			T2	10		T8	6		T12	40
auto[0]	auto[0]	others[3]	2913	1			T2	17		T8	6		T12	33
auto[0]	auto[0]	interest[1]	1711	1			T2	13		T8	7		T12	19
auto[0]	auto[0]	interest[4]	10053	1			T2	77		T8	42		T12	133
auto[0]	auto[0]	interest[64]	5137	1			T2	37		T8	18		T12	65
auto[0]	auto[1]	others[0]	9115	1			T2	38		T9	11		T12	74
auto[0]	auto[1]	others[1]	1467	1			T2	4		T12	8		T14	9
auto[0]	auto[1]	others[2]	1460	1			T2	3		T12	13		T14	11
auto[0]	auto[1]	others[3]	1667	1			T2	4		T12	12		T14	16
auto[0]	auto[1]	interest[1]	909	1			T2	7		T12	9		T14	10
auto[0]	auto[1]	interest[4]	6077	1			T2	24		T9	11		T12	47
auto[0]	auto[1]	interest[64]	2898	1			T2	19		T12	16		T14	11
auto[1]	auto[0]	others[0]	9101	1			T2	88		T8	19		T12	125
auto[1]	auto[0]	others[1]	1469	1			T2	8		T8	4		T12	21
auto[1]	auto[0]	others[2]	1579	1			T2	15		T8	4		T12	16
auto[1]	auto[0]	others[3]	1684	1			T2	7		T8	4		T12	32
auto[1]	auto[0]	interest[1]	945	1			T2	5		T8	2		T12	26
auto[1]	auto[0]	interest[4]	5918	1			T2	54		T8	12		T12	78
auto[1]	auto[0]	interest[64]	2973	1			T2	34		T8	5		T12	48

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal