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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
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T114 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3046148313 Jul 04 05:54:21 PM PDT 24 Jul 04 05:54:28 PM PDT 24 904005084 ps
T1036 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1154621143 Jul 04 05:54:24 PM PDT 24 Jul 04 05:54:26 PM PDT 24 96372361 ps
T112 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3576758267 Jul 04 05:54:27 PM PDT 24 Jul 04 05:54:29 PM PDT 24 56976829 ps
T1037 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3345364780 Jul 04 05:54:20 PM PDT 24 Jul 04 05:54:21 PM PDT 24 57650919 ps
T120 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2679108600 Jul 04 05:54:10 PM PDT 24 Jul 04 05:54:13 PM PDT 24 117384917 ps
T106 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4130211666 Jul 04 05:54:25 PM PDT 24 Jul 04 05:54:27 PM PDT 24 75838900 ps
T1038 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1889136811 Jul 04 05:54:22 PM PDT 24 Jul 04 05:54:23 PM PDT 24 18148181 ps
T145 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1873859230 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:36 PM PDT 24 536095657 ps
T1039 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1767912775 Jul 04 05:54:05 PM PDT 24 Jul 04 05:54:13 PM PDT 24 392091295 ps
T146 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1530670459 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:57 PM PDT 24 1047325945 ps
T1040 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2153025932 Jul 04 05:54:34 PM PDT 24 Jul 04 05:54:35 PM PDT 24 43034020 ps
T77 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4066685732 Jul 04 05:54:06 PM PDT 24 Jul 04 05:54:07 PM PDT 24 21471477 ps
T1041 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1633608855 Jul 04 05:54:04 PM PDT 24 Jul 04 05:54:05 PM PDT 24 11724766 ps
T1042 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3567324958 Jul 04 05:54:33 PM PDT 24 Jul 04 05:54:34 PM PDT 24 58014533 ps
T121 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2442878929 Jul 04 05:54:22 PM PDT 24 Jul 04 05:54:24 PM PDT 24 134969763 ps
T1043 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3317597485 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:34 PM PDT 24 23230556 ps
T100 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4143601405 Jul 04 05:54:23 PM PDT 24 Jul 04 05:54:28 PM PDT 24 666113161 ps
T1044 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2757222076 Jul 04 05:54:18 PM PDT 24 Jul 04 05:54:27 PM PDT 24 1265932619 ps
T122 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.642857982 Jul 04 05:54:02 PM PDT 24 Jul 04 05:54:25 PM PDT 24 3782080006 ps
T1045 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1553743388 Jul 04 05:54:25 PM PDT 24 Jul 04 05:54:26 PM PDT 24 17654336 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2233175448 Jul 04 05:54:02 PM PDT 24 Jul 04 05:54:05 PM PDT 24 181023493 ps
T147 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.995933283 Jul 04 05:54:06 PM PDT 24 Jul 04 05:54:19 PM PDT 24 3578068858 ps
T110 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2563331241 Jul 04 05:54:10 PM PDT 24 Jul 04 05:54:14 PM PDT 24 292069785 ps
T148 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3685811147 Jul 04 05:54:12 PM PDT 24 Jul 04 05:54:36 PM PDT 24 1060657721 ps
T149 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3870338372 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:35 PM PDT 24 110290369 ps
T1047 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4112332040 Jul 04 05:54:33 PM PDT 24 Jul 04 05:54:41 PM PDT 24 121144922 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.662954320 Jul 04 05:54:21 PM PDT 24 Jul 04 05:54:25 PM PDT 24 117041159 ps
T1049 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3837380169 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:34 PM PDT 24 31875356 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1404527191 Jul 04 05:54:09 PM PDT 24 Jul 04 05:54:10 PM PDT 24 14603179 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.296657962 Jul 04 05:54:08 PM PDT 24 Jul 04 05:54:16 PM PDT 24 256722362 ps
T1051 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3596760334 Jul 04 05:54:39 PM PDT 24 Jul 04 05:54:40 PM PDT 24 21262360 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3472076838 Jul 04 05:54:05 PM PDT 24 Jul 04 05:54:08 PM PDT 24 50490463 ps
T177 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3042677245 Jul 04 05:54:25 PM PDT 24 Jul 04 05:54:33 PM PDT 24 571729421 ps
T125 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4187186677 Jul 04 05:54:17 PM PDT 24 Jul 04 05:54:19 PM PDT 24 522872648 ps
T126 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3686456616 Jul 04 05:54:09 PM PDT 24 Jul 04 05:54:11 PM PDT 24 17080746 ps
T107 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1203649551 Jul 04 05:54:05 PM PDT 24 Jul 04 05:54:08 PM PDT 24 180694855 ps
T1052 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4119513884 Jul 04 05:54:19 PM PDT 24 Jul 04 05:54:26 PM PDT 24 1710248883 ps
T1053 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1305217538 Jul 04 05:54:24 PM PDT 24 Jul 04 05:54:26 PM PDT 24 108436338 ps
T78 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1015523490 Jul 04 05:54:09 PM PDT 24 Jul 04 05:54:11 PM PDT 24 177606954 ps
T1054 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2951559568 Jul 04 05:54:10 PM PDT 24 Jul 04 05:54:12 PM PDT 24 124007595 ps
T101 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.361427478 Jul 04 05:54:30 PM PDT 24 Jul 04 05:54:36 PM PDT 24 194630460 ps
T1055 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3498441525 Jul 04 05:54:16 PM PDT 24 Jul 04 05:54:17 PM PDT 24 35762854 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4192668760 Jul 04 05:54:20 PM PDT 24 Jul 04 05:54:44 PM PDT 24 360827969 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3316799734 Jul 04 05:54:04 PM PDT 24 Jul 04 05:54:05 PM PDT 24 105805187 ps
T1058 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1994349254 Jul 04 05:54:11 PM PDT 24 Jul 04 05:54:19 PM PDT 24 226882374 ps
T1059 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3372983264 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:32 PM PDT 24 51461584 ps
T1060 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1798989737 Jul 04 05:54:19 PM PDT 24 Jul 04 05:54:21 PM PDT 24 160458735 ps
T1061 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.570363130 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:33 PM PDT 24 32944575 ps
T1062 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.295901315 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:33 PM PDT 24 42465436 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.576442961 Jul 04 05:54:07 PM PDT 24 Jul 04 05:54:08 PM PDT 24 183691724 ps
T1064 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.150565122 Jul 04 05:54:33 PM PDT 24 Jul 04 05:54:36 PM PDT 24 272627185 ps
T173 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2826964435 Jul 04 05:54:36 PM PDT 24 Jul 04 05:54:57 PM PDT 24 934638514 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3121922996 Jul 04 05:54:23 PM PDT 24 Jul 04 05:54:45 PM PDT 24 3277626925 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.71459667 Jul 04 05:54:04 PM PDT 24 Jul 04 05:54:28 PM PDT 24 360323232 ps
T175 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.861396476 Jul 04 05:54:22 PM PDT 24 Jul 04 05:54:37 PM PDT 24 4354203827 ps
T1067 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.287304991 Jul 04 05:54:26 PM PDT 24 Jul 04 05:54:30 PM PDT 24 133682812 ps
T1068 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3735371509 Jul 04 05:54:19 PM PDT 24 Jul 04 05:54:20 PM PDT 24 24570425 ps
T1069 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2390901471 Jul 04 05:54:17 PM PDT 24 Jul 04 05:54:20 PM PDT 24 279458859 ps
T1070 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3207665264 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:36 PM PDT 24 103813859 ps
T102 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2590431023 Jul 04 05:54:16 PM PDT 24 Jul 04 05:54:20 PM PDT 24 373523726 ps
T1071 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3248211244 Jul 04 05:54:23 PM PDT 24 Jul 04 05:54:24 PM PDT 24 21786442 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.676823926 Jul 04 05:54:01 PM PDT 24 Jul 04 05:54:16 PM PDT 24 2680019693 ps
T1073 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.646357155 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:40 PM PDT 24 112496676 ps
T1074 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3546293828 Jul 04 05:54:38 PM PDT 24 Jul 04 05:54:39 PM PDT 24 12106658 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3263901831 Jul 04 05:54:05 PM PDT 24 Jul 04 05:54:10 PM PDT 24 2611274347 ps
T104 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1949516556 Jul 04 05:54:23 PM PDT 24 Jul 04 05:54:28 PM PDT 24 213910317 ps
T1076 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.261751229 Jul 04 05:54:08 PM PDT 24 Jul 04 05:54:10 PM PDT 24 70185715 ps
T1077 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3807512488 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:32 PM PDT 24 71392238 ps
T109 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4087732037 Jul 04 05:54:26 PM PDT 24 Jul 04 05:54:30 PM PDT 24 255828404 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.114075027 Jul 04 05:54:09 PM PDT 24 Jul 04 05:54:11 PM PDT 24 33367560 ps
T1079 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3894138394 Jul 04 05:54:25 PM PDT 24 Jul 04 05:54:27 PM PDT 24 110927316 ps
T1080 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.349234507 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:33 PM PDT 24 14347968 ps
T1081 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.147867979 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:34 PM PDT 24 34412812 ps
T1082 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.458398543 Jul 04 05:54:30 PM PDT 24 Jul 04 05:54:31 PM PDT 24 62596819 ps
T1083 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3711688204 Jul 04 05:54:22 PM PDT 24 Jul 04 05:54:24 PM PDT 24 108242434 ps
T1084 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3707723266 Jul 04 05:54:21 PM PDT 24 Jul 04 05:54:23 PM PDT 24 44846427 ps
T1085 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.184111541 Jul 04 05:54:39 PM PDT 24 Jul 04 05:54:40 PM PDT 24 28021239 ps
T1086 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.542743103 Jul 04 05:54:04 PM PDT 24 Jul 04 05:54:06 PM PDT 24 150773337 ps
T1087 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1161046787 Jul 04 05:54:33 PM PDT 24 Jul 04 05:54:34 PM PDT 24 12695994 ps
T1088 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.236392101 Jul 04 05:54:18 PM PDT 24 Jul 04 05:54:21 PM PDT 24 279154389 ps
T108 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2820936902 Jul 04 05:54:21 PM PDT 24 Jul 04 05:54:25 PM PDT 24 524750668 ps
T1089 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.191671781 Jul 04 05:54:05 PM PDT 24 Jul 04 05:54:06 PM PDT 24 18447038 ps
T172 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3307596323 Jul 04 05:54:05 PM PDT 24 Jul 04 05:54:09 PM PDT 24 486313082 ps
T1090 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3129730791 Jul 04 05:54:16 PM PDT 24 Jul 04 05:54:19 PM PDT 24 175505397 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3657208963 Jul 04 05:54:03 PM PDT 24 Jul 04 05:54:05 PM PDT 24 258290046 ps
T103 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3783361533 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:36 PM PDT 24 2257993722 ps
T1092 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1480457210 Jul 04 05:54:22 PM PDT 24 Jul 04 05:54:25 PM PDT 24 218948206 ps
T1093 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2019412934 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:33 PM PDT 24 40753918 ps
T1094 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.18378389 Jul 04 05:54:34 PM PDT 24 Jul 04 05:54:38 PM PDT 24 317430213 ps
T1095 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3430865619 Jul 04 05:54:37 PM PDT 24 Jul 04 05:54:37 PM PDT 24 19307181 ps
T1096 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3186516862 Jul 04 05:54:22 PM PDT 24 Jul 04 05:54:25 PM PDT 24 481763911 ps
T1097 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.698225364 Jul 04 05:54:03 PM PDT 24 Jul 04 05:54:08 PM PDT 24 2382657568 ps
T1098 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2104262314 Jul 04 05:54:33 PM PDT 24 Jul 04 05:54:34 PM PDT 24 20906103 ps
T1099 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4015869611 Jul 04 05:54:10 PM PDT 24 Jul 04 05:54:13 PM PDT 24 289738688 ps
T1100 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.645881555 Jul 04 05:54:10 PM PDT 24 Jul 04 05:54:11 PM PDT 24 79129302 ps
T1101 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1482541981 Jul 04 05:54:05 PM PDT 24 Jul 04 05:54:08 PM PDT 24 472786397 ps
T1102 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1466609022 Jul 04 05:54:35 PM PDT 24 Jul 04 05:54:36 PM PDT 24 20966828 ps
T1103 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1261389908 Jul 04 05:54:35 PM PDT 24 Jul 04 05:54:35 PM PDT 24 31623010 ps
T1104 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.245921364 Jul 04 05:54:35 PM PDT 24 Jul 04 05:54:37 PM PDT 24 107498475 ps
T1105 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2811506035 Jul 04 05:54:04 PM PDT 24 Jul 04 05:54:05 PM PDT 24 26047679 ps
T1106 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3943389817 Jul 04 05:54:24 PM PDT 24 Jul 04 05:54:28 PM PDT 24 455313183 ps
T1107 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1824143667 Jul 04 05:54:12 PM PDT 24 Jul 04 05:54:16 PM PDT 24 1846559507 ps
T1108 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3527897541 Jul 04 05:54:16 PM PDT 24 Jul 04 05:54:20 PM PDT 24 53000778 ps
T1109 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1744092590 Jul 04 05:54:08 PM PDT 24 Jul 04 05:54:10 PM PDT 24 170343558 ps
T1110 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1515999476 Jul 04 05:54:17 PM PDT 24 Jul 04 05:54:18 PM PDT 24 50515581 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3788201599 Jul 04 05:54:02 PM PDT 24 Jul 04 05:54:06 PM PDT 24 64344064 ps
T1112 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3937597491 Jul 04 05:54:39 PM PDT 24 Jul 04 05:54:40 PM PDT 24 13755229 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2458418047 Jul 04 05:54:20 PM PDT 24 Jul 04 05:54:22 PM PDT 24 76214865 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3926785436 Jul 04 05:54:10 PM PDT 24 Jul 04 05:54:12 PM PDT 24 118496801 ps
T1115 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2088852079 Jul 04 05:54:08 PM PDT 24 Jul 04 05:54:09 PM PDT 24 20665862 ps
T1116 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2992902978 Jul 04 05:54:18 PM PDT 24 Jul 04 05:54:21 PM PDT 24 174933913 ps
T1117 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3863764652 Jul 04 05:54:05 PM PDT 24 Jul 04 05:54:17 PM PDT 24 246108967 ps
T1118 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1419693787 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:36 PM PDT 24 177587795 ps
T1119 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1418650307 Jul 04 05:54:33 PM PDT 24 Jul 04 05:54:38 PM PDT 24 106013337 ps
T1120 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3531637664 Jul 04 05:54:36 PM PDT 24 Jul 04 05:54:37 PM PDT 24 29151234 ps
T1121 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1607180689 Jul 04 05:54:28 PM PDT 24 Jul 04 05:54:29 PM PDT 24 27348799 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3802599462 Jul 04 05:54:09 PM PDT 24 Jul 04 05:54:43 PM PDT 24 546870602 ps
T1123 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3322728269 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:32 PM PDT 24 119951057 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.191441169 Jul 04 05:54:06 PM PDT 24 Jul 04 05:54:13 PM PDT 24 1181815200 ps
T1125 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2908627118 Jul 04 05:54:23 PM PDT 24 Jul 04 05:54:27 PM PDT 24 136069469 ps
T176 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4260020226 Jul 04 05:54:16 PM PDT 24 Jul 04 05:54:40 PM PDT 24 1049922371 ps
T1126 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3950790932 Jul 04 05:54:18 PM PDT 24 Jul 04 05:54:21 PM PDT 24 164120977 ps
T1127 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1104957755 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:35 PM PDT 24 826197645 ps
T1128 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.379610146 Jul 04 05:54:32 PM PDT 24 Jul 04 05:54:33 PM PDT 24 13293710 ps
T1129 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2759689371 Jul 04 05:54:33 PM PDT 24 Jul 04 05:54:34 PM PDT 24 14843186 ps
T79 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3138126658 Jul 04 05:54:07 PM PDT 24 Jul 04 05:54:09 PM PDT 24 304199641 ps
T1130 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.463261183 Jul 04 05:54:29 PM PDT 24 Jul 04 05:54:32 PM PDT 24 496658119 ps
T1131 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1202590110 Jul 04 05:54:39 PM PDT 24 Jul 04 05:54:40 PM PDT 24 61638418 ps
T1132 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1905675546 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:32 PM PDT 24 14260922 ps
T1133 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3682436638 Jul 04 05:54:18 PM PDT 24 Jul 04 05:54:21 PM PDT 24 198599158 ps
T1134 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.727842722 Jul 04 05:54:23 PM PDT 24 Jul 04 05:54:25 PM PDT 24 61474800 ps
T1135 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4164248091 Jul 04 05:54:24 PM PDT 24 Jul 04 05:54:27 PM PDT 24 296228426 ps
T1136 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.970255236 Jul 04 05:54:34 PM PDT 24 Jul 04 05:54:35 PM PDT 24 30867091 ps
T1137 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1764812273 Jul 04 05:54:06 PM PDT 24 Jul 04 05:54:08 PM PDT 24 24897763 ps
T1138 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4177048135 Jul 04 05:54:06 PM PDT 24 Jul 04 05:54:22 PM PDT 24 703540679 ps
T1139 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1182333488 Jul 04 05:54:34 PM PDT 24 Jul 04 05:54:35 PM PDT 24 14278751 ps
T1140 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1792838335 Jul 04 05:54:09 PM PDT 24 Jul 04 05:54:14 PM PDT 24 172757504 ps
T1141 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4071091967 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:33 PM PDT 24 19167213 ps
T1142 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.731147915 Jul 04 05:54:03 PM PDT 24 Jul 04 05:54:04 PM PDT 24 31692514 ps
T178 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.887100904 Jul 04 05:54:02 PM PDT 24 Jul 04 05:54:23 PM PDT 24 16070305939 ps
T1143 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.680930764 Jul 04 05:54:23 PM PDT 24 Jul 04 05:54:24 PM PDT 24 16497370 ps
T1144 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2302975509 Jul 04 05:54:03 PM PDT 24 Jul 04 05:54:05 PM PDT 24 40361057 ps
T1145 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1305434101 Jul 04 05:54:34 PM PDT 24 Jul 04 05:54:36 PM PDT 24 62809086 ps
T1146 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2621991866 Jul 04 05:54:08 PM PDT 24 Jul 04 05:54:11 PM PDT 24 53390029 ps
T80 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2366995759 Jul 04 05:54:04 PM PDT 24 Jul 04 05:54:06 PM PDT 24 35520433 ps
T1147 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.735865162 Jul 04 05:54:31 PM PDT 24 Jul 04 05:54:35 PM PDT 24 843298368 ps
T174 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2407654289 Jul 04 05:54:21 PM PDT 24 Jul 04 05:54:41 PM PDT 24 796020627 ps
T1148 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3535704902 Jul 04 05:54:25 PM PDT 24 Jul 04 05:54:27 PM PDT 24 31381566 ps
T1149 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1314521234 Jul 04 05:54:21 PM PDT 24 Jul 04 05:54:22 PM PDT 24 41054182 ps
T1150 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1880434095 Jul 04 05:54:35 PM PDT 24 Jul 04 05:54:36 PM PDT 24 180387484 ps

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2389652961
Short name T2
Test name
Test status
Simulation time 17748583384 ps
CPU time 201.37 seconds
Started Jul 04 06:17:34 PM PDT 24
Finished Jul 04 06:20:56 PM PDT 24
Peak memory 266832 kb
Host smart-5fb12cf4-9c84-4aab-a9e1-c1c922265ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389652961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2389652961
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_upload.1336185024
Short name T16
Test name
Test status
Simulation time 44731179891 ps
CPU time 9.26 seconds
Started Jul 04 06:17:32 PM PDT 24
Finished Jul 04 06:17:41 PM PDT 24
Peak memory 233888 kb
Host smart-c73174bb-aa21-443d-8e7f-695ff4f2f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336185024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1336185024
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2711294528
Short name T20
Test name
Test status
Simulation time 82682254332 ps
CPU time 758 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:29:52 PM PDT 24
Peak memory 284828 kb
Host smart-bf6ea630-15f8-4db3-8043-873958c0f7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711294528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2711294528
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4178019393
Short name T97
Test name
Test status
Simulation time 1085668055 ps
CPU time 24.03 seconds
Started Jul 04 05:54:27 PM PDT 24
Finished Jul 04 05:54:51 PM PDT 24
Peak memory 215800 kb
Host smart-b1bb439c-936e-4974-b1d4-11be2c678de7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178019393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4178019393
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2335271045
Short name T22
Test name
Test status
Simulation time 72548305734 ps
CPU time 146.54 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:20:20 PM PDT 24
Peak memory 239676 kb
Host smart-1b706d10-fc8c-4afe-b020-0dc9fdcbb92e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335271045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2335271045
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3081330075
Short name T33
Test name
Test status
Simulation time 23155743560 ps
CPU time 370.4 seconds
Started Jul 04 06:17:48 PM PDT 24
Finished Jul 04 06:23:59 PM PDT 24
Peak memory 284184 kb
Host smart-c7547f7b-57db-4644-b081-d5accd17754d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081330075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3081330075
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1025179948
Short name T65
Test name
Test status
Simulation time 18423126 ps
CPU time 0.76 seconds
Started Jul 04 06:16:48 PM PDT 24
Finished Jul 04 06:16:49 PM PDT 24
Peak memory 217060 kb
Host smart-d9dda7c0-2fe4-4927-8baa-890fd413f91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025179948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1025179948
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1772803726
Short name T17
Test name
Test status
Simulation time 168030045173 ps
CPU time 352.99 seconds
Started Jul 04 06:17:54 PM PDT 24
Finished Jul 04 06:23:47 PM PDT 24
Peak memory 257116 kb
Host smart-de10c64a-29fb-45ae-908e-86185a318193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772803726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1772803726
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3756084980
Short name T206
Test name
Test status
Simulation time 50092591910 ps
CPU time 443.58 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:26:28 PM PDT 24
Peak memory 255892 kb
Host smart-2738dc54-b1ba-4660-8359-c2dfbbb2f689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756084980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3756084980
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2989307761
Short name T42
Test name
Test status
Simulation time 184471060178 ps
CPU time 454.23 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:24:43 PM PDT 24
Peak memory 266820 kb
Host smart-895a42b5-0e83-427c-b2e4-c23c0089e8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989307761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2989307761
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.4069686349
Short name T21
Test name
Test status
Simulation time 83606280 ps
CPU time 1.22 seconds
Started Jul 04 06:16:55 PM PDT 24
Finished Jul 04 06:16:56 PM PDT 24
Peak memory 236356 kb
Host smart-cb74c49e-c3be-4df9-a901-1e48bdd78e2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069686349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4069686349
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3565908223
Short name T36
Test name
Test status
Simulation time 5049065021 ps
CPU time 22.63 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:18:35 PM PDT 24
Peak memory 233748 kb
Host smart-8cd590c7-4c2e-4545-8556-07a3470374b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565908223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3565908223
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.430369536
Short name T193
Test name
Test status
Simulation time 42298303503 ps
CPU time 134.15 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:21:54 PM PDT 24
Peak memory 266008 kb
Host smart-c6234abc-2e3d-4890-8e5d-b9dac0511604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430369536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.430369536
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4143601405
Short name T100
Test name
Test status
Simulation time 666113161 ps
CPU time 4.76 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:28 PM PDT 24
Peak memory 215736 kb
Host smart-97c04121-c984-4fac-a278-643d93859105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143601405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4143601405
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1032664456
Short name T221
Test name
Test status
Simulation time 40206172198 ps
CPU time 126.25 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:19:15 PM PDT 24
Peak memory 256248 kb
Host smart-e45559e3-0577-40a1-b660-3596980062ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032664456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1032664456
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3987845551
Short name T152
Test name
Test status
Simulation time 37726710236 ps
CPU time 245.5 seconds
Started Jul 04 06:17:48 PM PDT 24
Finished Jul 04 06:21:54 PM PDT 24
Peak memory 270140 kb
Host smart-55843dab-b63f-4b9d-9422-1edfcebc29a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987845551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3987845551
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.42945505
Short name T75
Test name
Test status
Simulation time 26961200775 ps
CPU time 112.84 seconds
Started Jul 04 06:19:40 PM PDT 24
Finished Jul 04 06:21:33 PM PDT 24
Peak memory 266788 kb
Host smart-dcdbca68-b88d-4f72-be43-f492446a8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42945505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.42945505
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2442878929
Short name T121
Test name
Test status
Simulation time 134969763 ps
CPU time 1.36 seconds
Started Jul 04 05:54:22 PM PDT 24
Finished Jul 04 05:54:24 PM PDT 24
Peak memory 207304 kb
Host smart-a95f36fb-a326-4136-9608-dc31b95650ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442878929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2442878929
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1512090531
Short name T222
Test name
Test status
Simulation time 372368128167 ps
CPU time 479.72 seconds
Started Jul 04 06:17:18 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 258488 kb
Host smart-21124e55-846c-4129-97b1-b9c27a0e3abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512090531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1512090531
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2561717001
Short name T289
Test name
Test status
Simulation time 103258372305 ps
CPU time 1141.85 seconds
Started Jul 04 06:18:22 PM PDT 24
Finished Jul 04 06:37:25 PM PDT 24
Peak memory 299552 kb
Host smart-bf9df9e6-f3ed-42d4-8084-393db1ef9c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561717001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2561717001
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4022895050
Short name T192
Test name
Test status
Simulation time 152242848181 ps
CPU time 450.94 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:25:44 PM PDT 24
Peak memory 273712 kb
Host smart-6db10b1d-1c07-404c-bf9b-488da360b59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022895050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4022895050
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2592968541
Short name T518
Test name
Test status
Simulation time 40642693 ps
CPU time 0.96 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:17:26 PM PDT 24
Peak memory 217660 kb
Host smart-fb017d5f-72d8-40db-b6a6-315d86b2c3f0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592968541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2592968541
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2318554998
Short name T12
Test name
Test status
Simulation time 39971204310 ps
CPU time 306.79 seconds
Started Jul 04 06:18:31 PM PDT 24
Finished Jul 04 06:23:38 PM PDT 24
Peak memory 267764 kb
Host smart-dfbc9d92-8514-4088-b9f1-26f3a4a293d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318554998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2318554998
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2899951562
Short name T214
Test name
Test status
Simulation time 7563145676 ps
CPU time 53.04 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:18:02 PM PDT 24
Peak memory 263976 kb
Host smart-993d06e3-6367-4525-911b-4d177939ddf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899951562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2899951562
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1230160280
Short name T217
Test name
Test status
Simulation time 27583963763 ps
CPU time 224.61 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:22:52 PM PDT 24
Peak memory 255028 kb
Host smart-bc0693ca-9697-4ab5-aec3-2a1d79bdc42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230160280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1230160280
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1766171787
Short name T188
Test name
Test status
Simulation time 63242094208 ps
CPU time 234.88 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:21:23 PM PDT 24
Peak memory 250912 kb
Host smart-ece0c994-b5e0-41fe-a146-673f7fdd11a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766171787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1766171787
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1072578849
Short name T330
Test name
Test status
Simulation time 38042104 ps
CPU time 0.72 seconds
Started Jul 04 06:17:37 PM PDT 24
Finished Jul 04 06:17:38 PM PDT 24
Peak memory 206388 kb
Host smart-3c317008-fbd2-4a7c-92d3-a075428de1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072578849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1072578849
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2635536952
Short name T150
Test name
Test status
Simulation time 71917545583 ps
CPU time 92.69 seconds
Started Jul 04 06:18:51 PM PDT 24
Finished Jul 04 06:20:24 PM PDT 24
Peak memory 250432 kb
Host smart-883a38ed-9075-4082-839f-b4fba3c4fa54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635536952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2635536952
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2992032783
Short name T45
Test name
Test status
Simulation time 13718563566 ps
CPU time 94.35 seconds
Started Jul 04 06:18:15 PM PDT 24
Finished Jul 04 06:19:49 PM PDT 24
Peak memory 255032 kb
Host smart-3eea253e-782c-49e4-bed2-db3397b31035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992032783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2992032783
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2164019996
Short name T49
Test name
Test status
Simulation time 71243304773 ps
CPU time 669.62 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:28:37 PM PDT 24
Peak memory 258528 kb
Host smart-1b95bf98-2876-4484-98e3-890d994552eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164019996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2164019996
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2826964435
Short name T173
Test name
Test status
Simulation time 934638514 ps
CPU time 20.51 seconds
Started Jul 04 05:54:36 PM PDT 24
Finished Jul 04 05:54:57 PM PDT 24
Peak memory 215572 kb
Host smart-67820f2b-6d9a-45c6-b5cd-15d07cb2933e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826964435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2826964435
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1824143667
Short name T1107
Test name
Test status
Simulation time 1846559507 ps
CPU time 4.45 seconds
Started Jul 04 05:54:12 PM PDT 24
Finished Jul 04 05:54:16 PM PDT 24
Peak memory 215568 kb
Host smart-22ed213a-90dd-439d-8a4f-876003c77c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824143667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
824143667
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1185604027
Short name T180
Test name
Test status
Simulation time 2077855660 ps
CPU time 35.63 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:17:27 PM PDT 24
Peak memory 250980 kb
Host smart-8f2ffdec-1d77-4858-92db-b72d5d5bf80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185604027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1185604027
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2710656687
Short name T186
Test name
Test status
Simulation time 66566248447 ps
CPU time 321.1 seconds
Started Jul 04 06:17:41 PM PDT 24
Finished Jul 04 06:23:03 PM PDT 24
Peak memory 254084 kb
Host smart-4f5b3fb0-3110-4597-90ff-2ee540d1f61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710656687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2710656687
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.421170997
Short name T205
Test name
Test status
Simulation time 9795217826 ps
CPU time 157.36 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:21:42 PM PDT 24
Peak memory 251508 kb
Host smart-2b7482c5-6e23-4fc8-a310-6ab925def76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421170997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.421170997
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1365050482
Short name T136
Test name
Test status
Simulation time 471622351608 ps
CPU time 787.63 seconds
Started Jul 04 06:19:47 PM PDT 24
Finished Jul 04 06:32:55 PM PDT 24
Peak memory 270472 kb
Host smart-2b064591-32ab-4280-a232-fc8405218c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365050482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1365050482
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3237041151
Short name T47
Test name
Test status
Simulation time 154730747 ps
CPU time 5.54 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:17:04 PM PDT 24
Peak memory 238468 kb
Host smart-b2b64326-50f8-4647-8535-01770afd5004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237041151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3237041151
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.192966668
Short name T195
Test name
Test status
Simulation time 48492813271 ps
CPU time 151.41 seconds
Started Jul 04 06:18:11 PM PDT 24
Finished Jul 04 06:20:43 PM PDT 24
Peak memory 258508 kb
Host smart-33768d70-ad28-4c92-b0d4-1a6887cd248b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192966668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.192966668
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2033763816
Short name T141
Test name
Test status
Simulation time 11128407648 ps
CPU time 41.54 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:55 PM PDT 24
Peak memory 240744 kb
Host smart-815550bb-bebf-41b3-9318-40e7902a9e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033763816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2033763816
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1660527484
Short name T38
Test name
Test status
Simulation time 937302286 ps
CPU time 26.62 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:42 PM PDT 24
Peak memory 238596 kb
Host smart-fe979dfa-d619-4bd7-b3fd-723fc6ba929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660527484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1660527484
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1906062541
Short name T94
Test name
Test status
Simulation time 62297906 ps
CPU time 4.02 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:37 PM PDT 24
Peak memory 215692 kb
Host smart-4b01bbe1-f06b-4745-a536-7b338b448288
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906062541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1906062541
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2499763088
Short name T52
Test name
Test status
Simulation time 25329782248 ps
CPU time 282.71 seconds
Started Jul 04 06:16:49 PM PDT 24
Finished Jul 04 06:21:31 PM PDT 24
Peak memory 258476 kb
Host smart-950618c4-bbcd-4e79-b179-f6dff91ebe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499763088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2499763088
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.608366850
Short name T695
Test name
Test status
Simulation time 815184089 ps
CPU time 19.03 seconds
Started Jul 04 06:17:45 PM PDT 24
Finished Jul 04 06:18:04 PM PDT 24
Peak memory 242020 kb
Host smart-4b762f8b-1e08-434d-b102-752040b076c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608366850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.608366850
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1907886129
Short name T323
Test name
Test status
Simulation time 19102709587 ps
CPU time 46.73 seconds
Started Jul 04 06:18:10 PM PDT 24
Finished Jul 04 06:18:57 PM PDT 24
Peak memory 240056 kb
Host smart-06af37f2-420c-44a0-8fd7-c7fd7bb7df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907886129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1907886129
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1369505197
Short name T211
Test name
Test status
Simulation time 23155951279 ps
CPU time 213.55 seconds
Started Jul 04 06:18:29 PM PDT 24
Finished Jul 04 06:22:03 PM PDT 24
Peak memory 242248 kb
Host smart-3a95b424-d579-418e-aff2-4ede17eb2509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369505197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1369505197
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2058686462
Short name T771
Test name
Test status
Simulation time 12732272294 ps
CPU time 71.48 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:20:16 PM PDT 24
Peak memory 245048 kb
Host smart-a0251f17-06c7-4d51-90e6-78548b3a8151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058686462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2058686462
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2577721684
Short name T243
Test name
Test status
Simulation time 1103687251 ps
CPU time 9.93 seconds
Started Jul 04 06:16:49 PM PDT 24
Finished Jul 04 06:16:59 PM PDT 24
Peak memory 233772 kb
Host smart-529eca12-61a7-403b-b910-964d1d48f088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577721684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2577721684
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2366995759
Short name T80
Test name
Test status
Simulation time 35520433 ps
CPU time 1.19 seconds
Started Jul 04 05:54:04 PM PDT 24
Finished Jul 04 05:54:06 PM PDT 24
Peak memory 207348 kb
Host smart-2f0f0aeb-61fe-4b9d-b492-9bf95acfe614
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366995759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2366995759
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.642857982
Short name T122
Test name
Test status
Simulation time 3782080006 ps
CPU time 22.12 seconds
Started Jul 04 05:54:02 PM PDT 24
Finished Jul 04 05:54:25 PM PDT 24
Peak memory 215592 kb
Host smart-cdd7e0ac-cad8-487a-9af0-52ab204f4a1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642857982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.642857982
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.995933283
Short name T147
Test name
Test status
Simulation time 3578068858 ps
CPU time 12.71 seconds
Started Jul 04 05:54:06 PM PDT 24
Finished Jul 04 05:54:19 PM PDT 24
Peak memory 207372 kb
Host smart-57df98f4-c1f9-4179-bf72-0755382d7efa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995933283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.995933283
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1764812273
Short name T1137
Test name
Test status
Simulation time 24897763 ps
CPU time 1.55 seconds
Started Jul 04 05:54:06 PM PDT 24
Finished Jul 04 05:54:08 PM PDT 24
Peak memory 215556 kb
Host smart-88fe3cb2-c400-4de1-847b-d622ace63847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764812273 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1764812273
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2302975509
Short name T1144
Test name
Test status
Simulation time 40361057 ps
CPU time 1.4 seconds
Started Jul 04 05:54:03 PM PDT 24
Finished Jul 04 05:54:05 PM PDT 24
Peak memory 207292 kb
Host smart-ffbf5b8e-9253-4614-842b-6fc879d8186c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302975509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
302975509
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.191671781
Short name T1089
Test name
Test status
Simulation time 18447038 ps
CPU time 0.77 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:06 PM PDT 24
Peak memory 204280 kb
Host smart-4244554c-e3fb-4845-8b1d-5bf4d179da12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191671781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.191671781
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.542743103
Short name T1086
Test name
Test status
Simulation time 150773337 ps
CPU time 1.68 seconds
Started Jul 04 05:54:04 PM PDT 24
Finished Jul 04 05:54:06 PM PDT 24
Peak memory 215596 kb
Host smart-54b7c0f5-efb7-4b74-9792-22d861a8a12c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542743103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.542743103
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2811506035
Short name T1105
Test name
Test status
Simulation time 26047679 ps
CPU time 0.69 seconds
Started Jul 04 05:54:04 PM PDT 24
Finished Jul 04 05:54:05 PM PDT 24
Peak memory 203896 kb
Host smart-964cea70-3c21-4f0b-b0a3-a37daf4216b0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811506035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2811506035
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3263901831
Short name T1075
Test name
Test status
Simulation time 2611274347 ps
CPU time 4.52 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:10 PM PDT 24
Peak memory 215648 kb
Host smart-b4cb9fe7-485c-45d2-9bb3-6c0f54b8d562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263901831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3263901831
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.698225364
Short name T1097
Test name
Test status
Simulation time 2382657568 ps
CPU time 4.85 seconds
Started Jul 04 05:54:03 PM PDT 24
Finished Jul 04 05:54:08 PM PDT 24
Peak memory 215756 kb
Host smart-086f011c-12b9-4187-87e9-c0b0968b4bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698225364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.698225364
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.676823926
Short name T1072
Test name
Test status
Simulation time 2680019693 ps
CPU time 14.65 seconds
Started Jul 04 05:54:01 PM PDT 24
Finished Jul 04 05:54:16 PM PDT 24
Peak memory 215912 kb
Host smart-a42628da-2395-44dd-8021-a05c936a35fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676823926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.676823926
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1767912775
Short name T1039
Test name
Test status
Simulation time 392091295 ps
CPU time 7.76 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:13 PM PDT 24
Peak memory 215424 kb
Host smart-3203a526-0ba5-4a42-bccf-f13a7fa55aaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767912775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1767912775
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3863764652
Short name T1117
Test name
Test status
Simulation time 246108967 ps
CPU time 11.18 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:17 PM PDT 24
Peak memory 207388 kb
Host smart-76ce8dbf-4ec7-47ea-a1b7-0ef4c2f009e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863764652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3863764652
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4066685732
Short name T77
Test name
Test status
Simulation time 21471477 ps
CPU time 1.05 seconds
Started Jul 04 05:54:06 PM PDT 24
Finished Jul 04 05:54:07 PM PDT 24
Peak memory 207116 kb
Host smart-9b9ad476-72b4-4bd0-9812-7af4e3593025
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066685732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.4066685732
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3307596323
Short name T172
Test name
Test status
Simulation time 486313082 ps
CPU time 3.56 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:09 PM PDT 24
Peak memory 216844 kb
Host smart-53e797b5-e731-468f-9702-2e49264c43de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307596323 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3307596323
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3657208963
Short name T1091
Test name
Test status
Simulation time 258290046 ps
CPU time 2.1 seconds
Started Jul 04 05:54:03 PM PDT 24
Finished Jul 04 05:54:05 PM PDT 24
Peak memory 215456 kb
Host smart-0c025124-6637-4896-b4d8-36390848c0ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657208963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
657208963
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1446101951
Short name T1033
Test name
Test status
Simulation time 12049749 ps
CPU time 0.74 seconds
Started Jul 04 05:54:04 PM PDT 24
Finished Jul 04 05:54:05 PM PDT 24
Peak memory 203952 kb
Host smart-a672e14b-7d8f-44bf-a9d4-3513d0854b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446101951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
446101951
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.576442961
Short name T1063
Test name
Test status
Simulation time 183691724 ps
CPU time 1.19 seconds
Started Jul 04 05:54:07 PM PDT 24
Finished Jul 04 05:54:08 PM PDT 24
Peak memory 215564 kb
Host smart-b624a486-6c48-4d9d-80f8-6f4c194c5256
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576442961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.576442961
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1633608855
Short name T1041
Test name
Test status
Simulation time 11724766 ps
CPU time 0.73 seconds
Started Jul 04 05:54:04 PM PDT 24
Finished Jul 04 05:54:05 PM PDT 24
Peak memory 204220 kb
Host smart-a27ce050-ab34-47a7-830c-4299d9e06fb9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633608855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1633608855
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3788201599
Short name T1111
Test name
Test status
Simulation time 64344064 ps
CPU time 3.87 seconds
Started Jul 04 05:54:02 PM PDT 24
Finished Jul 04 05:54:06 PM PDT 24
Peak memory 215536 kb
Host smart-c05b7bc2-8698-40d1-bbc1-9a7081b0a46f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788201599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3788201599
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1482541981
Short name T1101
Test name
Test status
Simulation time 472786397 ps
CPU time 3.27 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:08 PM PDT 24
Peak memory 215808 kb
Host smart-dc8c1973-8717-45d7-8d53-63f969aff53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482541981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
482541981
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.887100904
Short name T178
Test name
Test status
Simulation time 16070305939 ps
CPU time 19.95 seconds
Started Jul 04 05:54:02 PM PDT 24
Finished Jul 04 05:54:23 PM PDT 24
Peak memory 215840 kb
Host smart-e75e477c-a5fb-4476-bdf2-eb519ca42c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887100904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.887100904
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1305217538
Short name T1053
Test name
Test status
Simulation time 108436338 ps
CPU time 1.93 seconds
Started Jul 04 05:54:24 PM PDT 24
Finished Jul 04 05:54:26 PM PDT 24
Peak memory 215684 kb
Host smart-cb64560b-4155-4015-9df1-0c8d5ec5fd5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305217538 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1305217538
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1889136811
Short name T1038
Test name
Test status
Simulation time 18148181 ps
CPU time 0.8 seconds
Started Jul 04 05:54:22 PM PDT 24
Finished Jul 04 05:54:23 PM PDT 24
Peak memory 204032 kb
Host smart-351e67a0-40c1-4479-b4bc-cb52d4b61193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889136811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1889136811
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.727842722
Short name T1134
Test name
Test status
Simulation time 61474800 ps
CPU time 1.9 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:25 PM PDT 24
Peak memory 215556 kb
Host smart-4c7c3f71-d783-441b-8c6f-b144fe76c2d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727842722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.727842722
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1480457210
Short name T1092
Test name
Test status
Simulation time 218948206 ps
CPU time 2.52 seconds
Started Jul 04 05:54:22 PM PDT 24
Finished Jul 04 05:54:25 PM PDT 24
Peak memory 215752 kb
Host smart-296c7f70-2dab-4808-ad3f-e23f81986328
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480457210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1480457210
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.180942510
Short name T93
Test name
Test status
Simulation time 116327884 ps
CPU time 6.77 seconds
Started Jul 04 05:54:25 PM PDT 24
Finished Jul 04 05:54:32 PM PDT 24
Peak memory 215488 kb
Host smart-66778f5b-9ea1-41a2-bbf3-1d3b5e83ce6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180942510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.180942510
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4087732037
Short name T109
Test name
Test status
Simulation time 255828404 ps
CPU time 3.66 seconds
Started Jul 04 05:54:26 PM PDT 24
Finished Jul 04 05:54:30 PM PDT 24
Peak memory 216816 kb
Host smart-cfecb185-4546-4ce4-864a-38f186209442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087732037 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4087732037
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4164248091
Short name T1135
Test name
Test status
Simulation time 296228426 ps
CPU time 2.18 seconds
Started Jul 04 05:54:24 PM PDT 24
Finished Jul 04 05:54:27 PM PDT 24
Peak memory 215556 kb
Host smart-deab2670-e76b-4309-a82c-ffd2634cd5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164248091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4164248091
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1553743388
Short name T1045
Test name
Test status
Simulation time 17654336 ps
CPU time 0.79 seconds
Started Jul 04 05:54:25 PM PDT 24
Finished Jul 04 05:54:26 PM PDT 24
Peak memory 204052 kb
Host smart-22265ff6-d0ca-45c1-b202-21bd5dd12476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553743388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1553743388
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3894138394
Short name T1079
Test name
Test status
Simulation time 110927316 ps
CPU time 1.98 seconds
Started Jul 04 05:54:25 PM PDT 24
Finished Jul 04 05:54:27 PM PDT 24
Peak memory 215536 kb
Host smart-a27b7050-a2d6-4983-8298-50f9b3ad239b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894138394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3894138394
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1949516556
Short name T104
Test name
Test status
Simulation time 213910317 ps
CPU time 4.66 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:28 PM PDT 24
Peak memory 215704 kb
Host smart-c4e4f0af-c2ff-4f34-9e3e-c62b21132e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949516556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1949516556
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3121922996
Short name T1065
Test name
Test status
Simulation time 3277626925 ps
CPU time 22.37 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:45 PM PDT 24
Peak memory 215616 kb
Host smart-bd7b3fb0-2279-4b4a-ae07-854242adf106
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121922996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3121922996
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3576758267
Short name T112
Test name
Test status
Simulation time 56976829 ps
CPU time 1.86 seconds
Started Jul 04 05:54:27 PM PDT 24
Finished Jul 04 05:54:29 PM PDT 24
Peak memory 215388 kb
Host smart-b1b65174-7254-4a49-bd8c-798d75241e19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576758267 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3576758267
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.381883245
Short name T118
Test name
Test status
Simulation time 278765657 ps
CPU time 2.54 seconds
Started Jul 04 05:54:25 PM PDT 24
Finished Jul 04 05:54:28 PM PDT 24
Peak memory 215492 kb
Host smart-eb214c33-5808-4d4b-a8ba-82a26ecc2844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381883245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.381883245
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.17648938
Short name T1027
Test name
Test status
Simulation time 14290874 ps
CPU time 0.79 seconds
Started Jul 04 05:54:24 PM PDT 24
Finished Jul 04 05:54:25 PM PDT 24
Peak memory 203944 kb
Host smart-757585cd-ff67-4b94-811f-c618ae475198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17648938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.17648938
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3186516862
Short name T1096
Test name
Test status
Simulation time 481763911 ps
CPU time 2.88 seconds
Started Jul 04 05:54:22 PM PDT 24
Finished Jul 04 05:54:25 PM PDT 24
Peak memory 215464 kb
Host smart-65174211-93aa-432a-9794-1aa61439a502
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186516862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3186516862
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2608683134
Short name T113
Test name
Test status
Simulation time 464613558 ps
CPU time 17.2 seconds
Started Jul 04 05:54:20 PM PDT 24
Finished Jul 04 05:54:37 PM PDT 24
Peak memory 215552 kb
Host smart-909f7adc-e412-45bf-ba16-58dba7633bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608683134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2608683134
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3535704902
Short name T1148
Test name
Test status
Simulation time 31381566 ps
CPU time 1.71 seconds
Started Jul 04 05:54:25 PM PDT 24
Finished Jul 04 05:54:27 PM PDT 24
Peak memory 215600 kb
Host smart-87739fd2-118b-4975-9511-861f6a207312
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535704902 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3535704902
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3707723266
Short name T1084
Test name
Test status
Simulation time 44846427 ps
CPU time 1.44 seconds
Started Jul 04 05:54:21 PM PDT 24
Finished Jul 04 05:54:23 PM PDT 24
Peak memory 215472 kb
Host smart-f91cb287-985d-4792-b4cf-e44f0c52849f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707723266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3707723266
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3248211244
Short name T1071
Test name
Test status
Simulation time 21786442 ps
CPU time 0.77 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:24 PM PDT 24
Peak memory 203932 kb
Host smart-820c75c3-b9d1-4e05-8fa8-caae2331e553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248211244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3248211244
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1154621143
Short name T1036
Test name
Test status
Simulation time 96372361 ps
CPU time 1.69 seconds
Started Jul 04 05:54:24 PM PDT 24
Finished Jul 04 05:54:26 PM PDT 24
Peak memory 207220 kb
Host smart-fce0c531-f340-43cc-b708-fc3cba0cb191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154621143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1154621143
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3943389817
Short name T1106
Test name
Test status
Simulation time 455313183 ps
CPU time 3.21 seconds
Started Jul 04 05:54:24 PM PDT 24
Finished Jul 04 05:54:28 PM PDT 24
Peak memory 215668 kb
Host smart-bca7f287-fc23-496c-b924-18044bffe076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943389817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3943389817
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3042677245
Short name T177
Test name
Test status
Simulation time 571729421 ps
CPU time 8 seconds
Started Jul 04 05:54:25 PM PDT 24
Finished Jul 04 05:54:33 PM PDT 24
Peak memory 215532 kb
Host smart-10847a73-f613-4d26-bdc7-791c5c00cf60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042677245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3042677245
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2458418047
Short name T1113
Test name
Test status
Simulation time 76214865 ps
CPU time 1.72 seconds
Started Jul 04 05:54:20 PM PDT 24
Finished Jul 04 05:54:22 PM PDT 24
Peak memory 215560 kb
Host smart-ab098a62-a8ab-484f-959c-a4ca7b649a98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458418047 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2458418047
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3711688204
Short name T1083
Test name
Test status
Simulation time 108242434 ps
CPU time 2.52 seconds
Started Jul 04 05:54:22 PM PDT 24
Finished Jul 04 05:54:24 PM PDT 24
Peak memory 215544 kb
Host smart-a15e0c06-09c5-4ba0-bd59-b4096a149012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711688204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3711688204
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.680930764
Short name T1143
Test name
Test status
Simulation time 16497370 ps
CPU time 0.76 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:24 PM PDT 24
Peak memory 204048 kb
Host smart-15039cf0-7750-4ef3-8f18-5691a817e4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680930764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.680930764
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2822168547
Short name T1029
Test name
Test status
Simulation time 61461924 ps
CPU time 3.86 seconds
Started Jul 04 05:54:26 PM PDT 24
Finished Jul 04 05:54:30 PM PDT 24
Peak memory 215472 kb
Host smart-6138833c-abb9-4511-b5c4-eb1f20dbfa20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822168547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2822168547
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4130211666
Short name T106
Test name
Test status
Simulation time 75838900 ps
CPU time 2.2 seconds
Started Jul 04 05:54:25 PM PDT 24
Finished Jul 04 05:54:27 PM PDT 24
Peak memory 215760 kb
Host smart-7337756f-69fa-4eaf-8abc-2b084c95b2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130211666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4130211666
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.861396476
Short name T175
Test name
Test status
Simulation time 4354203827 ps
CPU time 14.7 seconds
Started Jul 04 05:54:22 PM PDT 24
Finished Jul 04 05:54:37 PM PDT 24
Peak memory 215616 kb
Host smart-4769ba0d-7cde-48c0-b4be-ad57c5c38a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861396476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.861396476
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1419693787
Short name T1118
Test name
Test status
Simulation time 177587795 ps
CPU time 3.42 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 217344 kb
Host smart-bb4865ab-b708-421f-bfbe-cafedeb0edac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419693787 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1419693787
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1076091279
Short name T116
Test name
Test status
Simulation time 78281006 ps
CPU time 2.4 seconds
Started Jul 04 05:54:24 PM PDT 24
Finished Jul 04 05:54:27 PM PDT 24
Peak memory 207380 kb
Host smart-141ea6f5-7625-47a7-9023-0722f44dc630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076091279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1076091279
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.832181081
Short name T1031
Test name
Test status
Simulation time 16910570 ps
CPU time 0.76 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:24 PM PDT 24
Peak memory 204056 kb
Host smart-b2c0415d-d399-48a3-8a33-7fd651db43e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832181081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.832181081
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.735865162
Short name T1147
Test name
Test status
Simulation time 843298368 ps
CPU time 4.27 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 215536 kb
Host smart-82fb88c4-781f-4e29-8832-47b3c12c2979
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735865162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.735865162
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2995496391
Short name T105
Test name
Test status
Simulation time 275695157 ps
CPU time 3.93 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:27 PM PDT 24
Peak memory 215740 kb
Host smart-c1ee8f8b-a38b-47dc-815a-c093f83836e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995496391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2995496391
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3870338372
Short name T149
Test name
Test status
Simulation time 110290369 ps
CPU time 3.08 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 217052 kb
Host smart-fe617452-85c0-4e66-8a18-e9c37b0dc3bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870338372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3870338372
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2019412934
Short name T1093
Test name
Test status
Simulation time 40753918 ps
CPU time 2.05 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:33 PM PDT 24
Peak memory 215568 kb
Host smart-e62e6c5c-8b47-42a9-b59b-51d897ebf483
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019412934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2019412934
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1905675546
Short name T1132
Test name
Test status
Simulation time 14260922 ps
CPU time 0.73 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:32 PM PDT 24
Peak memory 204040 kb
Host smart-27875791-e346-40fe-a71e-334a01e27b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905675546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1905675546
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.245921364
Short name T1104
Test name
Test status
Simulation time 107498475 ps
CPU time 1.88 seconds
Started Jul 04 05:54:35 PM PDT 24
Finished Jul 04 05:54:37 PM PDT 24
Peak memory 215484 kb
Host smart-9d64ed48-9ebe-42f6-97b7-d2d07c456c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245921364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.245921364
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.361427478
Short name T101
Test name
Test status
Simulation time 194630460 ps
CPU time 5.22 seconds
Started Jul 04 05:54:30 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 215656 kb
Host smart-4c91f724-d815-4368-a590-0b25c139145c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361427478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.361427478
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1530670459
Short name T146
Test name
Test status
Simulation time 1047325945 ps
CPU time 24.74 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:57 PM PDT 24
Peak memory 215492 kb
Host smart-f7406ee1-0677-4118-b0e3-71f56c37f620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530670459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1530670459
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1418650307
Short name T1119
Test name
Test status
Simulation time 106013337 ps
CPU time 4.26 seconds
Started Jul 04 05:54:33 PM PDT 24
Finished Jul 04 05:54:38 PM PDT 24
Peak memory 216592 kb
Host smart-07ac7cf1-f858-4102-b306-93394734a53c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418650307 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1418650307
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3308251784
Short name T117
Test name
Test status
Simulation time 38108071 ps
CPU time 1.4 seconds
Started Jul 04 05:54:34 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 215460 kb
Host smart-4203e439-9bf2-4e59-abd4-d1ec42f7ada2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308251784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3308251784
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3322728269
Short name T1123
Test name
Test status
Simulation time 119951057 ps
CPU time 0.69 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:32 PM PDT 24
Peak memory 204272 kb
Host smart-412fc904-b793-4616-892f-a6a7fdad8465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322728269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3322728269
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1104957755
Short name T1127
Test name
Test status
Simulation time 826197645 ps
CPU time 4.3 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 215456 kb
Host smart-389e8f8e-8d9d-4049-a716-cdeec9b40aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104957755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1104957755
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3783361533
Short name T103
Test name
Test status
Simulation time 2257993722 ps
CPU time 3.9 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 215800 kb
Host smart-eff3c8d9-1655-40e1-ac63-dde8e5813bff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783361533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3783361533
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.646357155
Short name T1073
Test name
Test status
Simulation time 112496676 ps
CPU time 7.33 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:40 PM PDT 24
Peak memory 215512 kb
Host smart-956a917a-c7a8-4de2-875d-054f190beae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646357155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.646357155
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3207665264
Short name T1070
Test name
Test status
Simulation time 103813859 ps
CPU time 2.83 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 216652 kb
Host smart-e5d32a17-8491-44e4-b800-5dcfa78d712b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207665264 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3207665264
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1305434101
Short name T1145
Test name
Test status
Simulation time 62809086 ps
CPU time 1.2 seconds
Started Jul 04 05:54:34 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 207344 kb
Host smart-34c8ae32-24d1-4fd2-a141-88e68d9c0b80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305434101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1305434101
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.184111541
Short name T1085
Test name
Test status
Simulation time 28021239 ps
CPU time 0.74 seconds
Started Jul 04 05:54:39 PM PDT 24
Finished Jul 04 05:54:40 PM PDT 24
Peak memory 204304 kb
Host smart-3201f369-0cab-4ddc-b231-c61523270f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184111541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.184111541
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1873859230
Short name T145
Test name
Test status
Simulation time 536095657 ps
CPU time 3.08 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 215552 kb
Host smart-b23ba39d-7d4e-4382-9dd6-e4336a764350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873859230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1873859230
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.463261183
Short name T1130
Test name
Test status
Simulation time 496658119 ps
CPU time 3.59 seconds
Started Jul 04 05:54:29 PM PDT 24
Finished Jul 04 05:54:32 PM PDT 24
Peak memory 215756 kb
Host smart-12fd9416-f438-42de-a769-276ceb57266e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463261183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.463261183
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4112332040
Short name T1047
Test name
Test status
Simulation time 121144922 ps
CPU time 7.23 seconds
Started Jul 04 05:54:33 PM PDT 24
Finished Jul 04 05:54:41 PM PDT 24
Peak memory 215524 kb
Host smart-37e6cdbd-be4e-46ab-96af-0f8aac8f809d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112332040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4112332040
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.18378389
Short name T1094
Test name
Test status
Simulation time 317430213 ps
CPU time 3.72 seconds
Started Jul 04 05:54:34 PM PDT 24
Finished Jul 04 05:54:38 PM PDT 24
Peak memory 217992 kb
Host smart-93ce3a71-59aa-48ad-8f9a-13b401d088b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378389 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.18378389
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.147867979
Short name T1081
Test name
Test status
Simulation time 34412812 ps
CPU time 1.22 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:34 PM PDT 24
Peak memory 207368 kb
Host smart-4a0ecd3e-8e03-4cb1-b7b9-a778a745e22f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147867979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.147867979
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1182333488
Short name T1139
Test name
Test status
Simulation time 14278751 ps
CPU time 0.77 seconds
Started Jul 04 05:54:34 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 204260 kb
Host smart-54cbd447-417a-4612-9780-f798da52e8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182333488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1182333488
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.150565122
Short name T1064
Test name
Test status
Simulation time 272627185 ps
CPU time 3.14 seconds
Started Jul 04 05:54:33 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 207324 kb
Host smart-b4832123-3269-4599-9c65-7eff5e8cdcbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150565122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.150565122
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4177048135
Short name T1138
Test name
Test status
Simulation time 703540679 ps
CPU time 15.87 seconds
Started Jul 04 05:54:06 PM PDT 24
Finished Jul 04 05:54:22 PM PDT 24
Peak memory 215496 kb
Host smart-4f23964a-df7a-4bcd-922e-2582d917a8c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177048135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4177048135
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.71459667
Short name T1066
Test name
Test status
Simulation time 360323232 ps
CPU time 23.6 seconds
Started Jul 04 05:54:04 PM PDT 24
Finished Jul 04 05:54:28 PM PDT 24
Peak memory 207332 kb
Host smart-8203443d-58d5-4f84-b09c-cd538f28c9e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71459667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
bit_bash.71459667
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3138126658
Short name T79
Test name
Test status
Simulation time 304199641 ps
CPU time 1.3 seconds
Started Jul 04 05:54:07 PM PDT 24
Finished Jul 04 05:54:09 PM PDT 24
Peak memory 216568 kb
Host smart-50123ae1-7588-4ec8-b8fa-62b1a6291e80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138126658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3138126658
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2805730137
Short name T111
Test name
Test status
Simulation time 317940313 ps
CPU time 2.7 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:08 PM PDT 24
Peak memory 218032 kb
Host smart-0f92a77f-9ed7-422e-84ec-0edc05800433
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805730137 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2805730137
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2233175448
Short name T1046
Test name
Test status
Simulation time 181023493 ps
CPU time 2.67 seconds
Started Jul 04 05:54:02 PM PDT 24
Finished Jul 04 05:54:05 PM PDT 24
Peak memory 215556 kb
Host smart-eaa25a26-1b6d-4b1b-9c9b-df703bb4c0b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233175448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
233175448
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3316799734
Short name T1057
Test name
Test status
Simulation time 105805187 ps
CPU time 0.71 seconds
Started Jul 04 05:54:04 PM PDT 24
Finished Jul 04 05:54:05 PM PDT 24
Peak memory 203980 kb
Host smart-5fa427a0-d1e6-467d-a7e5-306f3cb39862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316799734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
316799734
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3472076838
Short name T124
Test name
Test status
Simulation time 50490463 ps
CPU time 2.18 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:08 PM PDT 24
Peak memory 215496 kb
Host smart-47dad1af-fac9-4fb3-9f8d-e3755d98dad6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472076838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3472076838
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.731147915
Short name T1142
Test name
Test status
Simulation time 31692514 ps
CPU time 0.67 seconds
Started Jul 04 05:54:03 PM PDT 24
Finished Jul 04 05:54:04 PM PDT 24
Peak memory 203836 kb
Host smart-d715434a-0a43-45b5-9d86-10d3a07b0c4d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731147915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.731147915
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1792838335
Short name T1140
Test name
Test status
Simulation time 172757504 ps
CPU time 4.44 seconds
Started Jul 04 05:54:09 PM PDT 24
Finished Jul 04 05:54:14 PM PDT 24
Peak memory 215560 kb
Host smart-8cdac19b-1690-4314-95c7-6ae0f66ac019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792838335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1792838335
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1203649551
Short name T107
Test name
Test status
Simulation time 180694855 ps
CPU time 2.78 seconds
Started Jul 04 05:54:05 PM PDT 24
Finished Jul 04 05:54:08 PM PDT 24
Peak memory 217312 kb
Host smart-29c4e5fc-9570-4ad9-bb54-e2f4efbba0f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203649551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
203649551
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.191441169
Short name T1124
Test name
Test status
Simulation time 1181815200 ps
CPU time 7.52 seconds
Started Jul 04 05:54:06 PM PDT 24
Finished Jul 04 05:54:13 PM PDT 24
Peak memory 215560 kb
Host smart-0f6476d6-76e1-4aa4-b69f-bc4903d54307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191441169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.191441169
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.284202225
Short name T1030
Test name
Test status
Simulation time 37149005 ps
CPU time 0.7 seconds
Started Jul 04 05:54:35 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 203952 kb
Host smart-ed6a2cb8-c5b5-41cb-a180-75ca7943611c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284202225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.284202225
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1607180689
Short name T1121
Test name
Test status
Simulation time 27348799 ps
CPU time 0.7 seconds
Started Jul 04 05:54:28 PM PDT 24
Finished Jul 04 05:54:29 PM PDT 24
Peak memory 203980 kb
Host smart-36921b32-0763-4cb1-980f-7721069bbe18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607180689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1607180689
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.349234507
Short name T1080
Test name
Test status
Simulation time 14347968 ps
CPU time 0.76 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:33 PM PDT 24
Peak memory 204352 kb
Host smart-f579519c-f2f1-40a0-af84-dd27c54282d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349234507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.349234507
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1161046787
Short name T1087
Test name
Test status
Simulation time 12695994 ps
CPU time 0.72 seconds
Started Jul 04 05:54:33 PM PDT 24
Finished Jul 04 05:54:34 PM PDT 24
Peak memory 203980 kb
Host smart-50e46ac6-9ba2-48ba-a436-aa68ed69a097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161046787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1161046787
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.295901315
Short name T1062
Test name
Test status
Simulation time 42465436 ps
CPU time 0.82 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:33 PM PDT 24
Peak memory 204280 kb
Host smart-f9a8fc71-7b41-4d69-81a2-9fb4e5f0f2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295901315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.295901315
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3372983264
Short name T1059
Test name
Test status
Simulation time 51461584 ps
CPU time 0.73 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:32 PM PDT 24
Peak memory 204016 kb
Host smart-6872a83e-26bf-4606-a102-e3d4be32f38f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372983264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3372983264
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3807512488
Short name T1077
Test name
Test status
Simulation time 71392238 ps
CPU time 0.7 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:32 PM PDT 24
Peak memory 204300 kb
Host smart-e9a4d63b-9d40-47de-b49b-52473078ce91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807512488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3807512488
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3317597485
Short name T1043
Test name
Test status
Simulation time 23230556 ps
CPU time 0.8 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:34 PM PDT 24
Peak memory 204268 kb
Host smart-5ffa6df7-0abf-4d35-908a-607c6335c9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317597485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3317597485
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1466609022
Short name T1102
Test name
Test status
Simulation time 20966828 ps
CPU time 0.71 seconds
Started Jul 04 05:54:35 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 204024 kb
Host smart-7cf6df6c-4407-42a5-b59c-8a6be25b87fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466609022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1466609022
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2104262314
Short name T1098
Test name
Test status
Simulation time 20906103 ps
CPU time 0.74 seconds
Started Jul 04 05:54:33 PM PDT 24
Finished Jul 04 05:54:34 PM PDT 24
Peak memory 204312 kb
Host smart-8abdd05c-244a-4dcb-a5b3-28920eecd1e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104262314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2104262314
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1994349254
Short name T1058
Test name
Test status
Simulation time 226882374 ps
CPU time 8.04 seconds
Started Jul 04 05:54:11 PM PDT 24
Finished Jul 04 05:54:19 PM PDT 24
Peak memory 215492 kb
Host smart-bea3600a-9866-4216-801a-0c47728cb77d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994349254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1994349254
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3802599462
Short name T1122
Test name
Test status
Simulation time 546870602 ps
CPU time 33.91 seconds
Started Jul 04 05:54:09 PM PDT 24
Finished Jul 04 05:54:43 PM PDT 24
Peak memory 215780 kb
Host smart-89de23f8-db38-4625-b5dc-6a32f33c7093
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802599462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3802599462
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3686456616
Short name T126
Test name
Test status
Simulation time 17080746 ps
CPU time 0.94 seconds
Started Jul 04 05:54:09 PM PDT 24
Finished Jul 04 05:54:11 PM PDT 24
Peak memory 207116 kb
Host smart-5c150d50-440f-45de-bdc2-f783947d9c23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686456616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3686456616
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2563331241
Short name T110
Test name
Test status
Simulation time 292069785 ps
CPU time 3.66 seconds
Started Jul 04 05:54:10 PM PDT 24
Finished Jul 04 05:54:14 PM PDT 24
Peak memory 217500 kb
Host smart-a6db1190-49c3-4649-bd53-f5e4a094413a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563331241 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2563331241
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.114075027
Short name T1078
Test name
Test status
Simulation time 33367560 ps
CPU time 1.24 seconds
Started Jul 04 05:54:09 PM PDT 24
Finished Jul 04 05:54:11 PM PDT 24
Peak memory 207432 kb
Host smart-bf4c2a57-36fe-4c2b-bc64-ba109a82debf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114075027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.114075027
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1404527191
Short name T1050
Test name
Test status
Simulation time 14603179 ps
CPU time 0.76 seconds
Started Jul 04 05:54:09 PM PDT 24
Finished Jul 04 05:54:10 PM PDT 24
Peak memory 203920 kb
Host smart-a3c9ca14-f061-43b0-8f8d-e57bd5ffe73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404527191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
404527191
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.261751229
Short name T1076
Test name
Test status
Simulation time 70185715 ps
CPU time 1.81 seconds
Started Jul 04 05:54:08 PM PDT 24
Finished Jul 04 05:54:10 PM PDT 24
Peak memory 215484 kb
Host smart-c5205dc1-eca0-4ca9-a622-bca540901e92
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261751229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.261751229
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3345364780
Short name T1037
Test name
Test status
Simulation time 57650919 ps
CPU time 0.67 seconds
Started Jul 04 05:54:20 PM PDT 24
Finished Jul 04 05:54:21 PM PDT 24
Peak memory 203836 kb
Host smart-77919ae1-5ec6-4ad1-acc0-1a20947b8a88
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345364780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3345364780
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.662954320
Short name T1048
Test name
Test status
Simulation time 117041159 ps
CPU time 3.68 seconds
Started Jul 04 05:54:21 PM PDT 24
Finished Jul 04 05:54:25 PM PDT 24
Peak memory 215480 kb
Host smart-aa236d18-6aa8-4dfc-9e57-e18490a7fe5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662954320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.662954320
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2407654289
Short name T174
Test name
Test status
Simulation time 796020627 ps
CPU time 20.16 seconds
Started Jul 04 05:54:21 PM PDT 24
Finished Jul 04 05:54:41 PM PDT 24
Peak memory 215468 kb
Host smart-4296f346-a817-4508-8729-a63cd9c40058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407654289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2407654289
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1880434095
Short name T1150
Test name
Test status
Simulation time 180387484 ps
CPU time 0.69 seconds
Started Jul 04 05:54:35 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 204028 kb
Host smart-9a9a2c48-3089-4bd8-91bb-1656780e1e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880434095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1880434095
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4071091967
Short name T1141
Test name
Test status
Simulation time 19167213 ps
CPU time 0.72 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:33 PM PDT 24
Peak memory 203980 kb
Host smart-917eccd3-7129-4e8e-84b0-a535a0387d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071091967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4071091967
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2759689371
Short name T1129
Test name
Test status
Simulation time 14843186 ps
CPU time 0.73 seconds
Started Jul 04 05:54:33 PM PDT 24
Finished Jul 04 05:54:34 PM PDT 24
Peak memory 204312 kb
Host smart-4e5a8032-9746-4486-9437-526b22d33bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759689371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2759689371
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3837380169
Short name T1049
Test name
Test status
Simulation time 31875356 ps
CPU time 0.78 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:34 PM PDT 24
Peak memory 204084 kb
Host smart-3a4a7b31-372c-40a1-ac05-05304bfd5825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837380169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3837380169
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4277531226
Short name T1026
Test name
Test status
Simulation time 19390017 ps
CPU time 0.7 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:32 PM PDT 24
Peak memory 204288 kb
Host smart-befd9e69-3cc1-4a34-ac5e-bd79087295e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277531226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4277531226
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.458398543
Short name T1082
Test name
Test status
Simulation time 62596819 ps
CPU time 0.77 seconds
Started Jul 04 05:54:30 PM PDT 24
Finished Jul 04 05:54:31 PM PDT 24
Peak memory 204208 kb
Host smart-5bc55304-6bf3-4fa5-9508-49e0fc286924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458398543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.458398543
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3546293828
Short name T1074
Test name
Test status
Simulation time 12106658 ps
CPU time 0.7 seconds
Started Jul 04 05:54:38 PM PDT 24
Finished Jul 04 05:54:39 PM PDT 24
Peak memory 204336 kb
Host smart-8add7f82-e240-4b06-8b45-0b5c9a7b1086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546293828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3546293828
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.977680277
Short name T1032
Test name
Test status
Simulation time 74718069 ps
CPU time 0.7 seconds
Started Jul 04 05:54:31 PM PDT 24
Finished Jul 04 05:54:32 PM PDT 24
Peak memory 204348 kb
Host smart-06fe59bf-c7b7-4c96-98b7-ff2bc2a316d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977680277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.977680277
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.570363130
Short name T1061
Test name
Test status
Simulation time 32944575 ps
CPU time 0.79 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:33 PM PDT 24
Peak memory 203952 kb
Host smart-aec8283e-8f75-4b7a-9e4b-7b77f50ebb47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570363130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.570363130
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.970255236
Short name T1136
Test name
Test status
Simulation time 30867091 ps
CPU time 0.74 seconds
Started Jul 04 05:54:34 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 204028 kb
Host smart-b203b23f-9acb-4a3e-9941-1789b3327cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970255236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.970255236
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.296657962
Short name T123
Test name
Test status
Simulation time 256722362 ps
CPU time 7.41 seconds
Started Jul 04 05:54:08 PM PDT 24
Finished Jul 04 05:54:16 PM PDT 24
Peak memory 215476 kb
Host smart-9d030052-3408-41d9-a70d-0ea5c0eea0c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296657962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.296657962
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4192668760
Short name T1056
Test name
Test status
Simulation time 360827969 ps
CPU time 23.19 seconds
Started Jul 04 05:54:20 PM PDT 24
Finished Jul 04 05:54:44 PM PDT 24
Peak memory 207196 kb
Host smart-2746a42a-3dbe-40d9-b1ec-b493a81657b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192668760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.4192668760
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1015523490
Short name T78
Test name
Test status
Simulation time 177606954 ps
CPU time 1.53 seconds
Started Jul 04 05:54:09 PM PDT 24
Finished Jul 04 05:54:11 PM PDT 24
Peak memory 216560 kb
Host smart-0501c08b-8c96-4fab-a274-6aece4861f7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015523490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1015523490
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2621991866
Short name T1146
Test name
Test status
Simulation time 53390029 ps
CPU time 3.51 seconds
Started Jul 04 05:54:08 PM PDT 24
Finished Jul 04 05:54:11 PM PDT 24
Peak memory 217424 kb
Host smart-a8bab472-a83c-4c1e-b5eb-3402edd07b12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621991866 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2621991866
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2088852079
Short name T1115
Test name
Test status
Simulation time 20665862 ps
CPU time 1.37 seconds
Started Jul 04 05:54:08 PM PDT 24
Finished Jul 04 05:54:09 PM PDT 24
Peak memory 207332 kb
Host smart-1dcdb024-9aa8-4723-86f9-352e152eac4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088852079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
088852079
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.257340104
Short name T1035
Test name
Test status
Simulation time 21511438 ps
CPU time 0.74 seconds
Started Jul 04 05:54:09 PM PDT 24
Finished Jul 04 05:54:10 PM PDT 24
Peak memory 204300 kb
Host smart-52b29ce9-d860-4232-9c4a-85e5ebad9fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257340104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.257340104
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4015869611
Short name T1099
Test name
Test status
Simulation time 289738688 ps
CPU time 2.2 seconds
Started Jul 04 05:54:10 PM PDT 24
Finished Jul 04 05:54:13 PM PDT 24
Peak memory 215592 kb
Host smart-205e0456-43c9-4570-919e-de62fbdcee20
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015869611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4015869611
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1314521234
Short name T1149
Test name
Test status
Simulation time 41054182 ps
CPU time 0.7 seconds
Started Jul 04 05:54:21 PM PDT 24
Finished Jul 04 05:54:22 PM PDT 24
Peak memory 204176 kb
Host smart-409f3e0e-287f-4a8e-a42a-b3ced594c578
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314521234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1314521234
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3926785436
Short name T1114
Test name
Test status
Simulation time 118496801 ps
CPU time 1.86 seconds
Started Jul 04 05:54:10 PM PDT 24
Finished Jul 04 05:54:12 PM PDT 24
Peak memory 215508 kb
Host smart-6f46411f-22f1-4f83-a204-c03bc05b8181
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926785436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3926785436
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2820936902
Short name T108
Test name
Test status
Simulation time 524750668 ps
CPU time 3.4 seconds
Started Jul 04 05:54:21 PM PDT 24
Finished Jul 04 05:54:25 PM PDT 24
Peak memory 215756 kb
Host smart-e9ed6060-f01b-4ac4-9a8d-23655a588f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820936902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
820936902
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3046148313
Short name T114
Test name
Test status
Simulation time 904005084 ps
CPU time 7.15 seconds
Started Jul 04 05:54:21 PM PDT 24
Finished Jul 04 05:54:28 PM PDT 24
Peak memory 215796 kb
Host smart-b1476f74-a23a-4c2a-95f2-3b6f7a471c28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046148313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3046148313
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.379610146
Short name T1128
Test name
Test status
Simulation time 13293710 ps
CPU time 0.69 seconds
Started Jul 04 05:54:32 PM PDT 24
Finished Jul 04 05:54:33 PM PDT 24
Peak memory 203892 kb
Host smart-36305fa3-0e9c-4557-92d8-9279083e6467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379610146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.379610146
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1261389908
Short name T1103
Test name
Test status
Simulation time 31623010 ps
CPU time 0.77 seconds
Started Jul 04 05:54:35 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 204268 kb
Host smart-a4799072-d0a1-45d1-9b5a-8ae3d9bde04d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261389908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1261389908
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2153025932
Short name T1040
Test name
Test status
Simulation time 43034020 ps
CPU time 0.75 seconds
Started Jul 04 05:54:34 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 204300 kb
Host smart-03219b76-73e6-47b2-8fd4-b8f0c32b2424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153025932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2153025932
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2649106977
Short name T1028
Test name
Test status
Simulation time 56401265 ps
CPU time 0.76 seconds
Started Jul 04 05:54:34 PM PDT 24
Finished Jul 04 05:54:35 PM PDT 24
Peak memory 204252 kb
Host smart-b2348029-e76a-43ab-b52b-8f6641002ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649106977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2649106977
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3567324958
Short name T1042
Test name
Test status
Simulation time 58014533 ps
CPU time 0.8 seconds
Started Jul 04 05:54:33 PM PDT 24
Finished Jul 04 05:54:34 PM PDT 24
Peak memory 204012 kb
Host smart-7400ec30-4d3b-4d94-8d89-f4be68a1b459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567324958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3567324958
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3531637664
Short name T1120
Test name
Test status
Simulation time 29151234 ps
CPU time 0.75 seconds
Started Jul 04 05:54:36 PM PDT 24
Finished Jul 04 05:54:37 PM PDT 24
Peak memory 204044 kb
Host smart-9701c5c8-88c5-4d94-90bc-cb48658a8e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531637664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3531637664
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3937597491
Short name T1112
Test name
Test status
Simulation time 13755229 ps
CPU time 0.72 seconds
Started Jul 04 05:54:39 PM PDT 24
Finished Jul 04 05:54:40 PM PDT 24
Peak memory 204280 kb
Host smart-5bebe164-7cde-4b87-adb0-7de925284395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937597491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3937597491
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3596760334
Short name T1051
Test name
Test status
Simulation time 21262360 ps
CPU time 0.75 seconds
Started Jul 04 05:54:39 PM PDT 24
Finished Jul 04 05:54:40 PM PDT 24
Peak memory 204288 kb
Host smart-c5c20478-dc68-4718-bc2b-1dfb4f1d2306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596760334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3596760334
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3430865619
Short name T1095
Test name
Test status
Simulation time 19307181 ps
CPU time 0.7 seconds
Started Jul 04 05:54:37 PM PDT 24
Finished Jul 04 05:54:37 PM PDT 24
Peak memory 203972 kb
Host smart-757900cd-170b-4579-9313-5e0c897901ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430865619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3430865619
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1202590110
Short name T1131
Test name
Test status
Simulation time 61638418 ps
CPU time 0.76 seconds
Started Jul 04 05:54:39 PM PDT 24
Finished Jul 04 05:54:40 PM PDT 24
Peak memory 203944 kb
Host smart-0c9ca3b7-914b-4e21-b24a-c2f1403c6e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202590110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1202590110
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1744092590
Short name T1109
Test name
Test status
Simulation time 170343558 ps
CPU time 1.52 seconds
Started Jul 04 05:54:08 PM PDT 24
Finished Jul 04 05:54:10 PM PDT 24
Peak memory 215656 kb
Host smart-0d3bbfeb-4c3e-4a19-9bce-fa8b0e8ddd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744092590 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1744092590
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2679108600
Short name T120
Test name
Test status
Simulation time 117384917 ps
CPU time 2.62 seconds
Started Jul 04 05:54:10 PM PDT 24
Finished Jul 04 05:54:13 PM PDT 24
Peak memory 207564 kb
Host smart-10a7970b-96e4-4f7a-95f5-82686e742e71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679108600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
679108600
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.645881555
Short name T1100
Test name
Test status
Simulation time 79129302 ps
CPU time 0.75 seconds
Started Jul 04 05:54:10 PM PDT 24
Finished Jul 04 05:54:11 PM PDT 24
Peak memory 204280 kb
Host smart-4fac7801-a678-46c0-978a-999e2ab844bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645881555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.645881555
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2951559568
Short name T1054
Test name
Test status
Simulation time 124007595 ps
CPU time 2.01 seconds
Started Jul 04 05:54:10 PM PDT 24
Finished Jul 04 05:54:12 PM PDT 24
Peak memory 207300 kb
Host smart-52e62346-0b37-4a23-929a-68daa548de0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951559568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2951559568
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2408635384
Short name T92
Test name
Test status
Simulation time 301500673 ps
CPU time 2.32 seconds
Started Jul 04 05:54:11 PM PDT 24
Finished Jul 04 05:54:14 PM PDT 24
Peak memory 215792 kb
Host smart-b2dbf4f4-5f8e-4e46-b35e-2e552fa0f8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408635384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
408635384
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1289916180
Short name T96
Test name
Test status
Simulation time 1589348169 ps
CPU time 13.2 seconds
Started Jul 04 05:54:09 PM PDT 24
Finished Jul 04 05:54:23 PM PDT 24
Peak memory 216188 kb
Host smart-29341e9b-55e4-4428-8c51-1928de58591b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289916180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1289916180
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3527897541
Short name T1108
Test name
Test status
Simulation time 53000778 ps
CPU time 3.61 seconds
Started Jul 04 05:54:16 PM PDT 24
Finished Jul 04 05:54:20 PM PDT 24
Peak memory 217860 kb
Host smart-7c4d4d82-b65d-4d91-bc42-2c1dbfd061d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527897541 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3527897541
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2578945096
Short name T119
Test name
Test status
Simulation time 117835788 ps
CPU time 1.31 seconds
Started Jul 04 05:54:16 PM PDT 24
Finished Jul 04 05:54:17 PM PDT 24
Peak memory 215492 kb
Host smart-e3581baf-359c-41df-8b5b-1e428a49e656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578945096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
578945096
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1515999476
Short name T1110
Test name
Test status
Simulation time 50515581 ps
CPU time 0.78 seconds
Started Jul 04 05:54:17 PM PDT 24
Finished Jul 04 05:54:18 PM PDT 24
Peak memory 203996 kb
Host smart-d60aadea-c644-482d-8865-40525f31c81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515999476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
515999476
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2992902978
Short name T1116
Test name
Test status
Simulation time 174933913 ps
CPU time 2.95 seconds
Started Jul 04 05:54:18 PM PDT 24
Finished Jul 04 05:54:21 PM PDT 24
Peak memory 215540 kb
Host smart-0aafd3bd-eac1-4e13-a2eb-d21bb2613421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992902978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2992902978
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3237891033
Short name T95
Test name
Test status
Simulation time 413238688 ps
CPU time 2.32 seconds
Started Jul 04 05:54:12 PM PDT 24
Finished Jul 04 05:54:14 PM PDT 24
Peak memory 215652 kb
Host smart-2e31b280-ff42-45d0-9a90-12df5d57f915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237891033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
237891033
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3685811147
Short name T148
Test name
Test status
Simulation time 1060657721 ps
CPU time 24.35 seconds
Started Jul 04 05:54:12 PM PDT 24
Finished Jul 04 05:54:36 PM PDT 24
Peak memory 216196 kb
Host smart-cc6611c5-32d7-4262-a989-2e58118c2c06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685811147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3685811147
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3129730791
Short name T1090
Test name
Test status
Simulation time 175505397 ps
CPU time 2.54 seconds
Started Jul 04 05:54:16 PM PDT 24
Finished Jul 04 05:54:19 PM PDT 24
Peak memory 216708 kb
Host smart-3aef3566-b275-4b4c-b7d4-83b5aa5b95bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129730791 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3129730791
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3280561879
Short name T115
Test name
Test status
Simulation time 109463314 ps
CPU time 1.84 seconds
Started Jul 04 05:54:18 PM PDT 24
Finished Jul 04 05:54:20 PM PDT 24
Peak memory 207320 kb
Host smart-d48f1595-672e-489a-b0ec-16205dc35e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280561879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
280561879
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3762355754
Short name T1034
Test name
Test status
Simulation time 14908885 ps
CPU time 0.74 seconds
Started Jul 04 05:54:17 PM PDT 24
Finished Jul 04 05:54:18 PM PDT 24
Peak memory 203980 kb
Host smart-9af1030a-0e1f-4f95-999c-2df9f5f3adb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762355754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
762355754
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3950790932
Short name T1126
Test name
Test status
Simulation time 164120977 ps
CPU time 2.66 seconds
Started Jul 04 05:54:18 PM PDT 24
Finished Jul 04 05:54:21 PM PDT 24
Peak memory 215532 kb
Host smart-7d9d0680-94c6-400e-b7fc-7ea3f3af9912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950790932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3950790932
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3682436638
Short name T1133
Test name
Test status
Simulation time 198599158 ps
CPU time 3.14 seconds
Started Jul 04 05:54:18 PM PDT 24
Finished Jul 04 05:54:21 PM PDT 24
Peak memory 215884 kb
Host smart-a56f8012-80a2-44e9-a812-710dfce556e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682436638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
682436638
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4119513884
Short name T1052
Test name
Test status
Simulation time 1710248883 ps
CPU time 6.91 seconds
Started Jul 04 05:54:19 PM PDT 24
Finished Jul 04 05:54:26 PM PDT 24
Peak memory 222500 kb
Host smart-28645787-1deb-42db-ad31-1f11a03eaac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119513884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4119513884
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.287304991
Short name T1067
Test name
Test status
Simulation time 133682812 ps
CPU time 3.49 seconds
Started Jul 04 05:54:26 PM PDT 24
Finished Jul 04 05:54:30 PM PDT 24
Peak memory 217632 kb
Host smart-d94c3f21-777c-4d5d-811a-fc069c530b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287304991 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.287304991
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4187186677
Short name T125
Test name
Test status
Simulation time 522872648 ps
CPU time 2.13 seconds
Started Jul 04 05:54:17 PM PDT 24
Finished Jul 04 05:54:19 PM PDT 24
Peak memory 215552 kb
Host smart-a7509896-9c6a-4359-9314-7ed1bc8a828e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187186677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
187186677
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3498441525
Short name T1055
Test name
Test status
Simulation time 35762854 ps
CPU time 0.81 seconds
Started Jul 04 05:54:16 PM PDT 24
Finished Jul 04 05:54:17 PM PDT 24
Peak memory 203996 kb
Host smart-ebf6df19-5f8a-432e-9be2-61c03b422512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498441525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
498441525
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2390901471
Short name T1069
Test name
Test status
Simulation time 279458859 ps
CPU time 1.97 seconds
Started Jul 04 05:54:17 PM PDT 24
Finished Jul 04 05:54:20 PM PDT 24
Peak memory 215540 kb
Host smart-fa71e989-aa87-4025-8db0-7349d9ce7c72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390901471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2390901471
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2590431023
Short name T102
Test name
Test status
Simulation time 373523726 ps
CPU time 2.9 seconds
Started Jul 04 05:54:16 PM PDT 24
Finished Jul 04 05:54:20 PM PDT 24
Peak memory 215660 kb
Host smart-f819639f-0c9f-4fda-84ed-14b1b9d15479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590431023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
590431023
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4260020226
Short name T176
Test name
Test status
Simulation time 1049922371 ps
CPU time 23.95 seconds
Started Jul 04 05:54:16 PM PDT 24
Finished Jul 04 05:54:40 PM PDT 24
Peak memory 215856 kb
Host smart-01788a68-2eb5-4120-9d04-c8e48bf996a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260020226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4260020226
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2908627118
Short name T1125
Test name
Test status
Simulation time 136069469 ps
CPU time 3.85 seconds
Started Jul 04 05:54:23 PM PDT 24
Finished Jul 04 05:54:27 PM PDT 24
Peak memory 217984 kb
Host smart-bb93513a-9b8e-4d9e-abd0-4a07bcd9236b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908627118 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2908627118
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1798989737
Short name T1060
Test name
Test status
Simulation time 160458735 ps
CPU time 2.17 seconds
Started Jul 04 05:54:19 PM PDT 24
Finished Jul 04 05:54:21 PM PDT 24
Peak memory 207388 kb
Host smart-508b1861-f60e-4aa5-baef-68aa3c2f70df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798989737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
798989737
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3735371509
Short name T1068
Test name
Test status
Simulation time 24570425 ps
CPU time 0.74 seconds
Started Jul 04 05:54:19 PM PDT 24
Finished Jul 04 05:54:20 PM PDT 24
Peak memory 204008 kb
Host smart-ca24a82d-fdb6-45b3-88fb-55973ad04ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735371509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
735371509
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2313642290
Short name T139
Test name
Test status
Simulation time 435412125 ps
CPU time 2.84 seconds
Started Jul 04 05:54:18 PM PDT 24
Finished Jul 04 05:54:21 PM PDT 24
Peak memory 215568 kb
Host smart-1f48d82a-ac45-45fd-9007-9caeb4b4481b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313642290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2313642290
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.236392101
Short name T1088
Test name
Test status
Simulation time 279154389 ps
CPU time 2.19 seconds
Started Jul 04 05:54:18 PM PDT 24
Finished Jul 04 05:54:21 PM PDT 24
Peak memory 216944 kb
Host smart-3b87c4d1-7411-4099-9c46-2cf876c2a63d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236392101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.236392101
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2757222076
Short name T1044
Test name
Test status
Simulation time 1265932619 ps
CPU time 8.93 seconds
Started Jul 04 05:54:18 PM PDT 24
Finished Jul 04 05:54:27 PM PDT 24
Peak memory 215552 kb
Host smart-3732f4ce-154d-4802-9899-9ba03bfc646a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757222076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2757222076
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3051766163
Short name T809
Test name
Test status
Simulation time 20399736 ps
CPU time 0.73 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:16:52 PM PDT 24
Peak memory 205840 kb
Host smart-8f959f1f-88fa-48bb-9857-379938d40af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051766163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
051766163
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3081968732
Short name T285
Test name
Test status
Simulation time 162407315 ps
CPU time 2.16 seconds
Started Jul 04 06:16:47 PM PDT 24
Finished Jul 04 06:16:50 PM PDT 24
Peak memory 225540 kb
Host smart-cbc1964a-882d-4053-8852-98df11e1504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081968732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3081968732
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1313390261
Short name T600
Test name
Test status
Simulation time 46238145 ps
CPU time 0.73 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:16:52 PM PDT 24
Peak memory 206808 kb
Host smart-40bd83c8-3019-43b2-848a-91167182f9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313390261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1313390261
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1345444234
Short name T377
Test name
Test status
Simulation time 3405633755 ps
CPU time 14.88 seconds
Started Jul 04 06:16:52 PM PDT 24
Finished Jul 04 06:17:07 PM PDT 24
Peak memory 239312 kb
Host smart-e6123731-3a16-419c-9f50-0fd857fa797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345444234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1345444234
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.318015740
Short name T204
Test name
Test status
Simulation time 22641987594 ps
CPU time 107.18 seconds
Started Jul 04 06:16:49 PM PDT 24
Finished Jul 04 06:18:36 PM PDT 24
Peak memory 274112 kb
Host smart-80ca70d5-9ada-44b8-ae51-187ecdcf1ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318015740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
318015740
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1392396572
Short name T310
Test name
Test status
Simulation time 8184453200 ps
CPU time 28.18 seconds
Started Jul 04 06:16:52 PM PDT 24
Finished Jul 04 06:17:20 PM PDT 24
Peak memory 242080 kb
Host smart-98dc1f9e-032b-469a-a83c-bf08ff07dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392396572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1392396572
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2715968299
Short name T822
Test name
Test status
Simulation time 21816250501 ps
CPU time 11.89 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:17:03 PM PDT 24
Peak memory 233876 kb
Host smart-b8838c69-1d52-42d5-b22f-fc07d516a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715968299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2715968299
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.675280745
Short name T549
Test name
Test status
Simulation time 215965863 ps
CPU time 7.99 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:16:59 PM PDT 24
Peak memory 241620 kb
Host smart-cabc0fe5-4d5b-4eff-9182-ae9c98b2d05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675280745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.675280745
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.916068993
Short name T756
Test name
Test status
Simulation time 54350041 ps
CPU time 1.02 seconds
Started Jul 04 06:16:48 PM PDT 24
Finished Jul 04 06:16:49 PM PDT 24
Peak memory 218920 kb
Host smart-b88df5df-98d9-4b84-a051-d667c9a32f0b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916068993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.916068993
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1249053706
Short name T271
Test name
Test status
Simulation time 1251675127 ps
CPU time 6.85 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:16:58 PM PDT 24
Peak memory 233744 kb
Host smart-bbe98874-375d-4e55-b87f-9f300ceb3b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249053706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1249053706
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4087582173
Short name T365
Test name
Test status
Simulation time 901895422 ps
CPU time 8.16 seconds
Started Jul 04 06:16:50 PM PDT 24
Finished Jul 04 06:16:58 PM PDT 24
Peak memory 220104 kb
Host smart-5790145b-9550-4dee-b2c7-9b7a80aafca6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4087582173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4087582173
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1931136619
Short name T66
Test name
Test status
Simulation time 36039008 ps
CPU time 0.96 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:16:52 PM PDT 24
Peak memory 236684 kb
Host smart-1fe5bc01-c603-487a-9702-107611c90233
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931136619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1931136619
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2597099939
Short name T825
Test name
Test status
Simulation time 5544572761 ps
CPU time 32.74 seconds
Started Jul 04 06:16:49 PM PDT 24
Finished Jul 04 06:17:22 PM PDT 24
Peak memory 250348 kb
Host smart-c7e32c11-314e-471f-965c-15f3f9bf9563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597099939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2597099939
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3841001315
Short name T765
Test name
Test status
Simulation time 35716444540 ps
CPU time 48.2 seconds
Started Jul 04 06:16:50 PM PDT 24
Finished Jul 04 06:17:39 PM PDT 24
Peak memory 217560 kb
Host smart-74668e8c-7878-4699-ba9a-2fc325419a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841001315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3841001315
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1978557610
Short name T350
Test name
Test status
Simulation time 19923235593 ps
CPU time 15.49 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:17:07 PM PDT 24
Peak memory 217500 kb
Host smart-b2eb4777-35f9-4a1f-9fcb-13f2813689d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978557610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1978557610
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3064884568
Short name T966
Test name
Test status
Simulation time 2464222013 ps
CPU time 8.54 seconds
Started Jul 04 06:16:49 PM PDT 24
Finished Jul 04 06:16:58 PM PDT 24
Peak memory 217444 kb
Host smart-39cda8e1-4c63-4c54-ae94-1b770af4ab5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064884568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3064884568
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2809205246
Short name T392
Test name
Test status
Simulation time 14227003 ps
CPU time 0.7 seconds
Started Jul 04 06:16:51 PM PDT 24
Finished Jul 04 06:16:52 PM PDT 24
Peak memory 206548 kb
Host smart-e9a9ec44-338b-481f-9c8e-e72b9d3ce7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809205246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2809205246
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.404185726
Short name T18
Test name
Test status
Simulation time 3709217656 ps
CPU time 8.54 seconds
Started Jul 04 06:16:49 PM PDT 24
Finished Jul 04 06:16:58 PM PDT 24
Peak memory 242008 kb
Host smart-ddf65370-495d-43e5-a76c-6d582ef2ad50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404185726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.404185726
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2390654230
Short name T677
Test name
Test status
Simulation time 64016521 ps
CPU time 0.74 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:16:59 PM PDT 24
Peak memory 206312 kb
Host smart-ffbb1be9-27cc-40d3-b13f-fa94fe1b3042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390654230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
390654230
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1725772200
Short name T508
Test name
Test status
Simulation time 388953641 ps
CPU time 3.15 seconds
Started Jul 04 06:16:56 PM PDT 24
Finished Jul 04 06:16:59 PM PDT 24
Peak memory 225636 kb
Host smart-524aba7d-271e-432b-b0c2-fab0f4ee1d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725772200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1725772200
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3384330931
Short name T983
Test name
Test status
Simulation time 45726832 ps
CPU time 0.79 seconds
Started Jul 04 06:16:52 PM PDT 24
Finished Jul 04 06:16:53 PM PDT 24
Peak memory 207784 kb
Host smart-7062434d-02a2-4fd0-86d7-8cec8f365dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384330931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3384330931
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2549689132
Short name T688
Test name
Test status
Simulation time 5681590938 ps
CPU time 77.24 seconds
Started Jul 04 06:16:53 PM PDT 24
Finished Jul 04 06:18:11 PM PDT 24
Peak memory 256164 kb
Host smart-29a3367c-006e-4365-a477-3050c98ff0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549689132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2549689132
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2488667094
Short name T288
Test name
Test status
Simulation time 48949892113 ps
CPU time 120.83 seconds
Started Jul 04 06:16:55 PM PDT 24
Finished Jul 04 06:18:56 PM PDT 24
Peak memory 256224 kb
Host smart-70b4d645-5808-4da4-8ebb-4efde35d433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488667094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2488667094
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.898997534
Short name T958
Test name
Test status
Simulation time 189891752609 ps
CPU time 502.4 seconds
Started Jul 04 06:16:55 PM PDT 24
Finished Jul 04 06:25:18 PM PDT 24
Peak memory 266852 kb
Host smart-271b56a6-2cf5-4c75-a191-e19cd435918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898997534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
898997534
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1548347072
Short name T987
Test name
Test status
Simulation time 29787898629 ps
CPU time 30.2 seconds
Started Jul 04 06:16:54 PM PDT 24
Finished Jul 04 06:17:24 PM PDT 24
Peak memory 241112 kb
Host smart-29f7de0c-0a54-43b0-b53d-4a80384a6f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548347072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1548347072
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2584081816
Short name T131
Test name
Test status
Simulation time 670628302 ps
CPU time 4.76 seconds
Started Jul 04 06:17:01 PM PDT 24
Finished Jul 04 06:17:06 PM PDT 24
Peak memory 233736 kb
Host smart-42bfa265-ccdd-435c-b63c-a8c716418e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584081816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2584081816
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1287221860
Short name T161
Test name
Test status
Simulation time 4550893994 ps
CPU time 21.49 seconds
Started Jul 04 06:16:53 PM PDT 24
Finished Jul 04 06:17:15 PM PDT 24
Peak memory 233932 kb
Host smart-38257a0a-8bc3-473b-b5c8-71457c4a3fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287221860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1287221860
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2568581510
Short name T683
Test name
Test status
Simulation time 15987819 ps
CPU time 1.13 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:16:59 PM PDT 24
Peak memory 217624 kb
Host smart-3fd3092d-a6fb-4389-beb6-daa0f9e80be5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568581510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2568581510
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.116562312
Short name T132
Test name
Test status
Simulation time 48424456808 ps
CPU time 13.23 seconds
Started Jul 04 06:16:56 PM PDT 24
Finished Jul 04 06:17:10 PM PDT 24
Peak memory 233864 kb
Host smart-ce83202e-d643-4c08-8709-fa2a420f74b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116562312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
116562312
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3222054676
Short name T714
Test name
Test status
Simulation time 927380030 ps
CPU time 4.14 seconds
Started Jul 04 06:16:54 PM PDT 24
Finished Jul 04 06:16:58 PM PDT 24
Peak memory 225540 kb
Host smart-471e1d22-e3ab-46bc-8475-dfff77cb3c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222054676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3222054676
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1769766646
Short name T344
Test name
Test status
Simulation time 3316326647 ps
CPU time 9.43 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:19 PM PDT 24
Peak memory 224452 kb
Host smart-92c0251b-9395-4eee-acf3-ba41668a36e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1769766646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1769766646
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3228176525
Short name T67
Test name
Test status
Simulation time 581908477 ps
CPU time 1.06 seconds
Started Jul 04 06:16:53 PM PDT 24
Finished Jul 04 06:16:54 PM PDT 24
Peak memory 236768 kb
Host smart-220d6fec-d43a-459d-a864-97187ed6d7e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228176525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3228176525
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3911108025
Short name T292
Test name
Test status
Simulation time 37764693194 ps
CPU time 329.64 seconds
Started Jul 04 06:16:59 PM PDT 24
Finished Jul 04 06:22:29 PM PDT 24
Peak memory 254532 kb
Host smart-383d7d18-a18b-4d26-aed5-2fda7d7ee30a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911108025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3911108025
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2043913036
Short name T964
Test name
Test status
Simulation time 29772959272 ps
CPU time 26.61 seconds
Started Jul 04 06:17:01 PM PDT 24
Finished Jul 04 06:17:27 PM PDT 24
Peak memory 217608 kb
Host smart-78ba0b5a-1a62-419f-a592-04ddd19564cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043913036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2043913036
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.247552376
Short name T860
Test name
Test status
Simulation time 6677380810 ps
CPU time 6.56 seconds
Started Jul 04 06:17:06 PM PDT 24
Finished Jul 04 06:17:13 PM PDT 24
Peak memory 217456 kb
Host smart-5c215d81-d314-439a-b4c9-6772c20f3352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247552376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.247552376
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2405614800
Short name T721
Test name
Test status
Simulation time 664135438 ps
CPU time 3.17 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 217376 kb
Host smart-b377710b-3c52-4020-85fc-0eafc67ead44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405614800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2405614800
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.818400941
Short name T644
Test name
Test status
Simulation time 43398673 ps
CPU time 0.74 seconds
Started Jul 04 06:16:56 PM PDT 24
Finished Jul 04 06:16:57 PM PDT 24
Peak memory 207000 kb
Host smart-93b77456-55fc-4524-9d80-d302e7d30e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818400941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.818400941
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1056775338
Short name T890
Test name
Test status
Simulation time 7405053041 ps
CPU time 17.14 seconds
Started Jul 04 06:16:55 PM PDT 24
Finished Jul 04 06:17:12 PM PDT 24
Peak memory 225696 kb
Host smart-7d87f3ea-c19b-4b43-8bec-7016e4e0bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056775338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1056775338
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1019776119
Short name T787
Test name
Test status
Simulation time 33072597 ps
CPU time 0.71 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:30 PM PDT 24
Peak memory 206388 kb
Host smart-7e836d11-1900-4e7a-9a8d-bc2140181eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019776119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1019776119
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4189799354
Short name T264
Test name
Test status
Simulation time 1841210808 ps
CPU time 4.99 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:17:33 PM PDT 24
Peak memory 225588 kb
Host smart-e9055032-8f03-4379-8595-2b3ba784327f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189799354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4189799354
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.552740250
Short name T471
Test name
Test status
Simulation time 20822133 ps
CPU time 0.83 seconds
Started Jul 04 06:17:18 PM PDT 24
Finished Jul 04 06:17:19 PM PDT 24
Peak memory 207832 kb
Host smart-3e72bafb-598a-48ca-8065-e065192f4dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552740250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.552740250
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2973713626
Short name T777
Test name
Test status
Simulation time 25029999933 ps
CPU time 177.45 seconds
Started Jul 04 06:17:32 PM PDT 24
Finished Jul 04 06:20:30 PM PDT 24
Peak memory 251912 kb
Host smart-3199e88c-b8f7-48e0-84b8-4645c4e0dc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973713626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2973713626
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.180089993
Short name T760
Test name
Test status
Simulation time 5349576004 ps
CPU time 13.98 seconds
Started Jul 04 06:17:32 PM PDT 24
Finished Jul 04 06:17:46 PM PDT 24
Peak memory 237340 kb
Host smart-bfba7577-49e2-45af-a4a2-e87b66b44683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180089993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.180089993
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1250333691
Short name T719
Test name
Test status
Simulation time 1021757391 ps
CPU time 14.7 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:17:38 PM PDT 24
Peak memory 235356 kb
Host smart-bef1a2a4-6e88-44b1-a124-915fa20d33aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250333691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1250333691
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2646783870
Short name T408
Test name
Test status
Simulation time 31329904795 ps
CPU time 57.3 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:18:24 PM PDT 24
Peak memory 238392 kb
Host smart-a92d644f-a333-4b6d-b8d7-d7ee93c84bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646783870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2646783870
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1018282944
Short name T160
Test name
Test status
Simulation time 601232393 ps
CPU time 2.48 seconds
Started Jul 04 06:17:21 PM PDT 24
Finished Jul 04 06:17:23 PM PDT 24
Peak memory 225312 kb
Host smart-a2a4e2f3-43b9-4945-933c-d07b7ea8e06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018282944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1018282944
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2821891763
Short name T673
Test name
Test status
Simulation time 231728499 ps
CPU time 5.73 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:35 PM PDT 24
Peak memory 233752 kb
Host smart-68a7ae52-eb96-4171-80cc-3ea2f98f47c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821891763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2821891763
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3359833926
Short name T867
Test name
Test status
Simulation time 26047113 ps
CPU time 1.09 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:17:29 PM PDT 24
Peak memory 217692 kb
Host smart-808da8c1-f11e-4ee7-83d5-9b2f9b5579ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359833926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3359833926
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.43044531
Short name T426
Test name
Test status
Simulation time 5897582294 ps
CPU time 11.71 seconds
Started Jul 04 06:17:26 PM PDT 24
Finished Jul 04 06:17:38 PM PDT 24
Peak memory 233920 kb
Host smart-759e2141-2d30-42cf-bdb5-bc6a3f0a0422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43044531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.43044531
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3680625332
Short name T732
Test name
Test status
Simulation time 142822887444 ps
CPU time 22.58 seconds
Started Jul 04 06:17:24 PM PDT 24
Finished Jul 04 06:17:47 PM PDT 24
Peak memory 240656 kb
Host smart-dbb1a50d-6a11-4879-ac16-d8f9a0056a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680625332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3680625332
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.23683634
Short name T473
Test name
Test status
Simulation time 133151068 ps
CPU time 3.59 seconds
Started Jul 04 06:17:32 PM PDT 24
Finished Jul 04 06:17:36 PM PDT 24
Peak memory 220120 kb
Host smart-6b36b7da-a9d9-486f-8acc-9694d1e2ac23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=23683634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direc
t.23683634
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1931103115
Short name T429
Test name
Test status
Simulation time 230297474 ps
CPU time 0.94 seconds
Started Jul 04 06:17:30 PM PDT 24
Finished Jul 04 06:17:31 PM PDT 24
Peak memory 207592 kb
Host smart-027f8c17-277e-40c9-bc24-603624f27da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931103115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1931103115
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1517345974
Short name T846
Test name
Test status
Simulation time 1420881925 ps
CPU time 18.66 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:17:44 PM PDT 24
Peak memory 217136 kb
Host smart-63969eb7-2307-4622-8871-b905099acf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517345974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1517345974
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3271272842
Short name T803
Test name
Test status
Simulation time 13409298 ps
CPU time 0.7 seconds
Started Jul 04 06:17:22 PM PDT 24
Finished Jul 04 06:17:23 PM PDT 24
Peak memory 206584 kb
Host smart-b3357104-456b-4f70-8791-edef6d187f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271272842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3271272842
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1831355856
Short name T629
Test name
Test status
Simulation time 73829888 ps
CPU time 1.68 seconds
Started Jul 04 06:17:19 PM PDT 24
Finished Jul 04 06:17:21 PM PDT 24
Peak memory 217344 kb
Host smart-28719b29-0a76-4977-9dab-d5dd93609674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831355856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1831355856
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1444903286
Short name T943
Test name
Test status
Simulation time 92209575 ps
CPU time 1 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 207992 kb
Host smart-6b2a2248-29ea-49dc-9161-084e9a024b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444903286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1444903286
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2404632082
Short name T373
Test name
Test status
Simulation time 184799337 ps
CPU time 2.16 seconds
Started Jul 04 06:17:20 PM PDT 24
Finished Jul 04 06:17:22 PM PDT 24
Peak memory 225444 kb
Host smart-94bfa77c-48ce-4713-b450-d3ed79e31f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404632082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2404632082
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.287053701
Short name T691
Test name
Test status
Simulation time 12839436 ps
CPU time 0.78 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:17:24 PM PDT 24
Peak memory 205764 kb
Host smart-0ecd4c99-e4d0-4b15-be4d-239fbb7535c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287053701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.287053701
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3553995064
Short name T333
Test name
Test status
Simulation time 14305645780 ps
CPU time 29.2 seconds
Started Jul 04 06:17:32 PM PDT 24
Finished Jul 04 06:18:02 PM PDT 24
Peak memory 225664 kb
Host smart-44ba1003-b3f3-4a59-8721-c1d962116b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553995064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3553995064
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.368786045
Short name T929
Test name
Test status
Simulation time 17802228 ps
CPU time 0.76 seconds
Started Jul 04 06:17:26 PM PDT 24
Finished Jul 04 06:17:27 PM PDT 24
Peak memory 207524 kb
Host smart-686a5ff5-073d-452f-bd1b-e16bc86b0a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368786045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.368786045
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3271705091
Short name T35
Test name
Test status
Simulation time 56373561553 ps
CPU time 97.58 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:19:05 PM PDT 24
Peak memory 256652 kb
Host smart-c32cdb2b-39e3-4625-8d0a-e1a27c3ec36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271705091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3271705091
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.30975767
Short name T796
Test name
Test status
Simulation time 51767088863 ps
CPU time 123.01 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:19:28 PM PDT 24
Peak memory 254584 kb
Host smart-585150a2-aab2-4249-943d-998eb89b1043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30975767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.30975767
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1583103876
Short name T134
Test name
Test status
Simulation time 46028122148 ps
CPU time 103.37 seconds
Started Jul 04 06:17:32 PM PDT 24
Finished Jul 04 06:19:16 PM PDT 24
Peak memory 242232 kb
Host smart-a28a5a3b-da93-4eef-8b93-402030c1095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583103876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1583103876
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1911741269
Short name T952
Test name
Test status
Simulation time 1108198281 ps
CPU time 17.1 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:17:43 PM PDT 24
Peak memory 233796 kb
Host smart-6d05c1f7-6742-4927-b1b6-9f9304a37338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911741269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1911741269
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.85703211
Short name T1006
Test name
Test status
Simulation time 1759553493 ps
CPU time 15.14 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:17:38 PM PDT 24
Peak memory 235008 kb
Host smart-f66e3d30-5445-405a-9171-1c0cc959fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85703211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.85703211
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3127009920
Short name T466
Test name
Test status
Simulation time 5917617026 ps
CPU time 28.14 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:57 PM PDT 24
Peak memory 233892 kb
Host smart-9d311ddd-058a-4b44-912b-7e80e6399453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127009920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3127009920
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2420594184
Short name T128
Test name
Test status
Simulation time 11130301759 ps
CPU time 26.04 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:17:51 PM PDT 24
Peak memory 233952 kb
Host smart-5923f9b6-a502-40d1-b745-42592bf5bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420594184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2420594184
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1761498869
Short name T693
Test name
Test status
Simulation time 24924287 ps
CPU time 1.02 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:29 PM PDT 24
Peak memory 218924 kb
Host smart-db81755b-1d78-42e7-a6bb-1dac9d8b13f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761498869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1761498869
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3918125226
Short name T823
Test name
Test status
Simulation time 515537730 ps
CPU time 4.4 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:17:29 PM PDT 24
Peak memory 225592 kb
Host smart-e53d8d17-938a-4c83-b9bb-6ed7f5536cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918125226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3918125226
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1669066469
Short name T674
Test name
Test status
Simulation time 39273422868 ps
CPU time 28.98 seconds
Started Jul 04 06:17:24 PM PDT 24
Finished Jul 04 06:17:54 PM PDT 24
Peak memory 233940 kb
Host smart-d61efbdb-7ddd-4532-8b40-f5fad14506af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669066469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1669066469
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3836307364
Short name T71
Test name
Test status
Simulation time 6792243351 ps
CPU time 17.33 seconds
Started Jul 04 06:17:26 PM PDT 24
Finished Jul 04 06:17:44 PM PDT 24
Peak memory 223116 kb
Host smart-24b51b22-ef8d-48b5-86de-029cdcb11d70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3836307364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3836307364
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3842775765
Short name T223
Test name
Test status
Simulation time 467507180606 ps
CPU time 804.77 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:30:53 PM PDT 24
Peak memory 284304 kb
Host smart-b1e1025d-7a0b-482c-be48-61394cf41ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842775765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3842775765
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.426420962
Short name T314
Test name
Test status
Simulation time 442112507 ps
CPU time 7.95 seconds
Started Jul 04 06:17:24 PM PDT 24
Finished Jul 04 06:17:32 PM PDT 24
Peak memory 217640 kb
Host smart-2c2a758c-0607-40ef-8de2-1d04b367bcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426420962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.426420962
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1321157982
Short name T976
Test name
Test status
Simulation time 10171606044 ps
CPU time 27.88 seconds
Started Jul 04 06:17:24 PM PDT 24
Finished Jul 04 06:17:52 PM PDT 24
Peak memory 217452 kb
Host smart-0f598d77-659c-4eb0-bf4f-98a6c261e7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321157982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1321157982
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4289815302
Short name T585
Test name
Test status
Simulation time 111347426 ps
CPU time 1.11 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:29 PM PDT 24
Peak memory 208980 kb
Host smart-27961527-0a47-45ce-8f38-a6b9d07ce9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289815302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4289815302
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.835371442
Short name T459
Test name
Test status
Simulation time 14320765 ps
CPU time 0.78 seconds
Started Jul 04 06:17:32 PM PDT 24
Finished Jul 04 06:17:33 PM PDT 24
Peak memory 206884 kb
Host smart-88abd6fd-315b-4f47-b472-36aacedd858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835371442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.835371442
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1519432311
Short name T774
Test name
Test status
Simulation time 3486823680 ps
CPU time 9.96 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:17:33 PM PDT 24
Peak memory 225688 kb
Host smart-5b1f64ce-12c5-4dfc-89ae-d6231c258f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519432311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1519432311
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2504379177
Short name T487
Test name
Test status
Simulation time 46772491 ps
CPU time 0.76 seconds
Started Jul 04 06:17:30 PM PDT 24
Finished Jul 04 06:17:31 PM PDT 24
Peak memory 205800 kb
Host smart-69cbe7f6-a0df-4244-b4bc-81a17e11b009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504379177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2504379177
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1987578049
Short name T493
Test name
Test status
Simulation time 848633397 ps
CPU time 4.72 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:35 PM PDT 24
Peak memory 225560 kb
Host smart-cc2e87fc-6452-477e-b0d0-70b8f9b76b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987578049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1987578049
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1910493394
Short name T633
Test name
Test status
Simulation time 27038348 ps
CPU time 0.74 seconds
Started Jul 04 06:17:26 PM PDT 24
Finished Jul 04 06:17:27 PM PDT 24
Peak memory 207868 kb
Host smart-03d6d1b3-6c2b-4386-a801-361f366006cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910493394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1910493394
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3739395553
Short name T199
Test name
Test status
Simulation time 4685771943 ps
CPU time 27.39 seconds
Started Jul 04 06:17:24 PM PDT 24
Finished Jul 04 06:17:52 PM PDT 24
Peak memory 258444 kb
Host smart-2d493739-b721-42c1-9069-bc6c55640564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739395553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3739395553
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.723609660
Short name T295
Test name
Test status
Simulation time 193912663706 ps
CPU time 383.46 seconds
Started Jul 04 06:17:30 PM PDT 24
Finished Jul 04 06:23:54 PM PDT 24
Peak memory 264620 kb
Host smart-57681067-8042-43ef-bcaf-801c9448ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723609660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.723609660
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.218036326
Short name T838
Test name
Test status
Simulation time 2149305926 ps
CPU time 18.19 seconds
Started Jul 04 06:17:31 PM PDT 24
Finished Jul 04 06:17:50 PM PDT 24
Peak memory 219032 kb
Host smart-362e987f-a9b6-4116-ae95-713eaed4fb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218036326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.218036326
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.471880269
Short name T620
Test name
Test status
Simulation time 402564419 ps
CPU time 2.8 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:17:28 PM PDT 24
Peak memory 225580 kb
Host smart-a7dde20c-f271-4dc8-82bb-a80d8808ae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471880269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.471880269
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1522396
Short name T522
Test name
Test status
Simulation time 1186161974 ps
CPU time 11.26 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:40 PM PDT 24
Peak memory 225516 kb
Host smart-c47a7ca8-0d9a-454c-abf1-d50688e7997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1522396
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2200652975
Short name T468
Test name
Test status
Simulation time 2187382930 ps
CPU time 28.88 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 241840 kb
Host smart-4a758671-bd1c-4106-a52f-4f7c44c1c35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200652975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2200652975
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.520359838
Short name T643
Test name
Test status
Simulation time 5625434433 ps
CPU time 6.5 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:17:32 PM PDT 24
Peak memory 233896 kb
Host smart-58c6becb-1172-43ad-92eb-8d1a005c210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520359838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.520359838
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.84578065
Short name T649
Test name
Test status
Simulation time 1113821211 ps
CPU time 5.35 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:17:33 PM PDT 24
Peak memory 233732 kb
Host smart-4092cdf5-7882-4f29-a9b6-bbf5b0c6a775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84578065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.84578065
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3034114540
Short name T334
Test name
Test status
Simulation time 8414299707 ps
CPU time 13.11 seconds
Started Jul 04 06:17:31 PM PDT 24
Finished Jul 04 06:17:45 PM PDT 24
Peak memory 219884 kb
Host smart-11315aca-e8bb-4dbe-83e8-e39b0bbd039a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3034114540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3034114540
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3079037469
Short name T34
Test name
Test status
Simulation time 141480801838 ps
CPU time 1205.8 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:37:35 PM PDT 24
Peak memory 287448 kb
Host smart-fad46038-f389-4bff-aaa9-60512290ceb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079037469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3079037469
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1478467005
Short name T660
Test name
Test status
Simulation time 8319408507 ps
CPU time 19.92 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:17:44 PM PDT 24
Peak memory 217424 kb
Host smart-a8f037d6-ad5c-4dca-9b00-3d8261b375d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478467005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1478467005
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.13356022
Short name T517
Test name
Test status
Simulation time 1368742093 ps
CPU time 9.28 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:39 PM PDT 24
Peak memory 217340 kb
Host smart-61575670-7e5d-4247-9744-29682da79199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13356022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.13356022
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.518772418
Short name T731
Test name
Test status
Simulation time 254777535 ps
CPU time 3.6 seconds
Started Jul 04 06:17:24 PM PDT 24
Finished Jul 04 06:17:28 PM PDT 24
Peak memory 217380 kb
Host smart-00e96f40-2600-4c3c-82db-969680fb23ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518772418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.518772418
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.38899201
Short name T841
Test name
Test status
Simulation time 35230358 ps
CPU time 0.88 seconds
Started Jul 04 06:17:24 PM PDT 24
Finished Jul 04 06:17:25 PM PDT 24
Peak memory 207988 kb
Host smart-2986798e-fa40-4069-af5e-ec95bcb17f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38899201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.38899201
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2590235789
Short name T652
Test name
Test status
Simulation time 1122929256 ps
CPU time 4.46 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:34 PM PDT 24
Peak memory 233744 kb
Host smart-1c3bd0cf-5e1b-42a8-bd7e-c1aad71515a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590235789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2590235789
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.417326264
Short name T98
Test name
Test status
Simulation time 149028208 ps
CPU time 3.9 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:33 PM PDT 24
Peak memory 233704 kb
Host smart-8f607c55-b8b2-4181-9b35-69d53f3489c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417326264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.417326264
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.14281783
Short name T653
Test name
Test status
Simulation time 288358840 ps
CPU time 0.76 seconds
Started Jul 04 06:17:32 PM PDT 24
Finished Jul 04 06:17:33 PM PDT 24
Peak memory 207856 kb
Host smart-0d99fd54-b747-445e-8922-932b5cc84c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14281783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.14281783
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1111470109
Short name T595
Test name
Test status
Simulation time 903881609 ps
CPU time 10.02 seconds
Started Jul 04 06:17:31 PM PDT 24
Finished Jul 04 06:17:42 PM PDT 24
Peak memory 237900 kb
Host smart-3b3fa877-ab02-4539-a259-84276748475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111470109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1111470109
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3697359201
Short name T218
Test name
Test status
Simulation time 139612197083 ps
CPU time 158.7 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:20:08 PM PDT 24
Peak memory 252492 kb
Host smart-6e7d2b55-a571-4e93-8a9b-9c9870a741c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697359201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3697359201
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1843877770
Short name T135
Test name
Test status
Simulation time 5603016528 ps
CPU time 58.4 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:18:26 PM PDT 24
Peak memory 234028 kb
Host smart-b79b24b3-b767-45ab-972c-4947846e2eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843877770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1843877770
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2281676885
Short name T724
Test name
Test status
Simulation time 5837569305 ps
CPU time 15.83 seconds
Started Jul 04 06:17:39 PM PDT 24
Finished Jul 04 06:17:55 PM PDT 24
Peak memory 235908 kb
Host smart-fb97d809-e34d-4bb2-a5bf-2e637b19dd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281676885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2281676885
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3466196387
Short name T297
Test name
Test status
Simulation time 6760871444 ps
CPU time 45.03 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:18:13 PM PDT 24
Peak memory 253876 kb
Host smart-2505cb80-7e7b-4227-8e45-4268d27a6c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466196387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3466196387
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2597660661
Short name T230
Test name
Test status
Simulation time 4003015698 ps
CPU time 12.99 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:43 PM PDT 24
Peak memory 225732 kb
Host smart-923b24f3-9e82-43f6-937e-9f9c74dbd9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597660661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2597660661
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4260848593
Short name T763
Test name
Test status
Simulation time 51987484194 ps
CPU time 43.45 seconds
Started Jul 04 06:17:31 PM PDT 24
Finished Jul 04 06:18:15 PM PDT 24
Peak memory 233884 kb
Host smart-4007a711-5aca-4f4a-b669-507ed189e1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260848593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4260848593
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.4001388410
Short name T26
Test name
Test status
Simulation time 259638780 ps
CPU time 1.12 seconds
Started Jul 04 06:17:31 PM PDT 24
Finished Jul 04 06:17:33 PM PDT 24
Peak memory 217684 kb
Host smart-2dc042f6-03ca-4ade-87de-6b5082e156ba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001388410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.4001388410
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1484676546
Short name T820
Test name
Test status
Simulation time 78689225 ps
CPU time 2.24 seconds
Started Jul 04 06:17:30 PM PDT 24
Finished Jul 04 06:17:32 PM PDT 24
Peak memory 224176 kb
Host smart-9bf183c9-6738-4ebc-acb3-6410f177e5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484676546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1484676546
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3121062587
Short name T386
Test name
Test status
Simulation time 64860954 ps
CPU time 2.31 seconds
Started Jul 04 06:17:37 PM PDT 24
Finished Jul 04 06:17:40 PM PDT 24
Peak memory 233740 kb
Host smart-d60ecf0b-5ae6-457a-a6e0-a94e80a1baa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121062587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3121062587
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4118531080
Short name T798
Test name
Test status
Simulation time 144467058 ps
CPU time 4.02 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:34 PM PDT 24
Peak memory 223628 kb
Host smart-a4ec74f3-1e1d-4e97-8c42-ada2b3f99435
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4118531080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4118531080
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1019623353
Short name T963
Test name
Test status
Simulation time 98839121632 ps
CPU time 196.83 seconds
Started Jul 04 06:17:33 PM PDT 24
Finished Jul 04 06:20:50 PM PDT 24
Peak memory 250364 kb
Host smart-eb3b6033-ad03-4c0d-ab04-bb7dcf7ecf80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019623353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1019623353
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2703025545
Short name T828
Test name
Test status
Simulation time 15873695113 ps
CPU time 20.13 seconds
Started Jul 04 06:17:30 PM PDT 24
Finished Jul 04 06:17:51 PM PDT 24
Peak memory 217520 kb
Host smart-e9f789b1-b4b9-41d9-91b2-42727413ce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703025545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2703025545
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1386356955
Short name T965
Test name
Test status
Simulation time 2836000609 ps
CPU time 6.7 seconds
Started Jul 04 06:17:37 PM PDT 24
Finished Jul 04 06:17:44 PM PDT 24
Peak memory 217476 kb
Host smart-85881fb6-49e2-4c5b-8a73-0c535f6ee4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386356955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1386356955
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1094264896
Short name T414
Test name
Test status
Simulation time 17987708 ps
CPU time 0.69 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:30 PM PDT 24
Peak memory 206524 kb
Host smart-7b3077ce-e13b-4cf7-98e1-27bb3cd4f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094264896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1094264896
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1067341601
Short name T521
Test name
Test status
Simulation time 433825381 ps
CPU time 0.98 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:17:28 PM PDT 24
Peak memory 208012 kb
Host smart-9793feb7-531f-4bbd-8ff2-ecb96b9b8a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067341601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1067341601
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2660832241
Short name T934
Test name
Test status
Simulation time 37830638 ps
CPU time 0.7 seconds
Started Jul 04 06:17:35 PM PDT 24
Finished Jul 04 06:17:36 PM PDT 24
Peak memory 206728 kb
Host smart-a1e8fcd5-9651-4658-a54f-085095451cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660832241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2660832241
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1387376667
Short name T447
Test name
Test status
Simulation time 519943705 ps
CPU time 4.01 seconds
Started Jul 04 06:17:37 PM PDT 24
Finished Jul 04 06:17:41 PM PDT 24
Peak memory 225604 kb
Host smart-e564cf2d-3b94-45a8-84f8-2ec7bf907751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387376667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1387376667
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2221851155
Short name T421
Test name
Test status
Simulation time 16949716 ps
CPU time 0.78 seconds
Started Jul 04 06:17:33 PM PDT 24
Finished Jul 04 06:17:34 PM PDT 24
Peak memory 207508 kb
Host smart-2fdb9e88-6a25-4885-acf3-4c4285d61764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221851155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2221851155
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2946001910
Short name T1018
Test name
Test status
Simulation time 4634074466 ps
CPU time 48.29 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 250316 kb
Host smart-ba04b9de-94b6-43ee-85f1-82185325abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946001910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2946001910
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.656439252
Short name T317
Test name
Test status
Simulation time 7316536459 ps
CPU time 60.48 seconds
Started Jul 04 06:17:37 PM PDT 24
Finished Jul 04 06:18:38 PM PDT 24
Peak memory 250416 kb
Host smart-5176e8a2-2f7d-441d-9fdc-1262a273513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656439252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.656439252
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.78420412
Short name T290
Test name
Test status
Simulation time 141613960619 ps
CPU time 329.54 seconds
Started Jul 04 06:17:33 PM PDT 24
Finished Jul 04 06:23:03 PM PDT 24
Peak memory 250456 kb
Host smart-bc0c8a22-e4f3-412c-9554-6310521467f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78420412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.78420412
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.377658076
Short name T761
Test name
Test status
Simulation time 2596763950 ps
CPU time 7.57 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:37 PM PDT 24
Peak memory 225708 kb
Host smart-68a9a5f5-6a17-445b-8e1e-59724bd9a684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377658076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.377658076
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3317118650
Short name T650
Test name
Test status
Simulation time 12752677015 ps
CPU time 110.07 seconds
Started Jul 04 06:17:37 PM PDT 24
Finished Jul 04 06:19:27 PM PDT 24
Peak memory 250344 kb
Host smart-82cfee48-dcb9-40db-ab04-e92e3bf4bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317118650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3317118650
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1939384632
Short name T7
Test name
Test status
Simulation time 105464255 ps
CPU time 1.98 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:17:30 PM PDT 24
Peak memory 225056 kb
Host smart-248da89a-9ede-403e-9267-63d160545257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939384632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1939384632
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3346444030
Short name T998
Test name
Test status
Simulation time 6679403950 ps
CPU time 61.64 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:18:30 PM PDT 24
Peak memory 241840 kb
Host smart-108429bb-e936-41d7-9f90-2a51b6d80bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346444030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3346444030
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3144913525
Short name T817
Test name
Test status
Simulation time 31095751 ps
CPU time 1.13 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:30 PM PDT 24
Peak memory 217636 kb
Host smart-9749fdf2-3869-4e4e-a727-723f198cee80
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144913525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3144913525
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1368619172
Short name T991
Test name
Test status
Simulation time 1946319567 ps
CPU time 7.44 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:37 PM PDT 24
Peak memory 241280 kb
Host smart-0e9a7409-68e0-4c69-8b87-8bdfcd0555b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368619172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1368619172
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3038612771
Short name T502
Test name
Test status
Simulation time 144847909 ps
CPU time 2.46 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:17:30 PM PDT 24
Peak memory 224288 kb
Host smart-513519b5-3509-46c0-a685-934fee1546bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038612771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3038612771
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.824685108
Short name T981
Test name
Test status
Simulation time 167055005 ps
CPU time 4.3 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:34 PM PDT 24
Peak memory 224072 kb
Host smart-a8b5c906-f660-4b29-b41c-87b5dfd3ae99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=824685108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.824685108
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1336128869
Short name T29
Test name
Test status
Simulation time 1838983321 ps
CPU time 10 seconds
Started Jul 04 06:17:35 PM PDT 24
Finished Jul 04 06:17:45 PM PDT 24
Peak memory 218960 kb
Host smart-abea477e-6e7a-4d77-8532-de710db2d319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336128869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1336128869
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.734183934
Short name T313
Test name
Test status
Simulation time 9577435985 ps
CPU time 20.52 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:49 PM PDT 24
Peak memory 221000 kb
Host smart-cf7960fa-0718-4776-9ebf-2e2fa63185d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734183934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.734183934
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.933473358
Short name T939
Test name
Test status
Simulation time 32307020 ps
CPU time 0.71 seconds
Started Jul 04 06:17:33 PM PDT 24
Finished Jul 04 06:17:34 PM PDT 24
Peak memory 206632 kb
Host smart-c33f27a3-de18-49d6-91c5-176961a0070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933473358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.933473358
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2152061709
Short name T73
Test name
Test status
Simulation time 205863470 ps
CPU time 1.86 seconds
Started Jul 04 06:17:33 PM PDT 24
Finished Jul 04 06:17:35 PM PDT 24
Peak memory 217412 kb
Host smart-7186f8a4-a0da-4dd8-84b2-4dfb980a0597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152061709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2152061709
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.269014236
Short name T55
Test name
Test status
Simulation time 47968330 ps
CPU time 0.89 seconds
Started Jul 04 06:17:30 PM PDT 24
Finished Jul 04 06:17:31 PM PDT 24
Peak memory 206984 kb
Host smart-b8720a40-514a-42fb-92a9-9542456306c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269014236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.269014236
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2986852751
Short name T257
Test name
Test status
Simulation time 822220340 ps
CPU time 3.11 seconds
Started Jul 04 06:17:29 PM PDT 24
Finished Jul 04 06:17:32 PM PDT 24
Peak memory 225584 kb
Host smart-daf0993f-bd7d-42e6-884a-dd082a49ba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986852751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2986852751
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4138748648
Short name T500
Test name
Test status
Simulation time 20130171 ps
CPU time 0.75 seconds
Started Jul 04 06:17:42 PM PDT 24
Finished Jul 04 06:17:43 PM PDT 24
Peak memory 206376 kb
Host smart-9671438e-a56c-4660-9d8e-f83f7d44a989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138748648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4138748648
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4276081411
Short name T158
Test name
Test status
Simulation time 316787594 ps
CPU time 3.39 seconds
Started Jul 04 06:17:38 PM PDT 24
Finished Jul 04 06:17:42 PM PDT 24
Peak memory 233788 kb
Host smart-b8f8d0c0-e59d-413f-90c0-a510f5900884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276081411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4276081411
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.284794049
Short name T602
Test name
Test status
Simulation time 14797633 ps
CPU time 0.79 seconds
Started Jul 04 06:17:41 PM PDT 24
Finished Jul 04 06:17:42 PM PDT 24
Peak memory 207464 kb
Host smart-4eb47691-0f57-45b4-9ca7-d6082559401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284794049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.284794049
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4233451369
Short name T59
Test name
Test status
Simulation time 8359816898 ps
CPU time 29.88 seconds
Started Jul 04 06:17:43 PM PDT 24
Finished Jul 04 06:18:13 PM PDT 24
Peak memory 250336 kb
Host smart-af334617-63d5-453c-bacd-efffd6e74d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233451369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4233451369
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.185051346
Short name T557
Test name
Test status
Simulation time 1843804031 ps
CPU time 47.65 seconds
Started Jul 04 06:17:40 PM PDT 24
Finished Jul 04 06:18:28 PM PDT 24
Peak memory 250248 kb
Host smart-adfc9006-6f08-4e66-8685-28bc50e73b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185051346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.185051346
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4007448152
Short name T827
Test name
Test status
Simulation time 10065208608 ps
CPU time 68.52 seconds
Started Jul 04 06:17:38 PM PDT 24
Finished Jul 04 06:18:47 PM PDT 24
Peak memory 242104 kb
Host smart-19183c7e-375d-45cc-b7b6-704e37f77bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007448152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4007448152
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3181355520
Short name T245
Test name
Test status
Simulation time 306738513 ps
CPU time 5.34 seconds
Started Jul 04 06:17:35 PM PDT 24
Finished Jul 04 06:17:41 PM PDT 24
Peak memory 225580 kb
Host smart-10a4e532-4f01-416b-b2b3-e161602de9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181355520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3181355520
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2110186410
Short name T885
Test name
Test status
Simulation time 8272975585 ps
CPU time 59.3 seconds
Started Jul 04 06:17:38 PM PDT 24
Finished Jul 04 06:18:38 PM PDT 24
Peak memory 251464 kb
Host smart-83e51a40-1b58-46c5-99fb-123b5ecd8cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110186410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2110186410
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2133503399
Short name T539
Test name
Test status
Simulation time 113895007 ps
CPU time 1.06 seconds
Started Jul 04 06:17:33 PM PDT 24
Finished Jul 04 06:17:34 PM PDT 24
Peak memory 217684 kb
Host smart-8b569e60-d64e-4aa2-84d8-db24c9378041
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133503399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2133503399
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1065545405
Short name T492
Test name
Test status
Simulation time 309676404 ps
CPU time 3.99 seconds
Started Jul 04 06:17:40 PM PDT 24
Finished Jul 04 06:17:44 PM PDT 24
Peak memory 225532 kb
Host smart-2eb0905b-1661-479c-9ea1-7f13769e084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065545405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1065545405
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2844414305
Short name T247
Test name
Test status
Simulation time 2784081689 ps
CPU time 6.12 seconds
Started Jul 04 06:17:39 PM PDT 24
Finished Jul 04 06:17:46 PM PDT 24
Peak memory 225692 kb
Host smart-8d6c7fb4-1263-4dfd-827d-9011f1bb065a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844414305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2844414305
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2600135246
Short name T550
Test name
Test status
Simulation time 484507309 ps
CPU time 4.46 seconds
Started Jul 04 06:17:35 PM PDT 24
Finished Jul 04 06:17:39 PM PDT 24
Peak memory 223424 kb
Host smart-4e517c3c-603a-4ea1-ace1-16cb6097624a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2600135246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2600135246
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.170346126
Short name T489
Test name
Test status
Simulation time 15409729686 ps
CPU time 142.43 seconds
Started Jul 04 06:17:36 PM PDT 24
Finished Jul 04 06:19:58 PM PDT 24
Peak memory 250444 kb
Host smart-921972c4-6caf-4262-acb3-686001791c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170346126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.170346126
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.37997677
Short name T378
Test name
Test status
Simulation time 721680908 ps
CPU time 4.7 seconds
Started Jul 04 06:17:40 PM PDT 24
Finished Jul 04 06:17:45 PM PDT 24
Peak memory 217488 kb
Host smart-85b79ade-20b4-475a-8f89-66dbc91a3344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37997677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.37997677
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1009032100
Short name T826
Test name
Test status
Simulation time 4838619036 ps
CPU time 14.2 seconds
Started Jul 04 06:17:42 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 217396 kb
Host smart-553395b7-90ce-45fc-bef3-564f398745a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009032100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1009032100
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2996547325
Short name T972
Test name
Test status
Simulation time 186480322 ps
CPU time 2.21 seconds
Started Jul 04 06:17:47 PM PDT 24
Finished Jul 04 06:17:50 PM PDT 24
Peak memory 217412 kb
Host smart-ef54fee7-db3f-4eb7-9e87-36343bfefef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996547325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2996547325
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1857287765
Short name T941
Test name
Test status
Simulation time 30403693 ps
CPU time 0.85 seconds
Started Jul 04 06:17:38 PM PDT 24
Finished Jul 04 06:17:39 PM PDT 24
Peak memory 208052 kb
Host smart-e21ff537-7fb2-4535-a29e-faa42fdc3a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857287765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1857287765
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.797053347
Short name T41
Test name
Test status
Simulation time 1006108965 ps
CPU time 6.21 seconds
Started Jul 04 06:17:37 PM PDT 24
Finished Jul 04 06:17:44 PM PDT 24
Peak memory 233744 kb
Host smart-021343db-c647-4968-8c15-bd53c3bf2f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797053347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.797053347
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1886337837
Short name T855
Test name
Test status
Simulation time 11205575 ps
CPU time 0.76 seconds
Started Jul 04 06:17:47 PM PDT 24
Finished Jul 04 06:17:48 PM PDT 24
Peak memory 206360 kb
Host smart-3bc7604d-267f-4db7-ae3b-c982ab3549dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886337837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1886337837
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.968731329
Short name T513
Test name
Test status
Simulation time 111866213 ps
CPU time 2.5 seconds
Started Jul 04 06:17:45 PM PDT 24
Finished Jul 04 06:17:48 PM PDT 24
Peak memory 225536 kb
Host smart-2c2884e6-4b60-48c7-a5e3-383f3ea8c19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968731329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.968731329
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2084676989
Short name T993
Test name
Test status
Simulation time 19724574 ps
CPU time 0.81 seconds
Started Jul 04 06:17:41 PM PDT 24
Finished Jul 04 06:17:42 PM PDT 24
Peak memory 207548 kb
Host smart-3a33d479-c609-4568-84cb-8ad0d05fe03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084676989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2084676989
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3813212082
Short name T795
Test name
Test status
Simulation time 59514388 ps
CPU time 0.82 seconds
Started Jul 04 06:17:48 PM PDT 24
Finished Jul 04 06:17:49 PM PDT 24
Peak memory 217180 kb
Host smart-62eb1315-3efc-4208-9aee-a1b0e414eccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813212082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3813212082
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2273757822
Short name T689
Test name
Test status
Simulation time 14045641015 ps
CPU time 108.42 seconds
Started Jul 04 06:17:45 PM PDT 24
Finished Jul 04 06:19:34 PM PDT 24
Peak memory 258612 kb
Host smart-1f8827aa-ca30-409f-afc6-586d1b3228cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273757822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2273757822
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1835115618
Short name T895
Test name
Test status
Simulation time 909736041 ps
CPU time 8.23 seconds
Started Jul 04 06:17:42 PM PDT 24
Finished Jul 04 06:17:51 PM PDT 24
Peak memory 225584 kb
Host smart-94b3333b-02b0-4f38-8048-5a1a5ef6fd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835115618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1835115618
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3713407482
Short name T46
Test name
Test status
Simulation time 33026896204 ps
CPU time 221.51 seconds
Started Jul 04 06:17:48 PM PDT 24
Finished Jul 04 06:21:30 PM PDT 24
Peak memory 251340 kb
Host smart-099edcdd-f155-468c-8181-7dfc1a283b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713407482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3713407482
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3637211586
Short name T279
Test name
Test status
Simulation time 766876136 ps
CPU time 9.28 seconds
Started Jul 04 06:17:41 PM PDT 24
Finished Jul 04 06:17:51 PM PDT 24
Peak memory 233772 kb
Host smart-53400480-430e-438f-90f7-8e184a067573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637211586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3637211586
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3983807537
Short name T601
Test name
Test status
Simulation time 5297710351 ps
CPU time 50.13 seconds
Started Jul 04 06:17:47 PM PDT 24
Finished Jul 04 06:18:37 PM PDT 24
Peak memory 241564 kb
Host smart-a14d897b-4cf4-48c8-a3cf-59d8e7419df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983807537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3983807537
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3270618874
Short name T889
Test name
Test status
Simulation time 23456518 ps
CPU time 1.03 seconds
Started Jul 04 06:17:41 PM PDT 24
Finished Jul 04 06:17:42 PM PDT 24
Peak memory 217692 kb
Host smart-110bca6d-eddf-4f80-8923-4e29070ad1bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270618874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3270618874
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.913432939
Short name T438
Test name
Test status
Simulation time 32388874 ps
CPU time 2.56 seconds
Started Jul 04 06:17:43 PM PDT 24
Finished Jul 04 06:17:46 PM PDT 24
Peak memory 233528 kb
Host smart-42ad0eab-87a1-4267-ac3e-816e7348945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913432939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.913432939
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.156516814
Short name T167
Test name
Test status
Simulation time 1184779137 ps
CPU time 10.83 seconds
Started Jul 04 06:17:49 PM PDT 24
Finished Jul 04 06:18:00 PM PDT 24
Peak memory 240468 kb
Host smart-19f7c4fd-87c5-4b32-8ba2-fced25be1442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156516814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.156516814
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1033934241
Short name T552
Test name
Test status
Simulation time 719134770 ps
CPU time 4.76 seconds
Started Jul 04 06:17:46 PM PDT 24
Finished Jul 04 06:17:50 PM PDT 24
Peak memory 223560 kb
Host smart-867feda2-595f-4ea9-ab5b-532bf6d836ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1033934241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1033934241
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3369182190
Short name T455
Test name
Test status
Simulation time 1728534746 ps
CPU time 19.95 seconds
Started Jul 04 06:17:43 PM PDT 24
Finished Jul 04 06:18:03 PM PDT 24
Peak memory 220496 kb
Host smart-32a9efb4-e899-4672-aa77-0eceab55b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369182190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3369182190
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4127803027
Short name T638
Test name
Test status
Simulation time 2394942943 ps
CPU time 6.28 seconds
Started Jul 04 06:17:36 PM PDT 24
Finished Jul 04 06:17:42 PM PDT 24
Peak memory 217508 kb
Host smart-4fbf62fb-f7a3-4121-a06a-757b5eb61983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127803027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4127803027
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3791255931
Short name T594
Test name
Test status
Simulation time 126070691 ps
CPU time 1.37 seconds
Started Jul 04 06:17:42 PM PDT 24
Finished Jul 04 06:17:43 PM PDT 24
Peak memory 217448 kb
Host smart-56b9d775-c0a6-4de8-856e-c5398930a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791255931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3791255931
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3615425605
Short name T956
Test name
Test status
Simulation time 66402186 ps
CPU time 0.77 seconds
Started Jul 04 06:17:43 PM PDT 24
Finished Jul 04 06:17:44 PM PDT 24
Peak memory 207012 kb
Host smart-2ba51fd0-4829-48ac-bed3-a551b1309688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615425605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3615425605
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2635531626
Short name T283
Test name
Test status
Simulation time 228660489 ps
CPU time 5.51 seconds
Started Jul 04 06:17:42 PM PDT 24
Finished Jul 04 06:17:48 PM PDT 24
Peak memory 233748 kb
Host smart-d6b1b896-f13e-4b55-a896-a09032db5c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635531626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2635531626
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2129807581
Short name T676
Test name
Test status
Simulation time 45714626 ps
CPU time 0.72 seconds
Started Jul 04 06:17:49 PM PDT 24
Finished Jul 04 06:17:50 PM PDT 24
Peak memory 206736 kb
Host smart-81e7b965-8d28-44d0-b5b3-ef63c7619163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129807581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2129807581
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1611287878
Short name T834
Test name
Test status
Simulation time 205063084 ps
CPU time 3.38 seconds
Started Jul 04 06:17:48 PM PDT 24
Finished Jul 04 06:17:51 PM PDT 24
Peak memory 225512 kb
Host smart-6100da40-e94d-4257-aedf-85f18e15a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611287878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1611287878
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.576450462
Short name T603
Test name
Test status
Simulation time 25694994 ps
CPU time 0.75 seconds
Started Jul 04 06:17:51 PM PDT 24
Finished Jul 04 06:17:52 PM PDT 24
Peak memory 206520 kb
Host smart-51478793-5712-4fef-b8a1-4f97045772ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576450462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.576450462
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3117577658
Short name T498
Test name
Test status
Simulation time 3403773347 ps
CPU time 8.4 seconds
Started Jul 04 06:17:46 PM PDT 24
Finished Jul 04 06:17:55 PM PDT 24
Peak memory 225664 kb
Host smart-b2394547-83a7-4093-ba52-5aaa6252b646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117577658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3117577658
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2564367695
Short name T612
Test name
Test status
Simulation time 14591090558 ps
CPU time 63.61 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:18:57 PM PDT 24
Peak memory 249648 kb
Host smart-43359b28-a7b7-4c2a-8a56-6313718082ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564367695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2564367695
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3359202075
Short name T928
Test name
Test status
Simulation time 39998077331 ps
CPU time 123.58 seconds
Started Jul 04 06:17:49 PM PDT 24
Finished Jul 04 06:19:52 PM PDT 24
Peak memory 250452 kb
Host smart-99030a2f-f446-427a-8617-d9345c899276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359202075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3359202075
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3272135037
Short name T764
Test name
Test status
Simulation time 257461297 ps
CPU time 4.15 seconds
Started Jul 04 06:17:46 PM PDT 24
Finished Jul 04 06:17:50 PM PDT 24
Peak memory 225552 kb
Host smart-f341173d-28a9-4b26-a09b-640ac6ab340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272135037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3272135037
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1053555672
Short name T234
Test name
Test status
Simulation time 48620808808 ps
CPU time 212.04 seconds
Started Jul 04 06:17:51 PM PDT 24
Finished Jul 04 06:21:23 PM PDT 24
Peak memory 254288 kb
Host smart-361ee015-520b-4454-abc8-f293325e344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053555672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1053555672
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1541157900
Short name T235
Test name
Test status
Simulation time 1497139834 ps
CPU time 10.25 seconds
Started Jul 04 06:17:52 PM PDT 24
Finished Jul 04 06:18:02 PM PDT 24
Peak memory 225548 kb
Host smart-13939abf-81c4-438f-9308-de372e91c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541157900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1541157900
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.73879674
Short name T554
Test name
Test status
Simulation time 1577347802 ps
CPU time 10.5 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:18:03 PM PDT 24
Peak memory 240752 kb
Host smart-8ea991e6-4f8e-490d-9fb6-62580a93083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73879674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.73879674
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.570044900
Short name T908
Test name
Test status
Simulation time 60994150 ps
CPU time 1.07 seconds
Started Jul 04 06:17:46 PM PDT 24
Finished Jul 04 06:17:48 PM PDT 24
Peak memory 217640 kb
Host smart-403fa962-1cd1-4a79-a803-73a2483c491e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570044900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.570044900
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3206455626
Short name T273
Test name
Test status
Simulation time 12896135320 ps
CPU time 33.88 seconds
Started Jul 04 06:17:46 PM PDT 24
Finished Jul 04 06:18:21 PM PDT 24
Peak memory 234964 kb
Host smart-8c1f3064-8a28-48a3-8022-a729725bf3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206455626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3206455626
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.721858933
Short name T927
Test name
Test status
Simulation time 1109386917 ps
CPU time 4.74 seconds
Started Jul 04 06:17:49 PM PDT 24
Finished Jul 04 06:17:54 PM PDT 24
Peak memory 225632 kb
Host smart-1b4dc96b-1540-42e8-a07e-72b507bb967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721858933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.721858933
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2071020311
Short name T140
Test name
Test status
Simulation time 5073823155 ps
CPU time 16.16 seconds
Started Jul 04 06:17:50 PM PDT 24
Finished Jul 04 06:18:07 PM PDT 24
Peak memory 221648 kb
Host smart-554f14bb-97a8-46fe-9aad-43081868f267
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071020311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2071020311
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4129097569
Short name T647
Test name
Test status
Simulation time 12846704615 ps
CPU time 26.72 seconds
Started Jul 04 06:17:47 PM PDT 24
Finished Jul 04 06:18:14 PM PDT 24
Peak memory 217808 kb
Host smart-f2843f0f-59e2-47eb-9ade-8fbbe7dc0440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129097569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4129097569
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2099764657
Short name T1002
Test name
Test status
Simulation time 4752512982 ps
CPU time 15.01 seconds
Started Jul 04 06:17:47 PM PDT 24
Finished Jul 04 06:18:03 PM PDT 24
Peak memory 217548 kb
Host smart-6da1f8b0-d728-4a91-bd94-a537d6bee1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099764657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2099764657
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2370915445
Short name T410
Test name
Test status
Simulation time 782558792 ps
CPU time 1.77 seconds
Started Jul 04 06:17:52 PM PDT 24
Finished Jul 04 06:17:54 PM PDT 24
Peak memory 217340 kb
Host smart-b0a70b7e-56e1-4a5d-aa71-ac30dae2db5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370915445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2370915445
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1705603832
Short name T942
Test name
Test status
Simulation time 31815261 ps
CPU time 0.75 seconds
Started Jul 04 06:17:50 PM PDT 24
Finished Jul 04 06:17:51 PM PDT 24
Peak memory 207004 kb
Host smart-66875870-8b4c-4cb1-81db-e873873f6949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705603832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1705603832
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4220398038
Short name T258
Test name
Test status
Simulation time 185295444 ps
CPU time 2.73 seconds
Started Jul 04 06:17:47 PM PDT 24
Finished Jul 04 06:17:50 PM PDT 24
Peak memory 225520 kb
Host smart-30120226-bf15-4f00-8af0-6f74aaffe611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220398038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4220398038
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3711529840
Short name T619
Test name
Test status
Simulation time 42930540 ps
CPU time 0.71 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:17:54 PM PDT 24
Peak memory 206748 kb
Host smart-acdd1676-d16a-4102-82ff-6874fda12347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711529840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3711529840
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2031257973
Short name T248
Test name
Test status
Simulation time 201352800 ps
CPU time 2.8 seconds
Started Jul 04 06:17:56 PM PDT 24
Finished Jul 04 06:17:59 PM PDT 24
Peak memory 233840 kb
Host smart-5d4f8b21-8891-4cd7-9de4-3599b9ee0c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031257973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2031257973
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3569337996
Short name T833
Test name
Test status
Simulation time 51060183 ps
CPU time 0.71 seconds
Started Jul 04 06:17:54 PM PDT 24
Finished Jul 04 06:17:55 PM PDT 24
Peak memory 206480 kb
Host smart-82f383f0-0aa1-43a2-aa66-04c9925837dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569337996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3569337996
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.959707225
Short name T181
Test name
Test status
Simulation time 13047226308 ps
CPU time 109.78 seconds
Started Jul 04 06:17:58 PM PDT 24
Finished Jul 04 06:19:48 PM PDT 24
Peak memory 265880 kb
Host smart-e559a508-0492-4011-9bc5-58d75c087fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959707225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.959707225
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.871321443
Short name T51
Test name
Test status
Simulation time 55048074513 ps
CPU time 247.41 seconds
Started Jul 04 06:18:05 PM PDT 24
Finished Jul 04 06:22:13 PM PDT 24
Peak memory 251460 kb
Host smart-8759ffd9-c450-41d9-a413-54c885e900ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871321443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.871321443
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2618153984
Short name T138
Test name
Test status
Simulation time 43598485963 ps
CPU time 377.32 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:24:11 PM PDT 24
Peak memory 268212 kb
Host smart-cf5b8949-e766-4fbc-9bd4-39ec1c81e965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618153984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2618153984
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.663240814
Short name T877
Test name
Test status
Simulation time 3888601452 ps
CPU time 19.43 seconds
Started Jul 04 06:17:48 PM PDT 24
Finished Jul 04 06:18:08 PM PDT 24
Peak memory 241964 kb
Host smart-1078cb65-7ecb-47fd-a995-cad68a2aad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663240814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.663240814
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1336736420
Short name T1004
Test name
Test status
Simulation time 2850546364 ps
CPU time 19.9 seconds
Started Jul 04 06:17:49 PM PDT 24
Finished Jul 04 06:18:09 PM PDT 24
Peak memory 242116 kb
Host smart-b4cff09e-eb6d-4e72-9acb-07e11f1802d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336736420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1336736420
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4100435993
Short name T804
Test name
Test status
Simulation time 1987276844 ps
CPU time 20.23 seconds
Started Jul 04 06:17:51 PM PDT 24
Finished Jul 04 06:18:11 PM PDT 24
Peak memory 225620 kb
Host smart-aa4dd15a-3f18-4f7f-a874-056cefab734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100435993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4100435993
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1761395275
Short name T995
Test name
Test status
Simulation time 168286360 ps
CPU time 5.19 seconds
Started Jul 04 06:17:50 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 225596 kb
Host smart-1402b71b-0fd8-4be2-9380-e9b7a09ed01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761395275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1761395275
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2055675450
Short name T506
Test name
Test status
Simulation time 16187302 ps
CPU time 1.08 seconds
Started Jul 04 06:17:48 PM PDT 24
Finished Jul 04 06:17:50 PM PDT 24
Peak memory 217704 kb
Host smart-dde6096e-78aa-4b5c-969e-72202c665dff
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055675450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2055675450
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2913612918
Short name T907
Test name
Test status
Simulation time 2565780159 ps
CPU time 7.74 seconds
Started Jul 04 06:17:50 PM PDT 24
Finished Jul 04 06:17:58 PM PDT 24
Peak memory 225644 kb
Host smart-f8eabfad-8136-493f-9bc5-c9c2dca1ff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913612918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2913612918
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.27131681
Short name T251
Test name
Test status
Simulation time 609274084 ps
CPU time 9.21 seconds
Started Jul 04 06:17:48 PM PDT 24
Finished Jul 04 06:17:58 PM PDT 24
Peak memory 241740 kb
Host smart-bd0abc68-0f3a-470a-865f-4faf2f387083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27131681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.27131681
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.154968692
Short name T537
Test name
Test status
Simulation time 4636562839 ps
CPU time 5.48 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:18:01 PM PDT 24
Peak memory 220496 kb
Host smart-479a1456-5d55-4b7c-9576-d547e130b52b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=154968692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.154968692
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3746607040
Short name T404
Test name
Test status
Simulation time 2408942583 ps
CPU time 16.23 seconds
Started Jul 04 06:17:52 PM PDT 24
Finished Jul 04 06:18:09 PM PDT 24
Peak memory 217504 kb
Host smart-efcb3afe-037d-4946-a0a5-5985709ae9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746607040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3746607040
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1863484408
Short name T640
Test name
Test status
Simulation time 357871664 ps
CPU time 3.41 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 217328 kb
Host smart-97e4fd09-0c72-465f-a9e4-c5aabec9dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863484408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1863484408
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.589214600
Short name T444
Test name
Test status
Simulation time 189289829 ps
CPU time 3.63 seconds
Started Jul 04 06:17:50 PM PDT 24
Finished Jul 04 06:17:54 PM PDT 24
Peak memory 217364 kb
Host smart-7c7bd7a2-ef88-4310-8e2c-811818303dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589214600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.589214600
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.852096921
Short name T938
Test name
Test status
Simulation time 61025539 ps
CPU time 0.89 seconds
Started Jul 04 06:17:47 PM PDT 24
Finished Jul 04 06:17:48 PM PDT 24
Peak memory 207428 kb
Host smart-8d548cf7-1751-48da-bb43-617b9618e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852096921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.852096921
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.340798787
Short name T932
Test name
Test status
Simulation time 1503149141 ps
CPU time 6.41 seconds
Started Jul 04 06:17:49 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 234792 kb
Host smart-4ca15507-1500-4204-8b6d-d2567732b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340798787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.340798787
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1095699585
Short name T766
Test name
Test status
Simulation time 32168581 ps
CPU time 0.72 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 206376 kb
Host smart-1a12741f-6a3f-47f8-a121-79a15d025c4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095699585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1095699585
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4030910356
Short name T870
Test name
Test status
Simulation time 67023564 ps
CPU time 2.85 seconds
Started Jul 04 06:17:58 PM PDT 24
Finished Jul 04 06:18:01 PM PDT 24
Peak memory 225544 kb
Host smart-038baaae-52a5-406d-ad8b-2c2e6b958352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030910356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4030910356
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.997207094
Short name T528
Test name
Test status
Simulation time 64967530 ps
CPU time 0.8 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 207868 kb
Host smart-3089ea05-a41b-4e3f-9a5c-cd7e64bbb6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997207094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.997207094
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.324394791
Short name T406
Test name
Test status
Simulation time 3486350437 ps
CPU time 34.85 seconds
Started Jul 04 06:17:56 PM PDT 24
Finished Jul 04 06:18:31 PM PDT 24
Peak memory 250288 kb
Host smart-2299d17e-8eb1-422a-b42a-2e0efccf9bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324394791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.324394791
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1746939437
Short name T419
Test name
Test status
Simulation time 7111935312 ps
CPU time 110.37 seconds
Started Jul 04 06:17:57 PM PDT 24
Finished Jul 04 06:19:48 PM PDT 24
Peak memory 264024 kb
Host smart-e08fb63c-cefc-46a8-8ef6-8afae8eb6b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746939437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1746939437
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2814025609
Short name T560
Test name
Test status
Simulation time 3225748587 ps
CPU time 12.36 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:18:07 PM PDT 24
Peak memory 235848 kb
Host smart-45d69333-e1ec-41a1-8d7e-6a9959682727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814025609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2814025609
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3731866587
Short name T89
Test name
Test status
Simulation time 19824247504 ps
CPU time 41.46 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:18:37 PM PDT 24
Peak memory 250348 kb
Host smart-7f61ed9a-8aa7-461e-a9f5-a4621c9ffdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731866587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3731866587
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2481627449
Short name T627
Test name
Test status
Simulation time 190339960 ps
CPU time 4.78 seconds
Started Jul 04 06:17:56 PM PDT 24
Finished Jul 04 06:18:01 PM PDT 24
Peak memory 233768 kb
Host smart-ef1c21aa-bb8b-4d12-9b9e-a69787836a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481627449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2481627449
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.152298523
Short name T164
Test name
Test status
Simulation time 29897112084 ps
CPU time 59.05 seconds
Started Jul 04 06:17:56 PM PDT 24
Finished Jul 04 06:18:55 PM PDT 24
Peak memory 233816 kb
Host smart-aaed0f42-56da-45b3-b942-b9fb66205b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152298523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.152298523
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4166943785
Short name T4
Test name
Test status
Simulation time 48625227 ps
CPU time 1.04 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 219004 kb
Host smart-22b66793-5327-4128-93c1-a8a566158b37
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166943785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4166943785
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3265210872
Short name T793
Test name
Test status
Simulation time 358054911 ps
CPU time 3.52 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:17:59 PM PDT 24
Peak memory 225568 kb
Host smart-9e79503d-3af3-498d-b960-8c0da1fc8b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265210872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3265210872
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3676748396
Short name T609
Test name
Test status
Simulation time 366197255 ps
CPU time 4.9 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:17:58 PM PDT 24
Peak memory 233780 kb
Host smart-cc83ef6d-b306-4279-9d1d-53dc41d82e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676748396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3676748396
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.694204728
Short name T361
Test name
Test status
Simulation time 105937402 ps
CPU time 4.26 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:18:00 PM PDT 24
Peak memory 220164 kb
Host smart-781ec2c5-8ae7-47ae-b2a2-3240c2de306a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=694204728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.694204728
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3922270602
Short name T154
Test name
Test status
Simulation time 333644954 ps
CPU time 1.12 seconds
Started Jul 04 06:17:59 PM PDT 24
Finished Jul 04 06:18:01 PM PDT 24
Peak memory 207976 kb
Host smart-305be1fb-4f50-4ad4-accf-29fcc42da209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922270602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3922270602
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3597763210
Short name T687
Test name
Test status
Simulation time 3913771923 ps
CPU time 22.25 seconds
Started Jul 04 06:17:58 PM PDT 24
Finished Jul 04 06:18:20 PM PDT 24
Peak memory 217492 kb
Host smart-685e6fb6-f3b8-4327-89f3-3abc4ddc2a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597763210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3597763210
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2694526230
Short name T512
Test name
Test status
Simulation time 6532704799 ps
CPU time 20.05 seconds
Started Jul 04 06:17:54 PM PDT 24
Finished Jul 04 06:18:15 PM PDT 24
Peak memory 217476 kb
Host smart-47f92fb3-e009-4449-aa8f-ad19ca989a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694526230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2694526230
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3756600746
Short name T72
Test name
Test status
Simulation time 20117369 ps
CPU time 1.06 seconds
Started Jul 04 06:17:58 PM PDT 24
Finished Jul 04 06:17:59 PM PDT 24
Peak memory 208072 kb
Host smart-6506597f-348b-49a1-a644-52f875e8ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756600746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3756600746
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2455779662
Short name T534
Test name
Test status
Simulation time 126897805 ps
CPU time 0.81 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:17:54 PM PDT 24
Peak memory 206992 kb
Host smart-00a003d4-7894-4fb4-b45e-2b9b5d255b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455779662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2455779662
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2068545022
Short name T409
Test name
Test status
Simulation time 2015518439 ps
CPU time 6.85 seconds
Started Jul 04 06:17:52 PM PDT 24
Finished Jul 04 06:17:59 PM PDT 24
Peak memory 233776 kb
Host smart-f9d10576-7998-4da8-a086-4453d5abf0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068545022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2068545022
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.313675198
Short name T370
Test name
Test status
Simulation time 43807873 ps
CPU time 0.72 seconds
Started Jul 04 06:16:57 PM PDT 24
Finished Jul 04 06:16:58 PM PDT 24
Peak memory 206388 kb
Host smart-70888a38-3f46-4045-83ea-61b52c727be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313675198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.313675198
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.73571468
Short name T663
Test name
Test status
Simulation time 1370386596 ps
CPU time 13.31 seconds
Started Jul 04 06:16:54 PM PDT 24
Finished Jul 04 06:17:08 PM PDT 24
Peak memory 225552 kb
Host smart-99052ca4-b658-4aa3-b0a2-aad8d114da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73571468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.73571468
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4234783895
Short name T900
Test name
Test status
Simulation time 60430934 ps
CPU time 0.77 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:10 PM PDT 24
Peak memory 207548 kb
Host smart-1595f907-ff8c-47a3-a667-1a897289ee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234783895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4234783895
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1542977971
Short name T294
Test name
Test status
Simulation time 7363983824 ps
CPU time 100.48 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:18:39 PM PDT 24
Peak memory 266068 kb
Host smart-8880f785-1759-44e1-b706-187105f2fa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542977971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1542977971
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.267762760
Short name T226
Test name
Test status
Simulation time 1837029928 ps
CPU time 29.06 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:38 PM PDT 24
Peak memory 233732 kb
Host smart-02388a62-ea31-43f8-bdc5-2fafaf293248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267762760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.267762760
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3612503214
Short name T236
Test name
Test status
Simulation time 552622594 ps
CPU time 3.75 seconds
Started Jul 04 06:16:53 PM PDT 24
Finished Jul 04 06:16:57 PM PDT 24
Peak memory 225488 kb
Host smart-6945c8a7-1aee-4b02-8910-b7e6ea2ab2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612503214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3612503214
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2475931079
Short name T634
Test name
Test status
Simulation time 1022627601 ps
CPU time 12.04 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:17:10 PM PDT 24
Peak memory 241568 kb
Host smart-bcb24d6f-1314-40c4-9e36-3fef191977a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475931079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2475931079
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1588157280
Short name T402
Test name
Test status
Simulation time 21176297 ps
CPU time 1.02 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:17:00 PM PDT 24
Peak memory 217692 kb
Host smart-0dc6da00-e84a-4820-a788-4ba3b5b94277
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588157280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1588157280
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1744702173
Short name T574
Test name
Test status
Simulation time 34010682 ps
CPU time 2.36 seconds
Started Jul 04 06:16:56 PM PDT 24
Finished Jul 04 06:16:58 PM PDT 24
Peak memory 233764 kb
Host smart-6762c24f-0d42-4d91-92ef-ac3817c28bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744702173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1744702173
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2797837031
Short name T694
Test name
Test status
Simulation time 3238617346 ps
CPU time 11.52 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:17:09 PM PDT 24
Peak memory 233876 kb
Host smart-95e04a71-e153-4905-b741-fa303b978f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797837031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2797837031
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3407257360
Short name T460
Test name
Test status
Simulation time 242137469 ps
CPU time 5.71 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 224060 kb
Host smart-2fab179d-3a08-46ad-bfaa-062b7a0f4904
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3407257360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3407257360
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3102011597
Short name T57
Test name
Test status
Simulation time 38748355768 ps
CPU time 110.87 seconds
Started Jul 04 06:16:53 PM PDT 24
Finished Jul 04 06:18:44 PM PDT 24
Peak memory 268188 kb
Host smart-f6b70c9f-8eb2-44e8-b3d6-aed86d902386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102011597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3102011597
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.571884035
Short name T443
Test name
Test status
Simulation time 11180673282 ps
CPU time 22.21 seconds
Started Jul 04 06:16:56 PM PDT 24
Finished Jul 04 06:17:19 PM PDT 24
Peak memory 217500 kb
Host smart-11724cb2-50bc-4cf8-a631-e30b57a257de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571884035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.571884035
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2562183887
Short name T542
Test name
Test status
Simulation time 1817126943 ps
CPU time 6.04 seconds
Started Jul 04 06:17:03 PM PDT 24
Finished Jul 04 06:17:09 PM PDT 24
Peak memory 217388 kb
Host smart-211f30a1-ed88-435d-933e-5aec98ab105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562183887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2562183887
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.35468594
Short name T840
Test name
Test status
Simulation time 313921092 ps
CPU time 1.8 seconds
Started Jul 04 06:16:55 PM PDT 24
Finished Jul 04 06:16:57 PM PDT 24
Peak memory 217320 kb
Host smart-861670dc-925e-4784-859b-d2d87fdb1fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35468594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.35468594
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3279388668
Short name T355
Test name
Test status
Simulation time 157737380 ps
CPU time 0.89 seconds
Started Jul 04 06:16:55 PM PDT 24
Finished Jul 04 06:16:56 PM PDT 24
Peak memory 206980 kb
Host smart-d8f50d62-6909-4bd0-8ee4-078c3f8740f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279388668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3279388668
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.213544860
Short name T706
Test name
Test status
Simulation time 1631248341 ps
CPU time 14.4 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:17:13 PM PDT 24
Peak memory 241440 kb
Host smart-95db9080-040d-4e5a-90a3-62a03b143451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213544860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.213544860
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1356436169
Short name T452
Test name
Test status
Simulation time 18306154 ps
CPU time 0.73 seconds
Started Jul 04 06:17:54 PM PDT 24
Finished Jul 04 06:17:55 PM PDT 24
Peak memory 206700 kb
Host smart-e4cecc2e-d046-4900-b549-2e6bca30f2ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356436169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1356436169
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1270032604
Short name T515
Test name
Test status
Simulation time 111518773 ps
CPU time 2.74 seconds
Started Jul 04 06:17:56 PM PDT 24
Finished Jul 04 06:17:59 PM PDT 24
Peak memory 233732 kb
Host smart-30af02d5-521a-4847-96d9-e8e88253f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270032604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1270032604
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3829594489
Short name T815
Test name
Test status
Simulation time 20620128 ps
CPU time 0.77 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:17:56 PM PDT 24
Peak memory 207548 kb
Host smart-9b8058c9-4170-4bd5-89ac-8bb4ba67d333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829594489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3829594489
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.898523880
Short name T198
Test name
Test status
Simulation time 3130145543 ps
CPU time 37 seconds
Started Jul 04 06:17:58 PM PDT 24
Finished Jul 04 06:18:35 PM PDT 24
Peak memory 256388 kb
Host smart-241858dd-a843-4e3e-9fa7-411b2eda8997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898523880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.898523880
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2265561519
Short name T442
Test name
Test status
Simulation time 18831852914 ps
CPU time 75.03 seconds
Started Jul 04 06:17:59 PM PDT 24
Finished Jul 04 06:19:14 PM PDT 24
Peak memory 250756 kb
Host smart-25ef555d-33da-4407-a983-f9cc8560ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265561519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2265561519
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.285417165
Short name T553
Test name
Test status
Simulation time 13547195860 ps
CPU time 10.58 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:18:06 PM PDT 24
Peak memory 218912 kb
Host smart-fb3fbd86-b46f-497e-9660-5432aa6be470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285417165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.285417165
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2408501370
Short name T351
Test name
Test status
Simulation time 68739218 ps
CPU time 3.23 seconds
Started Jul 04 06:17:56 PM PDT 24
Finished Jul 04 06:17:59 PM PDT 24
Peak memory 233776 kb
Host smart-f31c8ccb-342a-4844-9628-0a8c39688f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408501370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2408501370
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2589752271
Short name T196
Test name
Test status
Simulation time 3236540708 ps
CPU time 24.75 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 251288 kb
Host smart-5e9f0679-745c-4e2c-9a17-de0043c4bb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589752271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2589752271
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1226335002
Short name T430
Test name
Test status
Simulation time 878163667 ps
CPU time 6.08 seconds
Started Jul 04 06:17:58 PM PDT 24
Finished Jul 04 06:18:05 PM PDT 24
Peak memory 225476 kb
Host smart-f2b07b4b-01ab-4d89-8f32-96a05ef009f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226335002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1226335002
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2988493410
Short name T220
Test name
Test status
Simulation time 1943335905 ps
CPU time 22.04 seconds
Started Jul 04 06:18:00 PM PDT 24
Finished Jul 04 06:18:23 PM PDT 24
Peak memory 225556 kb
Host smart-40175f49-7e01-4cdc-bf26-4bc7908c0de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988493410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2988493410
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.934716420
Short name T293
Test name
Test status
Simulation time 423757315 ps
CPU time 7.81 seconds
Started Jul 04 06:17:57 PM PDT 24
Finished Jul 04 06:18:05 PM PDT 24
Peak memory 233724 kb
Host smart-f4fd4e3c-345e-4b00-80c3-e529a06497aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934716420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.934716420
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.429617864
Short name T225
Test name
Test status
Simulation time 796984117 ps
CPU time 6.9 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:18:02 PM PDT 24
Peak memory 233800 kb
Host smart-0d94a802-421b-4bad-8f09-4898cd977cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429617864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.429617864
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2805204322
Short name T501
Test name
Test status
Simulation time 2512824481 ps
CPU time 7.66 seconds
Started Jul 04 06:17:54 PM PDT 24
Finished Jul 04 06:18:02 PM PDT 24
Peak memory 220012 kb
Host smart-8e7a243e-3dd8-4687-95e0-35bfd7e32bf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2805204322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2805204322
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3563205143
Short name T153
Test name
Test status
Simulation time 8491055064 ps
CPU time 94.49 seconds
Started Jul 04 06:17:58 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 242172 kb
Host smart-3c2107a7-4251-4e9b-9703-127518d1524c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563205143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3563205143
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4151077158
Short name T484
Test name
Test status
Simulation time 7020465506 ps
CPU time 43.94 seconds
Started Jul 04 06:17:53 PM PDT 24
Finished Jul 04 06:18:38 PM PDT 24
Peak memory 217524 kb
Host smart-e61219cf-09c7-4974-899d-eb9dfd886b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151077158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4151077158
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.86802301
Short name T371
Test name
Test status
Simulation time 1212004332 ps
CPU time 2.95 seconds
Started Jul 04 06:17:54 PM PDT 24
Finished Jul 04 06:17:57 PM PDT 24
Peak memory 217356 kb
Host smart-41fe65a9-2bb6-49a7-8961-dec8332170c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86802301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.86802301
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.549170475
Short name T917
Test name
Test status
Simulation time 140184868 ps
CPU time 6.15 seconds
Started Jul 04 06:17:55 PM PDT 24
Finished Jul 04 06:18:01 PM PDT 24
Peak memory 217272 kb
Host smart-dcab462e-0019-464c-ab2a-fffa9ec434da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549170475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.549170475
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4014009547
Short name T575
Test name
Test status
Simulation time 59088206 ps
CPU time 0.78 seconds
Started Jul 04 06:17:58 PM PDT 24
Finished Jul 04 06:17:59 PM PDT 24
Peak memory 206964 kb
Host smart-1079ac22-15d6-416e-b1ad-34d8e39b68e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014009547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4014009547
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3842649042
Short name T424
Test name
Test status
Simulation time 82325727 ps
CPU time 3 seconds
Started Jul 04 06:17:56 PM PDT 24
Finished Jul 04 06:17:59 PM PDT 24
Peak memory 236848 kb
Host smart-2b574b27-f81c-40b2-b712-5a883a6e17f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842649042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3842649042
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2357462683
Short name T971
Test name
Test status
Simulation time 36233901 ps
CPU time 0.73 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:18:13 PM PDT 24
Peak memory 206300 kb
Host smart-ccba3418-fc52-4d89-8200-925b74f60f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357462683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2357462683
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.88040051
Short name T354
Test name
Test status
Simulation time 4551911518 ps
CPU time 11.64 seconds
Started Jul 04 06:18:07 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 233920 kb
Host smart-34b0ec57-782e-47c3-bf93-1f92d6b800d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88040051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.88040051
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.761261804
Short name T779
Test name
Test status
Simulation time 61145565 ps
CPU time 0.76 seconds
Started Jul 04 06:18:03 PM PDT 24
Finished Jul 04 06:18:04 PM PDT 24
Peak memory 206872 kb
Host smart-8f3fcbc7-2c64-44f3-828e-e147c95d8b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761261804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.761261804
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.618667089
Short name T162
Test name
Test status
Simulation time 3711890531 ps
CPU time 36.33 seconds
Started Jul 04 06:18:06 PM PDT 24
Finished Jul 04 06:18:43 PM PDT 24
Peak memory 250336 kb
Host smart-79971f1a-ddcd-4e5e-8627-fd79b2fb4235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618667089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.618667089
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3383313948
Short name T433
Test name
Test status
Simulation time 17683902218 ps
CPU time 162.79 seconds
Started Jul 04 06:18:06 PM PDT 24
Finished Jul 04 06:20:49 PM PDT 24
Peak memory 250828 kb
Host smart-d23afe31-04b1-4503-add9-6e1ffb13918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383313948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3383313948
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.909919081
Short name T352
Test name
Test status
Simulation time 6289739868 ps
CPU time 59.35 seconds
Started Jul 04 06:18:03 PM PDT 24
Finished Jul 04 06:19:03 PM PDT 24
Peak memory 234372 kb
Host smart-43909175-bc34-48c6-9689-62c5eb4c4292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909919081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.909919081
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3967174630
Short name T311
Test name
Test status
Simulation time 14755428790 ps
CPU time 115.38 seconds
Started Jul 04 06:18:02 PM PDT 24
Finished Jul 04 06:19:57 PM PDT 24
Peak memory 242116 kb
Host smart-2ac5cc2e-aa37-45c6-8f63-6878e702fbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967174630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3967174630
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2701073000
Short name T169
Test name
Test status
Simulation time 29395674133 ps
CPU time 253.85 seconds
Started Jul 04 06:18:03 PM PDT 24
Finished Jul 04 06:22:17 PM PDT 24
Peak memory 266584 kb
Host smart-a67cc8e3-c599-4b29-835a-d34a8f884a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701073000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2701073000
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2310687881
Short name T324
Test name
Test status
Simulation time 358298783 ps
CPU time 3.51 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:18:17 PM PDT 24
Peak memory 229700 kb
Host smart-1f2155d0-cd9e-4f25-af25-1ccda15f8d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310687881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2310687881
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3176693072
Short name T491
Test name
Test status
Simulation time 464316218 ps
CPU time 6.26 seconds
Started Jul 04 06:18:11 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 235992 kb
Host smart-ea77cbdd-5e63-4650-8cf9-1792ab975a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176693072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3176693072
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.86928567
Short name T546
Test name
Test status
Simulation time 9789061264 ps
CPU time 28.58 seconds
Started Jul 04 06:18:06 PM PDT 24
Finished Jul 04 06:18:35 PM PDT 24
Peak memory 233920 kb
Host smart-baf1e605-b712-4111-b8f6-78d5fd14e683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86928567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.86928567
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1487794504
Short name T599
Test name
Test status
Simulation time 450856799 ps
CPU time 4.27 seconds
Started Jul 04 06:18:06 PM PDT 24
Finished Jul 04 06:18:11 PM PDT 24
Peak memory 233748 kb
Host smart-f2e79d23-f78d-442c-be10-8b97a816070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487794504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1487794504
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1068876570
Short name T403
Test name
Test status
Simulation time 900028744 ps
CPU time 6.35 seconds
Started Jul 04 06:18:02 PM PDT 24
Finished Jul 04 06:18:08 PM PDT 24
Peak memory 220352 kb
Host smart-641e9506-a252-48bb-9d52-17907d7b0f26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1068876570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1068876570
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.768503685
Short name T734
Test name
Test status
Simulation time 47397870 ps
CPU time 1.05 seconds
Started Jul 04 06:18:08 PM PDT 24
Finished Jul 04 06:18:10 PM PDT 24
Peak memory 207772 kb
Host smart-464696e7-64ea-45cf-968b-3c4c8a9d1575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768503685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.768503685
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.208779225
Short name T951
Test name
Test status
Simulation time 725211827 ps
CPU time 9.34 seconds
Started Jul 04 06:18:01 PM PDT 24
Finished Jul 04 06:18:10 PM PDT 24
Peak memory 217564 kb
Host smart-55c864a1-e563-41d1-adb3-facc3c94e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208779225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.208779225
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2106635314
Short name T412
Test name
Test status
Simulation time 5777534717 ps
CPU time 4.78 seconds
Started Jul 04 06:18:07 PM PDT 24
Finished Jul 04 06:18:12 PM PDT 24
Peak memory 217428 kb
Host smart-3b2f3908-789f-421c-9df5-12aced513be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106635314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2106635314
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.942897892
Short name T583
Test name
Test status
Simulation time 137478445 ps
CPU time 2.39 seconds
Started Jul 04 06:18:04 PM PDT 24
Finished Jul 04 06:18:06 PM PDT 24
Peak memory 217432 kb
Host smart-b70121d1-1f3b-49f6-9311-457021cde167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942897892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.942897892
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4244890988
Short name T349
Test name
Test status
Simulation time 261298918 ps
CPU time 1.04 seconds
Started Jul 04 06:18:08 PM PDT 24
Finished Jul 04 06:18:10 PM PDT 24
Peak memory 207332 kb
Host smart-9a5e0be8-d159-467e-963d-79f5f402aded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244890988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4244890988
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3618982068
Short name T778
Test name
Test status
Simulation time 14195729515 ps
CPU time 26.09 seconds
Started Jul 04 06:18:03 PM PDT 24
Finished Jul 04 06:18:30 PM PDT 24
Peak memory 234896 kb
Host smart-08a4755d-a526-45b2-a057-f36f60b7c2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618982068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3618982068
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4097370776
Short name T1003
Test name
Test status
Simulation time 12333059 ps
CPU time 0.7 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:18:13 PM PDT 24
Peak memory 205760 kb
Host smart-8e181233-5782-4322-b59e-3a5a945297df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097370776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4097370776
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1992847782
Short name T538
Test name
Test status
Simulation time 94453648 ps
CPU time 2.03 seconds
Started Jul 04 06:18:05 PM PDT 24
Finished Jul 04 06:18:07 PM PDT 24
Peak memory 225244 kb
Host smart-14677133-4d0d-4d36-9ec1-8bf4d5d0ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992847782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1992847782
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.257782902
Short name T325
Test name
Test status
Simulation time 14750839 ps
CPU time 0.79 seconds
Started Jul 04 06:18:04 PM PDT 24
Finished Jul 04 06:18:05 PM PDT 24
Peak memory 207840 kb
Host smart-59e88b22-b3d1-4f08-9f29-38383f4b2557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257782902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.257782902
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3557454137
Short name T405
Test name
Test status
Simulation time 17575713129 ps
CPU time 90.24 seconds
Started Jul 04 06:18:06 PM PDT 24
Finished Jul 04 06:19:36 PM PDT 24
Peak memory 258348 kb
Host smart-d5916f83-27f3-4fc3-8e69-8d802b82a1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557454137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3557454137
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1372101855
Short name T772
Test name
Test status
Simulation time 10109154653 ps
CPU time 113.88 seconds
Started Jul 04 06:18:08 PM PDT 24
Finished Jul 04 06:20:02 PM PDT 24
Peak memory 250400 kb
Host smart-2a3a781d-2818-4728-ade3-e5a0f79c630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372101855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1372101855
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.657933190
Short name T499
Test name
Test status
Simulation time 14296182468 ps
CPU time 125.9 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:20:19 PM PDT 24
Peak memory 252656 kb
Host smart-fd3bf54d-2294-4596-b2e4-c9d1504cb7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657933190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.657933190
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2693562416
Short name T829
Test name
Test status
Simulation time 140553243 ps
CPU time 3.23 seconds
Started Jul 04 06:18:04 PM PDT 24
Finished Jul 04 06:18:08 PM PDT 24
Peak memory 233804 kb
Host smart-44df947b-9e3e-4c4a-a732-b98181cdb0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693562416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2693562416
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.524552588
Short name T280
Test name
Test status
Simulation time 2960847021 ps
CPU time 34.45 seconds
Started Jul 04 06:18:03 PM PDT 24
Finished Jul 04 06:18:38 PM PDT 24
Peak memory 235992 kb
Host smart-4ef8392d-2eb0-4374-bdff-2ed5c9e2afa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524552588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.524552588
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2677507650
Short name T39
Test name
Test status
Simulation time 2821085047 ps
CPU time 11.26 seconds
Started Jul 04 06:18:07 PM PDT 24
Finished Jul 04 06:18:19 PM PDT 24
Peak memory 249368 kb
Host smart-1cef5905-fcc8-48f3-9c24-c4122bcc5f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677507650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2677507650
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1090233019
Short name T475
Test name
Test status
Simulation time 63036634 ps
CPU time 2.73 seconds
Started Jul 04 06:18:01 PM PDT 24
Finished Jul 04 06:18:04 PM PDT 24
Peak memory 233520 kb
Host smart-0aadaa59-158b-41ae-9aca-66051f2bf9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090233019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1090233019
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.904406885
Short name T984
Test name
Test status
Simulation time 4025453262 ps
CPU time 8.22 seconds
Started Jul 04 06:18:06 PM PDT 24
Finished Jul 04 06:18:15 PM PDT 24
Peak memory 223276 kb
Host smart-a79074ab-5080-42ef-9b07-0c511f468d4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=904406885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.904406885
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2106640848
Short name T516
Test name
Test status
Simulation time 5597520295 ps
CPU time 31.67 seconds
Started Jul 04 06:18:06 PM PDT 24
Finished Jul 04 06:18:38 PM PDT 24
Peak memory 251632 kb
Host smart-1aea227d-4671-4ebf-8472-f361ed91e382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106640848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2106640848
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2651451886
Short name T851
Test name
Test status
Simulation time 8728834492 ps
CPU time 21.67 seconds
Started Jul 04 06:18:03 PM PDT 24
Finished Jul 04 06:18:25 PM PDT 24
Peak memory 221132 kb
Host smart-93069366-e37b-4c60-9457-1fb5438e4038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651451886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2651451886
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1464402601
Short name T762
Test name
Test status
Simulation time 1228454080 ps
CPU time 3.71 seconds
Started Jul 04 06:18:03 PM PDT 24
Finished Jul 04 06:18:07 PM PDT 24
Peak memory 217364 kb
Host smart-8e6bc640-1236-4301-82c2-c66210c2c120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464402601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1464402601
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3997278963
Short name T569
Test name
Test status
Simulation time 30738290 ps
CPU time 1.03 seconds
Started Jul 04 06:18:06 PM PDT 24
Finished Jul 04 06:18:07 PM PDT 24
Peak memory 208976 kb
Host smart-b3571484-5ea0-492e-9ad0-dd581827f896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997278963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3997278963
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2051615687
Short name T892
Test name
Test status
Simulation time 181394934 ps
CPU time 0.92 seconds
Started Jul 04 06:18:02 PM PDT 24
Finished Jul 04 06:18:04 PM PDT 24
Peak memory 207392 kb
Host smart-436044bf-b574-4894-bbc3-28694f23cc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051615687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2051615687
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2907975958
Short name T369
Test name
Test status
Simulation time 62259218 ps
CPU time 2.48 seconds
Started Jul 04 06:18:03 PM PDT 24
Finished Jul 04 06:18:05 PM PDT 24
Peak memory 225312 kb
Host smart-e4081bfa-bf9c-4256-aa41-426aea12e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907975958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2907975958
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.822585616
Short name T341
Test name
Test status
Simulation time 66637108 ps
CPU time 0.68 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:10 PM PDT 24
Peak memory 206744 kb
Host smart-f9cfa53e-3c58-4fd4-a078-4cfee4fa105f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822585616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.822585616
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1929980833
Short name T40
Test name
Test status
Simulation time 415803666 ps
CPU time 2.65 seconds
Started Jul 04 06:18:08 PM PDT 24
Finished Jul 04 06:18:11 PM PDT 24
Peak memory 225588 kb
Host smart-7a788f0c-ec18-4a7f-9dd3-8d213756cec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929980833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1929980833
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1176625861
Short name T440
Test name
Test status
Simulation time 37168983 ps
CPU time 0.81 seconds
Started Jul 04 06:18:02 PM PDT 24
Finished Jul 04 06:18:03 PM PDT 24
Peak memory 207480 kb
Host smart-e09b6fe9-f0e4-4404-8c05-5f922c60d8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176625861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1176625861
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3985659081
Short name T698
Test name
Test status
Simulation time 38604307487 ps
CPU time 278.28 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:22:50 PM PDT 24
Peak memory 258464 kb
Host smart-8714a282-e13f-4a96-b40b-f2996fd2ecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985659081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3985659081
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3669992817
Short name T1021
Test name
Test status
Simulation time 25661115340 ps
CPU time 177.85 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:21:11 PM PDT 24
Peak memory 241556 kb
Host smart-6ad11881-3a9c-4a68-9c9e-b735ba42a413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669992817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3669992817
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2164398687
Short name T76
Test name
Test status
Simulation time 4758420979 ps
CPU time 88.95 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:19:43 PM PDT 24
Peak memory 256644 kb
Host smart-6f0b0325-6fdb-4e5b-841f-1086c434ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164398687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2164398687
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2740675286
Short name T915
Test name
Test status
Simulation time 2209024974 ps
CPU time 4.87 seconds
Started Jul 04 06:18:08 PM PDT 24
Finished Jul 04 06:18:13 PM PDT 24
Peak memory 234004 kb
Host smart-a6298461-2504-4e11-877f-6a62f8ac6894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740675286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2740675286
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2962995298
Short name T727
Test name
Test status
Simulation time 59396396 ps
CPU time 0.79 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:10 PM PDT 24
Peak memory 216944 kb
Host smart-c209d0ff-8d18-4968-9b52-6d995ff5666d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962995298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2962995298
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1206657402
Short name T480
Test name
Test status
Simulation time 316581899 ps
CPU time 3.01 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:13 PM PDT 24
Peak memory 225508 kb
Host smart-ad3225bf-8f28-4dda-bab1-38bbd90dcc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206657402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1206657402
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3309077295
Short name T878
Test name
Test status
Simulation time 71592219306 ps
CPU time 74.14 seconds
Started Jul 04 06:18:10 PM PDT 24
Finished Jul 04 06:19:24 PM PDT 24
Peak memory 238936 kb
Host smart-4e076485-067f-47ff-bc66-2f24e0be17c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309077295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3309077295
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1115564846
Short name T224
Test name
Test status
Simulation time 16596063532 ps
CPU time 17.74 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:27 PM PDT 24
Peak memory 233888 kb
Host smart-91d01f6a-d322-4f92-83c0-503a999bf02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115564846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1115564846
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2015976449
Short name T58
Test name
Test status
Simulation time 2341268987 ps
CPU time 9 seconds
Started Jul 04 06:18:16 PM PDT 24
Finished Jul 04 06:18:26 PM PDT 24
Peak memory 233900 kb
Host smart-1ea95bdd-65af-4f45-a2c5-dc3f8141cd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015976449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2015976449
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3215250875
Short name T716
Test name
Test status
Simulation time 729954138 ps
CPU time 6.24 seconds
Started Jul 04 06:18:16 PM PDT 24
Finished Jul 04 06:18:23 PM PDT 24
Peak memory 222996 kb
Host smart-eb0e4492-d0ef-42b9-82a9-51787443bb94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3215250875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3215250875
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3260873227
Short name T563
Test name
Test status
Simulation time 12498111816 ps
CPU time 76.42 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:19:28 PM PDT 24
Peak memory 250364 kb
Host smart-6671e122-77ea-4a5c-bed6-009ee6084e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260873227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3260873227
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1220892108
Short name T726
Test name
Test status
Simulation time 18484789113 ps
CPU time 22.61 seconds
Started Jul 04 06:18:11 PM PDT 24
Finished Jul 04 06:18:34 PM PDT 24
Peak memory 217568 kb
Host smart-5f3cfc9d-0dfd-4fef-a084-21357ef67574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220892108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1220892108
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2107208832
Short name T950
Test name
Test status
Simulation time 2321379143 ps
CPU time 8.82 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 217556 kb
Host smart-6b036dbd-ac04-4c19-90ec-6103808d1d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107208832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2107208832
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.609136882
Short name T675
Test name
Test status
Simulation time 597276782 ps
CPU time 2.38 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:12 PM PDT 24
Peak memory 217424 kb
Host smart-6cdf7d97-b273-4903-963d-8c3e21cbba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609136882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.609136882
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2963359778
Short name T364
Test name
Test status
Simulation time 19579377 ps
CPU time 0.71 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:09 PM PDT 24
Peak memory 206528 kb
Host smart-de7cccaa-a235-438b-bcfc-507c4a24cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963359778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2963359778
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2567357162
Short name T671
Test name
Test status
Simulation time 2066896360 ps
CPU time 6.57 seconds
Started Jul 04 06:18:10 PM PDT 24
Finished Jul 04 06:18:17 PM PDT 24
Peak memory 225516 kb
Host smart-9a923c2d-f1ae-4088-9eaf-ef7e92beb8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567357162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2567357162
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1595849975
Short name T387
Test name
Test status
Simulation time 14138781 ps
CPU time 0.73 seconds
Started Jul 04 06:18:08 PM PDT 24
Finished Jul 04 06:18:09 PM PDT 24
Peak memory 205796 kb
Host smart-9d26019b-64d6-4b89-9a8b-ab5eeca74b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595849975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1595849975
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1813601911
Short name T902
Test name
Test status
Simulation time 115187284 ps
CPU time 2.63 seconds
Started Jul 04 06:18:10 PM PDT 24
Finished Jul 04 06:18:13 PM PDT 24
Peak memory 233752 kb
Host smart-aafcc915-3328-4743-820b-83730cca7127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813601911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1813601911
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1197060955
Short name T665
Test name
Test status
Simulation time 20162948 ps
CPU time 0.78 seconds
Started Jul 04 06:18:16 PM PDT 24
Finished Jul 04 06:18:17 PM PDT 24
Peak memory 207500 kb
Host smart-9f531ce5-9589-4f4c-9a6b-8c7fcd8bfb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197060955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1197060955
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3402427438
Short name T631
Test name
Test status
Simulation time 4358671881 ps
CPU time 36.19 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:46 PM PDT 24
Peak memory 250332 kb
Host smart-1edb5598-79c9-4206-bede-e762b94f6345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402427438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3402427438
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2712399517
Short name T207
Test name
Test status
Simulation time 4921980769 ps
CPU time 63.07 seconds
Started Jul 04 06:18:15 PM PDT 24
Finished Jul 04 06:19:19 PM PDT 24
Peak memory 252464 kb
Host smart-517d9a9c-1848-4a46-9d8c-f1de533f376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712399517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2712399517
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1437552975
Short name T467
Test name
Test status
Simulation time 1295759967 ps
CPU time 18.14 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:18:30 PM PDT 24
Peak memory 225676 kb
Host smart-6ce3fdda-8a9c-43bd-964a-3e9ecae86e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437552975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1437552975
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.985901036
Short name T572
Test name
Test status
Simulation time 279794165 ps
CPU time 3.34 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:17 PM PDT 24
Peak memory 233800 kb
Host smart-b78d7999-aead-4bd8-b3eb-1abf19977c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985901036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.985901036
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1701357832
Short name T879
Test name
Test status
Simulation time 3109666152 ps
CPU time 45.6 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:55 PM PDT 24
Peak memory 251324 kb
Host smart-0df544da-2002-4e07-bfbf-d217c586cf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701357832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1701357832
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1699866166
Short name T781
Test name
Test status
Simulation time 801890108 ps
CPU time 4.96 seconds
Started Jul 04 06:18:11 PM PDT 24
Finished Jul 04 06:18:16 PM PDT 24
Peak memory 225548 kb
Host smart-372dbdf0-7bb5-43d0-8ad9-f248b0c383b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699866166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1699866166
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2275104719
Short name T246
Test name
Test status
Simulation time 8304169548 ps
CPU time 40.6 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:50 PM PDT 24
Peak memory 242060 kb
Host smart-5298f902-908a-4b50-a1e7-46f0d9e946ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275104719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2275104719
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2798538459
Short name T212
Test name
Test status
Simulation time 7846716858 ps
CPU time 22.28 seconds
Started Jul 04 06:18:10 PM PDT 24
Finished Jul 04 06:18:32 PM PDT 24
Peak memory 233912 kb
Host smart-3a09d74c-e07f-4949-857f-21cf5e3cb5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798538459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2798538459
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3339484146
Short name T898
Test name
Test status
Simulation time 2400815525 ps
CPU time 7.14 seconds
Started Jul 04 06:18:15 PM PDT 24
Finished Jul 04 06:18:22 PM PDT 24
Peak memory 233892 kb
Host smart-9264b2ec-c3b0-4ff4-baf0-9a62f82f80ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339484146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3339484146
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3901704592
Short name T340
Test name
Test status
Simulation time 3214219985 ps
CPU time 12.05 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:27 PM PDT 24
Peak memory 221728 kb
Host smart-5407474f-ea66-4657-bc59-2d2d5ec7684a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3901704592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3901704592
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3607782778
Short name T32
Test name
Test status
Simulation time 60837956765 ps
CPU time 140.63 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:20:33 PM PDT 24
Peak memory 255324 kb
Host smart-8e98894f-bb3f-42fa-bc64-3dc68718b48d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607782778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3607782778
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2161867995
Short name T496
Test name
Test status
Simulation time 1268233062 ps
CPU time 18.18 seconds
Started Jul 04 06:18:11 PM PDT 24
Finished Jul 04 06:18:29 PM PDT 24
Peak memory 217344 kb
Host smart-3f82fb9f-fa7d-4497-9720-7be64447b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161867995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2161867995
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3715702283
Short name T615
Test name
Test status
Simulation time 4388862742 ps
CPU time 11.68 seconds
Started Jul 04 06:18:11 PM PDT 24
Finished Jul 04 06:18:23 PM PDT 24
Peak memory 217508 kb
Host smart-ae2e90f3-baa2-4446-b7c6-dec94cf732d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715702283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3715702283
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.363076967
Short name T664
Test name
Test status
Simulation time 76873009 ps
CPU time 1.29 seconds
Started Jul 04 06:18:17 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 217312 kb
Host smart-1ee3ac3e-8213-44df-bdb9-048bd5263602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363076967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.363076967
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4005158006
Short name T523
Test name
Test status
Simulation time 47036347 ps
CPU time 0.92 seconds
Started Jul 04 06:18:11 PM PDT 24
Finished Jul 04 06:18:13 PM PDT 24
Peak memory 206968 kb
Host smart-825780db-0d61-404e-a3a9-c24d9a8124a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005158006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4005158006
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2937605872
Short name T525
Test name
Test status
Simulation time 8176550085 ps
CPU time 8.08 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:23 PM PDT 24
Peak memory 225656 kb
Host smart-e6bdcdd5-4a02-4c0e-8874-1f6b8b3d4c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937605872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2937605872
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2172983819
Short name T63
Test name
Test status
Simulation time 23823750 ps
CPU time 0.72 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:18:14 PM PDT 24
Peak memory 205752 kb
Host smart-fec6525d-7e67-4ca5-a9cc-83831cc6eed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172983819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2172983819
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1630049220
Short name T87
Test name
Test status
Simulation time 2807444413 ps
CPU time 28.22 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:18:41 PM PDT 24
Peak memory 234928 kb
Host smart-0d7381ef-99f5-4d18-9542-7cac1533397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630049220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1630049220
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3698431033
Short name T690
Test name
Test status
Simulation time 19622753 ps
CPU time 0.79 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:15 PM PDT 24
Peak memory 207540 kb
Host smart-3259d763-2987-422b-a635-acb42c47fea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698431033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3698431033
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1769222996
Short name T394
Test name
Test status
Simulation time 513442473 ps
CPU time 13.63 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:18:23 PM PDT 24
Peak memory 242140 kb
Host smart-0a6697fe-8463-4aa2-a61e-c11f5c57510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769222996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1769222996
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.880786694
Short name T657
Test name
Test status
Simulation time 5714968065 ps
CPU time 39.04 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:53 PM PDT 24
Peak memory 242084 kb
Host smart-6cb8ab30-58aa-4702-8503-e7299f7f7818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880786694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.880786694
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3011609376
Short name T69
Test name
Test status
Simulation time 445035108 ps
CPU time 4.83 seconds
Started Jul 04 06:18:11 PM PDT 24
Finished Jul 04 06:18:16 PM PDT 24
Peak memory 225552 kb
Host smart-d2b6e9f8-a2e6-4116-bbb4-155ebe31fd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011609376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3011609376
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.463578187
Short name T679
Test name
Test status
Simulation time 25181135063 ps
CPU time 62.66 seconds
Started Jul 04 06:18:09 PM PDT 24
Finished Jul 04 06:19:12 PM PDT 24
Peak memory 233876 kb
Host smart-757c56e5-3c00-4140-aa7d-475c4705dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463578187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.463578187
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3989594609
Short name T752
Test name
Test status
Simulation time 455070830 ps
CPU time 4.51 seconds
Started Jul 04 06:18:07 PM PDT 24
Finished Jul 04 06:18:12 PM PDT 24
Peak memory 233840 kb
Host smart-85f848cf-6d39-4e41-95bb-c8db699efc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989594609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3989594609
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3438759531
Short name T909
Test name
Test status
Simulation time 1501085520 ps
CPU time 7 seconds
Started Jul 04 06:18:10 PM PDT 24
Finished Jul 04 06:18:17 PM PDT 24
Peak memory 225528 kb
Host smart-ea2d779e-8598-4c4a-b57b-756f08e7062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438759531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3438759531
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1796394566
Short name T614
Test name
Test status
Simulation time 192144237 ps
CPU time 3.52 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:18:16 PM PDT 24
Peak memory 220124 kb
Host smart-0c512016-a25b-4017-b6a3-72d6590728e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1796394566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1796394566
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3801104152
Short name T961
Test name
Test status
Simulation time 58176671350 ps
CPU time 630.37 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:28:44 PM PDT 24
Peak memory 258036 kb
Host smart-0e92d97d-a580-4356-b9c0-20add4fde08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801104152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3801104152
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2555875599
Short name T316
Test name
Test status
Simulation time 3320683699 ps
CPU time 16.86 seconds
Started Jul 04 06:18:08 PM PDT 24
Finished Jul 04 06:18:25 PM PDT 24
Peak memory 217500 kb
Host smart-27473e0d-1911-4b06-94ff-efb798f76a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555875599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2555875599
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1845774914
Short name T814
Test name
Test status
Simulation time 13847484994 ps
CPU time 20.85 seconds
Started Jul 04 06:18:12 PM PDT 24
Finished Jul 04 06:18:33 PM PDT 24
Peak memory 217492 kb
Host smart-d0c5d0fa-579f-4e4f-9512-a4b7b2786ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845774914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1845774914
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3456093539
Short name T866
Test name
Test status
Simulation time 248922587 ps
CPU time 1.43 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:18:15 PM PDT 24
Peak memory 217368 kb
Host smart-4ff86ea0-6c63-4ec9-aa85-eeb2ed7ca1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456093539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3456093539
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1910629653
Short name T372
Test name
Test status
Simulation time 29952453 ps
CPU time 0.7 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:15 PM PDT 24
Peak memory 206596 kb
Host smart-fde7bd41-bb64-4e3e-91c9-ef1e28854e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910629653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1910629653
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4129564118
Short name T722
Test name
Test status
Simulation time 6243245590 ps
CPU time 22.98 seconds
Started Jul 04 06:18:10 PM PDT 24
Finished Jul 04 06:18:34 PM PDT 24
Peak memory 233864 kb
Host smart-f5ef6470-b786-46f8-9497-889d0e0bf569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129564118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4129564118
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1508972259
Short name T509
Test name
Test status
Simulation time 40110730 ps
CPU time 0.71 seconds
Started Jul 04 06:18:18 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 205752 kb
Host smart-2341f822-1a34-43de-9f0c-f04917eabbbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508972259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1508972259
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.925606163
Short name T338
Test name
Test status
Simulation time 600505886 ps
CPU time 3.09 seconds
Started Jul 04 06:18:16 PM PDT 24
Finished Jul 04 06:18:19 PM PDT 24
Peak memory 225632 kb
Host smart-d07a9ff5-2e06-4128-99f0-3f7a8494d3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925606163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.925606163
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3227485016
Short name T985
Test name
Test status
Simulation time 22171927 ps
CPU time 0.78 seconds
Started Jul 04 06:18:13 PM PDT 24
Finished Jul 04 06:18:14 PM PDT 24
Peak memory 207876 kb
Host smart-6103f2d1-d5e1-4b3b-8565-7ee3af855c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227485016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3227485016
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4009836183
Short name T356
Test name
Test status
Simulation time 16724211032 ps
CPU time 8.67 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:23 PM PDT 24
Peak memory 225704 kb
Host smart-b8e6d0cf-64cf-46ce-914d-bf87285a3339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009836183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4009836183
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1028484074
Short name T852
Test name
Test status
Simulation time 1186572295 ps
CPU time 23.72 seconds
Started Jul 04 06:18:18 PM PDT 24
Finished Jul 04 06:18:42 PM PDT 24
Peak memory 250344 kb
Host smart-6a425d85-de98-46af-b0d6-3e8c20218d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028484074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1028484074
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3326399309
Short name T625
Test name
Test status
Simulation time 14839999535 ps
CPU time 23.6 seconds
Started Jul 04 06:18:19 PM PDT 24
Finished Jul 04 06:18:43 PM PDT 24
Peak memory 218824 kb
Host smart-5fe0b529-e66b-4892-9038-7cfc86bed716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326399309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3326399309
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2230271395
Short name T1008
Test name
Test status
Simulation time 2057497787 ps
CPU time 34.71 seconds
Started Jul 04 06:18:14 PM PDT 24
Finished Jul 04 06:18:49 PM PDT 24
Peak memory 240268 kb
Host smart-3d5aad27-46d2-492f-8840-0bbbd23b07cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230271395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2230271395
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.322643200
Short name T260
Test name
Test status
Simulation time 1884334179 ps
CPU time 10.24 seconds
Started Jul 04 06:18:18 PM PDT 24
Finished Jul 04 06:18:29 PM PDT 24
Peak memory 225536 kb
Host smart-56cd8fae-858e-4299-be59-a4c81dd6aa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322643200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.322643200
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4157009849
Short name T359
Test name
Test status
Simulation time 29540148 ps
CPU time 2.07 seconds
Started Jul 04 06:18:16 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 225212 kb
Host smart-588f3e01-5aa3-4418-9a27-17350949c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157009849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4157009849
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.167543838
Short name T1013
Test name
Test status
Simulation time 217930563 ps
CPU time 5.29 seconds
Started Jul 04 06:18:18 PM PDT 24
Finished Jul 04 06:18:24 PM PDT 24
Peak memory 241912 kb
Host smart-bb76786d-2abe-49f0-8ecb-ce47acf35dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167543838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.167543838
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4276304620
Short name T531
Test name
Test status
Simulation time 1235401071 ps
CPU time 4.55 seconds
Started Jul 04 06:18:17 PM PDT 24
Finished Jul 04 06:18:21 PM PDT 24
Peak memory 233800 kb
Host smart-c959ee57-2a9f-4e34-b206-49c157a99abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276304620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4276304620
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1087854341
Short name T1025
Test name
Test status
Simulation time 279532147 ps
CPU time 3.55 seconds
Started Jul 04 06:18:19 PM PDT 24
Finished Jul 04 06:18:22 PM PDT 24
Peak memory 224224 kb
Host smart-6a8ae826-8629-404c-9aac-999b285b24fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1087854341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1087854341
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4012863664
Short name T812
Test name
Test status
Simulation time 38806431997 ps
CPU time 371.04 seconds
Started Jul 04 06:18:15 PM PDT 24
Finished Jul 04 06:24:27 PM PDT 24
Peak memory 271544 kb
Host smart-efa3f851-f35a-4ebf-a6e3-0bce2c9e6812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012863664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4012863664
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1623953368
Short name T420
Test name
Test status
Simulation time 31360270096 ps
CPU time 46.03 seconds
Started Jul 04 06:18:15 PM PDT 24
Finished Jul 04 06:19:01 PM PDT 24
Peak memory 217504 kb
Host smart-8dadf04c-0ef1-4dd4-b0aa-63f5b75886e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623953368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1623953368
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3110789814
Short name T755
Test name
Test status
Simulation time 2184446897 ps
CPU time 3.15 seconds
Started Jul 04 06:18:17 PM PDT 24
Finished Jul 04 06:18:20 PM PDT 24
Peak memory 217444 kb
Host smart-c0933363-2500-4e89-9019-6f03d005dd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110789814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3110789814
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2501740629
Short name T700
Test name
Test status
Simulation time 35941723 ps
CPU time 1.17 seconds
Started Jul 04 06:18:15 PM PDT 24
Finished Jul 04 06:18:16 PM PDT 24
Peak memory 217432 kb
Host smart-904fc720-819d-4eba-8d58-c586b8c9c632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501740629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2501740629
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2627846151
Short name T977
Test name
Test status
Simulation time 51268914 ps
CPU time 0.92 seconds
Started Jul 04 06:18:15 PM PDT 24
Finished Jul 04 06:18:16 PM PDT 24
Peak memory 207228 kb
Host smart-a7c72544-8b72-492b-86da-d3a3aaddf135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627846151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2627846151
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2616442368
Short name T254
Test name
Test status
Simulation time 248607838 ps
CPU time 3.17 seconds
Started Jul 04 06:18:16 PM PDT 24
Finished Jul 04 06:18:20 PM PDT 24
Peak memory 241908 kb
Host smart-8641d02d-ffdb-430f-aee9-9812e5435c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616442368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2616442368
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2041286209
Short name T339
Test name
Test status
Simulation time 12929685 ps
CPU time 0.73 seconds
Started Jul 04 06:18:23 PM PDT 24
Finished Jul 04 06:18:24 PM PDT 24
Peak memory 205812 kb
Host smart-7d821205-6b9a-4ff3-846e-2b9622c2ee0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041286209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2041286209
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3611056761
Short name T792
Test name
Test status
Simulation time 3693296128 ps
CPU time 10.75 seconds
Started Jul 04 06:18:24 PM PDT 24
Finished Jul 04 06:18:35 PM PDT 24
Peak memory 233876 kb
Host smart-240ac02b-92cd-4377-a861-3c68274e70b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611056761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3611056761
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1258528823
Short name T555
Test name
Test status
Simulation time 61665404 ps
CPU time 0.76 seconds
Started Jul 04 06:18:17 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 207520 kb
Host smart-691ac429-9427-4538-bb55-dd6e419e2815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258528823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1258528823
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3854959433
Short name T996
Test name
Test status
Simulation time 62737907678 ps
CPU time 99.59 seconds
Started Jul 04 06:18:25 PM PDT 24
Finished Jul 04 06:20:05 PM PDT 24
Peak memory 250296 kb
Host smart-1b2a66a3-1007-4b6b-9f86-bd8261a12fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854959433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3854959433
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1505471314
Short name T189
Test name
Test status
Simulation time 34286195304 ps
CPU time 174.39 seconds
Started Jul 04 06:18:24 PM PDT 24
Finished Jul 04 06:21:19 PM PDT 24
Peak memory 266640 kb
Host smart-d45840ab-3347-4ad0-a403-766096e26b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505471314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1505471314
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.980772783
Short name T946
Test name
Test status
Simulation time 973508537 ps
CPU time 5.21 seconds
Started Jul 04 06:18:25 PM PDT 24
Finished Jul 04 06:18:30 PM PDT 24
Peak memory 225680 kb
Host smart-d80b0153-8bae-4dac-ba7d-9feeaf1a9d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980772783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.980772783
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2071414806
Short name T312
Test name
Test status
Simulation time 3407507521 ps
CPU time 6.76 seconds
Started Jul 04 06:18:22 PM PDT 24
Finished Jul 04 06:18:29 PM PDT 24
Peak memory 225672 kb
Host smart-a44291eb-39d1-4b6c-98c1-8330578c7cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071414806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2071414806
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4291340226
Short name T427
Test name
Test status
Simulation time 4368203090 ps
CPU time 16.6 seconds
Started Jul 04 06:18:25 PM PDT 24
Finished Jul 04 06:18:42 PM PDT 24
Peak memory 225728 kb
Host smart-b5f3e656-b9c9-4a80-8698-ab6dfac4dda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291340226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4291340226
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2530958760
Short name T588
Test name
Test status
Simulation time 138049263 ps
CPU time 4.8 seconds
Started Jul 04 06:18:15 PM PDT 24
Finished Jul 04 06:18:20 PM PDT 24
Peak memory 233840 kb
Host smart-35cc7816-d89c-40d8-b966-d6eea5036a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530958760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2530958760
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2598376951
Short name T894
Test name
Test status
Simulation time 386575955 ps
CPU time 2.91 seconds
Started Jul 04 06:18:23 PM PDT 24
Finished Jul 04 06:18:26 PM PDT 24
Peak memory 233788 kb
Host smart-e01eb010-0ef9-4699-b264-391adc9f6dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598376951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2598376951
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3111226772
Short name T906
Test name
Test status
Simulation time 157274760 ps
CPU time 2.59 seconds
Started Jul 04 06:18:18 PM PDT 24
Finished Jul 04 06:18:21 PM PDT 24
Peak memory 225572 kb
Host smart-5b581b31-dfed-4e1a-8504-7fa2bf212dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111226772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3111226772
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2898617448
Short name T969
Test name
Test status
Simulation time 188351006 ps
CPU time 4.19 seconds
Started Jul 04 06:18:19 PM PDT 24
Finished Jul 04 06:18:23 PM PDT 24
Peak memory 233840 kb
Host smart-3a5d631d-5589-4bbc-b0d9-a1d3e5a39175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898617448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2898617448
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3441222572
Short name T142
Test name
Test status
Simulation time 1806235508 ps
CPU time 10.1 seconds
Started Jul 04 06:18:22 PM PDT 24
Finished Jul 04 06:18:32 PM PDT 24
Peak memory 222960 kb
Host smart-9576da1f-9e62-40d2-b8ab-d74c2bb12372
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3441222572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3441222572
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2833870784
Short name T887
Test name
Test status
Simulation time 12740114 ps
CPU time 0.73 seconds
Started Jul 04 06:18:17 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 206680 kb
Host smart-ef2e24a2-22ac-4412-869e-001dca318a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833870784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2833870784
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1852915334
Short name T923
Test name
Test status
Simulation time 41434557 ps
CPU time 0.72 seconds
Started Jul 04 06:18:16 PM PDT 24
Finished Jul 04 06:18:17 PM PDT 24
Peak memory 206656 kb
Host smart-d1cc3c7f-8cb9-4abe-989e-879bbd6fa4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852915334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1852915334
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2192114225
Short name T568
Test name
Test status
Simulation time 54472028 ps
CPU time 1.39 seconds
Started Jul 04 06:18:16 PM PDT 24
Finished Jul 04 06:18:17 PM PDT 24
Peak memory 217408 kb
Host smart-9df85642-b3ca-4cc1-98e6-df41eefffc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192114225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2192114225
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3639335657
Short name T709
Test name
Test status
Simulation time 35294579 ps
CPU time 0.78 seconds
Started Jul 04 06:18:17 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 207000 kb
Host smart-d13a19a6-b2ec-45a6-a462-aad08d533865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639335657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3639335657
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2446896445
Short name T432
Test name
Test status
Simulation time 966347332 ps
CPU time 7.79 seconds
Started Jul 04 06:18:25 PM PDT 24
Finished Jul 04 06:18:33 PM PDT 24
Peak memory 233840 kb
Host smart-aaf23cd9-5dc1-4fed-a9e5-103e35d12a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446896445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2446896445
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2939104662
Short name T598
Test name
Test status
Simulation time 11880382 ps
CPU time 0.74 seconds
Started Jul 04 06:18:24 PM PDT 24
Finished Jul 04 06:18:24 PM PDT 24
Peak memory 206736 kb
Host smart-bc415d1e-3464-485a-9c7d-cbbf3dab8dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939104662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2939104662
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.362950166
Short name T413
Test name
Test status
Simulation time 483293576 ps
CPU time 4.53 seconds
Started Jul 04 06:18:25 PM PDT 24
Finished Jul 04 06:18:30 PM PDT 24
Peak memory 233768 kb
Host smart-5c7fcacf-9f35-471f-9d32-a65cb497dcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362950166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.362950166
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3411015862
Short name T816
Test name
Test status
Simulation time 18016450 ps
CPU time 0.8 seconds
Started Jul 04 06:18:24 PM PDT 24
Finished Jul 04 06:18:25 PM PDT 24
Peak memory 207884 kb
Host smart-32a5eca1-61e0-49a5-acea-dd1af0541b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411015862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3411015862
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2898815283
Short name T701
Test name
Test status
Simulation time 105539858068 ps
CPU time 215.59 seconds
Started Jul 04 06:18:26 PM PDT 24
Finished Jul 04 06:22:01 PM PDT 24
Peak memory 266700 kb
Host smart-31e48f6e-7fb5-49d1-b3fd-ee99c0a7043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898815283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2898815283
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1175867677
Short name T244
Test name
Test status
Simulation time 901916956 ps
CPU time 17 seconds
Started Jul 04 06:18:26 PM PDT 24
Finished Jul 04 06:18:43 PM PDT 24
Peak memory 239100 kb
Host smart-4b078a6e-77d8-4906-8990-e5b464ed31bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175867677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1175867677
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2056604455
Short name T253
Test name
Test status
Simulation time 12737729597 ps
CPU time 81.01 seconds
Started Jul 04 06:18:23 PM PDT 24
Finished Jul 04 06:19:44 PM PDT 24
Peak memory 262944 kb
Host smart-0c5f6a72-fd71-4f6b-836e-0cf8cc479a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056604455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2056604455
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4028561366
Short name T232
Test name
Test status
Simulation time 12660582890 ps
CPU time 46.82 seconds
Started Jul 04 06:18:27 PM PDT 24
Finished Jul 04 06:19:14 PM PDT 24
Peak memory 252372 kb
Host smart-61236de9-143e-46d4-97d4-b41185a9da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028561366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4028561366
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.4223288151
Short name T937
Test name
Test status
Simulation time 3288969851 ps
CPU time 26.07 seconds
Started Jul 04 06:18:22 PM PDT 24
Finished Jul 04 06:18:48 PM PDT 24
Peak memory 235588 kb
Host smart-e7701925-d26a-4ee4-8e3e-d42211de3c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223288151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.4223288151
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.357152225
Short name T233
Test name
Test status
Simulation time 2500097964 ps
CPU time 17.66 seconds
Started Jul 04 06:18:27 PM PDT 24
Finished Jul 04 06:18:45 PM PDT 24
Peak memory 231752 kb
Host smart-9928e21f-9f9f-42eb-9249-c0dba06bcf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357152225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.357152225
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2657377908
Short name T659
Test name
Test status
Simulation time 2511330202 ps
CPU time 7.95 seconds
Started Jul 04 06:18:25 PM PDT 24
Finished Jul 04 06:18:34 PM PDT 24
Peak memory 242036 kb
Host smart-9e6845c6-3669-459e-9723-3395ca2a66e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657377908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2657377908
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.631164130
Short name T275
Test name
Test status
Simulation time 220439864 ps
CPU time 2.98 seconds
Started Jul 04 06:18:22 PM PDT 24
Finished Jul 04 06:18:26 PM PDT 24
Peak memory 225488 kb
Host smart-fd921f5b-e7a8-480c-b1a9-61985db3f950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631164130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.631164130
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2507207968
Short name T483
Test name
Test status
Simulation time 347781236 ps
CPU time 3.84 seconds
Started Jul 04 06:18:23 PM PDT 24
Finished Jul 04 06:18:27 PM PDT 24
Peak memory 225580 kb
Host smart-005da9f0-0d17-4b10-a6c3-c87a7d248919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507207968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2507207968
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.785057022
Short name T686
Test name
Test status
Simulation time 2195799405 ps
CPU time 9.17 seconds
Started Jul 04 06:18:23 PM PDT 24
Finished Jul 04 06:18:33 PM PDT 24
Peak memory 220588 kb
Host smart-e4f2ba98-a039-4510-8912-db54d585538a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=785057022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.785057022
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3993657919
Short name T842
Test name
Test status
Simulation time 70670658133 ps
CPU time 782.11 seconds
Started Jul 04 06:18:23 PM PDT 24
Finished Jul 04 06:31:26 PM PDT 24
Peak memory 288992 kb
Host smart-67ea3648-2425-4c1e-b52b-5c145819452b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993657919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3993657919
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4210796819
Short name T1000
Test name
Test status
Simulation time 1873977499 ps
CPU time 9.5 seconds
Started Jul 04 06:18:27 PM PDT 24
Finished Jul 04 06:18:36 PM PDT 24
Peak memory 217348 kb
Host smart-fa2b10e8-901f-4007-ba92-febca0e00d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210796819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4210796819
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2196954097
Short name T884
Test name
Test status
Simulation time 1021669636 ps
CPU time 4.14 seconds
Started Jul 04 06:18:27 PM PDT 24
Finished Jul 04 06:18:31 PM PDT 24
Peak memory 217400 kb
Host smart-29fdee0b-b310-46b8-8e77-ce529b70e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196954097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2196954097
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3643588486
Short name T780
Test name
Test status
Simulation time 77824014 ps
CPU time 1.59 seconds
Started Jul 04 06:18:23 PM PDT 24
Finished Jul 04 06:18:24 PM PDT 24
Peak memory 217300 kb
Host smart-902c5808-32c6-499d-8306-4bb49801ea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643588486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3643588486
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1073411241
Short name T608
Test name
Test status
Simulation time 52998662 ps
CPU time 0.67 seconds
Started Jul 04 06:18:24 PM PDT 24
Finished Jul 04 06:18:25 PM PDT 24
Peak memory 206540 kb
Host smart-bc84d01f-c65a-4870-8444-36d6d0d3f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073411241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1073411241
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1481500054
Short name T99
Test name
Test status
Simulation time 381370243 ps
CPU time 2.19 seconds
Started Jul 04 06:18:22 PM PDT 24
Finished Jul 04 06:18:25 PM PDT 24
Peak memory 225256 kb
Host smart-e57d5594-6562-4d0a-b8be-946106771e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481500054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1481500054
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3674891911
Short name T165
Test name
Test status
Simulation time 139588350 ps
CPU time 0.72 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:18:31 PM PDT 24
Peak memory 206708 kb
Host smart-7c12630d-d68c-46ec-8e6a-3d9ada490ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674891911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3674891911
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3601363289
Short name T775
Test name
Test status
Simulation time 1746662717 ps
CPU time 10.22 seconds
Started Jul 04 06:18:31 PM PDT 24
Finished Jul 04 06:18:42 PM PDT 24
Peak memory 233804 kb
Host smart-13274538-485c-4279-a77b-da09bacec04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601363289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3601363289
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.517435795
Short name T163
Test name
Test status
Simulation time 62163287 ps
CPU time 0.76 seconds
Started Jul 04 06:18:24 PM PDT 24
Finished Jul 04 06:18:25 PM PDT 24
Peak memory 207552 kb
Host smart-a2439a12-be73-45a4-917e-dcd2cb6edde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517435795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.517435795
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4167470705
Short name T231
Test name
Test status
Simulation time 7134740097 ps
CPU time 76.18 seconds
Started Jul 04 06:18:31 PM PDT 24
Finished Jul 04 06:19:47 PM PDT 24
Peak memory 257132 kb
Host smart-f0dcad2a-9082-49e5-a102-582a88890655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167470705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4167470705
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.174756957
Short name T830
Test name
Test status
Simulation time 22480727685 ps
CPU time 237.3 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:22:27 PM PDT 24
Peak memory 251016 kb
Host smart-93cefbc2-f1f4-4e6c-8f69-99dc9f34cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174756957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.174756957
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3341615273
Short name T514
Test name
Test status
Simulation time 13194337049 ps
CPU time 92.72 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:20:03 PM PDT 24
Peak memory 265528 kb
Host smart-86f66f1a-f3ac-47c6-962c-908038c9558b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341615273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3341615273
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2594710778
Short name T859
Test name
Test status
Simulation time 1381035948 ps
CPU time 11.94 seconds
Started Jul 04 06:18:36 PM PDT 24
Finished Jul 04 06:18:48 PM PDT 24
Peak memory 233804 kb
Host smart-1a7b619e-31b7-4712-a2ce-65fba8811966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594710778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2594710778
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2328524601
Short name T818
Test name
Test status
Simulation time 5304265853 ps
CPU time 12.2 seconds
Started Jul 04 06:18:31 PM PDT 24
Finished Jul 04 06:18:44 PM PDT 24
Peak memory 242096 kb
Host smart-e8e43e88-41a9-493b-bc66-e31dbe8b643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328524601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2328524601
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3100234540
Short name T864
Test name
Test status
Simulation time 1142793833 ps
CPU time 3.94 seconds
Started Jul 04 06:18:32 PM PDT 24
Finished Jul 04 06:18:36 PM PDT 24
Peak memory 225572 kb
Host smart-44a9a355-9cf4-4672-852d-27c7a9f1c754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100234540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3100234540
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.4235084707
Short name T85
Test name
Test status
Simulation time 6480518197 ps
CPU time 14.51 seconds
Started Jul 04 06:18:31 PM PDT 24
Finished Jul 04 06:18:46 PM PDT 24
Peak memory 233868 kb
Host smart-a6400685-23e8-4507-8f50-afcb1a76198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235084707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4235084707
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.799249610
Short name T281
Test name
Test status
Simulation time 12589102210 ps
CPU time 37.27 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:19:08 PM PDT 24
Peak memory 233960 kb
Host smart-63b23773-d24c-43d8-a61e-ed4a77b4b0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799249610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.799249610
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2369839850
Short name T672
Test name
Test status
Simulation time 344802716 ps
CPU time 6.09 seconds
Started Jul 04 06:18:28 PM PDT 24
Finished Jul 04 06:18:35 PM PDT 24
Peak memory 241240 kb
Host smart-385fbadc-6a28-47c3-9ca0-1ea496c231c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369839850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2369839850
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.9082106
Short name T37
Test name
Test status
Simulation time 2306246680 ps
CPU time 9.48 seconds
Started Jul 04 06:18:36 PM PDT 24
Finished Jul 04 06:18:46 PM PDT 24
Peak memory 219904 kb
Host smart-47c347f5-adce-4b46-bca5-91318ce81ce0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=9082106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.9082106
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3719044192
Short name T155
Test name
Test status
Simulation time 40069703726 ps
CPU time 121.24 seconds
Started Jul 04 06:18:27 PM PDT 24
Finished Jul 04 06:20:29 PM PDT 24
Peak memory 258576 kb
Host smart-6132b596-279b-43a1-9a1d-bf28aedcfde9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719044192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3719044192
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3864587093
Short name T901
Test name
Test status
Simulation time 1558593290 ps
CPU time 7.93 seconds
Started Jul 04 06:18:26 PM PDT 24
Finished Jul 04 06:18:34 PM PDT 24
Peak memory 217788 kb
Host smart-8f9c0b57-81c8-4d4c-bbdd-e06878260e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864587093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3864587093
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3548003325
Short name T1007
Test name
Test status
Simulation time 1943239513 ps
CPU time 4.18 seconds
Started Jul 04 06:18:27 PM PDT 24
Finished Jul 04 06:18:31 PM PDT 24
Peak memory 217388 kb
Host smart-df88c7ab-408b-4d1b-bd5c-9611bee374b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548003325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3548003325
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3012989147
Short name T540
Test name
Test status
Simulation time 29857451 ps
CPU time 0.71 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:18:32 PM PDT 24
Peak memory 206592 kb
Host smart-c1aa3a07-b3e0-4320-a082-598aad67ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012989147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3012989147
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2227579775
Short name T485
Test name
Test status
Simulation time 24244353 ps
CPU time 0.8 seconds
Started Jul 04 06:18:27 PM PDT 24
Finished Jul 04 06:18:28 PM PDT 24
Peak memory 206968 kb
Host smart-cdac824b-b94c-46b9-8923-562d3642d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227579775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2227579775
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3762536641
Short name T955
Test name
Test status
Simulation time 462585022 ps
CPU time 9.96 seconds
Started Jul 04 06:18:32 PM PDT 24
Finished Jul 04 06:18:42 PM PDT 24
Peak memory 251148 kb
Host smart-843f10dc-85a2-4edb-83b1-fd52ae45468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762536641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3762536641
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3200614637
Short name T704
Test name
Test status
Simulation time 22311720 ps
CPU time 0.68 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:10 PM PDT 24
Peak memory 206320 kb
Host smart-72a135a4-f216-440c-8a11-e267b52d5b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200614637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
200614637
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1725936979
Short name T696
Test name
Test status
Simulation time 230901599 ps
CPU time 3.8 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 233732 kb
Host smart-a0457060-edb2-4cbc-8c75-df5e11a0931d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725936979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1725936979
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4269720822
Short name T416
Test name
Test status
Simulation time 43798494 ps
CPU time 0.8 seconds
Started Jul 04 06:16:58 PM PDT 24
Finished Jul 04 06:16:59 PM PDT 24
Peak memory 207868 kb
Host smart-6591e5e9-957d-4c58-af16-f9d0316b3b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269720822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4269720822
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3040994509
Short name T298
Test name
Test status
Simulation time 5820484071 ps
CPU time 55.5 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:18:07 PM PDT 24
Peak memory 250744 kb
Host smart-ffefce51-dfe9-422f-9557-3caa1fc1288f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040994509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3040994509
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.623066320
Short name T299
Test name
Test status
Simulation time 353949696234 ps
CPU time 798 seconds
Started Jul 04 06:17:07 PM PDT 24
Finished Jul 04 06:30:25 PM PDT 24
Peak memory 271244 kb
Host smart-cfc4733c-1236-4e1c-bfd2-0e1b0e27c4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623066320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.623066320
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2817484666
Short name T636
Test name
Test status
Simulation time 5036634990 ps
CPU time 37.47 seconds
Started Jul 04 06:17:03 PM PDT 24
Finished Jul 04 06:17:40 PM PDT 24
Peak memory 235656 kb
Host smart-cd3b6eb1-c16e-4cff-896f-39b504480f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817484666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2817484666
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2827949286
Short name T454
Test name
Test status
Simulation time 3519689162 ps
CPU time 27.35 seconds
Started Jul 04 06:17:02 PM PDT 24
Finished Jul 04 06:17:29 PM PDT 24
Peak memory 243440 kb
Host smart-24d1bfd3-852a-40c6-ab62-4c2df33ccd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827949286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2827949286
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.939331675
Short name T715
Test name
Test status
Simulation time 38905940557 ps
CPU time 159.99 seconds
Started Jul 04 06:17:05 PM PDT 24
Finished Jul 04 06:19:46 PM PDT 24
Peak memory 258512 kb
Host smart-c90c0cae-a12b-4ccc-a47d-782f929b20c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939331675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
939331675
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.995318634
Short name T684
Test name
Test status
Simulation time 892420570 ps
CPU time 12.03 seconds
Started Jul 04 06:17:05 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 233800 kb
Host smart-1061eb40-f473-4b3b-b216-56d8315f75b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995318634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.995318634
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2464421590
Short name T580
Test name
Test status
Simulation time 4121379022 ps
CPU time 45.29 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:18:00 PM PDT 24
Peak memory 233944 kb
Host smart-774e5064-bd27-45e9-b5f6-5875030d057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464421590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2464421590
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3621815881
Short name T398
Test name
Test status
Simulation time 25428173 ps
CPU time 1.15 seconds
Started Jul 04 06:17:03 PM PDT 24
Finished Jul 04 06:17:04 PM PDT 24
Peak memory 217700 kb
Host smart-b563efe6-4333-4c59-8814-40074be0e7b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621815881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3621815881
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.456150256
Short name T990
Test name
Test status
Simulation time 3782438730 ps
CPU time 8.48 seconds
Started Jul 04 06:17:02 PM PDT 24
Finished Jul 04 06:17:11 PM PDT 24
Peak memory 233924 kb
Host smart-a512aa68-c1e4-4810-9dcf-a586012f454d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456150256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
456150256
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3746397294
Short name T646
Test name
Test status
Simulation time 9357588127 ps
CPU time 6.78 seconds
Started Jul 04 06:17:06 PM PDT 24
Finished Jul 04 06:17:13 PM PDT 24
Peak memory 233864 kb
Host smart-3e713208-ef49-4351-a32d-432dd6750c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746397294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3746397294
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3126724461
Short name T393
Test name
Test status
Simulation time 1362455565 ps
CPU time 15.43 seconds
Started Jul 04 06:17:01 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 223368 kb
Host smart-20eef5b8-5612-4cb4-9cb3-547716cfef55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3126724461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3126724461
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.159287535
Short name T31
Test name
Test status
Simulation time 322530930 ps
CPU time 1.25 seconds
Started Jul 04 06:17:07 PM PDT 24
Finished Jul 04 06:17:09 PM PDT 24
Peak memory 237412 kb
Host smart-ec538681-0511-4437-b7ec-7a807a4e27cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159287535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.159287535
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.189680301
Short name T435
Test name
Test status
Simulation time 123705344 ps
CPU time 0.93 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:17:09 PM PDT 24
Peak memory 207768 kb
Host smart-dafcc39c-0b05-447f-82aa-941281d87f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189680301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.189680301
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3667786762
Short name T869
Test name
Test status
Simulation time 9382100482 ps
CPU time 27.2 seconds
Started Jul 04 06:16:55 PM PDT 24
Finished Jul 04 06:17:23 PM PDT 24
Peak memory 217760 kb
Host smart-f39ce52d-5d81-4170-beef-ed3acbeb1527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667786762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3667786762
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3744145252
Short name T713
Test name
Test status
Simulation time 2979243285 ps
CPU time 10.19 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 217584 kb
Host smart-1d88be65-23a9-4828-a2c5-41c14e19fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744145252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3744145252
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3685692017
Short name T27
Test name
Test status
Simulation time 112297726 ps
CPU time 1.25 seconds
Started Jul 04 06:17:17 PM PDT 24
Finished Jul 04 06:17:19 PM PDT 24
Peak memory 209128 kb
Host smart-fbd038df-6200-4a59-a418-47c8af0f14d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685692017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3685692017
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.715308023
Short name T919
Test name
Test status
Simulation time 20540453 ps
CPU time 0.74 seconds
Started Jul 04 06:17:04 PM PDT 24
Finished Jul 04 06:17:05 PM PDT 24
Peak memory 207004 kb
Host smart-990f1f6f-0956-4aac-a911-d90bce3a2c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715308023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.715308023
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2600002014
Short name T742
Test name
Test status
Simulation time 195524967 ps
CPU time 3.92 seconds
Started Jul 04 06:17:06 PM PDT 24
Finished Jul 04 06:17:10 PM PDT 24
Peak memory 233724 kb
Host smart-2c2d4e2e-3f35-4001-ad6c-ae588f37599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600002014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2600002014
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1822849257
Short name T64
Test name
Test status
Simulation time 21945006 ps
CPU time 0.77 seconds
Started Jul 04 06:18:28 PM PDT 24
Finished Jul 04 06:18:29 PM PDT 24
Peak memory 206360 kb
Host smart-4bece45f-a4fb-45ea-bb48-090d750ef24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822849257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1822849257
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1006601244
Short name T278
Test name
Test status
Simulation time 780322281 ps
CPU time 3.06 seconds
Started Jul 04 06:18:29 PM PDT 24
Finished Jul 04 06:18:32 PM PDT 24
Peak memory 225576 kb
Host smart-9771e644-3fba-4b05-a1f1-f9b6b047696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006601244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1006601244
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4060524171
Short name T857
Test name
Test status
Simulation time 76448669 ps
CPU time 0.82 seconds
Started Jul 04 06:18:31 PM PDT 24
Finished Jul 04 06:18:32 PM PDT 24
Peak memory 207544 kb
Host smart-fe610bfd-666e-4b7c-9b4b-bb00a51f9279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060524171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4060524171
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3749537954
Short name T788
Test name
Test status
Simulation time 5882826585 ps
CPU time 20.46 seconds
Started Jul 04 06:18:29 PM PDT 24
Finished Jul 04 06:18:49 PM PDT 24
Peak memory 237408 kb
Host smart-c3d2a04d-79a8-454d-8f0c-65fff042bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749537954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3749537954
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.9062991
Short name T872
Test name
Test status
Simulation time 60410534572 ps
CPU time 130.38 seconds
Started Jul 04 06:18:31 PM PDT 24
Finished Jul 04 06:20:42 PM PDT 24
Peak memory 250416 kb
Host smart-4a40b287-5f5b-4277-9020-d09226cfb727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9062991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.9062991
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2071618576
Short name T391
Test name
Test status
Simulation time 401749178 ps
CPU time 8.31 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:18:39 PM PDT 24
Peak memory 251104 kb
Host smart-eba1701d-a2ba-4671-a0b8-189d5b5f57f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071618576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2071618576
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4288559004
Short name T457
Test name
Test status
Simulation time 3162862208 ps
CPU time 57.35 seconds
Started Jul 04 06:18:29 PM PDT 24
Finished Jul 04 06:19:26 PM PDT 24
Peak memory 252772 kb
Host smart-0bc50d9c-11c3-4645-ac54-c44b14462ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288559004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4288559004
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3303585902
Short name T242
Test name
Test status
Simulation time 1142152280 ps
CPU time 6.7 seconds
Started Jul 04 06:18:29 PM PDT 24
Finished Jul 04 06:18:36 PM PDT 24
Peak memory 233840 kb
Host smart-d94ae828-d77b-43f9-9534-55c97f3c5ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303585902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3303585902
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1426416356
Short name T439
Test name
Test status
Simulation time 114657179 ps
CPU time 2.48 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:18:33 PM PDT 24
Peak memory 225520 kb
Host smart-6e91c20b-47d9-4a86-bbd8-e41b4ecc5232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426416356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1426416356
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.704380677
Short name T532
Test name
Test status
Simulation time 12945983597 ps
CPU time 6.38 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:18:37 PM PDT 24
Peak memory 225712 kb
Host smart-2aa131c9-77b0-4f5b-ab1e-ce4d155e3859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704380677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.704380677
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1736130607
Short name T267
Test name
Test status
Simulation time 122185781 ps
CPU time 2.47 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:18:33 PM PDT 24
Peak memory 233736 kb
Host smart-07a8d341-861c-4271-85b9-fd33baa0c473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736130607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1736130607
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3712105062
Short name T893
Test name
Test status
Simulation time 2927809312 ps
CPU time 8.28 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:18:39 PM PDT 24
Peak memory 221552 kb
Host smart-bd5a31d9-2794-4415-9324-4423b5b87b10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3712105062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3712105062
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3650057156
Short name T541
Test name
Test status
Simulation time 15997280802 ps
CPU time 44.24 seconds
Started Jul 04 06:18:31 PM PDT 24
Finished Jul 04 06:19:15 PM PDT 24
Peak memory 217508 kb
Host smart-f40535f3-65c6-48d3-b84e-6067627bb2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650057156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3650057156
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1300471929
Short name T335
Test name
Test status
Simulation time 17657641 ps
CPU time 0.74 seconds
Started Jul 04 06:18:30 PM PDT 24
Finished Jul 04 06:18:30 PM PDT 24
Peak memory 206596 kb
Host smart-8aacf329-83fa-4485-bfe4-8338bac7dd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300471929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1300471929
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3836349641
Short name T434
Test name
Test status
Simulation time 56482390 ps
CPU time 1.2 seconds
Started Jul 04 06:18:32 PM PDT 24
Finished Jul 04 06:18:33 PM PDT 24
Peak memory 217384 kb
Host smart-f5636043-64ef-4bb8-bb57-c595d41b8a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836349641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3836349641
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1423284795
Short name T494
Test name
Test status
Simulation time 20476957 ps
CPU time 0.75 seconds
Started Jul 04 06:18:32 PM PDT 24
Finished Jul 04 06:18:33 PM PDT 24
Peak memory 207008 kb
Host smart-7965a71e-50d5-45da-b011-da22eb3c5658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423284795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1423284795
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2660335952
Short name T250
Test name
Test status
Simulation time 332462961 ps
CPU time 2.91 seconds
Started Jul 04 06:18:33 PM PDT 24
Finished Jul 04 06:18:36 PM PDT 24
Peak memory 233732 kb
Host smart-39530e38-a28c-46ee-9225-8c594218034e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660335952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2660335952
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2277117726
Short name T345
Test name
Test status
Simulation time 19708279 ps
CPU time 0.71 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:18:39 PM PDT 24
Peak memory 205820 kb
Host smart-33011c9f-e419-4bd1-923b-b72194e3861b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277117726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2277117726
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2678801670
Short name T749
Test name
Test status
Simulation time 274713352 ps
CPU time 3.02 seconds
Started Jul 04 06:18:37 PM PDT 24
Finished Jul 04 06:18:41 PM PDT 24
Peak memory 233772 kb
Host smart-c55c3b8e-67d9-4950-96d0-10bdfd1fecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678801670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2678801670
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2089047331
Short name T328
Test name
Test status
Simulation time 49692736 ps
CPU time 0.83 seconds
Started Jul 04 06:18:32 PM PDT 24
Finished Jul 04 06:18:33 PM PDT 24
Peak memory 207556 kb
Host smart-74fd94e9-6560-4948-b8a4-2035986c2825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089047331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2089047331
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1099733304
Short name T873
Test name
Test status
Simulation time 43623976297 ps
CPU time 98.66 seconds
Started Jul 04 06:18:39 PM PDT 24
Finished Jul 04 06:20:18 PM PDT 24
Peak memory 257032 kb
Host smart-0f843be2-528d-4d89-bffa-722b3bb558c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099733304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1099733304
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2822316587
Short name T813
Test name
Test status
Simulation time 93616918839 ps
CPU time 468.74 seconds
Started Jul 04 06:18:37 PM PDT 24
Finished Jul 04 06:26:26 PM PDT 24
Peak memory 258644 kb
Host smart-aa20bea2-5b22-4e6c-9bb1-101c7286de7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822316587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2822316587
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1200517005
Short name T400
Test name
Test status
Simulation time 2765882439 ps
CPU time 31.78 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:19:10 PM PDT 24
Peak memory 225844 kb
Host smart-3da5a02a-e12e-421c-920a-37d0389b4d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200517005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1200517005
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1112795581
Short name T422
Test name
Test status
Simulation time 142984072 ps
CPU time 3.86 seconds
Started Jul 04 06:18:37 PM PDT 24
Finished Jul 04 06:18:42 PM PDT 24
Peak memory 233776 kb
Host smart-6c969271-318d-4c4b-8782-8aac9475f770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112795581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1112795581
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.831186147
Short name T770
Test name
Test status
Simulation time 19744844163 ps
CPU time 62.39 seconds
Started Jul 04 06:18:36 PM PDT 24
Finished Jul 04 06:19:39 PM PDT 24
Peak memory 254888 kb
Host smart-340ac9be-81e0-4ba4-8159-b2ce063518bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831186147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.831186147
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2526959620
Short name T936
Test name
Test status
Simulation time 56463421 ps
CPU time 3.04 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:18:41 PM PDT 24
Peak memory 225596 kb
Host smart-e773b1c2-4855-4224-a5d8-c46993a27141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526959620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2526959620
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3711496354
Short name T904
Test name
Test status
Simulation time 39459459669 ps
CPU time 96.54 seconds
Started Jul 04 06:18:37 PM PDT 24
Finished Jul 04 06:20:14 PM PDT 24
Peak memory 241400 kb
Host smart-0b24e8f7-55ac-47d5-8499-c92eecd79410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711496354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3711496354
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.913127538
Short name T291
Test name
Test status
Simulation time 73674361553 ps
CPU time 45.91 seconds
Started Jul 04 06:18:40 PM PDT 24
Finished Jul 04 06:19:26 PM PDT 24
Peak memory 233936 kb
Host smart-749028aa-6454-4ee9-abe9-9309c9f597cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913127538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.913127538
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3084630397
Short name T209
Test name
Test status
Simulation time 705762772 ps
CPU time 7.25 seconds
Started Jul 04 06:18:41 PM PDT 24
Finished Jul 04 06:18:49 PM PDT 24
Peak memory 241000 kb
Host smart-25471056-d021-409e-9b4b-48d124378902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084630397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3084630397
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1449964778
Short name T348
Test name
Test status
Simulation time 1542840067 ps
CPU time 6.79 seconds
Started Jul 04 06:18:41 PM PDT 24
Finished Jul 04 06:18:48 PM PDT 24
Peak memory 221484 kb
Host smart-59911986-fc5d-41f6-8da7-1cc3d02680ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449964778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1449964778
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2233430979
Short name T678
Test name
Test status
Simulation time 181690105 ps
CPU time 1.12 seconds
Started Jul 04 06:18:40 PM PDT 24
Finished Jul 04 06:18:41 PM PDT 24
Peak memory 207908 kb
Host smart-0450bc30-0713-44d2-af24-89bb8ff99a33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233430979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2233430979
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3765353170
Short name T769
Test name
Test status
Simulation time 438673613 ps
CPU time 7.94 seconds
Started Jul 04 06:18:29 PM PDT 24
Finished Jul 04 06:18:38 PM PDT 24
Peak memory 217344 kb
Host smart-1f924ae4-4b84-4293-9a72-8536d3908d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765353170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3765353170
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3986746547
Short name T622
Test name
Test status
Simulation time 317005335 ps
CPU time 2.87 seconds
Started Jul 04 06:18:29 PM PDT 24
Finished Jul 04 06:18:32 PM PDT 24
Peak memory 217324 kb
Host smart-f42235d6-f620-42ce-8427-af59463d0e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986746547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3986746547
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.476646120
Short name T368
Test name
Test status
Simulation time 20638055 ps
CPU time 1.12 seconds
Started Jul 04 06:18:37 PM PDT 24
Finished Jul 04 06:18:39 PM PDT 24
Peak memory 208316 kb
Host smart-baace707-add7-4ce1-aa99-cc9501f4e652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476646120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.476646120
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2091646209
Short name T329
Test name
Test status
Simulation time 322655468 ps
CPU time 0.94 seconds
Started Jul 04 06:18:39 PM PDT 24
Finished Jul 04 06:18:40 PM PDT 24
Peak memory 206996 kb
Host smart-1d2f7432-91bd-4e10-a3ae-65be23e3c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091646209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2091646209
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1301144522
Short name T918
Test name
Test status
Simulation time 14617419511 ps
CPU time 19.83 seconds
Started Jul 04 06:18:41 PM PDT 24
Finished Jul 04 06:19:01 PM PDT 24
Peak memory 225668 kb
Host smart-222b9ca0-f4a5-4843-9231-6bda85d0efb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301144522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1301144522
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3013922358
Short name T548
Test name
Test status
Simulation time 13963636 ps
CPU time 0.78 seconds
Started Jul 04 06:18:42 PM PDT 24
Finished Jul 04 06:18:42 PM PDT 24
Peak memory 205808 kb
Host smart-26753194-549c-4257-a393-53b95b825427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013922358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3013922358
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1032609557
Short name T973
Test name
Test status
Simulation time 151710805 ps
CPU time 3.62 seconds
Started Jul 04 06:18:39 PM PDT 24
Finished Jul 04 06:18:43 PM PDT 24
Peak memory 233796 kb
Host smart-6f1de926-d73e-41fa-a326-ce47eaf28256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032609557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1032609557
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3727640930
Short name T836
Test name
Test status
Simulation time 29474346 ps
CPU time 0.81 seconds
Started Jul 04 06:18:40 PM PDT 24
Finished Jul 04 06:18:41 PM PDT 24
Peak memory 207888 kb
Host smart-5246c18f-d351-4ae5-8198-b6840b4da4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727640930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3727640930
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.508599735
Short name T757
Test name
Test status
Simulation time 25696736569 ps
CPU time 120.86 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:20:39 PM PDT 24
Peak memory 257152 kb
Host smart-3d17fa83-3acf-422b-85c1-4879c8b9fae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508599735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.508599735
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3411847989
Short name T720
Test name
Test status
Simulation time 4680783048 ps
CPU time 36.14 seconds
Started Jul 04 06:18:36 PM PDT 24
Finished Jul 04 06:19:13 PM PDT 24
Peak memory 233920 kb
Host smart-39d58f4e-40ae-4196-ab38-db1e304e51af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411847989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3411847989
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.913424777
Short name T573
Test name
Test status
Simulation time 5354522608 ps
CPU time 69.97 seconds
Started Jul 04 06:18:37 PM PDT 24
Finished Jul 04 06:19:47 PM PDT 24
Peak memory 254972 kb
Host smart-5fe6a6fb-9565-4c99-9b33-8c7f2d9acfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913424777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.913424777
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2186609730
Short name T397
Test name
Test status
Simulation time 274531937 ps
CPU time 3.48 seconds
Started Jul 04 06:18:40 PM PDT 24
Finished Jul 04 06:18:44 PM PDT 24
Peak memory 225544 kb
Host smart-9f68f773-e15a-4018-8f31-79dbee28ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186609730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2186609730
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3592009405
Short name T380
Test name
Test status
Simulation time 13600826673 ps
CPU time 29.01 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:19:07 PM PDT 24
Peak memory 234944 kb
Host smart-e8dbd565-ad8c-4b05-b890-63a6bfb9ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592009405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3592009405
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3008796265
Short name T911
Test name
Test status
Simulation time 455134542 ps
CPU time 7.11 seconds
Started Jul 04 06:18:39 PM PDT 24
Finished Jul 04 06:18:47 PM PDT 24
Peak memory 225568 kb
Host smart-b6bd78dd-60bc-4bb4-9e2c-75ecf9aeee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008796265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3008796265
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3156880993
Short name T90
Test name
Test status
Simulation time 458643954 ps
CPU time 10.89 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:18:50 PM PDT 24
Peak memory 234780 kb
Host smart-0df0b242-3918-418f-8005-1dbd1503c523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156880993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3156880993
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.951362580
Short name T529
Test name
Test status
Simulation time 2118754719 ps
CPU time 6.89 seconds
Started Jul 04 06:18:36 PM PDT 24
Finished Jul 04 06:18:44 PM PDT 24
Peak memory 234872 kb
Host smart-e736d415-f970-4235-a35e-4571b1dfed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951362580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.951362580
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4069333655
Short name T1011
Test name
Test status
Simulation time 405520374 ps
CPU time 2.22 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:18:40 PM PDT 24
Peak memory 233560 kb
Host smart-cc7afc13-c665-41d5-8801-c753cac7217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069333655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4069333655
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1757893666
Short name T396
Test name
Test status
Simulation time 6346751472 ps
CPU time 14.3 seconds
Started Jul 04 06:18:40 PM PDT 24
Finished Jul 04 06:18:54 PM PDT 24
Peak memory 221208 kb
Host smart-aefc0b73-1eda-46fd-a9f7-c058a853d21b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1757893666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1757893666
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3267608842
Short name T808
Test name
Test status
Simulation time 20758492546 ps
CPU time 235.72 seconds
Started Jul 04 06:18:39 PM PDT 24
Finished Jul 04 06:22:35 PM PDT 24
Peak memory 252044 kb
Host smart-858761c0-7ad7-458e-81a4-dcac01355026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267608842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3267608842
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2338804509
Short name T847
Test name
Test status
Simulation time 2611610907 ps
CPU time 13.68 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:18:52 PM PDT 24
Peak memory 217508 kb
Host smart-eb0b665f-ad42-496a-809e-a435cae3d630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338804509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2338804509
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4211697539
Short name T81
Test name
Test status
Simulation time 1419591300 ps
CPU time 6.32 seconds
Started Jul 04 06:18:38 PM PDT 24
Finished Jul 04 06:18:45 PM PDT 24
Peak memory 217280 kb
Host smart-ded4d3e9-1dc9-444d-ac59-fd5076301c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211697539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4211697539
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1628111138
Short name T524
Test name
Test status
Simulation time 24611659 ps
CPU time 1.35 seconds
Started Jul 04 06:18:36 PM PDT 24
Finished Jul 04 06:18:38 PM PDT 24
Peak memory 217312 kb
Host smart-ead6b737-8646-4d18-bb3f-ccb26f29d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628111138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1628111138
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1577351667
Short name T577
Test name
Test status
Simulation time 182531441 ps
CPU time 1.01 seconds
Started Jul 04 06:18:39 PM PDT 24
Finished Jul 04 06:18:40 PM PDT 24
Peak memory 207004 kb
Host smart-e51fdedc-6ca1-4180-a408-499775ae373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577351667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1577351667
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1435373929
Short name T504
Test name
Test status
Simulation time 14856626601 ps
CPU time 10.18 seconds
Started Jul 04 06:18:37 PM PDT 24
Finished Jul 04 06:18:48 PM PDT 24
Peak memory 233904 kb
Host smart-b9844f56-32ca-482e-92e3-42ced9587cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435373929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1435373929
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.166476581
Short name T543
Test name
Test status
Simulation time 13701085 ps
CPU time 0.73 seconds
Started Jul 04 06:18:51 PM PDT 24
Finished Jul 04 06:18:52 PM PDT 24
Peak memory 206344 kb
Host smart-03ce38ce-50c5-49e6-ba0f-fa5d9771f45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166476581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.166476581
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1535391576
Short name T456
Test name
Test status
Simulation time 789591307 ps
CPU time 6.17 seconds
Started Jul 04 06:18:50 PM PDT 24
Finished Jul 04 06:18:57 PM PDT 24
Peak memory 225628 kb
Host smart-8358086c-e98f-49e2-acdd-0d05d61e189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535391576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1535391576
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1961685651
Short name T587
Test name
Test status
Simulation time 19595903 ps
CPU time 0.8 seconds
Started Jul 04 06:18:50 PM PDT 24
Finished Jul 04 06:18:51 PM PDT 24
Peak memory 207824 kb
Host smart-26f3aa0a-9dbf-4c0a-88c6-1dbcfad066f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961685651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1961685651
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.442857412
Short name T751
Test name
Test status
Simulation time 15626318971 ps
CPU time 42.46 seconds
Started Jul 04 06:18:51 PM PDT 24
Finished Jul 04 06:19:34 PM PDT 24
Peak memory 242064 kb
Host smart-df0cf831-839a-4fa2-95e3-593bb6927818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442857412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.442857412
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1330864454
Short name T321
Test name
Test status
Simulation time 17890572386 ps
CPU time 43.18 seconds
Started Jul 04 06:18:45 PM PDT 24
Finished Jul 04 06:19:28 PM PDT 24
Peak memory 240088 kb
Host smart-48899a15-c632-47db-a179-0d63df9f13df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330864454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1330864454
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1561445286
Short name T948
Test name
Test status
Simulation time 38455885793 ps
CPU time 407.47 seconds
Started Jul 04 06:18:45 PM PDT 24
Finished Jul 04 06:25:33 PM PDT 24
Peak memory 262292 kb
Host smart-cc42d702-1c4d-47c0-82cf-7bcf93f790fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561445286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1561445286
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1144051969
Short name T839
Test name
Test status
Simulation time 2538594708 ps
CPU time 8.91 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:19:01 PM PDT 24
Peak memory 233988 kb
Host smart-3812200b-cb50-4c4b-851a-ff0af5b2153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144051969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1144051969
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1663630260
Short name T216
Test name
Test status
Simulation time 19303558378 ps
CPU time 74.35 seconds
Started Jul 04 06:18:45 PM PDT 24
Finished Jul 04 06:20:00 PM PDT 24
Peak memory 233928 kb
Host smart-bde8c72b-277b-4496-a722-b0e3f415217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663630260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1663630260
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3650532948
Short name T423
Test name
Test status
Simulation time 632586139 ps
CPU time 4.04 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:58 PM PDT 24
Peak memory 233792 kb
Host smart-cca661c2-166d-4381-881a-56c2b1cc391f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650532948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3650532948
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.675044804
Short name T662
Test name
Test status
Simulation time 3152605907 ps
CPU time 26.71 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:19:20 PM PDT 24
Peak memory 236900 kb
Host smart-9cb5f8ff-c891-4389-9ed2-117233b66f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675044804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.675044804
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.63961745
Short name T886
Test name
Test status
Simulation time 307957749 ps
CPU time 6.79 seconds
Started Jul 04 06:18:45 PM PDT 24
Finished Jul 04 06:18:52 PM PDT 24
Peak memory 233780 kb
Host smart-44e27b3f-6782-4204-89b2-6649014fc3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63961745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.63961745
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1395116285
Short name T374
Test name
Test status
Simulation time 3178186052 ps
CPU time 6.97 seconds
Started Jul 04 06:18:46 PM PDT 24
Finished Jul 04 06:18:53 PM PDT 24
Peak memory 233936 kb
Host smart-5fbfb4cf-1b84-4043-bdda-8dfc098600de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395116285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1395116285
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2508060756
Short name T395
Test name
Test status
Simulation time 139794408 ps
CPU time 4.41 seconds
Started Jul 04 06:18:46 PM PDT 24
Finished Jul 04 06:18:50 PM PDT 24
Peak memory 223336 kb
Host smart-3099f91c-2b49-4dd9-83a5-e48ec9b6c1b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2508060756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2508060756
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1231201000
Short name T453
Test name
Test status
Simulation time 4306235035 ps
CPU time 6.7 seconds
Started Jul 04 06:18:45 PM PDT 24
Finished Jul 04 06:18:52 PM PDT 24
Peak memory 221016 kb
Host smart-6648d93d-3e28-45e6-b556-9c60a0adfdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231201000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1231201000
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3829631635
Short name T783
Test name
Test status
Simulation time 6992254080 ps
CPU time 20.27 seconds
Started Jul 04 06:18:51 PM PDT 24
Finished Jul 04 06:19:11 PM PDT 24
Peak memory 217496 kb
Host smart-b77db639-a883-4e7e-af91-1945074105b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829631635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3829631635
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2237957603
Short name T806
Test name
Test status
Simulation time 86742517 ps
CPU time 1.42 seconds
Started Jul 04 06:18:45 PM PDT 24
Finished Jul 04 06:18:47 PM PDT 24
Peak memory 217396 kb
Host smart-f8c853a0-cc6b-4381-ba97-b013a58ed759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237957603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2237957603
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4286704020
Short name T862
Test name
Test status
Simulation time 42718403 ps
CPU time 0.7 seconds
Started Jul 04 06:18:44 PM PDT 24
Finished Jul 04 06:18:45 PM PDT 24
Peak memory 207000 kb
Host smart-880145ad-3534-4847-a155-b6d8a76649cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286704020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4286704020
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3538275130
Short name T407
Test name
Test status
Simulation time 133616357 ps
CPU time 2.53 seconds
Started Jul 04 06:18:51 PM PDT 24
Finished Jul 04 06:18:54 PM PDT 24
Peak memory 233708 kb
Host smart-3b9f4605-95bb-4483-a855-6a94e052521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538275130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3538275130
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4139463753
Short name T62
Test name
Test status
Simulation time 12578807 ps
CPU time 0.74 seconds
Started Jul 04 06:18:58 PM PDT 24
Finished Jul 04 06:18:59 PM PDT 24
Peak memory 206384 kb
Host smart-67996e52-3e5f-47c4-9228-899c4b60a69c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139463753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4139463753
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2606376814
Short name T241
Test name
Test status
Simulation time 2498120865 ps
CPU time 4.16 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:18:58 PM PDT 24
Peak memory 233904 kb
Host smart-e2cb9eec-4b69-4c8d-88ec-090acf67ef4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606376814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2606376814
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1263260556
Short name T931
Test name
Test status
Simulation time 67389055 ps
CPU time 0.76 seconds
Started Jul 04 06:18:50 PM PDT 24
Finished Jul 04 06:18:51 PM PDT 24
Peak memory 207828 kb
Host smart-0ec25b2f-ff33-4810-b316-55fc9841d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263260556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1263260556
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3814194591
Short name T970
Test name
Test status
Simulation time 164085434703 ps
CPU time 98.73 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:20:33 PM PDT 24
Peak memory 249984 kb
Host smart-3872b6c1-4038-471f-aba7-54dd8f9195e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814194591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3814194591
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3568425528
Short name T843
Test name
Test status
Simulation time 19984227089 ps
CPU time 87.68 seconds
Started Jul 04 06:18:51 PM PDT 24
Finished Jul 04 06:20:19 PM PDT 24
Peak memory 253580 kb
Host smart-51a95f51-af40-4748-884a-805439a56460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568425528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3568425528
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3047625253
Short name T133
Test name
Test status
Simulation time 25334902245 ps
CPU time 76.43 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:20:11 PM PDT 24
Peak memory 251044 kb
Host smart-ab573a31-37ed-48a5-b3e2-5532289858a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047625253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3047625253
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.439978226
Short name T616
Test name
Test status
Simulation time 432185109 ps
CPU time 3.11 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:18:56 PM PDT 24
Peak memory 225584 kb
Host smart-359764cd-c0ed-4c92-9b08-d8f467317727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439978226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.439978226
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.682571896
Short name T520
Test name
Test status
Simulation time 6665428269 ps
CPU time 45.23 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:19:40 PM PDT 24
Peak memory 252280 kb
Host smart-f37789a0-ec8d-4e2a-946b-dfc91dc53f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682571896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.682571896
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1506991166
Short name T669
Test name
Test status
Simulation time 538108415 ps
CPU time 8.36 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:19:02 PM PDT 24
Peak memory 225636 kb
Host smart-8a07fc2b-5e48-4fad-8953-fee9fc565e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506991166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1506991166
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1935707929
Short name T238
Test name
Test status
Simulation time 8438627018 ps
CPU time 22.19 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:19:16 PM PDT 24
Peak memory 233936 kb
Host smart-f7d9cfea-a137-4683-918f-505bac0785a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935707929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1935707929
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2573037052
Short name T670
Test name
Test status
Simulation time 32190306910 ps
CPU time 26.35 seconds
Started Jul 04 06:18:45 PM PDT 24
Finished Jul 04 06:19:12 PM PDT 24
Peak memory 225616 kb
Host smart-3b56c37a-c667-48f8-91af-a61809d84146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573037052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2573037052
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3900972507
Short name T259
Test name
Test status
Simulation time 555370299 ps
CPU time 2.59 seconds
Started Jul 04 06:18:50 PM PDT 24
Finished Jul 04 06:18:53 PM PDT 24
Peak memory 225524 kb
Host smart-5ba534e2-a5ff-439a-bf62-c4d3359eb5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900972507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3900972507
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.71891387
Short name T1016
Test name
Test status
Simulation time 1373823116 ps
CPU time 5.75 seconds
Started Jul 04 06:18:56 PM PDT 24
Finished Jul 04 06:19:02 PM PDT 24
Peak memory 223136 kb
Host smart-7432e26a-fe67-4e4d-909e-91cdf361c727
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=71891387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.71891387
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1877551829
Short name T300
Test name
Test status
Simulation time 136138274509 ps
CPU time 582.98 seconds
Started Jul 04 06:18:56 PM PDT 24
Finished Jul 04 06:28:39 PM PDT 24
Peak memory 261548 kb
Host smart-ff562206-f138-4e43-9c0e-a6234d122f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877551829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1877551829
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2785879311
Short name T319
Test name
Test status
Simulation time 9992135232 ps
CPU time 31.07 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:19:23 PM PDT 24
Peak memory 217568 kb
Host smart-9bbc855c-d982-4268-b4c0-cf03e5dc1152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785879311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2785879311
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2278213549
Short name T810
Test name
Test status
Simulation time 11182971839 ps
CPU time 8.19 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:19:00 PM PDT 24
Peak memory 217468 kb
Host smart-1267f472-4d50-43f7-a1ab-e710f805d537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278213549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2278213549
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3303632741
Short name T735
Test name
Test status
Simulation time 24204364 ps
CPU time 1.43 seconds
Started Jul 04 06:18:51 PM PDT 24
Finished Jul 04 06:18:52 PM PDT 24
Peak memory 217444 kb
Host smart-0d1ce339-1afd-4583-93d7-909f50cc44ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303632741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3303632741
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4006089350
Short name T581
Test name
Test status
Simulation time 53355145 ps
CPU time 0.73 seconds
Started Jul 04 06:18:46 PM PDT 24
Finished Jul 04 06:18:47 PM PDT 24
Peak memory 206996 kb
Host smart-76ac9dc4-6cd2-4d13-915c-1c53465288a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006089350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4006089350
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2607756345
Short name T545
Test name
Test status
Simulation time 614778125 ps
CPU time 7.85 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:19:03 PM PDT 24
Peak memory 242016 kb
Host smart-c99d57ab-1a8f-478a-b67f-e98df2d46ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607756345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2607756345
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3558337289
Short name T903
Test name
Test status
Simulation time 37571995 ps
CPU time 0.72 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:54 PM PDT 24
Peak memory 206384 kb
Host smart-b3094ed7-75b2-41b5-9127-08985589a86a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558337289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3558337289
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3538982065
Short name T461
Test name
Test status
Simulation time 112672869 ps
CPU time 2.39 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:56 PM PDT 24
Peak memory 225600 kb
Host smart-dccd64dd-e49b-4a41-93db-2dd694a9d5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538982065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3538982065
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3040459635
Short name T824
Test name
Test status
Simulation time 66686732 ps
CPU time 0.76 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:54 PM PDT 24
Peak memory 206516 kb
Host smart-b237c023-3fad-420c-91a7-c69a463976ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040459635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3040459635
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.445895089
Short name T448
Test name
Test status
Simulation time 21315518920 ps
CPU time 41.61 seconds
Started Jul 04 06:18:56 PM PDT 24
Finished Jul 04 06:19:38 PM PDT 24
Peak memory 242032 kb
Host smart-30f7b06c-565a-4c4e-aa06-eef87e93a7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445895089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.445895089
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2804064912
Short name T48
Test name
Test status
Simulation time 25073253382 ps
CPU time 56.77 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:19:49 PM PDT 24
Peak memory 250988 kb
Host smart-ae95ff47-13c4-4df5-995d-f35a2364b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804064912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2804064912
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1197117589
Short name T1024
Test name
Test status
Simulation time 11780082918 ps
CPU time 21.19 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:19:16 PM PDT 24
Peak memory 225840 kb
Host smart-e85f5625-e18c-41df-855f-e68a22c2c0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197117589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1197117589
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2818689041
Short name T697
Test name
Test status
Simulation time 3243192867 ps
CPU time 22.59 seconds
Started Jul 04 06:18:57 PM PDT 24
Finished Jul 04 06:19:20 PM PDT 24
Peak memory 225676 kb
Host smart-349df019-40fb-4a0c-bb48-72b792c80a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818689041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2818689041
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1988328884
Short name T208
Test name
Test status
Simulation time 38778876620 ps
CPU time 137.94 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:21:11 PM PDT 24
Peak memory 256124 kb
Host smart-3a035f4d-cb33-4955-ad54-529052686064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988328884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1988328884
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3850159621
Short name T954
Test name
Test status
Simulation time 6757893317 ps
CPU time 20.68 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:19:14 PM PDT 24
Peak memory 240696 kb
Host smart-e3a004f8-b010-4328-bd45-0dcc1d4e0605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850159621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3850159621
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3298005818
Short name T618
Test name
Test status
Simulation time 78045169 ps
CPU time 2.3 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:56 PM PDT 24
Peak memory 224188 kb
Host smart-38506c50-af9c-4233-9fa5-cc314d1f49f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298005818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3298005818
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.81278111
Short name T702
Test name
Test status
Simulation time 2473267228 ps
CPU time 6.08 seconds
Started Jul 04 06:18:56 PM PDT 24
Finished Jul 04 06:19:02 PM PDT 24
Peak memory 225660 kb
Host smart-9533468e-6441-4c56-95c8-6d8a9a22458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81278111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.81278111
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1788198586
Short name T703
Test name
Test status
Simulation time 119696293 ps
CPU time 4.34 seconds
Started Jul 04 06:18:57 PM PDT 24
Finished Jul 04 06:19:01 PM PDT 24
Peak memory 224048 kb
Host smart-1d839714-0b0e-4dbd-aa38-dd41c4e727e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1788198586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1788198586
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.316600183
Short name T166
Test name
Test status
Simulation time 185643314 ps
CPU time 1.09 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:54 PM PDT 24
Peak memory 208048 kb
Host smart-f273b42e-e7a2-4154-b9fc-d05dd20fb991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316600183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.316600183
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.37122418
Short name T320
Test name
Test status
Simulation time 6119333287 ps
CPU time 14.97 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:19:09 PM PDT 24
Peak memory 217544 kb
Host smart-e359478f-ef88-4994-a7ea-64952abbf758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37122418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.37122418
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1952180098
Short name T858
Test name
Test status
Simulation time 137523817 ps
CPU time 1.47 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:55 PM PDT 24
Peak memory 208140 kb
Host smart-8dff07d0-1951-4375-a704-dc1681f82baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952180098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1952180098
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1740105743
Short name T367
Test name
Test status
Simulation time 179552866 ps
CPU time 1.27 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:55 PM PDT 24
Peak memory 217436 kb
Host smart-0f5d3ade-ad02-4902-bf61-ef8b6d578574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740105743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1740105743
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1651249144
Short name T754
Test name
Test status
Simulation time 21335309 ps
CPU time 0.78 seconds
Started Jul 04 06:18:56 PM PDT 24
Finished Jul 04 06:18:58 PM PDT 24
Peak memory 206968 kb
Host smart-cc9418db-51d4-4984-947d-2de82c23fb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651249144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1651249144
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3158696049
Short name T642
Test name
Test status
Simulation time 243108472 ps
CPU time 4.92 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:18:59 PM PDT 24
Peak memory 233836 kb
Host smart-6e46c2a0-507c-4484-992d-fb7fe2841911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158696049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3158696049
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2902784438
Short name T736
Test name
Test status
Simulation time 19526077 ps
CPU time 0.72 seconds
Started Jul 04 06:19:06 PM PDT 24
Finished Jul 04 06:19:07 PM PDT 24
Peak memory 206408 kb
Host smart-91e7b2f1-f289-4782-b2be-2439146c35f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902784438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2902784438
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.588966831
Short name T1019
Test name
Test status
Simulation time 223984866 ps
CPU time 2.1 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:18:55 PM PDT 24
Peak memory 224672 kb
Host smart-1732e9b0-745b-465b-bd07-5e9f96b0a6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588966831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.588966831
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2846426081
Short name T327
Test name
Test status
Simulation time 74569521 ps
CPU time 0.82 seconds
Started Jul 04 06:18:58 PM PDT 24
Finished Jul 04 06:18:59 PM PDT 24
Peak memory 207860 kb
Host smart-ff6ac89b-ca91-4ff6-bdbd-6f8724cd436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846426081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2846426081
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2236984720
Short name T449
Test name
Test status
Simulation time 10537703727 ps
CPU time 36.09 seconds
Started Jul 04 06:18:56 PM PDT 24
Finished Jul 04 06:19:32 PM PDT 24
Peak memory 242124 kb
Host smart-ac3f4435-a6b9-4bad-acb3-0d0401220fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236984720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2236984720
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.217529129
Short name T547
Test name
Test status
Simulation time 2685920533 ps
CPU time 48.55 seconds
Started Jul 04 06:18:55 PM PDT 24
Finished Jul 04 06:19:43 PM PDT 24
Peak memory 252024 kb
Host smart-e19e8952-7065-4414-ab7d-59d48c45b0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217529129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.217529129
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.182700067
Short name T182
Test name
Test status
Simulation time 10701577586 ps
CPU time 59.98 seconds
Started Jul 04 06:19:02 PM PDT 24
Finished Jul 04 06:20:02 PM PDT 24
Peak memory 250412 kb
Host smart-efc8af92-922d-432b-99bf-21aa89915e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182700067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.182700067
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1793700001
Short name T304
Test name
Test status
Simulation time 359800838 ps
CPU time 10.8 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:19:04 PM PDT 24
Peak memory 236028 kb
Host smart-c0c2dce7-6b39-4d2a-b0f1-a8c68f33b38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793700001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1793700001
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.125378931
Short name T758
Test name
Test status
Simulation time 4247353152 ps
CPU time 55.19 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:19:49 PM PDT 24
Peak memory 242108 kb
Host smart-9197a14e-2f0b-4968-8bef-e463c91c8935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125378931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.125378931
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1062225720
Short name T748
Test name
Test status
Simulation time 998550412 ps
CPU time 4.86 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:18:58 PM PDT 24
Peak memory 228956 kb
Host smart-119774a9-7f48-4ae2-98f6-5aaf5dbf9389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062225720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1062225720
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3370037974
Short name T930
Test name
Test status
Simulation time 661347144 ps
CPU time 4.14 seconds
Started Jul 04 06:18:51 PM PDT 24
Finished Jul 04 06:18:56 PM PDT 24
Peak memory 241988 kb
Host smart-ea33b09f-16d2-4ca7-a3c5-6570385f55a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370037974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3370037974
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1369897749
Short name T610
Test name
Test status
Simulation time 607736593 ps
CPU time 6.66 seconds
Started Jul 04 06:18:58 PM PDT 24
Finished Jul 04 06:19:05 PM PDT 24
Peak memory 241564 kb
Host smart-c9a37829-350f-4f29-afb7-e1b4eeb41105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369897749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1369897749
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1050236420
Short name T875
Test name
Test status
Simulation time 145276524 ps
CPU time 3.25 seconds
Started Jul 04 06:18:53 PM PDT 24
Finished Jul 04 06:18:57 PM PDT 24
Peak memory 233720 kb
Host smart-dc6dcf7e-fbe3-4b10-9435-240ce3913ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050236420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1050236420
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2596545026
Short name T143
Test name
Test status
Simulation time 1999889312 ps
CPU time 7.48 seconds
Started Jul 04 06:18:56 PM PDT 24
Finished Jul 04 06:19:03 PM PDT 24
Peak memory 223008 kb
Host smart-ed517736-bbca-428e-8b34-2ac9df9a9db0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2596545026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2596545026
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.741638200
Short name T989
Test name
Test status
Simulation time 68894895 ps
CPU time 1.13 seconds
Started Jul 04 06:19:02 PM PDT 24
Finished Jul 04 06:19:03 PM PDT 24
Peak memory 208560 kb
Host smart-f712b131-cd68-4cd9-a20b-4f790ff1bfa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741638200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.741638200
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2368418223
Short name T821
Test name
Test status
Simulation time 665207433 ps
CPU time 6.95 seconds
Started Jul 04 06:18:55 PM PDT 24
Finished Jul 04 06:19:02 PM PDT 24
Peak memory 217384 kb
Host smart-79e9f0d4-d423-4a6d-b94a-aab8466e2d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368418223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2368418223
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.42883334
Short name T767
Test name
Test status
Simulation time 12301926697 ps
CPU time 15.83 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:19:10 PM PDT 24
Peak memory 217460 kb
Host smart-70ca204e-4932-46d4-900c-73292bb84eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42883334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.42883334
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3824429049
Short name T53
Test name
Test status
Simulation time 88703148 ps
CPU time 1.58 seconds
Started Jul 04 06:18:54 PM PDT 24
Finished Jul 04 06:18:56 PM PDT 24
Peak memory 217392 kb
Host smart-fab2b4a5-f2d0-4d05-8181-369196fbbdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824429049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3824429049
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.284190968
Short name T61
Test name
Test status
Simulation time 31184278 ps
CPU time 0.78 seconds
Started Jul 04 06:18:55 PM PDT 24
Finished Jul 04 06:18:56 PM PDT 24
Peak memory 206960 kb
Host smart-221b5f14-f0f6-4520-a946-0d0b354203fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284190968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.284190968
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3063442244
Short name T888
Test name
Test status
Simulation time 2685604585 ps
CPU time 6.34 seconds
Started Jul 04 06:18:52 PM PDT 24
Finished Jul 04 06:19:00 PM PDT 24
Peak memory 225720 kb
Host smart-e6cdc784-4ae1-49d2-8341-7dba81e06d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063442244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3063442244
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2187011864
Short name T831
Test name
Test status
Simulation time 12018474 ps
CPU time 0.7 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:19:04 PM PDT 24
Peak memory 205776 kb
Host smart-4f2383fd-33c1-4250-97fa-8a3b4e7a267e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187011864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2187011864
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.183654536
Short name T445
Test name
Test status
Simulation time 2544367251 ps
CPU time 4.57 seconds
Started Jul 04 06:19:06 PM PDT 24
Finished Jul 04 06:19:11 PM PDT 24
Peak memory 233928 kb
Host smart-e77897a8-ee2f-4a34-886d-9000c2f90b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183654536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.183654536
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.413281748
Short name T332
Test name
Test status
Simulation time 46203731 ps
CPU time 0.76 seconds
Started Jul 04 06:19:06 PM PDT 24
Finished Jul 04 06:19:07 PM PDT 24
Peak memory 206476 kb
Host smart-f43b0be6-5034-42e9-9da9-95652b47c540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413281748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.413281748
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3203041839
Short name T458
Test name
Test status
Simulation time 4722632985 ps
CPU time 52.77 seconds
Started Jul 04 06:19:01 PM PDT 24
Finished Jul 04 06:19:54 PM PDT 24
Peak memory 254532 kb
Host smart-b24d38de-734d-4987-9be8-80b9b2578418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203041839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3203041839
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2092005047
Short name T490
Test name
Test status
Simulation time 9668200859 ps
CPU time 69.62 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:20:14 PM PDT 24
Peak memory 250464 kb
Host smart-a0b6fb14-075f-4abd-8b76-f08579753522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092005047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2092005047
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1198900932
Short name T556
Test name
Test status
Simulation time 2589511231 ps
CPU time 15.25 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:23 PM PDT 24
Peak memory 224324 kb
Host smart-9766f3fc-18fd-4d20-862f-177d80d43122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198900932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1198900932
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.89694021
Short name T1023
Test name
Test status
Simulation time 2521184009 ps
CPU time 22.2 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:30 PM PDT 24
Peak memory 241780 kb
Host smart-73674f1c-9c64-4acf-8e5e-f16fa91a00be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89694021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.89694021
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1238519019
Short name T959
Test name
Test status
Simulation time 430687602 ps
CPU time 3.73 seconds
Started Jul 04 06:19:03 PM PDT 24
Finished Jul 04 06:19:07 PM PDT 24
Peak memory 225552 kb
Host smart-95158e97-50d7-421c-ad3c-d3c662e6ee93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238519019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1238519019
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3565300296
Short name T44
Test name
Test status
Simulation time 4513906966 ps
CPU time 28.83 seconds
Started Jul 04 06:19:03 PM PDT 24
Finished Jul 04 06:19:32 PM PDT 24
Peak memory 233896 kb
Host smart-de56f4f7-a0ae-4cf4-897b-aee60bfb5f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565300296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3565300296
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3617293213
Short name T914
Test name
Test status
Simulation time 8463997550 ps
CPU time 9.76 seconds
Started Jul 04 06:19:03 PM PDT 24
Finished Jul 04 06:19:13 PM PDT 24
Peak memory 240804 kb
Host smart-a6cc0fa7-0471-49e9-9ed1-c71efda7e050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617293213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3617293213
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4218305149
Short name T441
Test name
Test status
Simulation time 75000796 ps
CPU time 2.28 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:19:06 PM PDT 24
Peak memory 224880 kb
Host smart-bc84741d-26fa-4b32-be24-b6b332d68308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218305149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4218305149
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1138406711
Short name T986
Test name
Test status
Simulation time 2130911583 ps
CPU time 7.11 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:19:12 PM PDT 24
Peak memory 219752 kb
Host smart-71df36df-9e9c-4544-a412-eb95e31308ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1138406711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1138406711
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1310438503
Short name T579
Test name
Test status
Simulation time 40662096835 ps
CPU time 79.44 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:20:27 PM PDT 24
Peak memory 250224 kb
Host smart-2e57561a-f748-4914-8793-bdb80292fc19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310438503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1310438503
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.973570976
Short name T916
Test name
Test status
Simulation time 6708447571 ps
CPU time 8 seconds
Started Jul 04 06:19:05 PM PDT 24
Finished Jul 04 06:19:13 PM PDT 24
Peak memory 217476 kb
Host smart-00c390cb-9e42-430f-9cc8-b2f3ba08cfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973570976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.973570976
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1287493620
Short name T342
Test name
Test status
Simulation time 1467175252 ps
CPU time 6.08 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:19:11 PM PDT 24
Peak memory 217216 kb
Host smart-7b41e04d-a513-46e4-9ebb-d48eda007fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287493620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1287493620
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1847174153
Short name T564
Test name
Test status
Simulation time 50311368 ps
CPU time 1.76 seconds
Started Jul 04 06:19:02 PM PDT 24
Finished Jul 04 06:19:04 PM PDT 24
Peak memory 217388 kb
Host smart-fc73ee44-47af-4a4e-881f-c9c8c12abcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847174153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1847174153
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2417213228
Short name T592
Test name
Test status
Simulation time 145262081 ps
CPU time 1.19 seconds
Started Jul 04 06:19:06 PM PDT 24
Finished Jul 04 06:19:08 PM PDT 24
Peak memory 208036 kb
Host smart-4b0d7367-6521-4a18-bc6e-ac3d3cb72ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417213228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2417213228
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.248096770
Short name T213
Test name
Test status
Simulation time 17582430686 ps
CPU time 25.99 seconds
Started Jul 04 06:19:05 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 241812 kb
Host smart-900630bb-0c64-4f32-85c1-5f821f20477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248096770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.248096770
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.477110300
Short name T431
Test name
Test status
Simulation time 43018250 ps
CPU time 0.78 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:08 PM PDT 24
Peak memory 206720 kb
Host smart-42eb2077-f27c-4f32-aeab-7d6c091df8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477110300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.477110300
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2153110334
Short name T343
Test name
Test status
Simulation time 995377764 ps
CPU time 8.68 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:15 PM PDT 24
Peak memory 225568 kb
Host smart-063d20a7-e783-411f-8730-cba7bd9fdc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153110334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2153110334
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3786070538
Short name T978
Test name
Test status
Simulation time 27473629 ps
CPU time 0.86 seconds
Started Jul 04 06:19:06 PM PDT 24
Finished Jul 04 06:19:07 PM PDT 24
Peak memory 207888 kb
Host smart-bd9eaa6b-2943-4f37-b247-9caf67b1113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786070538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3786070538
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3179235140
Short name T685
Test name
Test status
Simulation time 329420164 ps
CPU time 3.48 seconds
Started Jul 04 06:19:06 PM PDT 24
Finished Jul 04 06:19:10 PM PDT 24
Peak memory 218892 kb
Host smart-f8af91e4-d9e7-4521-b43c-23fcdf44df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179235140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3179235140
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3261856996
Short name T590
Test name
Test status
Simulation time 328853810 ps
CPU time 12.17 seconds
Started Jul 04 06:19:04 PM PDT 24
Finished Jul 04 06:19:17 PM PDT 24
Peak memory 234816 kb
Host smart-8be9333d-6ba3-4c16-94e3-af4f3c58a4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261856996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3261856996
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1470982558
Short name T5
Test name
Test status
Simulation time 6379265236 ps
CPU time 44.48 seconds
Started Jul 04 06:19:03 PM PDT 24
Finished Jul 04 06:19:47 PM PDT 24
Peak memory 236732 kb
Host smart-4159cd82-8183-40c7-985a-e59d58ca9e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470982558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1470982558
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1571127327
Short name T418
Test name
Test status
Simulation time 616634135 ps
CPU time 5.64 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:13 PM PDT 24
Peak memory 233348 kb
Host smart-44c93403-7f93-4d63-a455-e1eea9f97edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571127327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1571127327
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3979839771
Short name T526
Test name
Test status
Simulation time 4908894492 ps
CPU time 7.04 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:15 PM PDT 24
Peak memory 225676 kb
Host smart-7d7f5c66-6292-4bd5-937a-fb31a5e8435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979839771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3979839771
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3380726868
Short name T274
Test name
Test status
Simulation time 1473254106 ps
CPU time 4.46 seconds
Started Jul 04 06:19:01 PM PDT 24
Finished Jul 04 06:19:06 PM PDT 24
Peak memory 225572 kb
Host smart-247d2f92-4e13-411d-96bd-5108757d533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380726868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3380726868
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4091473835
Short name T505
Test name
Test status
Simulation time 6186459852 ps
CPU time 18.74 seconds
Started Jul 04 06:19:02 PM PDT 24
Finished Jul 04 06:19:21 PM PDT 24
Peak memory 233920 kb
Host smart-16270e36-0b5a-4473-b268-1b7416e332b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091473835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4091473835
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3168472341
Short name T728
Test name
Test status
Simulation time 1095191947 ps
CPU time 4.03 seconds
Started Jul 04 06:19:02 PM PDT 24
Finished Jul 04 06:19:07 PM PDT 24
Peak memory 223436 kb
Host smart-8db92eec-8c61-48c3-aa74-b9b6b7da68cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3168472341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3168472341
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1151153633
Short name T953
Test name
Test status
Simulation time 7117214923 ps
CPU time 30.25 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:37 PM PDT 24
Peak memory 217572 kb
Host smart-b5b69495-a873-46de-a190-ba9e860f1615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151153633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1151153633
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1784394987
Short name T753
Test name
Test status
Simulation time 866415581 ps
CPU time 2.06 seconds
Started Jul 04 06:19:02 PM PDT 24
Finished Jul 04 06:19:04 PM PDT 24
Peak memory 217132 kb
Host smart-4f534141-5c93-4be3-a02e-a3805a25c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784394987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1784394987
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2517369392
Short name T561
Test name
Test status
Simulation time 44199005 ps
CPU time 0.82 seconds
Started Jul 04 06:19:03 PM PDT 24
Finished Jul 04 06:19:05 PM PDT 24
Peak memory 207520 kb
Host smart-a8422518-954b-4b2e-9e06-f4d73c5f37e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517369392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2517369392
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.791290505
Short name T935
Test name
Test status
Simulation time 76984132 ps
CPU time 0.8 seconds
Started Jul 04 06:19:03 PM PDT 24
Finished Jul 04 06:19:05 PM PDT 24
Peak memory 206980 kb
Host smart-80f5620e-08b9-43ce-a05d-e600a1152445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791290505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.791290505
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2682155709
Short name T621
Test name
Test status
Simulation time 5169389829 ps
CPU time 8.36 seconds
Started Jul 04 06:19:01 PM PDT 24
Finished Jul 04 06:19:09 PM PDT 24
Peak memory 225728 kb
Host smart-89372982-bb45-4608-b6b0-5d8b795f4627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682155709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2682155709
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2266201569
Short name T390
Test name
Test status
Simulation time 13147984 ps
CPU time 0.76 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:16 PM PDT 24
Peak memory 206396 kb
Host smart-ce40a842-9650-4388-884c-a9fe2a455f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266201569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2266201569
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1572934550
Short name T249
Test name
Test status
Simulation time 2267041028 ps
CPU time 17.93 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 233876 kb
Host smart-14fb21d4-b9a4-411d-a4c4-522b15fd338f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572934550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1572934550
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2944505003
Short name T60
Test name
Test status
Simulation time 20643957 ps
CPU time 0.78 seconds
Started Jul 04 06:19:01 PM PDT 24
Finished Jul 04 06:19:02 PM PDT 24
Peak memory 207496 kb
Host smart-a5ef7189-9ed9-4970-815c-399b489f519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944505003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2944505003
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.290450578
Short name T170
Test name
Test status
Simulation time 7171461615 ps
CPU time 95.06 seconds
Started Jul 04 06:19:12 PM PDT 24
Finished Jul 04 06:20:48 PM PDT 24
Peak memory 256200 kb
Host smart-11e8153d-f3c9-46c7-9908-c5a298ca81da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290450578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.290450578
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1962581350
Short name T482
Test name
Test status
Simulation time 228809021475 ps
CPU time 185.55 seconds
Started Jul 04 06:19:13 PM PDT 24
Finished Jul 04 06:22:19 PM PDT 24
Peak memory 250436 kb
Host smart-b527ec4d-f299-4942-ae89-1011a1cef7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962581350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1962581350
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3958386686
Short name T794
Test name
Test status
Simulation time 16648453467 ps
CPU time 41.78 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:56 PM PDT 24
Peak memory 225784 kb
Host smart-e6466d57-b439-4e2a-bf5d-603de7df6738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958386686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3958386686
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2208215136
Short name T309
Test name
Test status
Simulation time 1891385510 ps
CPU time 21.78 seconds
Started Jul 04 06:19:13 PM PDT 24
Finished Jul 04 06:19:36 PM PDT 24
Peak memory 241932 kb
Host smart-4ee9f6e5-106d-486f-94a4-5523a44a8e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208215136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2208215136
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.4092096370
Short name T303
Test name
Test status
Simulation time 20096809502 ps
CPU time 163.38 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:21:58 PM PDT 24
Peak memory 256012 kb
Host smart-cd90d762-9100-45af-961f-b454fe179fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092096370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.4092096370
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.149040077
Short name T992
Test name
Test status
Simulation time 1621923323 ps
CPU time 15.95 seconds
Started Jul 04 06:19:00 PM PDT 24
Finished Jul 04 06:19:16 PM PDT 24
Peak memory 233836 kb
Host smart-6e5c3e45-e65b-4eb3-a16f-0d0a161941a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149040077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.149040077
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.548314383
Short name T363
Test name
Test status
Simulation time 289523204 ps
CPU time 2.16 seconds
Started Jul 04 06:19:12 PM PDT 24
Finished Jul 04 06:19:14 PM PDT 24
Peak memory 223908 kb
Host smart-d2d03bf6-aebc-49fe-88ec-5b544516f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548314383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.548314383
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.994386309
Short name T474
Test name
Test status
Simulation time 561277873 ps
CPU time 3.33 seconds
Started Jul 04 06:19:03 PM PDT 24
Finished Jul 04 06:19:07 PM PDT 24
Peak memory 225612 kb
Host smart-a0089e12-d9e2-40b6-b0b4-6b8d974b097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994386309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.994386309
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3403380851
Short name T605
Test name
Test status
Simulation time 9264998012 ps
CPU time 9.05 seconds
Started Jul 04 06:19:01 PM PDT 24
Finished Jul 04 06:19:10 PM PDT 24
Peak memory 233820 kb
Host smart-acd3956f-c9b9-4617-a557-20b644df7a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403380851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3403380851
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.125398707
Short name T411
Test name
Test status
Simulation time 220010396 ps
CPU time 3.41 seconds
Started Jul 04 06:19:15 PM PDT 24
Finished Jul 04 06:19:19 PM PDT 24
Peak memory 219940 kb
Host smart-e9f74e1a-3271-4a03-8d7f-174580082698
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=125398707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.125398707
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2809865836
Short name T137
Test name
Test status
Simulation time 137338415670 ps
CPU time 420.8 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:26:15 PM PDT 24
Peak memory 272568 kb
Host smart-73ef7755-472f-4418-959a-64989596642f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809865836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2809865836
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1479527170
Short name T717
Test name
Test status
Simulation time 27083390638 ps
CPU time 39.71 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:48 PM PDT 24
Peak memory 217228 kb
Host smart-f737c6f6-1761-4b25-9167-a8cc100a44a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479527170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1479527170
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3901690292
Short name T566
Test name
Test status
Simulation time 847992232 ps
CPU time 3.17 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:11 PM PDT 24
Peak memory 217264 kb
Host smart-69204dd0-d803-4f52-9a56-5905f7fc1383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901690292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3901690292
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3005022233
Short name T478
Test name
Test status
Simulation time 52649297 ps
CPU time 1.78 seconds
Started Jul 04 06:19:01 PM PDT 24
Finished Jul 04 06:19:03 PM PDT 24
Peak memory 217400 kb
Host smart-8456dd7f-4fe4-4e5a-9b84-25374724b6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005022233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3005022233
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.333462742
Short name T784
Test name
Test status
Simulation time 157784784 ps
CPU time 0.84 seconds
Started Jul 04 06:19:07 PM PDT 24
Finished Jul 04 06:19:08 PM PDT 24
Peak memory 206996 kb
Host smart-7d9aebe9-63b8-4655-8f50-554fb2e026a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333462742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.333462742
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.515364040
Short name T944
Test name
Test status
Simulation time 854593692 ps
CPU time 5.37 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:20 PM PDT 24
Peak memory 241760 kb
Host smart-14730d3e-6cd1-4de7-9250-7cdc7b58bb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515364040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.515364040
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.6678575
Short name T507
Test name
Test status
Simulation time 31299530 ps
CPU time 0.77 seconds
Started Jul 04 06:17:01 PM PDT 24
Finished Jul 04 06:17:02 PM PDT 24
Peak memory 206396 kb
Host smart-ff6db906-840b-44df-83b5-434ae8a23667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6678575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.6678575
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3962054703
Short name T266
Test name
Test status
Simulation time 2721205061 ps
CPU time 3.59 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 233888 kb
Host smart-e6a02118-0dde-4423-9196-88f296a4fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962054703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3962054703
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3882750480
Short name T861
Test name
Test status
Simulation time 16482850 ps
CPU time 0.8 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 207520 kb
Host smart-b5935b8d-bd0f-4049-9d54-80e3107fa8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882750480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3882750480
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3471513059
Short name T786
Test name
Test status
Simulation time 37829425057 ps
CPU time 277.66 seconds
Started Jul 04 06:17:05 PM PDT 24
Finished Jul 04 06:21:43 PM PDT 24
Peak memory 267696 kb
Host smart-dd4d5cb5-7a71-4dd0-b37c-d8de57db496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471513059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3471513059
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1332643370
Short name T597
Test name
Test status
Simulation time 5432957559 ps
CPU time 46.8 seconds
Started Jul 04 06:17:06 PM PDT 24
Finished Jul 04 06:17:53 PM PDT 24
Peak memory 250388 kb
Host smart-46d501ab-6ec1-4e4c-84d5-1e97e124564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332643370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1332643370
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4009801521
Short name T194
Test name
Test status
Simulation time 49559669524 ps
CPU time 109.63 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:19:02 PM PDT 24
Peak memory 255088 kb
Host smart-ffa11371-19dd-480c-8c52-9d2ee91b2dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009801521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4009801521
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.134189063
Short name T376
Test name
Test status
Simulation time 1331076285 ps
CPU time 6 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:17:14 PM PDT 24
Peak memory 233840 kb
Host smart-40fc65eb-0232-4c5a-a1a1-e123cf338d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134189063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.134189063
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4101934232
Short name T263
Test name
Test status
Simulation time 54225047202 ps
CPU time 104.92 seconds
Started Jul 04 06:17:01 PM PDT 24
Finished Jul 04 06:18:46 PM PDT 24
Peak memory 274664 kb
Host smart-e0988069-6577-49b8-a235-8b9d86f17384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101934232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4101934232
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4275612437
Short name T626
Test name
Test status
Simulation time 3023829364 ps
CPU time 8.27 seconds
Started Jul 04 06:17:11 PM PDT 24
Finished Jul 04 06:17:20 PM PDT 24
Peak memory 220184 kb
Host smart-9680a3b8-ec3f-46bb-bf0f-2271670997c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275612437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4275612437
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1758975034
Short name T229
Test name
Test status
Simulation time 1383919056 ps
CPU time 9.72 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:24 PM PDT 24
Peak memory 225524 kb
Host smart-39eb42c2-5d90-4c8c-a7e6-0b2c7f4dc000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758975034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1758975034
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1572659631
Short name T74
Test name
Test status
Simulation time 226932911 ps
CPU time 1.07 seconds
Started Jul 04 06:17:04 PM PDT 24
Finished Jul 04 06:17:05 PM PDT 24
Peak memory 218980 kb
Host smart-f71d7fe5-ddbb-41b2-8f27-c3f20a9518e4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572659631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1572659631
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.583146314
Short name T415
Test name
Test status
Simulation time 10138555272 ps
CPU time 9.2 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:21 PM PDT 24
Peak memory 233880 kb
Host smart-78cd0832-d32b-4f9b-b6b6-66982aeac4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583146314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
583146314
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.638055638
Short name T849
Test name
Test status
Simulation time 2297802530 ps
CPU time 10.53 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:23 PM PDT 24
Peak memory 250420 kb
Host smart-0dd72e89-8399-4cf7-963e-71e2ecae18bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638055638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.638055638
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1308834052
Short name T86
Test name
Test status
Simulation time 581346020 ps
CPU time 5.9 seconds
Started Jul 04 06:17:02 PM PDT 24
Finished Jul 04 06:17:08 PM PDT 24
Peak memory 224012 kb
Host smart-2a3687fc-0e79-41c9-b135-b25d6b4f4dd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1308834052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1308834052
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1222336766
Short name T23
Test name
Test status
Simulation time 87879809 ps
CPU time 1.17 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:14 PM PDT 24
Peak memory 237452 kb
Host smart-751bf218-e4c4-4cac-b003-56ef6db7723d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222336766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1222336766
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2293745437
Short name T708
Test name
Test status
Simulation time 205733722524 ps
CPU time 523.07 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:25:56 PM PDT 24
Peak memory 266812 kb
Host smart-acbd8044-bbc9-49a0-9caa-46d5e91cff6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293745437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2293745437
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1457462167
Short name T680
Test name
Test status
Simulation time 2502687930 ps
CPU time 5.25 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 217508 kb
Host smart-4beb538a-5bbc-469b-b192-b720197fc0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457462167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1457462167
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3634471239
Short name T385
Test name
Test status
Simulation time 23839888517 ps
CPU time 16.26 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:29 PM PDT 24
Peak memory 218688 kb
Host smart-2aaf2bc3-3733-4379-84bc-a98d9a5ebe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634471239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3634471239
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1197627477
Short name T469
Test name
Test status
Simulation time 963677322 ps
CPU time 1.81 seconds
Started Jul 04 06:17:05 PM PDT 24
Finished Jul 04 06:17:07 PM PDT 24
Peak memory 217380 kb
Host smart-c3bc879d-48e6-4dfb-ad65-5cf89b86961e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197627477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1197627477
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.668779087
Short name T666
Test name
Test status
Simulation time 40480522 ps
CPU time 0.84 seconds
Started Jul 04 06:17:07 PM PDT 24
Finished Jul 04 06:17:08 PM PDT 24
Peak memory 206984 kb
Host smart-71527210-b820-4b09-a2b5-620a3786f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668779087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.668779087
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3532863680
Short name T265
Test name
Test status
Simulation time 3544142873 ps
CPU time 13.72 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:17:28 PM PDT 24
Peak memory 242044 kb
Host smart-cb90e44d-2ada-4188-9643-f065271b0953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532863680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3532863680
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1207599142
Short name T353
Test name
Test status
Simulation time 29680450 ps
CPU time 0.7 seconds
Started Jul 04 06:19:15 PM PDT 24
Finished Jul 04 06:19:16 PM PDT 24
Peak memory 205800 kb
Host smart-ec5ef30f-726c-4dc4-9c01-8d30f4222226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207599142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1207599142
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3135669944
Short name T84
Test name
Test status
Simulation time 4441643357 ps
CPU time 20.61 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:35 PM PDT 24
Peak memory 225656 kb
Host smart-25e2bf67-a9fb-4da3-b1c4-fbffdc659d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135669944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3135669944
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1325259546
Short name T10
Test name
Test status
Simulation time 38508849 ps
CPU time 0.81 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:16 PM PDT 24
Peak memory 207896 kb
Host smart-5f84530e-8931-4c87-aeed-e8a5ea248a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325259546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1325259546
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2602597092
Short name T190
Test name
Test status
Simulation time 16630619895 ps
CPU time 64.99 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:20:20 PM PDT 24
Peak memory 228144 kb
Host smart-e1727d46-449a-4187-bb12-059bab98a7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602597092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2602597092
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1018777734
Short name T607
Test name
Test status
Simulation time 27246337884 ps
CPU time 31.65 seconds
Started Jul 04 06:19:15 PM PDT 24
Finished Jul 04 06:19:47 PM PDT 24
Peak memory 238336 kb
Host smart-7c4aaeb9-99fd-4840-b0fc-328305662ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018777734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1018777734
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2132244554
Short name T854
Test name
Test status
Simulation time 113429765097 ps
CPU time 255.39 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:23:30 PM PDT 24
Peak memory 268980 kb
Host smart-6378f77e-e136-4033-b547-514a35bb8ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132244554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2132244554
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.835865241
Short name T307
Test name
Test status
Simulation time 850946105 ps
CPU time 11.74 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:26 PM PDT 24
Peak memory 225612 kb
Host smart-c2ae22ea-37a4-425a-a703-6821898deb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835865241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.835865241
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.977962292
Short name T179
Test name
Test status
Simulation time 27964817676 ps
CPU time 106.26 seconds
Started Jul 04 06:19:15 PM PDT 24
Finished Jul 04 06:21:01 PM PDT 24
Peak memory 249992 kb
Host smart-a7269655-137e-457c-b7a2-3344f360c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977962292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.977962292
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2227085678
Short name T747
Test name
Test status
Simulation time 201306963 ps
CPU time 4.68 seconds
Started Jul 04 06:19:13 PM PDT 24
Finished Jul 04 06:19:18 PM PDT 24
Peak memory 225612 kb
Host smart-7f58a118-52b1-4b0b-bede-cbc3c0a80cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227085678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2227085678
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1408763616
Short name T668
Test name
Test status
Simulation time 19733858462 ps
CPU time 38.46 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:56 PM PDT 24
Peak memory 225696 kb
Host smart-9e2aef37-13e1-4f40-92b4-d9ef26ac104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408763616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1408763616
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3666129285
Short name T270
Test name
Test status
Simulation time 23037723610 ps
CPU time 17.75 seconds
Started Jul 04 06:19:13 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 233956 kb
Host smart-390c71d6-0417-4a95-a255-d6a065ee7efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666129285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3666129285
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2836685829
Short name T681
Test name
Test status
Simulation time 169234203 ps
CPU time 3.11 seconds
Started Jul 04 06:19:16 PM PDT 24
Finished Jul 04 06:19:20 PM PDT 24
Peak memory 225508 kb
Host smart-4e2683e5-8206-4ce0-8648-c9cb0379d304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836685829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2836685829
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.993911064
Short name T565
Test name
Test status
Simulation time 4423185414 ps
CPU time 8.83 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:23 PM PDT 24
Peak memory 221720 kb
Host smart-c9833a5e-1552-47ce-b248-091067c4ca5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=993911064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.993911064
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.158140308
Short name T960
Test name
Test status
Simulation time 17220703399 ps
CPU time 172.11 seconds
Started Jul 04 06:19:15 PM PDT 24
Finished Jul 04 06:22:08 PM PDT 24
Peak memory 252892 kb
Host smart-3a616155-70f9-423d-b7d6-9782863a297b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158140308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.158140308
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1030591199
Short name T924
Test name
Test status
Simulation time 2320029699 ps
CPU time 17.17 seconds
Started Jul 04 06:19:13 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 217440 kb
Host smart-0c066f4c-8e56-49c1-87e1-d195b2a12725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030591199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1030591199
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3332163199
Short name T326
Test name
Test status
Simulation time 1923609969 ps
CPU time 9.38 seconds
Started Jul 04 06:19:15 PM PDT 24
Finished Jul 04 06:19:25 PM PDT 24
Peak memory 217324 kb
Host smart-c617fbad-88a0-48da-a9cc-4c38f28a68d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332163199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3332163199
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3606312762
Short name T730
Test name
Test status
Simulation time 702034138 ps
CPU time 1.54 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:16 PM PDT 24
Peak memory 217340 kb
Host smart-a1cfeef9-e7fd-43e5-8476-ecf3565caa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606312762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3606312762
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3463675688
Short name T586
Test name
Test status
Simulation time 42579362 ps
CPU time 0.83 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:15 PM PDT 24
Peak memory 207008 kb
Host smart-a5ef2cce-6f71-49c6-bfde-9fc459a752b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463675688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3463675688
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1653404219
Short name T584
Test name
Test status
Simulation time 421700909 ps
CPU time 2.37 seconds
Started Jul 04 06:19:14 PM PDT 24
Finished Jul 04 06:19:17 PM PDT 24
Peak memory 224948 kb
Host smart-f6f664f7-a2e2-49a2-871f-390c6eb6b34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653404219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1653404219
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3831572318
Short name T559
Test name
Test status
Simulation time 42028962 ps
CPU time 0.79 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:19:30 PM PDT 24
Peak memory 206336 kb
Host smart-f0e559ff-cd1c-44ff-9c7b-af4664a85690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831572318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3831572318
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1667068566
Short name T947
Test name
Test status
Simulation time 40891159 ps
CPU time 2.21 seconds
Started Jul 04 06:19:19 PM PDT 24
Finished Jul 04 06:19:21 PM PDT 24
Peak memory 225496 kb
Host smart-dc6b3343-0df0-4a1b-b0a8-7517ec76d45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667068566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1667068566
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1427425237
Short name T519
Test name
Test status
Simulation time 27571851 ps
CPU time 0.76 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:18 PM PDT 24
Peak memory 207524 kb
Host smart-362e87e9-1a46-4a53-94a5-9e6b6ffe08ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427425237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1427425237
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1940681957
Short name T739
Test name
Test status
Simulation time 10654662 ps
CPU time 0.74 seconds
Started Jul 04 06:19:19 PM PDT 24
Finished Jul 04 06:19:20 PM PDT 24
Peak memory 216868 kb
Host smart-42aae24e-48ff-4cc2-8c43-1047be4a2b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940681957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1940681957
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.429466124
Short name T789
Test name
Test status
Simulation time 19358773207 ps
CPU time 151.97 seconds
Started Jul 04 06:19:21 PM PDT 24
Finished Jul 04 06:21:54 PM PDT 24
Peak memory 256084 kb
Host smart-07fb6e27-2b82-4ead-9b62-378028e71f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429466124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.429466124
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1873953194
Short name T296
Test name
Test status
Simulation time 110443910292 ps
CPU time 477.14 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:27:24 PM PDT 24
Peak memory 267512 kb
Host smart-7c46b785-8152-4b8f-bd61-6ec7cbf668e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873953194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1873953194
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.420962073
Short name T667
Test name
Test status
Simulation time 23165775597 ps
CPU time 47.06 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:20:05 PM PDT 24
Peak memory 242076 kb
Host smart-75c652ad-9605-453c-9b7d-764771e516f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420962073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.420962073
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3699136759
Short name T227
Test name
Test status
Simulation time 1352993109 ps
CPU time 5.34 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:22 PM PDT 24
Peak memory 233764 kb
Host smart-5b4d1d2d-7ae9-484a-b242-2119a0f1dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699136759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3699136759
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.630178031
Short name T19
Test name
Test status
Simulation time 1413150968 ps
CPU time 10.36 seconds
Started Jul 04 06:19:18 PM PDT 24
Finished Jul 04 06:19:28 PM PDT 24
Peak memory 233808 kb
Host smart-e1c00cfd-35a6-4bed-a301-d1dcf883b765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630178031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.630178031
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4150728405
Short name T276
Test name
Test status
Simulation time 4588259648 ps
CPU time 5.37 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:23 PM PDT 24
Peak memory 225728 kb
Host smart-9d326e4f-4e33-406d-b068-05c09c9732d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150728405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4150728405
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3429749094
Short name T637
Test name
Test status
Simulation time 159378166943 ps
CPU time 29.06 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:46 PM PDT 24
Peak memory 250896 kb
Host smart-5c554fe4-e417-4f89-9fa5-0bb9c0a4866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429749094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3429749094
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.373521113
Short name T1
Test name
Test status
Simulation time 1176294100 ps
CPU time 4.55 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:22 PM PDT 24
Peak memory 219808 kb
Host smart-f611e071-6d0a-44c2-a8f5-a28deae3bb8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=373521113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.373521113
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.566108943
Short name T151
Test name
Test status
Simulation time 43016344833 ps
CPU time 440.68 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:26:50 PM PDT 24
Peak memory 268220 kb
Host smart-1aaa3dd5-ffff-4a63-b086-64fcca61524e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566108943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.566108943
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.965697252
Short name T25
Test name
Test status
Simulation time 348845038 ps
CPU time 2.52 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:20 PM PDT 24
Peak memory 217376 kb
Host smart-40e924d1-c980-4730-9d9a-e53813d72a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965697252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.965697252
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2098298352
Short name T759
Test name
Test status
Simulation time 5520206316 ps
CPU time 11.07 seconds
Started Jul 04 06:19:15 PM PDT 24
Finished Jul 04 06:19:27 PM PDT 24
Peak memory 217488 kb
Host smart-09038169-1a43-4f38-b087-74f1a61c7d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098298352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2098298352
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1457038018
Short name T536
Test name
Test status
Simulation time 330511763 ps
CPU time 3 seconds
Started Jul 04 06:19:18 PM PDT 24
Finished Jul 04 06:19:21 PM PDT 24
Peak memory 217396 kb
Host smart-36df045b-8ef9-4a34-8054-b77c16b3e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457038018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1457038018
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2385250075
Short name T707
Test name
Test status
Simulation time 142708446 ps
CPU time 0.88 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:19 PM PDT 24
Peak memory 208016 kb
Host smart-c15ba79c-1b87-4972-9e9b-f6942401daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385250075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2385250075
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3443231405
Short name T168
Test name
Test status
Simulation time 431442358 ps
CPU time 7.2 seconds
Started Jul 04 06:19:17 PM PDT 24
Finished Jul 04 06:19:25 PM PDT 24
Peak memory 225608 kb
Host smart-410ab81c-14b3-49b6-9b98-b81e46bdc121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443231405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3443231405
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1647120877
Short name T462
Test name
Test status
Simulation time 40987690 ps
CPU time 0.71 seconds
Started Jul 04 06:19:22 PM PDT 24
Finished Jul 04 06:19:23 PM PDT 24
Peak memory 206360 kb
Host smart-80c185b7-57e5-4ec8-ba50-55206e5cd911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647120877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1647120877
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3731808911
Short name T497
Test name
Test status
Simulation time 343243111 ps
CPU time 2.12 seconds
Started Jul 04 06:19:21 PM PDT 24
Finished Jul 04 06:19:24 PM PDT 24
Peak memory 225608 kb
Host smart-2246b4ad-a420-4f1c-ab0e-a340f37a6db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731808911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3731808911
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4079041686
Short name T768
Test name
Test status
Simulation time 52261205 ps
CPU time 0.82 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 207796 kb
Host smart-696ad0f1-a643-4633-96e1-4769ac9890e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079041686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4079041686
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.637620154
Short name T465
Test name
Test status
Simulation time 95036266818 ps
CPU time 149.56 seconds
Started Jul 04 06:19:24 PM PDT 24
Finished Jul 04 06:21:54 PM PDT 24
Peak memory 250772 kb
Host smart-6626b1aa-330a-41c3-a421-c7946642fa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637620154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.637620154
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.222255959
Short name T200
Test name
Test status
Simulation time 27696803454 ps
CPU time 155.71 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:22:02 PM PDT 24
Peak memory 250368 kb
Host smart-03626c2a-a35f-46f8-87d6-bc8cf89a4e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222255959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.222255959
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2660195402
Short name T910
Test name
Test status
Simulation time 39108432456 ps
CPU time 160.68 seconds
Started Jul 04 06:19:20 PM PDT 24
Finished Jul 04 06:22:01 PM PDT 24
Peak memory 267844 kb
Host smart-3ac7e52a-2f19-415a-8035-d75a9d6d23bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660195402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2660195402
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1728486386
Short name T470
Test name
Test status
Simulation time 2750217280 ps
CPU time 5 seconds
Started Jul 04 06:19:24 PM PDT 24
Finished Jul 04 06:19:30 PM PDT 24
Peak memory 234992 kb
Host smart-529ba845-e603-4637-afbe-2f4b3b25f31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728486386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1728486386
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2598708631
Short name T725
Test name
Test status
Simulation time 238496442514 ps
CPU time 132 seconds
Started Jul 04 06:19:22 PM PDT 24
Finished Jul 04 06:21:35 PM PDT 24
Peak memory 257060 kb
Host smart-583f341d-2a82-439a-8f67-2720cc4ae431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598708631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2598708631
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1857401557
Short name T184
Test name
Test status
Simulation time 1286659253 ps
CPU time 12.13 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:19:38 PM PDT 24
Peak memory 233800 kb
Host smart-040e75cd-e835-4c3d-a2c3-bedca6911ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857401557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1857401557
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.80817430
Short name T255
Test name
Test status
Simulation time 674899000 ps
CPU time 3.87 seconds
Started Jul 04 06:19:23 PM PDT 24
Finished Jul 04 06:19:27 PM PDT 24
Peak memory 233828 kb
Host smart-e5f8c99b-2c7f-4723-b0b8-d0f4915c3433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80817430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.80817430
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3787525813
Short name T533
Test name
Test status
Simulation time 395355633 ps
CPU time 4.52 seconds
Started Jul 04 06:19:20 PM PDT 24
Finished Jul 04 06:19:25 PM PDT 24
Peak memory 233812 kb
Host smart-32ddb842-aa05-45b7-a9f2-2d5ef2920e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787525813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3787525813
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.190156209
Short name T191
Test name
Test status
Simulation time 423825773 ps
CPU time 4.72 seconds
Started Jul 04 06:19:24 PM PDT 24
Finished Jul 04 06:19:30 PM PDT 24
Peak memory 241736 kb
Host smart-90daaad2-9a63-4211-aaff-65b361064bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190156209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.190156209
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2632582181
Short name T624
Test name
Test status
Simulation time 210202609 ps
CPU time 4.76 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 223940 kb
Host smart-660849a3-70c4-48bc-abb0-0e0a2342c913
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2632582181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2632582181
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2761624323
Short name T50
Test name
Test status
Simulation time 52435409531 ps
CPU time 321.91 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:24:48 PM PDT 24
Peak memory 274056 kb
Host smart-7799a662-3a70-491c-a7fd-615c4a3d7bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761624323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2761624323
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1803286590
Short name T920
Test name
Test status
Simulation time 973849546 ps
CPU time 8.3 seconds
Started Jul 04 06:19:25 PM PDT 24
Finished Jul 04 06:19:34 PM PDT 24
Peak memory 220632 kb
Host smart-736087c0-785a-4cf7-890e-270b577c8ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803286590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1803286590
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4066351010
Short name T437
Test name
Test status
Simulation time 1111723247 ps
CPU time 4.61 seconds
Started Jul 04 06:19:23 PM PDT 24
Finished Jul 04 06:19:28 PM PDT 24
Peak memory 217128 kb
Host smart-e564f62b-bc06-466a-b29b-809a333c16cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066351010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4066351010
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4136626997
Short name T912
Test name
Test status
Simulation time 292360808 ps
CPU time 5.09 seconds
Started Jul 04 06:19:22 PM PDT 24
Finished Jul 04 06:19:28 PM PDT 24
Peak memory 217404 kb
Host smart-a85de3f2-50fe-4609-9841-1e9817c7bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136626997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4136626997
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.760017111
Short name T718
Test name
Test status
Simulation time 18922418 ps
CPU time 0.74 seconds
Started Jul 04 06:19:22 PM PDT 24
Finished Jul 04 06:19:23 PM PDT 24
Peak memory 207004 kb
Host smart-193ae36a-2a7b-4c29-b658-d7d78c360edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760017111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.760017111
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2859948281
Short name T926
Test name
Test status
Simulation time 857974823 ps
CPU time 6.97 seconds
Started Jul 04 06:19:29 PM PDT 24
Finished Jul 04 06:19:37 PM PDT 24
Peak memory 222392 kb
Host smart-8dca80dc-004d-4f97-9056-993526f9a1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859948281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2859948281
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.98179880
Short name T723
Test name
Test status
Simulation time 57895738 ps
CPU time 0.73 seconds
Started Jul 04 06:19:32 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 206332 kb
Host smart-14b07036-b985-435a-a091-e432a6351426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98179880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.98179880
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1915897691
Short name T596
Test name
Test status
Simulation time 471536190 ps
CPU time 2.47 seconds
Started Jul 04 06:19:23 PM PDT 24
Finished Jul 04 06:19:26 PM PDT 24
Peak memory 225544 kb
Host smart-22cb8cb0-d476-4acc-b16d-c5d18148aca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915897691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1915897691
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4246749354
Short name T13
Test name
Test status
Simulation time 20968162 ps
CPU time 0.82 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:19:27 PM PDT 24
Peak memory 207532 kb
Host smart-98ab36a0-8f04-418d-921d-17bdad4219ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246749354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4246749354
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2795220542
Short name T187
Test name
Test status
Simulation time 43976749723 ps
CPU time 227.47 seconds
Started Jul 04 06:19:24 PM PDT 24
Finished Jul 04 06:23:11 PM PDT 24
Peak memory 281656 kb
Host smart-ab2f26c4-3a44-477b-9cda-86819da66f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795220542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2795220542
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.648732710
Short name T252
Test name
Test status
Simulation time 40935752833 ps
CPU time 151.68 seconds
Started Jul 04 06:19:21 PM PDT 24
Finished Jul 04 06:21:53 PM PDT 24
Peak memory 255448 kb
Host smart-4e25d5f0-087a-4201-ba0f-8975386ceef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648732710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.648732710
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3985497899
Short name T382
Test name
Test status
Simulation time 18912972616 ps
CPU time 137.39 seconds
Started Jul 04 06:19:31 PM PDT 24
Finished Jul 04 06:21:49 PM PDT 24
Peak memory 240660 kb
Host smart-0273a58a-67af-4a67-8893-5b0274faa1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985497899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3985497899
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1442094842
Short name T790
Test name
Test status
Simulation time 380239206 ps
CPU time 4.92 seconds
Started Jul 04 06:19:25 PM PDT 24
Finished Jul 04 06:19:30 PM PDT 24
Peak memory 231128 kb
Host smart-8b8bf4ce-f71d-49e9-b429-d2a18edfda45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442094842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1442094842
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2043020779
Short name T949
Test name
Test status
Simulation time 71059167801 ps
CPU time 63.22 seconds
Started Jul 04 06:19:22 PM PDT 24
Finished Jul 04 06:20:25 PM PDT 24
Peak memory 234008 kb
Host smart-32e6959d-c038-4d4d-bf90-c97beaa461c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043020779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2043020779
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.976499018
Short name T215
Test name
Test status
Simulation time 1221159398 ps
CPU time 13.36 seconds
Started Jul 04 06:19:24 PM PDT 24
Finished Jul 04 06:19:37 PM PDT 24
Peak memory 233764 kb
Host smart-5f8fe568-05ab-4641-9476-9a953e8252c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976499018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.976499018
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1355111306
Short name T871
Test name
Test status
Simulation time 280939505 ps
CPU time 2.17 seconds
Started Jul 04 06:19:21 PM PDT 24
Finished Jul 04 06:19:23 PM PDT 24
Peak memory 225224 kb
Host smart-4361100c-87cf-4e25-b7b1-8c98992463da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355111306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1355111306
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3295156982
Short name T472
Test name
Test status
Simulation time 1949926883 ps
CPU time 6.76 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 225564 kb
Host smart-0b1e3971-5b29-4341-8248-adeeed32d504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295156982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3295156982
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1249273405
Short name T611
Test name
Test status
Simulation time 35269523 ps
CPU time 2.41 seconds
Started Jul 04 06:19:22 PM PDT 24
Finished Jul 04 06:19:25 PM PDT 24
Peak memory 233484 kb
Host smart-7291c654-4b52-4ddb-bd1d-7bf6d0018212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249273405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1249273405
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4201323823
Short name T785
Test name
Test status
Simulation time 1996474201 ps
CPU time 11.87 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:19:38 PM PDT 24
Peak memory 221508 kb
Host smart-636e2a5f-eebc-4656-a880-81ff6ec44813
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201323823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4201323823
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.561921311
Short name T741
Test name
Test status
Simulation time 23073515848 ps
CPU time 41.09 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:20:09 PM PDT 24
Peak memory 242208 kb
Host smart-f4dea8ef-560c-4ba9-b8db-22d02b53fe58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561921311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.561921311
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.421629169
Short name T56
Test name
Test status
Simulation time 55926716652 ps
CPU time 22.33 seconds
Started Jul 04 06:19:22 PM PDT 24
Finished Jul 04 06:19:45 PM PDT 24
Peak memory 217484 kb
Host smart-b982859d-2747-4898-8972-fe265cae8e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421629169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.421629169
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2811877632
Short name T905
Test name
Test status
Simulation time 1018017838 ps
CPU time 3.19 seconds
Started Jul 04 06:19:25 PM PDT 24
Finished Jul 04 06:19:29 PM PDT 24
Peak memory 217288 kb
Host smart-f7cd2c56-dd85-4736-9b3b-e740ecc8b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811877632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2811877632
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.686615234
Short name T933
Test name
Test status
Simulation time 44101183 ps
CPU time 0.86 seconds
Started Jul 04 06:19:24 PM PDT 24
Finished Jul 04 06:19:25 PM PDT 24
Peak memory 207616 kb
Host smart-88914938-0d3b-475a-b300-5699b1776808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686615234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.686615234
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1688664988
Short name T130
Test name
Test status
Simulation time 13302858 ps
CPU time 0.69 seconds
Started Jul 04 06:19:31 PM PDT 24
Finished Jul 04 06:19:32 PM PDT 24
Peak memory 206504 kb
Host smart-53739e25-19b6-4ee6-82e1-4dcaaa0ff82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688664988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1688664988
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3932298503
Short name T692
Test name
Test status
Simulation time 4603202574 ps
CPU time 4.38 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 225756 kb
Host smart-7abcb861-6774-4478-9a73-93984685d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932298503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3932298503
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2074499435
Short name T940
Test name
Test status
Simulation time 14970725 ps
CPU time 0.68 seconds
Started Jul 04 06:19:29 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 206728 kb
Host smart-1cf94010-a26a-4d0c-bfeb-22f1f7402a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074499435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2074499435
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.28997402
Short name T1022
Test name
Test status
Simulation time 321067310 ps
CPU time 2.13 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 225488 kb
Host smart-2cf5c9f7-c181-4d11-bceb-79d0b8cee7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28997402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.28997402
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.713946009
Short name T1010
Test name
Test status
Simulation time 16413278 ps
CPU time 0.8 seconds
Started Jul 04 06:19:20 PM PDT 24
Finished Jul 04 06:19:21 PM PDT 24
Peak memory 207524 kb
Host smart-82e73a1f-869f-4fdd-b490-72e15162cb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713946009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.713946009
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3188678816
Short name T417
Test name
Test status
Simulation time 18096371391 ps
CPU time 68.75 seconds
Started Jul 04 06:19:23 PM PDT 24
Finished Jul 04 06:20:32 PM PDT 24
Peak memory 235664 kb
Host smart-6c300b6a-1eff-467e-aa51-90b1d7e00bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188678816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3188678816
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3771525273
Short name T782
Test name
Test status
Simulation time 11236946104 ps
CPU time 81.77 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:20:50 PM PDT 24
Peak memory 239512 kb
Host smart-46c6324a-56f8-49e6-af94-38af0862f8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771525273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3771525273
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.116985314
Short name T202
Test name
Test status
Simulation time 23868054318 ps
CPU time 273.26 seconds
Started Jul 04 06:19:29 PM PDT 24
Finished Jul 04 06:24:02 PM PDT 24
Peak memory 252688 kb
Host smart-3873dc78-9ded-4b18-8bb6-97e929e0040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116985314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.116985314
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4053104750
Short name T11
Test name
Test status
Simulation time 249161858 ps
CPU time 5.54 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:19:32 PM PDT 24
Peak memory 233832 kb
Host smart-973274be-c3dd-49be-af9e-a7ad5f0f95de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053104750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4053104750
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1529448544
Short name T805
Test name
Test status
Simulation time 26131994239 ps
CPU time 60.15 seconds
Started Jul 04 06:19:23 PM PDT 24
Finished Jul 04 06:20:23 PM PDT 24
Peak memory 241912 kb
Host smart-0b31293a-6707-40f8-ad83-bbd6e06607f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529448544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1529448544
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2107565669
Short name T256
Test name
Test status
Simulation time 9766698636 ps
CPU time 25.86 seconds
Started Jul 04 06:19:20 PM PDT 24
Finished Jul 04 06:19:46 PM PDT 24
Peak memory 233928 kb
Host smart-f20fdd3a-88ed-4dbe-8850-fc83bdf1f25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107565669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2107565669
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3043236760
Short name T980
Test name
Test status
Simulation time 1129596831 ps
CPU time 8.3 seconds
Started Jul 04 06:19:25 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 233728 kb
Host smart-5c96f43a-e62b-4676-bf61-c1b8e21f933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043236760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3043236760
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1730477657
Short name T272
Test name
Test status
Simulation time 715047110 ps
CPU time 7.33 seconds
Started Jul 04 06:19:25 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 225512 kb
Host smart-04a4a93f-5890-4370-b791-337feb368fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730477657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1730477657
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3745589049
Short name T897
Test name
Test status
Simulation time 2077869871 ps
CPU time 6.62 seconds
Started Jul 04 06:19:26 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 233780 kb
Host smart-8d99a125-2b77-4521-bc89-24e71c1a1b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745589049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3745589049
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1263595383
Short name T144
Test name
Test status
Simulation time 687572511 ps
CPU time 6.58 seconds
Started Jul 04 06:19:32 PM PDT 24
Finished Jul 04 06:19:39 PM PDT 24
Peak memory 222524 kb
Host smart-1e1b5eb7-835b-4587-a4ad-609f5ab5dc6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1263595383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1263595383
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3732022268
Short name T968
Test name
Test status
Simulation time 176097675 ps
CPU time 0.93 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 207852 kb
Host smart-a9e14c3c-4159-4515-a572-ec156aea56a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732022268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3732022268
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.661842818
Short name T15
Test name
Test status
Simulation time 1785458123 ps
CPU time 10.9 seconds
Started Jul 04 06:19:25 PM PDT 24
Finished Jul 04 06:19:36 PM PDT 24
Peak memory 217348 kb
Host smart-72e852e0-4595-4c37-a4dc-0b6bc886f715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661842818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.661842818
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.859104440
Short name T530
Test name
Test status
Simulation time 262009081 ps
CPU time 1.7 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 208900 kb
Host smart-0dfc9008-99ec-4dc6-abc7-c4612a30629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859104440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.859104440
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3768432219
Short name T428
Test name
Test status
Simulation time 189708050 ps
CPU time 2.27 seconds
Started Jul 04 06:19:20 PM PDT 24
Finished Jul 04 06:19:23 PM PDT 24
Peak memory 217376 kb
Host smart-51be2187-1558-461c-8f41-d59419ce3bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768432219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3768432219
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3559273536
Short name T974
Test name
Test status
Simulation time 56622215 ps
CPU time 0.98 seconds
Started Jul 04 06:19:23 PM PDT 24
Finished Jul 04 06:19:24 PM PDT 24
Peak memory 208020 kb
Host smart-4c8405d9-ecb8-4f17-b6f2-5548dd7a19a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559273536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3559273536
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.302721673
Short name T881
Test name
Test status
Simulation time 115062165 ps
CPU time 2.74 seconds
Started Jul 04 06:19:25 PM PDT 24
Finished Jul 04 06:19:29 PM PDT 24
Peak memory 225564 kb
Host smart-135d3fcf-3be2-4d68-b983-8d67a72e19a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302721673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.302721673
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2749497505
Short name T488
Test name
Test status
Simulation time 48140784 ps
CPU time 0.71 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:19:29 PM PDT 24
Peak memory 206300 kb
Host smart-0e19cc21-917c-4aec-aa37-3bf12fcb46f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749497505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2749497505
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1724091878
Short name T436
Test name
Test status
Simulation time 1033018287 ps
CPU time 11.33 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:42 PM PDT 24
Peak memory 233692 kb
Host smart-245fe17c-7661-40fb-a006-3f046105b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724091878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1724091878
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3266987586
Short name T389
Test name
Test status
Simulation time 39689278 ps
CPU time 0.84 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 207548 kb
Host smart-b42aa162-aa73-41ab-a092-ba21dc63d246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266987586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3266987586
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2869110120
Short name T925
Test name
Test status
Simulation time 8633905377 ps
CPU time 45.58 seconds
Started Jul 04 06:19:27 PM PDT 24
Finished Jul 04 06:20:13 PM PDT 24
Peak memory 250324 kb
Host smart-26fe86cc-93e7-473a-ad22-595f366bfc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869110120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2869110120
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3362638346
Short name T606
Test name
Test status
Simulation time 58834420982 ps
CPU time 196.59 seconds
Started Jul 04 06:19:32 PM PDT 24
Finished Jul 04 06:22:49 PM PDT 24
Peak memory 255476 kb
Host smart-3a86d373-f885-4272-959f-af55e3f9c7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362638346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3362638346
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3256090240
Short name T183
Test name
Test status
Simulation time 52718808399 ps
CPU time 207.88 seconds
Started Jul 04 06:19:29 PM PDT 24
Finished Jul 04 06:22:58 PM PDT 24
Peak memory 282688 kb
Host smart-585f4b61-1dc4-4f7c-82d0-726a9b505296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256090240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3256090240
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2876010812
Short name T308
Test name
Test status
Simulation time 1952259673 ps
CPU time 19.31 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:49 PM PDT 24
Peak memory 235872 kb
Host smart-886dae0b-0453-4123-957e-248c7c027362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876010812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2876010812
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.4022565927
Short name T495
Test name
Test status
Simulation time 116933804365 ps
CPU time 211.54 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:23:02 PM PDT 24
Peak memory 251588 kb
Host smart-339593a3-e77a-49c4-bbe9-e7555880f078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022565927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.4022565927
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2988796220
Short name T661
Test name
Test status
Simulation time 960754035 ps
CPU time 5.62 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:19:34 PM PDT 24
Peak memory 225520 kb
Host smart-fcbdfe1c-d3a9-4615-8b4f-0537bca4d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988796220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2988796220
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.288995261
Short name T277
Test name
Test status
Simulation time 1431903944 ps
CPU time 14.26 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:19:43 PM PDT 24
Peak memory 233792 kb
Host smart-99cc6bc6-0e6e-41b2-b8d0-52e2f9bdf4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288995261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.288995261
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1536087442
Short name T658
Test name
Test status
Simulation time 426367216 ps
CPU time 3.59 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:34 PM PDT 24
Peak memory 233076 kb
Host smart-0e40c93b-4e86-4a89-9947-319b7e2ef86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536087442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1536087442
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.733370560
Short name T797
Test name
Test status
Simulation time 1010432435 ps
CPU time 8.61 seconds
Started Jul 04 06:19:29 PM PDT 24
Finished Jul 04 06:19:38 PM PDT 24
Peak memory 233824 kb
Host smart-0e22aad9-33b3-4e05-a0ee-627db4370f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733370560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.733370560
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1997183910
Short name T811
Test name
Test status
Simulation time 918357071 ps
CPU time 4.23 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 220248 kb
Host smart-5c3b6f29-2509-4da4-808d-d5cac9fe5e06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1997183910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1997183910
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3501445701
Short name T639
Test name
Test status
Simulation time 57879020 ps
CPU time 1.02 seconds
Started Jul 04 06:19:32 PM PDT 24
Finished Jul 04 06:19:33 PM PDT 24
Peak memory 207524 kb
Host smart-f27994db-54a5-461f-bfdd-b96ee73abe43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501445701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3501445701
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4110149845
Short name T1014
Test name
Test status
Simulation time 6283854346 ps
CPU time 11.28 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:42 PM PDT 24
Peak memory 220712 kb
Host smart-9b8f2814-a3fa-4c47-9e5d-a1e781183b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110149845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4110149845
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3607425460
Short name T1005
Test name
Test status
Simulation time 22485331167 ps
CPU time 9.59 seconds
Started Jul 04 06:19:29 PM PDT 24
Finished Jul 04 06:19:39 PM PDT 24
Peak memory 217496 kb
Host smart-624d0d21-7f7e-468b-aef2-c7b2c3f04484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607425460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3607425460
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.689467815
Short name T705
Test name
Test status
Simulation time 90968178 ps
CPU time 1.62 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:32 PM PDT 24
Peak memory 217376 kb
Host smart-641fff9a-bd81-4dda-986c-162f885f621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689467815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.689467815
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.31799856
Short name T379
Test name
Test status
Simulation time 31415803 ps
CPU time 0.78 seconds
Started Jul 04 06:19:29 PM PDT 24
Finished Jul 04 06:19:30 PM PDT 24
Peak memory 206980 kb
Host smart-f06970e3-88e1-402a-8831-e76e31264055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31799856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.31799856
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1235484831
Short name T591
Test name
Test status
Simulation time 3706771218 ps
CPU time 12.77 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:44 PM PDT 24
Peak memory 233812 kb
Host smart-b4fb247c-38dc-43de-bb3e-e113f9ce3173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235484831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1235484831
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1208454905
Short name T617
Test name
Test status
Simulation time 21391306 ps
CPU time 0.7 seconds
Started Jul 04 06:19:41 PM PDT 24
Finished Jul 04 06:19:42 PM PDT 24
Peak memory 205796 kb
Host smart-c870d1c1-4eb6-4f46-8abb-e6b40dbbe1db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208454905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1208454905
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.767347857
Short name T551
Test name
Test status
Simulation time 593186099 ps
CPU time 8.76 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:49 PM PDT 24
Peak memory 225596 kb
Host smart-d3af9efa-b1e1-4894-b496-2e79ddab76c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767347857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.767347857
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3835818231
Short name T648
Test name
Test status
Simulation time 13903304 ps
CPU time 0.83 seconds
Started Jul 04 06:19:33 PM PDT 24
Finished Jul 04 06:19:34 PM PDT 24
Peak memory 207528 kb
Host smart-9ac5fbeb-67af-4ade-ac51-df7fe4399a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835818231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3835818231
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1475704685
Short name T651
Test name
Test status
Simulation time 293687530 ps
CPU time 8.75 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:19:47 PM PDT 24
Peak memory 241948 kb
Host smart-ade1bbec-e2ab-4603-8f06-a9bd001f5075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475704685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1475704685
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1285652232
Short name T729
Test name
Test status
Simulation time 150460030192 ps
CPU time 101.55 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:21:19 PM PDT 24
Peak memory 249484 kb
Host smart-f00604c1-b52b-4113-b9c8-f23d280c1235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285652232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1285652232
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.436095184
Short name T975
Test name
Test status
Simulation time 1269221645 ps
CPU time 20.67 seconds
Started Jul 04 06:19:40 PM PDT 24
Finished Jul 04 06:20:01 PM PDT 24
Peak memory 241964 kb
Host smart-d9718be3-36d5-444d-a716-52ee4abd6cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436095184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.436095184
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2261375187
Short name T346
Test name
Test status
Simulation time 52814466 ps
CPU time 0.75 seconds
Started Jul 04 06:19:36 PM PDT 24
Finished Jul 04 06:19:37 PM PDT 24
Peak memory 216948 kb
Host smart-747a352c-0a68-4c81-b96e-34a6a9a8e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261375187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2261375187
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1997092491
Short name T880
Test name
Test status
Simulation time 8427702198 ps
CPU time 16.67 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:47 PM PDT 24
Peak memory 233352 kb
Host smart-89bc9d06-9aa9-4b1d-87b7-9d566f69c641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997092491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1997092491
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3658827497
Short name T682
Test name
Test status
Simulation time 1524082652 ps
CPU time 7.82 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:38 PM PDT 24
Peak memory 225560 kb
Host smart-9f95e7ce-3f65-4690-b62e-c548ebfe35a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658827497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3658827497
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2252054990
Short name T269
Test name
Test status
Simulation time 45785085 ps
CPU time 2.7 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:19:31 PM PDT 24
Peak memory 233792 kb
Host smart-2793c689-bfee-4eea-af2b-afaded3a10f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252054990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2252054990
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3555631286
Short name T1009
Test name
Test status
Simulation time 9455074736 ps
CPU time 24.59 seconds
Started Jul 04 06:19:29 PM PDT 24
Finished Jul 04 06:19:55 PM PDT 24
Peak memory 233892 kb
Host smart-66bb6620-8dec-4c62-8e44-3a470712d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555631286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3555631286
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1739809606
Short name T383
Test name
Test status
Simulation time 1925832526 ps
CPU time 6.72 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:46 PM PDT 24
Peak memory 223320 kb
Host smart-3cc2debc-dc66-43a2-b346-edf9a5c92dc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1739809606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1739809606
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4167630336
Short name T30
Test name
Test status
Simulation time 19723183286 ps
CPU time 61.23 seconds
Started Jul 04 06:19:41 PM PDT 24
Finished Jul 04 06:20:43 PM PDT 24
Peak memory 255544 kb
Host smart-593278c3-f27b-4cae-8341-e8760146188a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167630336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4167630336
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3732030789
Short name T399
Test name
Test status
Simulation time 1287692136 ps
CPU time 7.07 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:37 PM PDT 24
Peak memory 217428 kb
Host smart-307d8275-5070-4703-a7cf-3b72b3473ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732030789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3732030789
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3894031193
Short name T865
Test name
Test status
Simulation time 1234549917 ps
CPU time 7.63 seconds
Started Jul 04 06:19:28 PM PDT 24
Finished Jul 04 06:19:36 PM PDT 24
Peak memory 217340 kb
Host smart-7ee445ea-4458-4345-b74e-fe6733be35b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894031193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3894031193
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3353838336
Short name T331
Test name
Test status
Simulation time 184202257 ps
CPU time 3.26 seconds
Started Jul 04 06:19:30 PM PDT 24
Finished Jul 04 06:19:34 PM PDT 24
Peak memory 217388 kb
Host smart-96202b7b-99fe-413b-b3d8-44d60327a625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353838336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3353838336
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1565325236
Short name T746
Test name
Test status
Simulation time 119333658 ps
CPU time 1.02 seconds
Started Jul 04 06:19:31 PM PDT 24
Finished Jul 04 06:19:32 PM PDT 24
Peak memory 207352 kb
Host smart-9b73d613-bf43-4394-9e2f-433ad3c282dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565325236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1565325236
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.722050980
Short name T945
Test name
Test status
Simulation time 330071668 ps
CPU time 2.46 seconds
Started Jul 04 06:19:40 PM PDT 24
Finished Jul 04 06:19:43 PM PDT 24
Peak memory 233788 kb
Host smart-c1847eff-5e44-4c38-8f4e-15a8531ed41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722050980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.722050980
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4264528547
Short name T921
Test name
Test status
Simulation time 14056345 ps
CPU time 0.84 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:19:40 PM PDT 24
Peak memory 206424 kb
Host smart-bbcf1d6d-a454-4809-aa43-c62751363fe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264528547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4264528547
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2092303497
Short name T1015
Test name
Test status
Simulation time 1507916781 ps
CPU time 6.33 seconds
Started Jul 04 06:19:40 PM PDT 24
Finished Jul 04 06:19:46 PM PDT 24
Peak memory 233808 kb
Host smart-4275efa8-7d93-46bc-87fb-e612e2a94638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092303497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2092303497
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1513798223
Short name T366
Test name
Test status
Simulation time 15835255 ps
CPU time 0.77 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:19:38 PM PDT 24
Peak memory 207564 kb
Host smart-6ce4df6d-5ed3-4368-ac55-db74c518580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513798223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1513798223
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2822801172
Short name T1020
Test name
Test status
Simulation time 35232461573 ps
CPU time 271.16 seconds
Started Jul 04 06:19:42 PM PDT 24
Finished Jul 04 06:24:13 PM PDT 24
Peak memory 256228 kb
Host smart-0ef71279-14dc-43ff-b4dc-05618f31ff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822801172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2822801172
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1081124885
Short name T318
Test name
Test status
Simulation time 1552390512 ps
CPU time 16.45 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:56 PM PDT 24
Peak memory 218852 kb
Host smart-69c3b969-b3f2-495d-a641-2a49de3ef25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081124885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1081124885
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.678651732
Short name T268
Test name
Test status
Simulation time 21865575762 ps
CPU time 78.05 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:20:58 PM PDT 24
Peak memory 256060 kb
Host smart-b2a66b3b-d4bc-4e6b-9a05-7eca69ba163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678651732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.678651732
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1009913584
Short name T562
Test name
Test status
Simulation time 1815822689 ps
CPU time 4.18 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:44 PM PDT 24
Peak memory 225548 kb
Host smart-af1b5b98-d390-452d-9c59-099623ed53e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009913584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1009913584
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3599267227
Short name T737
Test name
Test status
Simulation time 3607067983 ps
CPU time 8.51 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:19:46 PM PDT 24
Peak memory 233920 kb
Host smart-9670a9cf-1a16-4648-9bfb-c7bfdb8102ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599267227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3599267227
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2415782064
Short name T711
Test name
Test status
Simulation time 529355364 ps
CPU time 4.5 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:45 PM PDT 24
Peak memory 233820 kb
Host smart-c12cdc63-dd21-457f-b1b3-447b8dff0feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415782064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2415782064
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1068337720
Short name T301
Test name
Test status
Simulation time 1942410246 ps
CPU time 7.77 seconds
Started Jul 04 06:19:40 PM PDT 24
Finished Jul 04 06:19:48 PM PDT 24
Peak memory 225488 kb
Host smart-8cf4e064-5e03-4dad-88a7-7226dac05f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068337720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1068337720
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2795601014
Short name T262
Test name
Test status
Simulation time 524808599 ps
CPU time 3.23 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:43 PM PDT 24
Peak memory 225580 kb
Host smart-fabcba9c-3038-4011-a821-290023d9ea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795601014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2795601014
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.253604002
Short name T358
Test name
Test status
Simulation time 1306563318 ps
CPU time 5.34 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:45 PM PDT 24
Peak memory 224672 kb
Host smart-fd099eb6-ddee-42d1-a8dd-ba0efef14901
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=253604002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.253604002
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1620543080
Short name T284
Test name
Test status
Simulation time 83990068599 ps
CPU time 402.64 seconds
Started Jul 04 06:19:43 PM PDT 24
Finished Jul 04 06:26:26 PM PDT 24
Peak memory 266616 kb
Host smart-82d43b35-7587-45e2-b12f-ca12e5858842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620543080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1620543080
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4127909207
Short name T315
Test name
Test status
Simulation time 12396091894 ps
CPU time 29.69 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:20:10 PM PDT 24
Peak memory 217652 kb
Host smart-daddbdbb-96c5-405a-b479-80aeb9ea0783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127909207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4127909207
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4182235009
Short name T863
Test name
Test status
Simulation time 2451981428 ps
CPU time 6.05 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:19:44 PM PDT 24
Peak memory 217524 kb
Host smart-09e0e091-6b24-40bc-acde-f1307d93218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182235009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4182235009
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4137410602
Short name T450
Test name
Test status
Simulation time 72853269 ps
CPU time 1.12 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:19:39 PM PDT 24
Peak memory 209248 kb
Host smart-3592a592-c711-486c-b02a-9d05cab84b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137410602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4137410602
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1479432742
Short name T54
Test name
Test status
Simulation time 24188254 ps
CPU time 0.76 seconds
Started Jul 04 06:19:41 PM PDT 24
Finished Jul 04 06:19:42 PM PDT 24
Peak memory 206960 kb
Host smart-81da6fa4-9e77-4b01-bca5-b7a252bbdc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479432742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1479432742
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.341299239
Short name T999
Test name
Test status
Simulation time 9015551513 ps
CPU time 23.35 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:20:02 PM PDT 24
Peak memory 233872 kb
Host smart-31c7a95c-666d-45a9-aa37-0378d3185515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341299239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.341299239
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2450815670
Short name T362
Test name
Test status
Simulation time 40370103 ps
CPU time 0.73 seconds
Started Jul 04 06:19:45 PM PDT 24
Finished Jul 04 06:19:46 PM PDT 24
Peak memory 206372 kb
Host smart-b5cc50b5-d7f7-4ec5-a72a-f74a465c07ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450815670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2450815670
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1084531565
Short name T159
Test name
Test status
Simulation time 378157736 ps
CPU time 2.83 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:19:41 PM PDT 24
Peak memory 225500 kb
Host smart-b571b24c-5a7b-4cb2-ab91-639544a6ebfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084531565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1084531565
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2853964654
Short name T401
Test name
Test status
Simulation time 25394123 ps
CPU time 0.78 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:19:39 PM PDT 24
Peak memory 207492 kb
Host smart-c17cc0df-a098-43ad-809f-464be1218ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853964654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2853964654
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.626582656
Short name T1001
Test name
Test status
Simulation time 16742145227 ps
CPU time 173.8 seconds
Started Jul 04 06:19:45 PM PDT 24
Finished Jul 04 06:22:39 PM PDT 24
Peak memory 254504 kb
Host smart-ebcfa279-0106-48c5-96d9-440087436a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626582656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.626582656
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2586098855
Short name T239
Test name
Test status
Simulation time 26806734356 ps
CPU time 83.68 seconds
Started Jul 04 06:19:44 PM PDT 24
Finished Jul 04 06:21:08 PM PDT 24
Peak memory 257508 kb
Host smart-eff8eb0e-37dd-4816-acfc-8b347a2443b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586098855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2586098855
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1565105496
Short name T844
Test name
Test status
Simulation time 16100064660 ps
CPU time 179.31 seconds
Started Jul 04 06:19:46 PM PDT 24
Finished Jul 04 06:22:46 PM PDT 24
Peak memory 266624 kb
Host smart-c6b3f219-6cd1-4128-9ef0-555a7fed63d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565105496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1565105496
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3942007397
Short name T837
Test name
Test status
Simulation time 5024299161 ps
CPU time 49.28 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:20:28 PM PDT 24
Peak memory 250332 kb
Host smart-5d875633-b2df-4e49-a470-174ac197abde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942007397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3942007397
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.4200326601
Short name T582
Test name
Test status
Simulation time 165373269167 ps
CPU time 276.25 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:24:14 PM PDT 24
Peak memory 256060 kb
Host smart-339ddfb7-dd6b-41ae-9199-94cb03fbde8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200326601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.4200326601
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1043360527
Short name T570
Test name
Test status
Simulation time 231794609 ps
CPU time 3.54 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:43 PM PDT 24
Peak memory 225540 kb
Host smart-15117f60-9aef-4584-b7a3-2226bb31a214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043360527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1043360527
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1422136614
Short name T740
Test name
Test status
Simulation time 27708289522 ps
CPU time 49.46 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:20:28 PM PDT 24
Peak memory 237884 kb
Host smart-d8728fc5-efbf-418e-8d09-cf0de2287434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422136614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1422136614
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1391251236
Short name T286
Test name
Test status
Simulation time 2299878007 ps
CPU time 9.87 seconds
Started Jul 04 06:19:41 PM PDT 24
Finished Jul 04 06:19:52 PM PDT 24
Peak memory 233884 kb
Host smart-e4c828e0-8eb5-4be1-804d-8dda3e07ee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391251236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1391251236
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2117710953
Short name T503
Test name
Test status
Simulation time 22730637352 ps
CPU time 8.05 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:19:47 PM PDT 24
Peak memory 233872 kb
Host smart-d46f0684-4416-481b-ba54-99fb656f6c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117710953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2117710953
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4060715843
Short name T535
Test name
Test status
Simulation time 101660689 ps
CPU time 3.25 seconds
Started Jul 04 06:19:39 PM PDT 24
Finished Jul 04 06:19:43 PM PDT 24
Peak memory 220520 kb
Host smart-c9f856d0-d20f-4289-adef-9e0bdf6f56bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4060715843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4060715843
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4294501906
Short name T156
Test name
Test status
Simulation time 1593414281 ps
CPU time 32.76 seconds
Started Jul 04 06:19:44 PM PDT 24
Finished Jul 04 06:20:17 PM PDT 24
Peak memory 250148 kb
Host smart-cc18b141-dd7d-4823-969e-f4b52648c544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294501906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4294501906
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.629588427
Short name T589
Test name
Test status
Simulation time 2466870081 ps
CPU time 24.37 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:20:03 PM PDT 24
Peak memory 217512 kb
Host smart-dadefd6a-e82e-4e88-8f04-26f13d19a9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629588427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.629588427
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2665953572
Short name T800
Test name
Test status
Simulation time 3837223300 ps
CPU time 5.98 seconds
Started Jul 04 06:19:38 PM PDT 24
Finished Jul 04 06:19:44 PM PDT 24
Peak memory 217476 kb
Host smart-503e7531-8420-4c4a-9fc6-4785e9d3274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665953572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2665953572
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3603091176
Short name T632
Test name
Test status
Simulation time 15347506 ps
CPU time 0.99 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:19:39 PM PDT 24
Peak memory 208264 kb
Host smart-971e677d-49fd-4bad-a06b-346d51e27a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603091176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3603091176
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.752396566
Short name T375
Test name
Test status
Simulation time 127792596 ps
CPU time 0.88 seconds
Started Jul 04 06:19:42 PM PDT 24
Finished Jul 04 06:19:43 PM PDT 24
Peak memory 206984 kb
Host smart-dd1b563a-482f-49ee-af94-6527fcb1159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752396566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.752396566
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3629515584
Short name T623
Test name
Test status
Simulation time 3027055840 ps
CPU time 7.34 seconds
Started Jul 04 06:19:37 PM PDT 24
Finished Jul 04 06:19:45 PM PDT 24
Peak memory 233848 kb
Host smart-d60fefa6-9450-4f02-a760-cf234425348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629515584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3629515584
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2206474353
Short name T819
Test name
Test status
Simulation time 43882928 ps
CPU time 0.72 seconds
Started Jul 04 06:19:45 PM PDT 24
Finished Jul 04 06:19:46 PM PDT 24
Peak memory 206736 kb
Host smart-aee30038-b746-423c-8b0b-dcc167d077c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206474353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2206474353
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.218196356
Short name T240
Test name
Test status
Simulation time 244120264 ps
CPU time 5.3 seconds
Started Jul 04 06:19:46 PM PDT 24
Finished Jul 04 06:19:52 PM PDT 24
Peak memory 225504 kb
Host smart-86bfe115-3589-415b-bc1f-101a41746770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218196356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.218196356
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3349754231
Short name T337
Test name
Test status
Simulation time 36698078 ps
CPU time 0.79 seconds
Started Jul 04 06:19:46 PM PDT 24
Finished Jul 04 06:19:47 PM PDT 24
Peak memory 206448 kb
Host smart-e22814be-f1b6-431e-b366-f5c8f8da93af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349754231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3349754231
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1255636789
Short name T544
Test name
Test status
Simulation time 18623490566 ps
CPU time 47.58 seconds
Started Jul 04 06:19:53 PM PDT 24
Finished Jul 04 06:20:41 PM PDT 24
Peak memory 258512 kb
Host smart-fddf884d-9158-462c-9b94-1056f8c00c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255636789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1255636789
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.572351826
Short name T896
Test name
Test status
Simulation time 48945390368 ps
CPU time 88.13 seconds
Started Jul 04 06:19:47 PM PDT 24
Finished Jul 04 06:21:15 PM PDT 24
Peak memory 251332 kb
Host smart-69803147-0b61-411a-9544-676ce92b73b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572351826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.572351826
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2277391546
Short name T883
Test name
Test status
Simulation time 2546557341 ps
CPU time 6.23 seconds
Started Jul 04 06:19:45 PM PDT 24
Finished Jul 04 06:19:51 PM PDT 24
Peak memory 225740 kb
Host smart-9b78178e-2763-4dcd-8a51-0baed6c288e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277391546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2277391546
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1974295960
Short name T799
Test name
Test status
Simulation time 5778550319 ps
CPU time 79.47 seconds
Started Jul 04 06:19:46 PM PDT 24
Finished Jul 04 06:21:06 PM PDT 24
Peak memory 255380 kb
Host smart-10e9b82d-abdb-42df-aa9a-8c597f2d2356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974295960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1974295960
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3363435293
Short name T874
Test name
Test status
Simulation time 402948436 ps
CPU time 5.14 seconds
Started Jul 04 06:19:46 PM PDT 24
Finished Jul 04 06:19:52 PM PDT 24
Peak memory 233776 kb
Host smart-85e13267-19a3-41ee-9e98-4b9391a76ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363435293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3363435293
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.715465378
Short name T3
Test name
Test status
Simulation time 2966817966 ps
CPU time 26.02 seconds
Started Jul 04 06:19:48 PM PDT 24
Finished Jul 04 06:20:14 PM PDT 24
Peak memory 251096 kb
Host smart-feb675b3-ab42-4bc1-a1c8-ef7c4ce3b838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715465378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.715465378
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1654441634
Short name T576
Test name
Test status
Simulation time 712217002 ps
CPU time 2.49 seconds
Started Jul 04 06:19:45 PM PDT 24
Finished Jul 04 06:19:48 PM PDT 24
Peak memory 225564 kb
Host smart-1372046f-b937-4a17-9bcf-bf81cea2c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654441634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1654441634
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4225175950
Short name T486
Test name
Test status
Simulation time 9868975640 ps
CPU time 10.79 seconds
Started Jul 04 06:19:48 PM PDT 24
Finished Jul 04 06:19:59 PM PDT 24
Peak memory 225768 kb
Host smart-33d125f1-25c7-4932-96eb-bf668ae721bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225175950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4225175950
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1980971833
Short name T850
Test name
Test status
Simulation time 3541555313 ps
CPU time 8.39 seconds
Started Jul 04 06:19:44 PM PDT 24
Finished Jul 04 06:19:53 PM PDT 24
Peak memory 222916 kb
Host smart-d0381077-4aa7-4998-8be4-248979d6f507
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1980971833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1980971833
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1361097510
Short name T210
Test name
Test status
Simulation time 22716171603 ps
CPU time 214.94 seconds
Started Jul 04 06:19:50 PM PDT 24
Finished Jul 04 06:23:25 PM PDT 24
Peak memory 258572 kb
Host smart-945b7aff-3468-4a35-8115-f83cd815972b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361097510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1361097510
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2180117978
Short name T8
Test name
Test status
Simulation time 8440949093 ps
CPU time 14.39 seconds
Started Jul 04 06:19:48 PM PDT 24
Finished Jul 04 06:20:03 PM PDT 24
Peak memory 217440 kb
Host smart-1951f461-b220-49e7-879f-0730c75556d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180117978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2180117978
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3557687765
Short name T14
Test name
Test status
Simulation time 1539040100 ps
CPU time 5.56 seconds
Started Jul 04 06:19:46 PM PDT 24
Finished Jul 04 06:19:52 PM PDT 24
Peak memory 217372 kb
Host smart-c06b4e5a-e88c-49c8-9a3b-07ab9746b66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557687765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3557687765
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3452053689
Short name T384
Test name
Test status
Simulation time 386014814 ps
CPU time 2.83 seconds
Started Jul 04 06:19:47 PM PDT 24
Finished Jul 04 06:19:50 PM PDT 24
Peak memory 217340 kb
Host smart-e4bf2d11-f1f1-45ed-b967-19b4d47e3be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452053689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3452053689
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3376580673
Short name T9
Test name
Test status
Simulation time 110648043 ps
CPU time 0.8 seconds
Started Jul 04 06:19:44 PM PDT 24
Finished Jul 04 06:19:45 PM PDT 24
Peak memory 206976 kb
Host smart-76b23f70-b85e-4217-956d-b72080595391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376580673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3376580673
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1818471817
Short name T171
Test name
Test status
Simulation time 137339343 ps
CPU time 2.5 seconds
Started Jul 04 06:19:45 PM PDT 24
Finished Jul 04 06:19:48 PM PDT 24
Peak memory 233736 kb
Host smart-f639509d-3296-422d-a075-9db705a932e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818471817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1818471817
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2697592611
Short name T360
Test name
Test status
Simulation time 11614957 ps
CPU time 0.7 seconds
Started Jul 04 06:17:10 PM PDT 24
Finished Jul 04 06:17:11 PM PDT 24
Peak memory 205768 kb
Host smart-96eb8449-eb18-462d-9d74-e1d102832a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697592611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
697592611
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1801275194
Short name T802
Test name
Test status
Simulation time 830257844 ps
CPU time 3.81 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 233768 kb
Host smart-190a8359-6cc1-488f-80fd-af1b4d181739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801275194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1801275194
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1623135552
Short name T882
Test name
Test status
Simulation time 19288679 ps
CPU time 0.78 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:17:15 PM PDT 24
Peak memory 207460 kb
Host smart-52482449-6021-415b-9925-878c6f28b69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623135552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1623135552
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1118941914
Short name T613
Test name
Test status
Simulation time 83082366 ps
CPU time 0.78 seconds
Started Jul 04 06:17:07 PM PDT 24
Finished Jul 04 06:17:08 PM PDT 24
Peak memory 216892 kb
Host smart-1c07f2b2-11e6-4f91-b2bf-7f3a26685b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118941914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1118941914
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1820682447
Short name T853
Test name
Test status
Simulation time 4921993612 ps
CPU time 79.87 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:18:30 PM PDT 24
Peak memory 258256 kb
Host smart-29407d51-d01e-4f55-a10b-d0a5a26ac9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820682447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1820682447
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1339581592
Short name T28
Test name
Test status
Simulation time 63143169795 ps
CPU time 129.8 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:19:27 PM PDT 24
Peak memory 250356 kb
Host smart-e0637d1f-1053-4542-967f-2066f5d0f3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339581592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1339581592
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1818106607
Short name T129
Test name
Test status
Simulation time 17590100898 ps
CPU time 30.92 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:17:39 PM PDT 24
Peak memory 233900 kb
Host smart-86e7a901-d2fb-4fb3-8617-fdef5444f938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818106607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1818106607
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3226705818
Short name T88
Test name
Test status
Simulation time 25911919900 ps
CPU time 67.76 seconds
Started Jul 04 06:17:11 PM PDT 24
Finished Jul 04 06:18:19 PM PDT 24
Peak memory 253672 kb
Host smart-cce1441c-a5ec-4d1e-8023-d1ca64185a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226705818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3226705818
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1035353132
Short name T738
Test name
Test status
Simulation time 1348741987 ps
CPU time 14.53 seconds
Started Jul 04 06:17:07 PM PDT 24
Finished Jul 04 06:17:22 PM PDT 24
Peak memory 234044 kb
Host smart-29eff030-bae2-498b-9395-368d270b4369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035353132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1035353132
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1089527886
Short name T464
Test name
Test status
Simulation time 12267744866 ps
CPU time 8.74 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:24 PM PDT 24
Peak memory 225708 kb
Host smart-4069ef49-1aec-410e-8b06-55cc6ddc159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089527886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1089527886
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.4236411076
Short name T835
Test name
Test status
Simulation time 28695584 ps
CPU time 1.08 seconds
Started Jul 04 06:17:04 PM PDT 24
Finished Jul 04 06:17:05 PM PDT 24
Peak memory 217676 kb
Host smart-bd6d7c9e-7db6-43ac-b350-f817471315c9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236411076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.4236411076
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1752034470
Short name T302
Test name
Test status
Simulation time 18630397169 ps
CPU time 7.35 seconds
Started Jul 04 06:17:11 PM PDT 24
Finished Jul 04 06:17:19 PM PDT 24
Peak memory 225668 kb
Host smart-40f5d79f-ef67-4d3d-94e1-ecfce4470e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752034470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1752034470
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3952268042
Short name T261
Test name
Test status
Simulation time 6202028674 ps
CPU time 14.01 seconds
Started Jul 04 06:17:02 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 233864 kb
Host smart-a5f50da9-995d-4cc1-880f-08f4c18975bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952268042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3952268042
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1452921620
Short name T957
Test name
Test status
Simulation time 5709451870 ps
CPU time 17.63 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:27 PM PDT 24
Peak memory 219880 kb
Host smart-6b2d3c7d-d5fc-4b9b-b29f-c2bc4d267957
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1452921620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1452921620
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.785092572
Short name T710
Test name
Test status
Simulation time 3112208630 ps
CPU time 9.21 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:23 PM PDT 24
Peak memory 217572 kb
Host smart-b14bec32-5972-4d6c-9181-9f75876cb43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785092572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.785092572
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2786687887
Short name T578
Test name
Test status
Simulation time 3446343333 ps
CPU time 4.58 seconds
Started Jul 04 06:17:04 PM PDT 24
Finished Jul 04 06:17:09 PM PDT 24
Peak memory 217468 kb
Host smart-5725b00f-a7ff-416a-81dd-2009cba55600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786687887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2786687887
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2220555350
Short name T733
Test name
Test status
Simulation time 34773856 ps
CPU time 0.81 seconds
Started Jul 04 06:17:05 PM PDT 24
Finished Jul 04 06:17:06 PM PDT 24
Peak memory 206952 kb
Host smart-6e971d50-42fc-4bfc-b055-7514665ebad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220555350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2220555350
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.926679152
Short name T807
Test name
Test status
Simulation time 33362774 ps
CPU time 0.79 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:14 PM PDT 24
Peak memory 206992 kb
Host smart-efaf0ca3-34d4-4734-b24b-15584afe0c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926679152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.926679152
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3461207856
Short name T43
Test name
Test status
Simulation time 200242794 ps
CPU time 2.62 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 225612 kb
Host smart-7f2bc360-4799-4b0f-b426-71c05fe2acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461207856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3461207856
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3167454174
Short name T656
Test name
Test status
Simulation time 22028414 ps
CPU time 0.74 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:14 PM PDT 24
Peak memory 206360 kb
Host smart-6dce1ffe-fac1-49c0-b03d-49ddd5871be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167454174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
167454174
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3955105762
Short name T593
Test name
Test status
Simulation time 462812706 ps
CPU time 2.42 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:12 PM PDT 24
Peak memory 233748 kb
Host smart-7a395673-eb2e-4c84-8908-9ea6360cb92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955105762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3955105762
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.721296231
Short name T357
Test name
Test status
Simulation time 15867443 ps
CPU time 0.79 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 207524 kb
Host smart-903244aa-18a1-43c6-ad52-5d3c5a126739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721296231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.721296231
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.859586576
Short name T201
Test name
Test status
Simulation time 42093514617 ps
CPU time 83.48 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:18:37 PM PDT 24
Peak memory 250352 kb
Host smart-fb494e0f-6370-4274-b333-9376198f9a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859586576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.859586576
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3470826990
Short name T988
Test name
Test status
Simulation time 69692828073 ps
CPU time 308.05 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:22:23 PM PDT 24
Peak memory 258028 kb
Host smart-86203611-86ff-45ff-a888-77eb6b9959e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470826990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3470826990
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2891386570
Short name T306
Test name
Test status
Simulation time 5664276646 ps
CPU time 23.78 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:17:41 PM PDT 24
Peak memory 225656 kb
Host smart-96249d20-abbf-43d7-99a5-75aa0e72b2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891386570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2891386570
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1269238334
Short name T511
Test name
Test status
Simulation time 2579188458 ps
CPU time 11.67 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:21 PM PDT 24
Peak memory 238052 kb
Host smart-119268c4-6904-40c0-891f-028260c7a1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269238334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1269238334
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.360415335
Short name T997
Test name
Test status
Simulation time 28561571745 ps
CPU time 13.03 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:25 PM PDT 24
Peak memory 233860 kb
Host smart-a67c23ff-d31f-43cc-a3b3-47cc567d489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360415335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.360415335
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.951077433
Short name T70
Test name
Test status
Simulation time 34147154109 ps
CPU time 34.9 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:17:52 PM PDT 24
Peak memory 241004 kb
Host smart-e9cef289-d12e-4907-bdd9-4a9f28a5537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951077433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.951077433
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4253490053
Short name T6
Test name
Test status
Simulation time 15265284 ps
CPU time 1.09 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:15 PM PDT 24
Peak memory 217676 kb
Host smart-4e7d2d2f-b0a6-45f3-be86-4bb97c758e67
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253490053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4253490053
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4204886709
Short name T91
Test name
Test status
Simulation time 1238257424 ps
CPU time 5.22 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 225620 kb
Host smart-6abfaf76-0983-4711-ad80-1864bfb52cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204886709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4204886709
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3650498010
Short name T219
Test name
Test status
Simulation time 6922426904 ps
CPU time 18 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:17:33 PM PDT 24
Peak memory 233904 kb
Host smart-f3f10d6d-488d-4f1c-909b-cd32ef08a9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650498010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3650498010
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2124242028
Short name T571
Test name
Test status
Simulation time 391451786 ps
CPU time 4.92 seconds
Started Jul 04 06:17:11 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 224140 kb
Host smart-93ef52a0-5b35-4fbf-a164-c0f976e561a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2124242028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2124242028
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3114770792
Short name T157
Test name
Test status
Simulation time 78466592675 ps
CPU time 216.66 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:20:53 PM PDT 24
Peak memory 269608 kb
Host smart-5f143568-ae48-4bee-a860-67ec8a1fc2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114770792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3114770792
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.410548794
Short name T388
Test name
Test status
Simulation time 490688294 ps
CPU time 5.51 seconds
Started Jul 04 06:17:10 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 217404 kb
Host smart-58e366ce-8395-4e7b-9caf-41ef0eb3f5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410548794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.410548794
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.138686034
Short name T1012
Test name
Test status
Simulation time 1332424980 ps
CPU time 1.8 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:15 PM PDT 24
Peak memory 208792 kb
Host smart-a4afbcbe-a204-4314-9014-dd97635a2283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138686034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.138686034
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3232336018
Short name T635
Test name
Test status
Simulation time 80823537 ps
CPU time 1.37 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 217268 kb
Host smart-209df923-a77e-4dc8-8397-05435eaa9c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232336018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3232336018
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1242875058
Short name T876
Test name
Test status
Simulation time 156739153 ps
CPU time 0.82 seconds
Started Jul 04 06:17:17 PM PDT 24
Finished Jul 04 06:17:18 PM PDT 24
Peak memory 206980 kb
Host smart-bbf79e80-d70b-4040-b983-3a959d7c1cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242875058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1242875058
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.534857003
Short name T982
Test name
Test status
Simulation time 1987250949 ps
CPU time 5.78 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:17:14 PM PDT 24
Peak memory 225588 kb
Host smart-5a6c57ea-6874-4175-94ec-0a3a22005147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534857003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.534857003
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3496798456
Short name T832
Test name
Test status
Simulation time 15897237 ps
CPU time 0.75 seconds
Started Jul 04 06:17:10 PM PDT 24
Finished Jul 04 06:17:11 PM PDT 24
Peak memory 205808 kb
Host smart-15be7505-464e-46dd-86a3-82f492de9f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496798456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
496798456
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1647632906
Short name T962
Test name
Test status
Simulation time 2432127921 ps
CPU time 11.12 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:17:26 PM PDT 24
Peak memory 233900 kb
Host smart-ba739b8e-14e0-49b8-8318-0542fc4d4a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647632906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1647632906
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1669155491
Short name T868
Test name
Test status
Simulation time 40279595 ps
CPU time 0.83 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:10 PM PDT 24
Peak memory 207528 kb
Host smart-607c9452-d82f-41d4-b3fd-c408f3560e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669155491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1669155491
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1418300471
Short name T856
Test name
Test status
Simulation time 3962204533 ps
CPU time 94.66 seconds
Started Jul 04 06:17:11 PM PDT 24
Finished Jul 04 06:18:46 PM PDT 24
Peak memory 270844 kb
Host smart-71a593f5-9736-4d52-b159-a0dcd1365974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418300471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1418300471
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4124333512
Short name T773
Test name
Test status
Simulation time 19935487311 ps
CPU time 185.83 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:20:18 PM PDT 24
Peak memory 256308 kb
Host smart-d4ad806b-c1df-4318-9db7-c0edc4483485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124333512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4124333512
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.720904346
Short name T604
Test name
Test status
Simulation time 8750833655 ps
CPU time 38.38 seconds
Started Jul 04 06:17:19 PM PDT 24
Finished Jul 04 06:17:58 PM PDT 24
Peak memory 235048 kb
Host smart-63b7ec78-396a-4c8c-8af9-755437c236b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720904346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
720904346
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.693544975
Short name T237
Test name
Test status
Simulation time 111924358 ps
CPU time 5.49 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:21 PM PDT 24
Peak memory 239152 kb
Host smart-34a1f535-28b7-4df0-b275-a6413875b8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693544975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.693544975
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.350852923
Short name T287
Test name
Test status
Simulation time 2846648585 ps
CPU time 61.5 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 258120 kb
Host smart-c23047eb-65dc-4774-b6c3-b9aa7e7e4dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350852923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
350852923
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3129885854
Short name T425
Test name
Test status
Simulation time 1426652202 ps
CPU time 14.87 seconds
Started Jul 04 06:17:18 PM PDT 24
Finished Jul 04 06:17:34 PM PDT 24
Peak memory 233824 kb
Host smart-39126395-a773-4ba5-9bc1-cab385c8beac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129885854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3129885854
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1546553158
Short name T282
Test name
Test status
Simulation time 892979357 ps
CPU time 5.49 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:17:22 PM PDT 24
Peak memory 233784 kb
Host smart-64a67650-dd27-4acf-8947-126167887d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546553158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1546553158
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.847710321
Short name T347
Test name
Test status
Simulation time 76218593 ps
CPU time 1.07 seconds
Started Jul 04 06:17:10 PM PDT 24
Finished Jul 04 06:17:11 PM PDT 24
Peak memory 217692 kb
Host smart-8bb011ac-08f5-4058-ad4b-f8e6c90280cb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847710321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.847710321
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2476588367
Short name T127
Test name
Test status
Simulation time 101623665 ps
CPU time 2.57 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:17:19 PM PDT 24
Peak memory 233564 kb
Host smart-2963288f-a5c5-46d6-8e8c-f5d79024700d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476588367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2476588367
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3645488250
Short name T476
Test name
Test status
Simulation time 287852229 ps
CPU time 2.17 seconds
Started Jul 04 06:17:09 PM PDT 24
Finished Jul 04 06:17:11 PM PDT 24
Peak memory 224892 kb
Host smart-439efec5-be4b-4da2-998c-1b794ff41a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645488250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3645488250
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2169927350
Short name T654
Test name
Test status
Simulation time 3706484909 ps
CPU time 15.64 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:31 PM PDT 24
Peak memory 223196 kb
Host smart-ae2fa64f-8526-4ded-ba2e-ce511ffdf43e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2169927350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2169927350
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3851115637
Short name T891
Test name
Test status
Simulation time 45194497374 ps
CPU time 101.5 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:18:57 PM PDT 24
Peak memory 250696 kb
Host smart-7eac4f62-1479-4a2c-a6f8-6ef66e7c979f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851115637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3851115637
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1021247834
Short name T322
Test name
Test status
Simulation time 1278889818 ps
CPU time 7.65 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 217480 kb
Host smart-73094550-c10d-4c1a-9d1a-6c76ce09374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021247834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1021247834
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3586843153
Short name T336
Test name
Test status
Simulation time 7236680832 ps
CPU time 12.52 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:25 PM PDT 24
Peak memory 217464 kb
Host smart-522e9601-2d05-4a17-a98a-371e17f3d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586843153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3586843153
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1480054685
Short name T743
Test name
Test status
Simulation time 88481538 ps
CPU time 3.69 seconds
Started Jul 04 06:17:08 PM PDT 24
Finished Jul 04 06:17:11 PM PDT 24
Peak memory 217384 kb
Host smart-36a96c77-02a1-4bae-83e3-0cefe25ab938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480054685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1480054685
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.328704632
Short name T922
Test name
Test status
Simulation time 83586784 ps
CPU time 0.92 seconds
Started Jul 04 06:17:16 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 206964 kb
Host smart-0f43c2ad-fe8a-4117-a33e-30c3196d05db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328704632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.328704632
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2739018695
Short name T185
Test name
Test status
Simulation time 8506958970 ps
CPU time 11.16 seconds
Started Jul 04 06:17:11 PM PDT 24
Finished Jul 04 06:17:22 PM PDT 24
Peak memory 233216 kb
Host smart-b673a520-22db-4251-8522-0189a544f57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739018695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2739018695
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1536594040
Short name T801
Test name
Test status
Simulation time 38283618 ps
CPU time 0.72 seconds
Started Jul 04 06:17:19 PM PDT 24
Finished Jul 04 06:17:20 PM PDT 24
Peak memory 206412 kb
Host smart-a536e0cf-0fdc-4a32-b8b9-c0d952af7964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536594040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
536594040
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2270300664
Short name T776
Test name
Test status
Simulation time 543066423 ps
CPU time 4.56 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:20 PM PDT 24
Peak memory 233780 kb
Host smart-4456fbe6-7b0d-4af7-91a4-140e4b50c634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270300664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2270300664
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1307153130
Short name T641
Test name
Test status
Simulation time 116870399 ps
CPU time 0.8 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 206816 kb
Host smart-6d2652bd-a164-49a1-802f-8e931b977247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307153130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1307153130
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1268188637
Short name T527
Test name
Test status
Simulation time 21995384552 ps
CPU time 55.75 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:18:25 PM PDT 24
Peak memory 233948 kb
Host smart-f4070625-64d2-44e2-8c2a-e40630f4c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268188637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1268188637
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4110066217
Short name T203
Test name
Test status
Simulation time 19778371933 ps
CPU time 98.47 seconds
Started Jul 04 06:17:21 PM PDT 24
Finished Jul 04 06:19:00 PM PDT 24
Peak memory 264872 kb
Host smart-21638f57-cc73-4f23-9889-2b8288358694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110066217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4110066217
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.793843746
Short name T197
Test name
Test status
Simulation time 19065432771 ps
CPU time 212.2 seconds
Started Jul 04 06:17:20 PM PDT 24
Finished Jul 04 06:20:52 PM PDT 24
Peak memory 264320 kb
Host smart-7d8b4ebf-819d-4d06-a3c0-54ec6d1ef07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793843746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
793843746
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1945901974
Short name T845
Test name
Test status
Simulation time 2729337771 ps
CPU time 3.81 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:19 PM PDT 24
Peak memory 233900 kb
Host smart-80609179-a050-490c-97fb-3de1a4b6a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945901974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1945901974
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.849490612
Short name T967
Test name
Test status
Simulation time 39192873484 ps
CPU time 282.83 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:22:06 PM PDT 24
Peak memory 262948 kb
Host smart-0cc9f971-dcd6-4a33-8389-3256bb1a341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849490612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
849490612
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2275403928
Short name T913
Test name
Test status
Simulation time 107653818 ps
CPU time 2.08 seconds
Started Jul 04 06:17:17 PM PDT 24
Finished Jul 04 06:17:20 PM PDT 24
Peak memory 225112 kb
Host smart-dd300833-3156-4e8f-a05e-51ac751939a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275403928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2275403928
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2552260858
Short name T628
Test name
Test status
Simulation time 4570077336 ps
CPU time 23.25 seconds
Started Jul 04 06:17:12 PM PDT 24
Finished Jul 04 06:17:36 PM PDT 24
Peak memory 233900 kb
Host smart-23d7d86d-5659-48bc-a339-b5d629ce5eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552260858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2552260858
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1709620219
Short name T899
Test name
Test status
Simulation time 33737662 ps
CPU time 1.08 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 217648 kb
Host smart-f6c0c949-f3a7-41b8-9334-8ebae10d9944
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709620219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1709620219
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.856498591
Short name T750
Test name
Test status
Simulation time 5467091841 ps
CPU time 7.64 seconds
Started Jul 04 06:17:13 PM PDT 24
Finished Jul 04 06:17:21 PM PDT 24
Peak memory 233844 kb
Host smart-47d99df4-b2b2-467c-b0d6-5aaed8203a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856498591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
856498591
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3314163715
Short name T558
Test name
Test status
Simulation time 155615666 ps
CPU time 4.77 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:20 PM PDT 24
Peak memory 233796 kb
Host smart-d76cc3e9-1b4f-4fdd-a7e9-87f1efe01b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314163715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3314163715
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.496951197
Short name T567
Test name
Test status
Simulation time 655831430 ps
CPU time 5.25 seconds
Started Jul 04 06:17:24 PM PDT 24
Finished Jul 04 06:17:30 PM PDT 24
Peak memory 224120 kb
Host smart-d1b473fa-0de2-4bc8-9b18-f9bbccae8a98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=496951197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.496951197
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1703675865
Short name T24
Test name
Test status
Simulation time 5231967045 ps
CPU time 60.77 seconds
Started Jul 04 06:17:17 PM PDT 24
Finished Jul 04 06:18:18 PM PDT 24
Peak memory 233960 kb
Host smart-e4df1890-e57e-4818-8cc1-336d668c65b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703675865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1703675865
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.174724368
Short name T479
Test name
Test status
Simulation time 14557855665 ps
CPU time 31.07 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:17:45 PM PDT 24
Peak memory 217476 kb
Host smart-f98a1539-fa74-4cb9-b06b-4d25888bb0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174724368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.174724368
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2457087369
Short name T481
Test name
Test status
Simulation time 27927444 ps
CPU time 0.69 seconds
Started Jul 04 06:17:14 PM PDT 24
Finished Jul 04 06:17:15 PM PDT 24
Peak memory 206616 kb
Host smart-5f4436cd-d442-4792-b986-b9ae1ac4ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457087369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2457087369
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4156677111
Short name T699
Test name
Test status
Simulation time 11974874 ps
CPU time 0.69 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 206556 kb
Host smart-be01ab61-f4cc-438d-a043-03e1c638f36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156677111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4156677111
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3634828738
Short name T68
Test name
Test status
Simulation time 240478945 ps
CPU time 0.91 seconds
Started Jul 04 06:17:20 PM PDT 24
Finished Jul 04 06:17:21 PM PDT 24
Peak memory 207000 kb
Host smart-7486116a-6237-47e4-9d1e-9ccc782be106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634828738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3634828738
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2130806255
Short name T655
Test name
Test status
Simulation time 825161905 ps
CPU time 3.48 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:19 PM PDT 24
Peak memory 233792 kb
Host smart-aaaa2f20-6dd0-4fc7-94ab-9f3dc27c8804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130806255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2130806255
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1229635103
Short name T712
Test name
Test status
Simulation time 33890548 ps
CPU time 0.73 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 205804 kb
Host smart-a7eb4292-0986-4855-afd0-3d660f1a001f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229635103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
229635103
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.791409867
Short name T1017
Test name
Test status
Simulation time 224498905 ps
CPU time 4.04 seconds
Started Jul 04 06:17:21 PM PDT 24
Finished Jul 04 06:17:25 PM PDT 24
Peak memory 225544 kb
Host smart-e322682d-a48b-4b0d-aa0e-ea09175a62f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791409867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.791409867
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.356502792
Short name T645
Test name
Test status
Simulation time 33579251 ps
CPU time 0.78 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:16 PM PDT 24
Peak memory 207868 kb
Host smart-af5d63cf-cdb9-4654-9f26-6c16fb7467a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356502792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.356502792
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4172699674
Short name T979
Test name
Test status
Simulation time 46972351893 ps
CPU time 143.35 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:19:49 PM PDT 24
Peak memory 249936 kb
Host smart-d312fcc0-ca53-4103-a443-914c6a1de7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172699674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4172699674
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.288123055
Short name T463
Test name
Test status
Simulation time 13553664306 ps
CPU time 100.21 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:19:04 PM PDT 24
Peak memory 242092 kb
Host smart-6768211f-f681-414b-bd55-de4106a2f99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288123055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.288123055
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1284448377
Short name T848
Test name
Test status
Simulation time 6802651767 ps
CPU time 46.69 seconds
Started Jul 04 06:17:27 PM PDT 24
Finished Jul 04 06:18:14 PM PDT 24
Peak memory 241520 kb
Host smart-aa9e693a-e0c1-4794-924a-6b197f621fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284448377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1284448377
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.252858032
Short name T305
Test name
Test status
Simulation time 311719755 ps
CPU time 10.63 seconds
Started Jul 04 06:17:23 PM PDT 24
Finished Jul 04 06:17:35 PM PDT 24
Peak memory 233828 kb
Host smart-018730b2-517a-4c40-9e7c-029b920a3198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252858032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.252858032
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3682159875
Short name T510
Test name
Test status
Simulation time 36916329760 ps
CPU time 272.99 seconds
Started Jul 04 06:17:17 PM PDT 24
Finished Jul 04 06:21:50 PM PDT 24
Peak memory 251500 kb
Host smart-28819f97-2c11-4610-a8de-356eab63c335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682159875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3682159875
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.736598574
Short name T630
Test name
Test status
Simulation time 340217475 ps
CPU time 5.92 seconds
Started Jul 04 06:17:17 PM PDT 24
Finished Jul 04 06:17:24 PM PDT 24
Peak memory 225600 kb
Host smart-80c1c661-8b38-419f-999d-b5f5cdb9dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736598574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.736598574
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1812774407
Short name T745
Test name
Test status
Simulation time 1913799014 ps
CPU time 21.91 seconds
Started Jul 04 06:17:21 PM PDT 24
Finished Jul 04 06:17:43 PM PDT 24
Peak memory 249804 kb
Host smart-2c42444f-9aeb-4649-af0e-3f4f69e02d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812774407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1812774407
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.578767751
Short name T451
Test name
Test status
Simulation time 69614733 ps
CPU time 1.04 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:17:26 PM PDT 24
Peak memory 217656 kb
Host smart-7c695166-0a60-4fb3-abc7-0b8bbfc96013
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578767751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.578767751
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2929683281
Short name T477
Test name
Test status
Simulation time 35799461 ps
CPU time 2.55 seconds
Started Jul 04 06:17:28 PM PDT 24
Finished Jul 04 06:17:31 PM PDT 24
Peak memory 233536 kb
Host smart-6750fbfd-403f-439a-9377-8e29a4f12fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929683281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2929683281
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4080065402
Short name T381
Test name
Test status
Simulation time 1109713436 ps
CPU time 5.35 seconds
Started Jul 04 06:17:19 PM PDT 24
Finished Jul 04 06:17:24 PM PDT 24
Peak memory 233760 kb
Host smart-9ffa2805-40bc-4bde-a49a-c2a75401bf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080065402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4080065402
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2689952665
Short name T994
Test name
Test status
Simulation time 255193749 ps
CPU time 5.58 seconds
Started Jul 04 06:17:20 PM PDT 24
Finished Jul 04 06:17:26 PM PDT 24
Peak memory 223216 kb
Host smart-5c7dc0e1-2fc4-4333-9068-be19c8ff7374
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2689952665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2689952665
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2695733700
Short name T791
Test name
Test status
Simulation time 101671561283 ps
CPU time 221 seconds
Started Jul 04 06:17:21 PM PDT 24
Finished Jul 04 06:21:02 PM PDT 24
Peak memory 250524 kb
Host smart-5c33afad-e44e-4e78-a1f9-74cc6644a08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695733700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2695733700
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.195140706
Short name T744
Test name
Test status
Simulation time 5334002458 ps
CPU time 26.17 seconds
Started Jul 04 06:17:17 PM PDT 24
Finished Jul 04 06:17:43 PM PDT 24
Peak memory 218996 kb
Host smart-6a2ff30e-be2a-4238-8f7b-7777c83fedd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195140706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.195140706
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1971341570
Short name T83
Test name
Test status
Simulation time 647793258 ps
CPU time 4.75 seconds
Started Jul 04 06:17:25 PM PDT 24
Finished Jul 04 06:17:30 PM PDT 24
Peak memory 217332 kb
Host smart-fe8fb6ee-ffcf-4983-a318-0cdd51cb82ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971341570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1971341570
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3101292209
Short name T446
Test name
Test status
Simulation time 71807403 ps
CPU time 1.35 seconds
Started Jul 04 06:17:26 PM PDT 24
Finished Jul 04 06:17:28 PM PDT 24
Peak memory 217404 kb
Host smart-28090a7e-9216-4402-a534-da38eb488051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101292209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3101292209
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4104718199
Short name T82
Test name
Test status
Simulation time 72851092 ps
CPU time 0.84 seconds
Started Jul 04 06:17:15 PM PDT 24
Finished Jul 04 06:17:17 PM PDT 24
Peak memory 206976 kb
Host smart-dc918a58-8dad-44d1-a453-baa43da969b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104718199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4104718199
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2495246835
Short name T228
Test name
Test status
Simulation time 12775016023 ps
CPU time 7.77 seconds
Started Jul 04 06:17:26 PM PDT 24
Finished Jul 04 06:17:35 PM PDT 24
Peak memory 225696 kb
Host smart-253fbd0e-6986-4647-bef7-fb583bebb78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495246835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2495246835
Directory /workspace/9.spi_device_upload/latest
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