Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2177278	1			T2	1		T3	17984		T4	1
all_values[1]	2177278	1			T2	1		T3	17984		T4	1
all_values[2]	2177278	1			T2	1		T3	17984		T4	1
all_values[3]	2177278	1			T2	1		T3	17984		T4	1
all_values[4]	2177278	1			T2	1		T3	17984		T4	1
all_values[5]	2177278	1			T2	1		T3	17984		T4	1
all_values[6]	2177278	1			T2	1		T3	17984		T4	1
all_values[7]	2177278	1			T2	1		T3	17984		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17102886

1

T2

8

T3

143872

T4

8

auto[1]

315338

1

T5

78

T14

71

T16

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17390011

1

T2

8

T3

143872

T4

8

auto[1]

28213

1

T5

152

T6

214

T14

54

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2115156	1			T2	1		T3	17984		T4	1
all_values[0]	auto[0]	auto[1]	13409	1			T5	60		T6	129		T15	259
all_values[0]	auto[1]	auto[0]	48269	1			T5	7		T14	3		T16	5
all_values[0]	auto[1]	auto[1]	444	1			T5	3		T14	4		T19	3
all_values[1]	auto[0]	auto[0]	2140194	1			T2	1		T3	17984		T4	1
all_values[1]	auto[0]	auto[1]	9020	1			T5	36		T6	67		T14	5
all_values[1]	auto[1]	auto[0]	27773	1			T5	6		T14	6		T16	1
all_values[1]	auto[1]	auto[1]	291	1			T5	3		T14	3		T19	1
all_values[2]	auto[0]	auto[0]	2135452	1			T2	1		T3	17984		T4	1
all_values[2]	auto[0]	auto[1]	2759	1			T5	3		T6	18		T14	3
all_values[2]	auto[1]	auto[0]	38859	1			T5	3		T14	6		T19	5
all_values[2]	auto[1]	auto[1]	208	1			T5	5		T14	2		T19	1
all_values[3]	auto[0]	auto[0]	2138002	1			T2	1		T3	17984		T4	1
all_values[3]	auto[0]	auto[1]	208	1			T5	2		T14	3		T16	2
all_values[3]	auto[1]	auto[0]	38868	1			T5	5		T14	3		T19	2
all_values[3]	auto[1]	auto[1]	200	1			T5	6		T14	6		T16	1
all_values[4]	auto[0]	auto[0]	2160419	1			T2	1		T3	17984		T4	1
all_values[4]	auto[0]	auto[1]	216	1			T5	4		T14	3		T19	1
all_values[4]	auto[1]	auto[0]	16437	1			T5	2		T14	4		T16	6
all_values[4]	auto[1]	auto[1]	206	1			T5	7		T14	5		T19	2
all_values[5]	auto[0]	auto[0]	2145533	1			T2	1		T3	17984		T4	1
all_values[5]	auto[0]	auto[1]	172	1			T5	1		T14	2		T16	1
all_values[5]	auto[1]	auto[0]	31376	1			T5	9		T14	4		T16	3
all_values[5]	auto[1]	auto[1]	197	1			T5	4		T14	4		T16	1
all_values[6]	auto[0]	auto[0]	2132414	1			T2	1		T3	17984		T4	1
all_values[6]	auto[0]	auto[1]	224	1			T5	5		T14	4		T16	2
all_values[6]	auto[1]	auto[0]	44413	1			T5	4		T14	4		T19	1
all_values[6]	auto[1]	auto[1]	227	1			T5	5		T14	5		T16	1
all_values[7]	auto[0]	auto[0]	2109493	1			T2	1		T3	17984		T4	1
all_values[7]	auto[0]	auto[1]	215	1			T5	5		T16	1		T19	2
all_values[7]	auto[1]	auto[0]	67353	1			T5	6		T14	7		T16	4
all_values[7]	auto[1]	auto[1]	217	1			T5	3		T14	5		T19	4