Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37899	1			T3	155		T5	225		T6	165
auto[SpiFlashAddrCfg]	8011	1			T3	62		T5	49		T6	42
auto[SpiFlashAddr3b]	9639	1			T3	74		T5	60		T6	51
auto[SpiFlashAddr4b]	7966	1			T3	45		T4	4		T5	54

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36049

1

T3

214

T4

4

T5

225

auto[1]

27466

1

T3

122

T5

163

T6

129

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33227

1

T3

148

T4

4

T5

219

auto[1]

30288

1

T3

188

T5

169

T6

167

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42913	1			T3	186		T5	252		T6	185
values[1]	1133	1			T3	9		T5	9		T6	9
values[2]	1567	1			T3	8		T5	12		T6	3
values[3]	1534	1			T3	7		T5	13		T6	14
values[4]	1553	1			T3	7		T4	2		T5	11
values[5]	1503	1			T3	8		T5	9		T6	6
values[6]	1511	1			T3	11		T5	13		T6	10
values[7]	1481	1			T3	11		T5	8		T6	6
values[8]	10320	1			T3	89		T4	2		T5	61

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33229

1

T3

336

T4

4

T6

298

auto[1]

30286

1

T5

388

T11

10

T32

418

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

60042

1

T3

320

T4

4

T5

376

write

3473

1

T3

16

T5

12

T6

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20029

1

T3

136

T4

4

T5

143

valids[0x1]

43486

1

T3

200

T5

245

T6

203

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1629	1			T3	9		T5	16		T6	2
internal_process_ops[0x5a]	1631	1			T3	5		T5	15		T6	9
internal_process_ops[0x05]	23456	1			T3	90		T5	119		T6	104
internal_process_ops[0x35]	1651	1			T3	7		T5	5		T6	10
internal_process_ops[0x15]	1606	1			T3	7		T5	10		T6	7
internal_process_ops[0x03]	1132	1			T3	13		T4	2		T5	4
internal_process_ops[0x0b]	1179	1			T3	9		T5	3		T6	10
internal_process_ops[0x3b]	1069	1			T3	11		T5	3		T6	7
internal_process_ops[0x6b]	1052	1			T3	12		T4	2		T5	7
internal_process_ops[0xbb]	1178	1			T3	14		T5	4		T6	7
internal_process_ops[0xeb]	1108	1			T3	9		T5	5		T6	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61773

1

T3

327

T4

4

T5

381

auto[1]

1742

1

T3

9

T5

7

T6

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60973

1

T3

330

T4

4

T5

381

auto[1]

2542

1

T3

6

T5

7

T6

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11272

1

T3

115

T6

105

T7

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6636

1

T3

37

T6

59

T10

42

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2265

1

T3

28

T6

24

T10

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2027

1

T3

24

T6

13

T10

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2738

1

T3

44

T6

17

T7

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2314

1

T3

27

T6

26

T10

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2167

1

T3

15

T4

4

T6

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2090

1

T3

30

T6

24

T10

15

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

92

1

T3

1

T43

2

T162

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

97

1

T3

2

T6

1

T57

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

107

1

T35

1

T39

1

T57

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

111

1

T10

1

T35

1

T36

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

122

1

T3

4

T6

3

T8

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

101

1

T3

3

T10

3

T23

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

100

1

T3

2

T6

1

T23

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

114

1

T3

1

T6

1

T23

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

122

1

T6

4

T35

2

T57

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

112

1

T3

2

T6

1

T10

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

88

1

T6

2

T57

1

T163

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T3

1

T6

1

T10

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

134

1

T6

1

T23

1

T35

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

105

1

T10

2

T23

2

T35

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T35

2

T164

1

T163

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

116

1

T6

2

T23

1

T37

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11112

1

T5

151

T32

203

T15

174

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8042

1

T5

72

T32

84

T15

187

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1450

1

T5

28

T11

8

T32

22

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1437

1

T5

21

T32

16

T15

50

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1858

1

T5

21

T32

23

T15

44

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1790

1

T5

33

T32

23

T15

66

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1431

1

T5

19

T11

2

T32

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1413

1

T5

31

T32

19

T15

41

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T15

1

T44

1

T16

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

106

1

T5

1

T32

3

T15

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

119

1

T5

1

T15

8

T89

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T15

3

T44

1

T16

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T32

3

T15

2

T44

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

99

1

T32

2

T16

2

T28

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T15

3

T16

2

T28

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

91

1

T32

1

T15

2

T16

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

119

1

T5

1

T15

3

T75

7

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

121

1

T32

4

T15

1

T44

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

133

1

T15

1

T44

1

T16

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

134

1

T5

5

T32

1

T15

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T5

3

T32

2

T75

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

108

1

T5

1

T15

1

T16

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T32

3

T15

2

T16

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

121

1

T15

5

T16

2

T88

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4157	1			T3	38		T6	33		T8	2
auto[0]	values[0]	valids[0x1]	16888	1			T3	148		T6	152		T7	6
auto[0]	values[1]	valids[0x1]	631	1			T3	9		T6	9		T10	6
auto[0]	values[2]	valids[0x0]	583	1			T3	6		T6	1		T10	4
auto[0]	values[2]	valids[0x1]	362	1			T3	2		T6	2		T10	1
auto[0]	values[3]	valids[0x0]	577	1			T3	5		T6	6		T9	4
auto[0]	values[3]	valids[0x1]	323	1			T3	2		T6	8		T8	2
auto[0]	values[4]	valids[0x0]	531	1			T3	5		T4	2		T6	5
auto[0]	values[4]	valids[0x1]	346	1			T3	2		T6	4		T10	1
auto[0]	values[5]	valids[0x0]	550	1			T3	7		T6	4		T10	2
auto[0]	values[5]	valids[0x1]	336	1			T3	1		T6	2		T7	4
auto[0]	values[6]	valids[0x0]	618	1			T3	5		T6	7		T9	2
auto[0]	values[6]	valids[0x1]	304	1			T3	6		T6	3		T10	1
auto[0]	values[7]	valids[0x0]	599	1			T3	9		T6	6		T8	2
auto[0]	values[7]	valids[0x1]	278	1			T3	2		T10	2		T23	3
auto[0]	values[8]	valids[0x0]	3841	1			T3	61		T4	2		T6	33
auto[0]	values[8]	valids[0x1]	2305	1			T3	28		T6	23		T7	6
auto[1]	values[0]	valids[0x0]	3872	1			T5	66		T32	48		T15	113
auto[1]	values[0]	valids[0x1]	17996	1			T5	186		T11	1		T32	276
auto[1]	values[1]	valids[0x1]	502	1			T5	9		T32	9		T15	22
auto[1]	values[2]	valids[0x0]	390	1			T5	11		T11	4		T32	5
auto[1]	values[2]	valids[0x1]	232	1			T5	1		T11	2		T32	3
auto[1]	values[3]	valids[0x0]	371	1			T5	5		T32	9		T15	11
auto[1]	values[3]	valids[0x1]	263	1			T5	8		T32	4		T15	4
auto[1]	values[4]	valids[0x0]	384	1			T5	7		T11	3		T32	5
auto[1]	values[4]	valids[0x1]	292	1			T5	4		T32	3		T15	11
auto[1]	values[5]	valids[0x0]	378	1			T5	6		T32	4		T15	15
auto[1]	values[5]	valids[0x1]	239	1			T5	3		T32	4		T15	11
auto[1]	values[6]	valids[0x0]	368	1			T5	11		T32	4		T15	13
auto[1]	values[6]	valids[0x1]	221	1			T5	2		T32	1		T15	8
auto[1]	values[7]	valids[0x0]	366	1			T5	6		T32	7		T15	11
auto[1]	values[7]	valids[0x1]	238	1			T5	2		T32	1		T15	4
auto[1]	values[8]	valids[0x0]	2444	1			T5	31		T32	18		T15	49
auto[1]	values[8]	valids[0x1]	1730	1			T5	30		T32	17		T15	49