Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3650712

1

T3

22768

T4

1

T5

10552

auto[1]

33912

1

T3

76

T5

108

T6

98

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142318

1

T3

63

T4

1

T5

62

auto[1]

2542306

1

T3

22781

T5

10598

T6

11254

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	678174	1			T3	603		T4	1		T5	548
auto[524288:1048575]	420390	1			T3	5382		T5	577		T6	516
auto[1048576:1572863]	445910	1			T3	261		T5	1331		T6	532
auto[1572864:2097151]	432114	1			T3	4220		T5	130		T6	2122
auto[2097152:2621439]	383336	1			T3	514		T5	386		T6	23
auto[2621440:3145727]	402425	1			T3	4983		T5	3918		T6	18
auto[3145728:3670015]	463083	1			T3	5494		T5	3737		T6	2470
auto[3670016:4194303]	459192	1			T3	1387		T5	33		T6	4586

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2576338

1

T3

22836

T4

1

T5

10658

auto[1]

1108286

1

T3

8

T5

2

T6

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3165693

1

T3

18099

T4

1

T5

9034

auto[1]

518931

1

T3

4745

T5

1626

T6

4536

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	238962	1			T3	7		T4	1		T5	6
auto[0]	auto[0]	auto[0:524287]	auto[1]	369795	1			T3	596		T5	540		T6	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	127409	1			T3	5		T5	7		T6	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	220635	1			T3	5377		T5	264		T7	1024
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	141877	1			T3	1		T5	7		T6	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	233457	1			T3	256		T5	264		T6	8
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	138658	1			T3	5		T5	2		T6	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	232863	1			T3	2001		T5	128		T6	2088
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	102290	1			T3	2		T5	2		T7	269
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	222476	1			T3	512		T5	128		T10	517
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	119399	1			T3	10		T5	10		T6	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	225357	1			T3	4943		T5	3867		T6	7
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	150394	1			T3	4		T5	12		T6	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	238321	1			T3	2946		T5	3686		T6	22
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	109954	1			T3	7		T5	3		T6	14
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	266352	1			T3	1362		T5	1		T6	4539
auto[0]	auto[1]	auto[0:524287]	auto[0]	1629	1			T5	2		T6	1		T10	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	63220	1			T6	1024		T32	2978		T44	2691
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1511	1			T5	2		T6	2		T32	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	65529	1			T5	304		T6	512		T32	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	638	1			T3	4		T5	1		T6	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	65873	1			T5	1058		T6	512		T15	130
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	537	1			T3	1		T6	5		T32	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	56367	1			T3	2207		T6	1		T15	771
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1144	1			T6	6		T32	1		T15	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53065	1			T5	256		T6	12		T32	101
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	533	1			T3	5		T5	1		T32	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53099	1			T3	2		T5	1		T15	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1261	1			T3	3		T6	2		T23	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	69649	1			T3	2509		T6	2444		T32	258
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2021	1			T3	3		T23	10		T44	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	76437	1			T23	313		T35	384		T28	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	524	1			T6	1		T10	1		T43	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3192	1			T6	22		T10	11		T43	7
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	394	1			T10	2		T32	1		T15	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4298	1			T10	8		T32	16		T15	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	470	1			T5	1		T6	3		T23	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2759	1			T6	4		T23	1		T32	39
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	430	1			T3	1		T6	1		T23	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2445	1			T3	5		T6	14		T23	24
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	374	1			T23	1		T15	5		T35	19
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2872	1			T23	27		T15	36		T35	135
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	389	1			T3	1		T5	2		T6	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2745	1			T3	11		T5	36		T6	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	384	1			T3	1		T5	2		T10	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2144	1			T3	31		T5	37		T10	26
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	419	1			T3	1		T5	1		T6	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3655	1			T3	14		T5	28		T6	29
auto[1]	auto[1]	auto[0:524287]	auto[0]	109	1			T32	1		T35	7		T75	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	743	1			T32	38		T75	27		T18	49
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	88	1			T32	1		T75	3		T190	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	526	1			T32	4		T75	46		T190	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	93	1			T28	1		T88	11		T212	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	743	1			T212	19		T192	22		T203	60
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	76	1			T6	1		T15	3		T28	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	738	1			T6	8		T15	6		T88	141
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	94	1			T6	2		T15	1		T16	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1021	1			T6	3		T16	8		T38	8
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	87	1			T3	2		T5	1		T15	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	816	1			T3	9		T15	1		T28	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	91	1			T32	2		T15	1		T44	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	839	1			T32	43		T44	128		T16	34
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	79	1			T35	7		T81	1		T185	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	275	1			T185	3		T127	2		T203	17

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2035104	1			T3	18032		T4	1		T5	8926
auto[0]	auto[0]	auto[1]	1103095	1			T3	2		T5	1		T6	1
auto[0]	auto[1]	auto[0]	508066	1			T3	4733		T5	1624		T6	4522
auto[0]	auto[1]	auto[1]	4447	1			T3	1		T5	1		T32	1
auto[1]	auto[0]	auto[0]	26889	1			T3	61		T5	107		T6	84
auto[1]	auto[0]	auto[1]	605	1			T3	4		T10	5		T23	1
auto[1]	auto[1]	auto[0]	6279	1			T3	10		T5	1		T6	14
auto[1]	auto[1]	auto[1]	139	1			T3	1		T32	2		T15	2