Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2177278	1			T2	1		T3	17984		T4	1
all_pins[1]	2177278	1			T2	1		T3	17984		T4	1
all_pins[2]	2177278	1			T2	1		T3	17984		T4	1
all_pins[3]	2177278	1			T2	1		T3	17984		T4	1
all_pins[4]	2177278	1			T2	1		T3	17984		T4	1
all_pins[5]	2177278	1			T2	1		T3	17984		T4	1
all_pins[6]	2177278	1			T2	1		T3	17984		T4	1
all_pins[7]	2177278	1			T2	1		T3	17984		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17372993	1			T2	8		T3	143872		T4	8
values[0x1]	45231	1			T5	36		T14	34		T16	3
transitions[0x0=>0x1]	44140	1			T5	22		T14	18		T16	3
transitions[0x1=>0x0]	44146	1			T5	22		T14	18		T16	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2176790	1			T2	1		T3	17984		T4	1
all_pins[0]	values[0x1]	488	1			T5	3		T14	4		T19	3
all_pins[0]	transitions[0x0=>0x1]	441	1			T5	3		T14	3		T19	3
all_pins[0]	transitions[0x1=>0x0]	269	1			T5	3		T14	2		T19	1
all_pins[1]	values[0x0]	2176962	1			T2	1		T3	17984		T4	1
all_pins[1]	values[0x1]	316	1			T5	3		T14	3		T19	1
all_pins[1]	transitions[0x0=>0x1]	267	1			T5	3		T14	1		T19	1
all_pins[1]	transitions[0x1=>0x0]	165	1			T5	5		T19	1		T21	2
all_pins[2]	values[0x0]	2177064	1			T2	1		T3	17984		T4	1
all_pins[2]	values[0x1]	214	1			T5	5		T14	2		T19	1
all_pins[2]	transitions[0x0=>0x1]	170	1			T5	3		T14	1		T19	1
all_pins[2]	transitions[0x1=>0x0]	156	1			T5	4		T14	5		T16	1
all_pins[3]	values[0x0]	2177078	1			T2	1		T3	17984		T4	1
all_pins[3]	values[0x1]	200	1			T5	6		T14	6		T16	1
all_pins[3]	transitions[0x0=>0x1]	149	1			T5	1		T14	2		T16	1
all_pins[3]	transitions[0x1=>0x0]	155	1			T5	2		T14	1		T19	2
all_pins[4]	values[0x0]	2177072	1			T2	1		T3	17984		T4	1
all_pins[4]	values[0x1]	206	1			T5	7		T14	5		T19	2
all_pins[4]	transitions[0x0=>0x1]	150	1			T5	5		T14	2		T19	1
all_pins[4]	transitions[0x1=>0x0]	834	1			T5	2		T14	1		T16	1
all_pins[5]	values[0x0]	2176388	1			T2	1		T3	17984		T4	1
all_pins[5]	values[0x1]	890	1			T5	4		T14	4		T16	1
all_pins[5]	transitions[0x0=>0x1]	159	1			T5	2		T14	3		T16	1
all_pins[5]	transitions[0x1=>0x0]	41969	1			T5	3		T14	4		T16	1
all_pins[6]	values[0x0]	2134578	1			T2	1		T3	17984		T4	1
all_pins[6]	values[0x1]	42700	1			T5	5		T14	5		T16	1
all_pins[6]	transitions[0x0=>0x1]	42634	1			T5	2		T14	1		T16	1
all_pins[6]	transitions[0x1=>0x0]	151	1			T14	1		T19	3		T161	3
all_pins[7]	values[0x0]	2177061	1			T2	1		T3	17984		T4	1
all_pins[7]	values[0x1]	217	1			T5	3		T14	5		T19	4
all_pins[7]	transitions[0x0=>0x1]	170	1			T5	3		T14	5		T19	3
all_pins[7]	transitions[0x1=>0x0]	447	1			T5	3		T14	4		T19	2