Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19327

1

T3

214

T4

4

T6

169

auto[1]

13902

1

T3

122

T6

129

T10

75

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4139	1			T3	40		T6	20		T10	40
values[1]	3729	1			T3	20		T6	22		T23	60
values[2]	4266	1			T3	31		T4	4		T6	21
values[3]	4420	1			T6	89		T23	20		T43	31
values[4]	4143	1			T3	55		T6	30		T8	14
values[5]	3921	1			T3	26		T6	79		T10	75
values[6]	4098	1			T3	124		T9	22		T23	22
values[7]	4513	1			T3	40		T6	37		T10	49

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4537	1			T23	85		T162	6		T71	8
values[1]	3696	1			T3	20		T6	20		T10	20
values[2]	4038	1			T3	26		T6	44		T10	75
values[3]	3569	1			T3	75		T6	22		T7	16
values[4]	4335	1			T3	135		T6	69		T23	22
values[5]	4282	1			T3	40		T6	102		T8	14
values[6]	5188	1			T3	40		T6	20		T10	20
values[7]	3584	1			T4	4		T6	21		T10	49

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	240	1			T23	20		T76	9		T208	7
auto[0]	values[0]	values[1]	271	1			T6	6		T10	10		T23	63
auto[0]	values[0]	values[2]	318	1			T10	13		T35	12		T57	95
auto[0]	values[0]	values[3]	288	1			T20	12		T192	13		T225	6
auto[0]	values[0]	values[4]	249	1			T3	8		T20	13		T192	15
auto[0]	values[0]	values[5]	324	1			T3	15		T163	10		T188	12
auto[0]	values[0]	values[6]	444	1			T188	13		T185	11		T192	34
auto[0]	values[0]	values[7]	199	1			T226	14		T57	12		T188	7
auto[0]	values[1]	values[0]	287	1			T39	9		T227	2		T214	14
auto[0]	values[1]	values[1]	87	1			T163	12		T185	18		T228	10
auto[0]	values[1]	values[2]	217	1			T23	16		T127	12		T214	27
auto[0]	values[1]	values[3]	243	1			T6	16		T197	8		T229	15
auto[0]	values[1]	values[4]	328	1			T185	56		T76	14		T129	12
auto[0]	values[1]	values[5]	318	1			T23	9		T38	9		T127	19
auto[0]	values[1]	values[6]	340	1			T3	9		T192	12		T76	12
auto[0]	values[1]	values[7]	206	1			T195	8		T74	12		T230	2
auto[0]	values[2]	values[0]	446	1			T71	8		T154	24		T231	69
auto[0]	values[2]	values[1]	279	1			T35	12		T232	10		T233	10
auto[0]	values[2]	values[2]	215	1			T208	9		T184	17		T179	33
auto[0]	values[2]	values[3]	203	1			T7	16		T180	16		T133	6
auto[0]	values[2]	values[4]	311	1			T3	7		T38	16		T185	20
auto[0]	values[2]	values[5]	390	1			T57	10		T185	9		T179	15
auto[0]	values[2]	values[6]	298	1			T183	12		T35	12		T194	14
auto[0]	values[2]	values[7]	292	1			T4	4		T6	12		T23	49
auto[0]	values[3]	values[0]	324	1			T23	13		T39	48		T188	8
auto[0]	values[3]	values[1]	512	1			T234	10		T35	20		T163	31
auto[0]	values[3]	values[2]	298	1			T39	8		T57	9		T20	9
auto[0]	values[3]	values[3]	222	1			T43	31		T163	8		T229	50
auto[0]	values[3]	values[4]	404	1			T6	65		T163	15		T192	7
auto[0]	values[3]	values[5]	295	1			T235	4		T39	10		T192	24
auto[0]	values[3]	values[6]	273	1			T6	15		T185	14		T236	4
auto[0]	values[3]	values[7]	215	1			T129	10		T179	8		T225	12
auto[0]	values[4]	values[0]	255	1			T162	6		T39	13		T163	11
auto[0]	values[4]	values[1]	241	1			T57	8		T208	19		T184	12
auto[0]	values[4]	values[2]	328	1			T186	2		T38	10		T192	15
auto[0]	values[4]	values[3]	266	1			T3	42		T188	12		T208	12
auto[0]	values[4]	values[4]	407	1			T164	11		T127	8		T237	12
auto[0]	values[4]	values[5]	309	1			T6	13		T8	14		T127	25
auto[0]	values[4]	values[6]	335	1			T163	14		T20	13		T208	13
auto[0]	values[4]	values[7]	316	1			T23	9		T164	24		T163	13
auto[0]	values[5]	values[0]	314	1			T185	38		T192	16		T193	12
auto[0]	values[5]	values[1]	242	1			T185	24		T22	22		T157	11
auto[0]	values[5]	values[2]	380	1			T3	16		T6	24		T10	45
auto[0]	values[5]	values[3]	318	1			T90	14		T38	15		T180	14
auto[0]	values[5]	values[4]	274	1			T193	14		T233	11		T229	11
auto[0]	values[5]	values[5]	385	1			T6	9		T163	13		T185	10
auto[0]	values[5]	values[6]	408	1			T10	13		T91	12		T163	22
auto[0]	values[5]	values[7]	229	1			T238	2		T154	44		T239	20
auto[0]	values[6]	values[0]	253	1			T57	14		T215	5		T218	9
auto[0]	values[6]	values[1]	257	1			T240	4		T163	14		T192	5
auto[0]	values[6]	values[2]	236	1			T34	25		T164	7		T241	12
auto[0]	values[6]	values[3]	231	1			T3	16		T9	22		T188	26
auto[0]	values[6]	values[4]	379	1			T3	69		T23	14		T113	12
auto[0]	values[6]	values[5]	309	1			T173	2		T164	9		T211	16
auto[0]	values[6]	values[6]	515	1			T3	8		T76	12		T127	28
auto[0]	values[6]	values[7]	237	1			T76	21		T127	20		T208	13
auto[0]	values[7]	values[0]	587	1			T20	13		T84	22		T184	18
auto[0]	values[7]	values[1]	359	1			T3	12		T242	14		T57	9
auto[0]	values[7]	values[2]	226	1			T192	9		T214	26		T218	15
auto[0]	values[7]	values[3]	301	1			T57	59		T163	17		T179	18
auto[0]	values[7]	values[4]	271	1			T83	8		T188	9		T20	28
auto[0]	values[7]	values[5]	158	1			T3	12		T6	9		T233	10
auto[0]	values[7]	values[6]	253	1			T243	4		T76	11		T184	16
auto[0]	values[7]	values[7]	412	1			T10	8		T188	8		T185	10
auto[1]	values[0]	values[0]	390	1			T23	45		T76	11		T208	162
auto[1]	values[0]	values[1]	159	1			T6	14		T10	10		T23	11
auto[1]	values[0]	values[2]	164	1			T10	7		T35	8		T57	7
auto[1]	values[0]	values[3]	133	1			T20	9		T192	33		T225	14
auto[1]	values[0]	values[4]	172	1			T3	12		T244	2		T20	7
auto[1]	values[0]	values[5]	268	1			T3	5		T163	64		T188	8
auto[1]	values[0]	values[6]	347	1			T188	7		T185	9		T192	5
auto[1]	values[0]	values[7]	173	1			T57	8		T188	13		T177	12
auto[1]	values[1]	values[0]	217	1			T39	28		T214	6		T218	10
auto[1]	values[1]	values[1]	38	1			T163	18		T185	7		T245	8
auto[1]	values[1]	values[2]	153	1			T23	24		T127	8		T214	26
auto[1]	values[1]	values[3]	352	1			T6	6		T229	40		T246	8
auto[1]	values[1]	values[4]	276	1			T185	11		T76	6		T129	8
auto[1]	values[1]	values[5]	175	1			T23	11		T38	11		T127	6
auto[1]	values[1]	values[6]	326	1			T3	11		T192	31		T76	8
auto[1]	values[1]	values[7]	166	1			T247	6		T231	9		T248	14
auto[1]	values[2]	values[0]	151	1			T154	28		T231	8		T189	31
auto[1]	values[2]	values[1]	136	1			T35	8		T233	10		T179	6
auto[1]	values[2]	values[2]	282	1			T208	11		T184	7		T179	12
auto[1]	values[2]	values[3]	94	1			T37	8		T180	8		T177	7
auto[1]	values[2]	values[4]	339	1			T3	24		T38	4		T185	10
auto[1]	values[2]	values[5]	276	1			T57	31		T185	23		T249	20
auto[1]	values[2]	values[6]	333	1			T35	8		T217	10		T214	6
auto[1]	values[2]	values[7]	221	1			T6	9		T23	7		T76	7
auto[1]	values[3]	values[0]	160	1			T23	7		T39	8		T188	12
auto[1]	values[3]	values[1]	185	1			T35	20		T163	9		T127	6
auto[1]	values[3]	values[2]	427	1			T39	73		T57	11		T20	32
auto[1]	values[3]	values[3]	252	1			T163	54		T229	7		T22	9
auto[1]	values[3]	values[4]	188	1			T6	4		T163	5		T192	13
auto[1]	values[3]	values[5]	337	1			T39	10		T192	11		T208	5
auto[1]	values[3]	values[6]	190	1			T6	5		T185	6		T214	13
auto[1]	values[3]	values[7]	138	1			T250	12		T129	10		T179	12
auto[1]	values[4]	values[0]	192	1			T39	7		T163	9		T193	7
auto[1]	values[4]	values[1]	271	1			T57	12		T208	3		T184	8
auto[1]	values[4]	values[2]	240	1			T38	10		T192	7		T184	6
auto[1]	values[4]	values[3]	214	1			T3	13		T188	8		T208	8
auto[1]	values[4]	values[4]	192	1			T164	9		T127	12		T178	20
auto[1]	values[4]	values[5]	194	1			T6	17		T223	20		T127	15
auto[1]	values[4]	values[6]	170	1			T163	6		T216	10		T20	7
auto[1]	values[4]	values[7]	213	1			T23	11		T164	16		T163	10
auto[1]	values[5]	values[0]	272	1			T185	8		T251	8		T192	4
auto[1]	values[5]	values[1]	137	1			T185	19		T22	5		T157	9
auto[1]	values[5]	values[2]	237	1			T3	10		T6	20		T10	10
auto[1]	values[5]	values[3]	133	1			T38	5		T180	7		T49	7
auto[1]	values[5]	values[4]	187	1			T193	6		T233	9		T229	22
auto[1]	values[5]	values[5]	124	1			T6	26		T163	7		T185	10
auto[1]	values[5]	values[6]	184	1			T10	7		T163	8		T185	6
auto[1]	values[5]	values[7]	97	1			T252	12		T154	7		T239	8
auto[1]	values[6]	values[0]	197	1			T57	8		T215	15		T218	11
auto[1]	values[6]	values[1]	273	1			T163	20		T192	15		T76	10
auto[1]	values[6]	values[2]	159	1			T34	22		T164	13		T241	8
auto[1]	values[6]	values[3]	149	1			T3	4		T188	14		T192	39
auto[1]	values[6]	values[4]	184	1			T3	15		T23	8		T38	4
auto[1]	values[6]	values[5]	186	1			T164	11		T211	4		T253	4
auto[1]	values[6]	values[6]	347	1			T3	12		T76	8		T127	10
auto[1]	values[6]	values[7]	186	1			T76	19		T127	9		T208	7
auto[1]	values[7]	values[0]	252	1			T20	27		T184	7		T193	6
auto[1]	values[7]	values[1]	249	1			T3	8		T36	16		T57	22
auto[1]	values[7]	values[2]	158	1			T192	18		T214	9		T218	5
auto[1]	values[7]	values[3]	170	1			T57	17		T163	11		T179	7
auto[1]	values[7]	values[4]	174	1			T188	11		T20	5		T193	5
auto[1]	values[7]	values[5]	234	1			T3	8		T6	28		T198	18
auto[1]	values[7]	values[6]	425	1			T76	9		T184	7		T178	87
auto[1]	values[7]	values[7]	284	1			T10	41		T188	12		T185	10