Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16783

1

T3

160

T4

2

T6

186

auto[1]

46732

1

T3

176

T4

2

T5

388

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1398	1			T3	15		T4	2		T5	7
auto[4:7]	26749	1			T3	107		T5	147		T6	118
auto[8:11]	1424	1			T3	9		T5	6		T6	12
auto[12:15]	320	1			T3	7		T5	2		T6	2
auto[16:19]	320	1			T3	1		T5	4		T6	1
auto[20:23]	1857	1			T3	11		T5	10		T6	7
auto[24:27]	329	1			T3	2		T5	3		T6	2
auto[28:31]	332	1			T3	1		T5	3		T6	5
auto[32:35]	293	1			T3	3		T5	4		T6	1
auto[36:39]	395	1			T3	2		T5	8		T6	1
auto[40:43]	336	1			T3	2		T10	1		T23	3
auto[44:47]	378	1			T5	8		T6	6		T9	4
auto[48:51]	358	1			T5	4		T6	1		T10	1
auto[52:55]	1884	1			T3	7		T5	7		T6	10
auto[56:59]	1357	1			T3	12		T5	3		T6	7
auto[60:63]	340	1			T3	1		T6	2		T10	1
auto[64:67]	332	1			T5	8		T6	2		T15	2
auto[68:71]	338	1			T5	1		T6	2		T23	1
auto[72:75]	321	1			T3	2		T6	1		T32	1
auto[76:79]	392	1			T3	2		T6	2		T23	1
auto[80:83]	288	1			T3	1		T5	1		T6	1
auto[84:87]	370	1			T3	1		T5	1		T6	2
auto[88:91]	1868	1			T3	7		T5	16		T6	10
auto[92:95]	341	1			T6	2		T10	5		T32	1
auto[96:99]	372	1			T3	2		T6	1		T15	4
auto[100:103]	344	1			T3	3		T5	3		T6	3
auto[104:107]	1304	1			T3	13		T4	2		T5	8
auto[108:111]	335	1			T5	2		T6	4		T10	2
auto[112:115]	360	1			T3	1		T5	4		T6	1
auto[116:119]	343	1			T3	3		T5	3		T6	1
auto[120:123]	328	1			T3	5		T6	1		T23	3
auto[124:127]	316	1			T3	1		T5	3		T6	2
auto[128:131]	338	1			T3	4		T5	2		T6	1
auto[132:135]	334	1			T3	2		T5	1		T23	1
auto[136:139]	410	1			T3	1		T6	2		T10	1
auto[140:143]	331	1			T3	2		T5	6		T6	1
auto[144:147]	307	1			T3	2		T6	5		T23	2
auto[148:151]	358	1			T3	1		T5	1		T23	1
auto[152:155]	338	1			T3	1		T5	5		T6	1
auto[156:159]	1887	1			T3	12		T5	19		T6	3
auto[160:163]	361	1			T3	3		T5	2		T32	1
auto[164:167]	324	1			T5	2		T6	2		T15	11
auto[168:171]	401	1			T3	9		T5	5		T6	1
auto[172:175]	313	1			T5	1		T6	2		T10	1
auto[176:179]	306	1			T3	4		T5	1		T6	3
auto[180:183]	1932	1			T3	9		T5	15		T6	13
auto[184:187]	1422	1			T3	17		T5	6		T6	9
auto[188:191]	353	1			T3	1		T5	5		T6	3
auto[192:195]	328	1			T3	3		T5	1		T6	3
auto[196:199]	352	1			T3	2		T5	3		T6	1
auto[200:203]	330	1			T23	1		T43	2		T32	5
auto[204:207]	345	1			T3	3		T5	2		T6	1
auto[208:211]	358	1			T3	1		T5	1		T6	3
auto[212:215]	339	1			T3	7		T6	2		T23	4
auto[216:219]	327	1			T3	1		T5	2		T8	2
auto[220:223]	350	1			T3	2		T10	1		T23	2
auto[224:227]	314	1			T3	2		T5	2		T23	3
auto[228:231]	301	1			T3	1		T5	5		T6	3
auto[232:235]	2831	1			T3	16		T5	18		T6	8
auto[236:239]	301	1			T5	5		T6	1		T9	2
auto[240:243]	356	1			T3	3		T5	6		T23	3
auto[244:247]	354	1			T3	1		T5	1		T8	2
auto[248:251]	299	1			T3	1		T5	3		T6	1
auto[252:255]	293	1			T3	4		T5	2		T6	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	487	1			T3	9		T4	1		T6	5
auto[0:3]	auto[1]	911	1			T3	6		T4	1		T5	7
auto[4:7]	auto[0]	6437	1			T3	23		T6	92		T9	2
auto[4:7]	auto[1]	20312	1			T3	84		T5	147		T6	26
auto[8:11]	auto[0]	519	1			T3	5		T6	4		T7	3
auto[8:11]	auto[1]	905	1			T3	4		T5	6		T6	8
auto[12:15]	auto[0]	89	1			T3	7		T6	2		T34	1
auto[12:15]	auto[1]	231	1			T5	2		T32	1		T15	1
auto[16:19]	auto[0]	81	1			T3	1		T6	1		T23	3
auto[16:19]	auto[1]	239	1			T5	4		T90	1		T15	6
auto[20:23]	auto[0]	463	1			T3	2		T6	3		T10	2
auto[20:23]	auto[1]	1394	1			T3	9		T5	10		T6	4
auto[24:27]	auto[0]	84	1			T6	2		T10	2		T38	1
auto[24:27]	auto[1]	245	1			T3	2		T5	3		T23	1
auto[28:31]	auto[0]	90	1			T6	3		T35	4		T250	1
auto[28:31]	auto[1]	242	1			T3	1		T5	3		T6	2
auto[32:35]	auto[0]	70	1			T3	1		T10	2		T163	2
auto[32:35]	auto[1]	223	1			T3	2		T5	4		T6	1
auto[36:39]	auto[0]	121	1			T3	1		T10	2		T23	2
auto[36:39]	auto[1]	274	1			T3	1		T5	8		T6	1
auto[40:43]	auto[0]	114	1			T3	2		T10	1		T23	2
auto[40:43]	auto[1]	222	1			T23	1		T32	2		T15	2
auto[44:47]	auto[0]	98	1			T9	2		T10	1		T23	5
auto[44:47]	auto[1]	280	1			T5	8		T6	6		T9	2
auto[48:51]	auto[0]	87	1			T6	1		T10	1		T35	2
auto[48:51]	auto[1]	271	1			T5	4		T32	2		T15	3
auto[52:55]	auto[0]	516	1			T3	4		T6	7		T7	1
auto[52:55]	auto[1]	1368	1			T3	3		T5	7		T6	3
auto[56:59]	auto[0]	494	1			T3	9		T6	7		T23	3
auto[56:59]	auto[1]	863	1			T3	3		T5	3		T10	3
auto[60:63]	auto[0]	90	1			T3	1		T6	2		T10	1
auto[60:63]	auto[1]	250	1			T32	1		T15	8		T16	4
auto[64:67]	auto[0]	80	1			T6	2		T35	2		T34	1
auto[64:67]	auto[1]	252	1			T5	8		T15	2		T44	1
auto[68:71]	auto[0]	80	1			T162	1		T74	2		T39	3
auto[68:71]	auto[1]	258	1			T5	1		T6	2		T23	1
auto[72:75]	auto[0]	94	1			T6	1		T39	4		T163	2
auto[72:75]	auto[1]	227	1			T3	2		T32	1		T15	5
auto[76:79]	auto[0]	87	1			T3	2		T39	1		T57	3
auto[76:79]	auto[1]	305	1			T6	2		T23	1		T32	4
auto[80:83]	auto[0]	77	1			T3	1		T23	1		T163	2
auto[80:83]	auto[1]	211	1			T5	1		T6	1		T32	1
auto[84:87]	auto[0]	94	1			T3	1		T6	2		T38	1
auto[84:87]	auto[1]	276	1			T5	1		T10	2		T23	1
auto[88:91]	auto[0]	468	1			T3	3		T6	7		T7	2
auto[88:91]	auto[1]	1400	1			T3	4		T5	16		T6	3
auto[92:95]	auto[0]	83	1			T6	2		T10	4		T180	1
auto[92:95]	auto[1]	258	1			T10	1		T32	1		T15	4
auto[96:99]	auto[0]	97	1			T3	2		T163	1		T20	1
auto[96:99]	auto[1]	275	1			T6	1		T15	4		T44	1
auto[100:103]	auto[0]	94	1			T57	2		T163	1		T20	1
auto[100:103]	auto[1]	250	1			T3	3		T5	3		T6	3
auto[104:107]	auto[0]	466	1			T3	8		T4	1		T10	2
auto[104:107]	auto[1]	838	1			T3	5		T4	1		T5	8
auto[108:111]	auto[0]	68	1			T10	1		T23	1		T43	2
auto[108:111]	auto[1]	267	1			T5	2		T6	4		T10	1
auto[112:115]	auto[0]	104	1			T3	1		T10	3		T23	1
auto[112:115]	auto[1]	256	1			T5	4		T6	1		T23	5
auto[116:119]	auto[0]	78	1			T57	1		T185	2		T20	2
auto[116:119]	auto[1]	265	1			T3	3		T5	3		T6	1
auto[120:123]	auto[0]	96	1			T3	2		T23	3		T250	2
auto[120:123]	auto[1]	232	1			T3	3		T6	1		T32	1
auto[124:127]	auto[0]	71	1			T35	2		T163	1		T188	2
auto[124:127]	auto[1]	245	1			T3	1		T5	3		T6	2
auto[128:131]	auto[0]	95	1			T3	3		T6	1		T197	1
auto[128:131]	auto[1]	243	1			T3	1		T5	2		T32	1
auto[132:135]	auto[0]	89	1			T90	2		T34	1		T39	2
auto[132:135]	auto[1]	245	1			T3	2		T5	1		T23	1
auto[136:139]	auto[0]	102	1			T3	1		T6	1		T10	1
auto[136:139]	auto[1]	308	1			T6	1		T23	1		T32	4
auto[140:143]	auto[0]	78	1			T3	2		T6	1		T23	4
auto[140:143]	auto[1]	253	1			T5	6		T10	2		T32	2
auto[144:147]	auto[0]	83	1			T6	5		T23	2		T35	1
auto[144:147]	auto[1]	224	1			T3	2		T15	11		T44	1
auto[148:151]	auto[0]	87	1			T3	1		T197	1		T39	1
auto[148:151]	auto[1]	271	1			T5	1		T23	1		T32	5
auto[152:155]	auto[0]	91	1			T3	1		T43	1		T35	4
auto[152:155]	auto[1]	247	1			T5	5		T6	1		T43	1
auto[156:159]	auto[0]	491	1			T3	9		T6	3		T7	2
auto[156:159]	auto[1]	1396	1			T3	3		T5	19		T7	2
auto[160:163]	auto[0]	94	1			T3	3		T34	1		T57	3
auto[160:163]	auto[1]	267	1			T5	2		T32	1		T15	11
auto[164:167]	auto[0]	82	1			T6	1		T35	2		T39	2
auto[164:167]	auto[1]	242	1			T5	2		T6	1		T15	11
auto[168:171]	auto[0]	108	1			T3	6		T6	1		T10	3
auto[168:171]	auto[1]	293	1			T3	3		T5	5		T32	5
auto[172:175]	auto[0]	91	1			T6	2		T10	1		T250	1
auto[172:175]	auto[1]	222	1			T5	1		T23	1		T32	2
auto[176:179]	auto[0]	95	1			T3	2		T6	2		T10	1
auto[176:179]	auto[1]	211	1			T3	2		T5	1		T6	1
auto[180:183]	auto[0]	511	1			T3	5		T6	5		T9	1
auto[180:183]	auto[1]	1421	1			T3	4		T5	15		T6	8
auto[184:187]	auto[0]	512	1			T3	12		T6	6		T10	2
auto[184:187]	auto[1]	910	1			T3	5		T5	6		T6	3
auto[188:191]	auto[0]	85	1			T57	2		T164	1		T187	1
auto[188:191]	auto[1]	268	1			T3	1		T5	5		T6	3
auto[192:195]	auto[0]	102	1			T3	3		T6	2		T9	2
auto[192:195]	auto[1]	226	1			T5	1		T6	1		T9	2
auto[196:199]	auto[0]	101	1			T57	2		T164	1		T163	1
auto[196:199]	auto[1]	251	1			T3	2		T5	3		T6	1
auto[200:203]	auto[0]	78	1			T43	1		T34	3		T164	1
auto[200:203]	auto[1]	252	1			T23	1		T43	1		T32	5
auto[204:207]	auto[0]	83	1			T8	2		T10	1		T180	2
auto[204:207]	auto[1]	262	1			T3	3		T5	2		T6	1
auto[208:211]	auto[0]	91	1			T3	1		T6	2		T23	1
auto[208:211]	auto[1]	267	1			T5	1		T6	1		T10	4
auto[212:215]	auto[0]	81	1			T3	6		T23	4		T39	2
auto[212:215]	auto[1]	258	1			T3	1		T6	2		T32	1
auto[216:219]	auto[0]	63	1			T8	1		T20	1		T192	1
auto[216:219]	auto[1]	264	1			T3	1		T5	2		T8	1
auto[220:223]	auto[0]	85	1			T3	2		T43	1		T35	1
auto[220:223]	auto[1]	265	1			T10	1		T23	2		T43	1
auto[224:227]	auto[0]	91	1			T3	1		T23	3		T38	3
auto[224:227]	auto[1]	223	1			T3	1		T5	2		T15	3
auto[228:231]	auto[0]	87	1			T3	1		T6	2		T35	2
auto[228:231]	auto[1]	214	1			T5	5		T6	1		T23	3
auto[232:235]	auto[0]	871	1			T3	10		T6	7		T8	1
auto[232:235]	auto[1]	1960	1			T3	6		T5	18		T6	1
auto[236:239]	auto[0]	60	1			T9	1		T23	1		T39	2
auto[236:239]	auto[1]	241	1			T5	5		T6	1		T9	1
auto[240:243]	auto[0]	75	1			T3	1		T23	3		T35	2
auto[240:243]	auto[1]	281	1			T3	2		T5	6		T32	4
auto[244:247]	auto[0]	112	1			T8	1		T35	1		T38	2
auto[244:247]	auto[1]	242	1			T3	1		T5	1		T8	1
auto[248:251]	auto[0]	66	1			T3	1		T127	1		T129	1
auto[248:251]	auto[1]	233	1			T5	3		T6	1		T23	1
auto[252:255]	auto[0]	66	1			T3	4		T6	2		T74	2
auto[252:255]	auto[1]	227	1			T5	2		T6	3		T10	1