Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	389	1			T3	7		T6	1		T7	6
auto[ReadAddrCrossIntoMailbox]	288	1			T3	6		T10	4		T23	2
auto[ReadAddrCrossOutOfMailbox]	350	1			T3	8		T6	4		T10	5
auto[ReadAddrCrossAllMailbox]	207	1			T3	2		T10	1		T23	3
auto[ReadAddrOutsideMailbox]	3866	1			T3	45		T4	2		T6	35

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2494

1

T3

47

T4

1

T6

21

auto[1]

2606

1

T3

21

T4

1

T6

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	851	1			T3	13		T6	5		T10	2
read_ops[0x0b]	882	1			T3	9		T6	10		T7	6
read_ops[0x3b]	822	1			T3	11		T6	7		T10	3
read_ops[0x6b]	813	1			T3	12		T4	2		T6	6
read_ops[0xbb]	891	1			T3	14		T6	7		T10	5
read_ops[0xeb]	841	1			T3	9		T6	5		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T185	1		T127	2		T178	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T188	1		T185	2		T76	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T10	1		T57	1		T129	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T34	1		T163	1		T188	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T10	1		T57	2		T193	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T3	2		T35	1		T163	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T178	1		T49	1		T191	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T34	1		T177	2		T22	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T3	8		T6	3		T23	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	339	1			T3	3		T6	2		T23	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T7	3		T57	1		T163	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T6	1		T7	3		T35	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T164	1		T129	1		T193	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T188	1		T225	1		T218	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T6	1		T35	1		T188	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T3	1		T10	2		T129	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T34	1		T57	2		T178	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T76	1		T208	2		T233	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	333	1			T3	5		T6	1		T8	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	348	1			T3	3		T6	7		T8	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T3	1		T194	1		T57	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T3	1		T35	1		T194	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T3	2		T38	1		T185	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T23	1		T35	1		T163	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T3	1		T38	1		T39	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T34	2		T39	1		T57	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T185	1		T127	1		T211	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T10	1		T163	1		T254	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	310	1			T3	5		T6	7		T23	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T3	1		T10	2		T23	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T3	2		T34	1		T57	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T35	1		T192	1		T184	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T3	2		T10	1		T163	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T3	1		T35	1		T163	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T23	1		T39	1		T57	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T23	1		T76	2		T129	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T3	1		T23	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T178	3		T214	1		T229	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T3	3		T4	1		T10	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T3	3		T4	1		T6	6
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T3	3		T10	1		T195	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T195	1		T57	2		T163	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T3	1		T10	1		T57	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T76	1		T127	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	43	1			T3	2		T6	2		T23	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T3	1		T10	1		T35	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T23	1		T57	1		T185	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T23	1		T76	1		T127	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T3	6		T6	2		T23	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	354	1			T3	1		T6	3		T10	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T10	1		T35	1		T194	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T10	1		T194	1		T38	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T163	1		T76	1		T184	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T10	1		T23	1		T35	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T6	1		T23	1		T35	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T3	1		T10	1		T21	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T184	1		T22	1		T154	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T3	1		T76	1		T129	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	320	1			T3	5		T6	4		T8	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T3	2		T8	1		T10	2