Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3781	1			T3	91		T6	50		T8	14
values[1]	4327	1			T3	55		T4	4		T23	42
values[2]	4105	1			T3	40		T6	41		T9	22
values[3]	3891	1			T6	20		T10	75		T23	20
values[4]	4181	1			T3	64		T6	35		T90	14
values[5]	4175	1			T3	46		T43	31		T240	4
values[6]	4378	1			T3	40		T7	16		T23	65
values[7]	4391	1			T6	152		T10	20		T23	96

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4435	1			T3	55		T6	30		T10	20
values[1]	3900	1			T3	20		T6	24		T10	20
values[2]	4604	1			T3	40		T6	57		T23	116
values[3]	4045	1			T3	51		T6	40		T10	49
values[4]	4338	1			T6	78		T37	8		T235	4
values[5]	3521	1			T3	46		T4	4		T8	14
values[6]	4111	1			T3	40		T6	69		T7	16
values[7]	4275	1			T3	84		T23	40		T244	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32363

1

T3

327

T4

4

T6

292

auto[1]

866

1

T3

9

T6

6

T10

10

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	697	1			T6	27		T10	18		T34	23
auto[0]	values[0]	values[1]	409	1			T164	20		T192	20		T255	18
auto[0]	values[0]	values[2]	385	1			T3	20		T6	19		T164	20
auto[0]	values[0]	values[3]	315	1			T3	31		T35	18		T163	38
auto[0]	values[0]	values[4]	583	1			T37	6		T197	8		T254	8
auto[0]	values[0]	values[5]	303	1			T8	14		T57	20		T20	24
auto[0]	values[0]	values[6]	555	1			T3	18		T23	20		T234	10
auto[0]	values[0]	values[7]	426	1			T3	20		T38	20		T57	20
auto[0]	values[1]	values[0]	424	1			T3	34		T194	14		T39	20
auto[0]	values[1]	values[1]	509	1			T36	14		T71	8		T192	22
auto[0]	values[1]	values[2]	902	1			T23	22		T34	21		T196	6
auto[0]	values[1]	values[3]	440	1			T3	20		T127	49		T249	20
auto[0]	values[1]	values[4]	538	1			T57	59		T20	41		T129	18
auto[0]	values[1]	values[5]	246	1			T4	4		T177	19		T179	22
auto[0]	values[1]	values[6]	472	1			T39	20		T129	59		T133	6
auto[0]	values[1]	values[7]	682	1			T23	20		T163	29		T127	26
auto[0]	values[2]	values[0]	424	1			T180	22		T163	20		T192	61
auto[0]	values[2]	values[1]	523	1			T163	73		T20	20		T192	37
auto[0]	values[2]	values[2]	544	1			T3	20		T23	73		T193	20
auto[0]	values[2]	values[3]	475	1			T6	20		T10	45		T35	20
auto[0]	values[2]	values[4]	803	1			T6	21		T39	34		T57	53
auto[0]	values[2]	values[5]	382	1			T9	22		T113	12		T185	43
auto[0]	values[2]	values[6]	483	1			T3	20		T35	18		T91	12
auto[0]	values[2]	values[7]	368	1			T57	20		T185	19		T216	10
auto[0]	values[3]	values[0]	431	1			T163	20		T256	2		T185	20
auto[0]	values[3]	values[1]	363	1			T10	20		T186	2		T250	12
auto[0]	values[3]	values[2]	383	1			T257	20		T258	21		T259	12
auto[0]	values[3]	values[3]	408	1			T6	20		T129	20		T193	20
auto[0]	values[3]	values[4]	428	1			T260	16		T163	26		T22	20
auto[0]	values[3]	values[5]	678	1			T10	52		T185	19		T20	19
auto[0]	values[3]	values[6]	526	1			T23	17		T35	20		T188	39
auto[0]	values[3]	values[7]	577	1			T244	2		T163	29		T21	20
auto[0]	values[4]	values[0]	374	1			T195	8		T188	20		T185	20
auto[0]	values[4]	values[1]	394	1			T188	19		T214	34		T233	20
auto[0]	values[4]	values[2]	558	1			T163	20		T185	20		T129	30
auto[0]	values[4]	values[3]	777	1			T38	20		T185	28		T127	19
auto[0]	values[4]	values[4]	436	1			T6	35		T237	12		T261	14
auto[0]	values[4]	values[5]	302	1			T185	20		T76	20		T178	20
auto[0]	values[4]	values[6]	397	1			T90	14		T226	14		T185	43
auto[0]	values[4]	values[7]	826	1			T3	63		T35	20		T188	19
auto[0]	values[5]	values[0]	290	1			T164	20		T49	20		T218	19
auto[0]	values[5]	values[1]	922	1			T3	19		T43	31		T57	101
auto[0]	values[5]	values[2]	421	1			T39	20		T220	18		T215	19
auto[0]	values[5]	values[3]	462	1			T192	17		T177	20		T214	20
auto[0]	values[5]	values[4]	458	1			T38	18		T20	22		T192	20
auto[0]	values[5]	values[5]	459	1			T3	22		T35	19		T127	32
auto[0]	values[5]	values[6]	512	1			T240	4		T183	12		T57	22
auto[0]	values[5]	values[7]	541	1			T232	10		T57	20		T164	20
auto[0]	values[6]	values[0]	906	1			T3	20		T74	12		T164	20
auto[0]	values[6]	values[1]	358	1			T180	20		T227	2		T76	17
auto[0]	values[6]	values[2]	648	1			T20	33		T192	45		T76	20
auto[0]	values[6]	values[3]	385	1			T76	20		T127	20		T21	20
auto[0]	values[6]	values[4]	529	1			T76	19		T127	42		T215	20
auto[0]	values[6]	values[5]	540	1			T3	20		T23	44		T243	4
auto[0]	values[6]	values[6]	495	1			T7	16		T23	18		T242	14
auto[0]	values[6]	values[7]	394	1			T177	20		T193	24		T191	20
auto[0]	values[7]	values[0]	790	1			T23	56		T163	61		T76	20
auto[0]	values[7]	values[1]	321	1			T6	23		T163	20		T76	20
auto[0]	values[7]	values[2]	676	1			T6	37		T23	20		T173	2
auto[0]	values[7]	values[3]	674	1			T163	23		T188	20		T238	2
auto[0]	values[7]	values[4]	424	1			T6	22		T235	4		T38	20
auto[0]	values[7]	values[5]	516	1			T10	19		T83	8		T134	4
auto[0]	values[7]	values[6]	540	1			T6	68		T39	20		T20	21
auto[0]	values[7]	values[7]	356	1			T23	20		T39	55		T179	22
auto[1]	values[0]	values[0]	17	1			T6	3		T10	2		T34	2
auto[1]	values[0]	values[1]	21	1			T255	2		T262	3		T263	4
auto[1]	values[0]	values[2]	7	1			T6	1		T264	1		T265	3
auto[1]	values[0]	values[3]	7	1			T35	2		T163	2		T225	1
auto[1]	values[0]	values[4]	16	1			T37	2		T22	1		T207	3
auto[1]	values[0]	values[5]	13	1			T20	3		T184	5		T49	1
auto[1]	values[0]	values[6]	20	1			T3	2		T184	5		T215	1
auto[1]	values[0]	values[7]	7	1			T188	2		T266	2		T267	1
auto[1]	values[1]	values[0]	12	1			T3	1		T21	2		T22	1
auto[1]	values[1]	values[1]	16	1			T36	2		T215	2		T206	1
auto[1]	values[1]	values[2]	19	1			T34	1		T185	2		T193	1
auto[1]	values[1]	values[3]	11	1			T127	1		T205	1		T218	2
auto[1]	values[1]	values[4]	18	1			T57	2		T129	2		T258	4
auto[1]	values[1]	values[5]	3	1			T177	1		T179	1		T268	1
auto[1]	values[1]	values[6]	17	1			T129	3		T269	3		T262	1
auto[1]	values[1]	values[7]	18	1			T163	1		T269	2		T225	3
auto[1]	values[2]	values[0]	11	1			T180	2		T192	1		T76	3
auto[1]	values[2]	values[1]	10	1			T163	1		T192	2		T49	1
auto[1]	values[2]	values[2]	6	1			T23	1		T193	1		T205	1
auto[1]	values[2]	values[3]	19	1			T10	4		T185	1		T192	1
auto[1]	values[2]	values[4]	30	1			T39	3		T57	3		T164	3
auto[1]	values[2]	values[5]	7	1			T215	1		T262	3		T270	1
auto[1]	values[2]	values[6]	15	1			T35	2		T178	2		T229	1
auto[1]	values[2]	values[7]	5	1			T185	1		T262	1		T268	1
auto[1]	values[3]	values[0]	7	1			T271	2		T207	2		T265	3
auto[1]	values[3]	values[1]	13	1			T272	2		T273	3		T274	1
auto[1]	values[3]	values[2]	11	1			T258	1		T275	2		T276	1
auto[1]	values[3]	values[3]	6	1			T277	2		T278	2		T138	1
auto[1]	values[3]	values[4]	14	1			T163	2		T253	4		T191	1
auto[1]	values[3]	values[5]	14	1			T10	3		T185	1		T20	1
auto[1]	values[3]	values[6]	13	1			T23	3		T188	1		T20	1
auto[1]	values[3]	values[7]	19	1			T163	1		T229	4		T154	2
auto[1]	values[4]	values[0]	10	1			T22	1		T279	1		T273	2
auto[1]	values[4]	values[1]	7	1			T188	1		T214	1		T182	1
auto[1]	values[4]	values[2]	10	1			T177	1		T179	1		T275	1
auto[1]	values[4]	values[3]	34	1			T185	2		T127	1		T214	2
auto[1]	values[4]	values[4]	15	1			T193	2		T178	2		T229	1
auto[1]	values[4]	values[5]	3	1			T205	1		T179	2		-	-
auto[1]	values[4]	values[6]	15	1			T185	3		T22	5		T280	1
auto[1]	values[4]	values[7]	23	1			T3	1		T188	1		T184	4
auto[1]	values[5]	values[0]	10	1			T218	1		T280	2		T273	1
auto[1]	values[5]	values[1]	13	1			T3	1		T57	1		T188	1
auto[1]	values[5]	values[2]	13	1			T220	2		T215	1		T258	1
auto[1]	values[5]	values[3]	12	1			T192	3		T205	1		T49	2
auto[1]	values[5]	values[4]	18	1			T38	2		T20	2		T22	3
auto[1]	values[5]	values[5]	15	1			T3	4		T35	1		T127	5
auto[1]	values[5]	values[6]	22	1			T22	4		T157	1		T279	1
auto[1]	values[5]	values[7]	7	1			T20	1		T281	1		T272	1
auto[1]	values[6]	values[0]	14	1			T192	1		T76	1		T208	2
auto[1]	values[6]	values[1]	12	1			T180	1		T76	3		T184	1
auto[1]	values[6]	values[2]	9	1			T192	1		T215	4		T154	2
auto[1]	values[6]	values[3]	10	1			T178	3		T279	3		T276	1
auto[1]	values[6]	values[4]	19	1			T76	1		T127	3		T239	1
auto[1]	values[6]	values[5]	26	1			T23	1		T38	3		T127	3
auto[1]	values[6]	values[6]	17	1			T23	2		T198	4		T205	1
auto[1]	values[6]	values[7]	16	1			T193	3		T154	3		T282	2
auto[1]	values[7]	values[0]	18	1			T163	1		T193	2		T233	1
auto[1]	values[7]	values[1]	9	1			T6	1		T127	2		T193	2
auto[1]	values[7]	values[2]	12	1			T283	1		T284	1		T285	2
auto[1]	values[7]	values[3]	10	1			T229	1		T239	3		T286	1
auto[1]	values[7]	values[4]	9	1			T135	2		T157	1		T206	2
auto[1]	values[7]	values[5]	14	1			T10	1		T178	1		T287	2
auto[1]	values[7]	values[6]	12	1			T6	1		T285	2		T288	7
auto[1]	values[7]	values[7]	10	1			T39	1		T247	2		T241	1