Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

Group : spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_4b_en	2	0	2	100.00	100	1	1	2
cp_prev_addr_4b_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	4	0	4	100.00	100	1	1	0

Summary for Variable cp_addr_4b_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_4b_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1522

1

T3

6

T5

12

T6

2

auto[1]

1607

1

T3

7

T5

13

T6

10

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Summary for Variable cp_prev_addr_4b_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_prev_addr_4b_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1514

1

T3

5

T5

11

T6

3

auto[1]

1615

1

T3

8

T5

14

T6

9

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Summary for Cross cr_all

Samples crossed: cp_addr_4b_en cp_prev_addr_4b_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_4b_en

cp_prev_addr_4b_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

778

1

T3

3

T5

5

T9

2

auto[0]

auto[1]

744

1

T3

3

T5

7

T6

2

auto[1]

auto[0]

736

1

T3

2

T5

6

T6

3

auto[1]

auto[1]

871

1

T3

5

T5

7

T6

7