Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	847	1			T5	14		T14	14		T16	4
all_values[1]	847	1			T5	14		T14	14		T16	4
all_values[2]	847	1			T5	14		T14	14		T16	4
all_values[3]	847	1			T5	14		T14	14		T16	4
all_values[4]	847	1			T5	14		T14	14		T16	4
all_values[5]	847	1			T5	14		T14	14		T16	4
all_values[6]	847	1			T5	14		T14	14		T16	4
all_values[7]	847	1			T5	14		T14	14		T16	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3683

1

T5

62

T14

59

T16

22

auto[1]

3093

1

T5

50

T14

53

T16

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2637

1

T5

35

T14

47

T16

17

auto[1]

4139

1

T5

77

T14

65

T16

15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3806

1

T5

62

T14

63

T16

20

auto[1]

2970

1

T5

50

T14

49

T16

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	185	1			T5	3		T14	7		T19	3
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T5	1		T19	1		T161	3
all_values[0]	auto[0]	auto[1]	auto[0]	130	1			T5	3		T14	1		T16	1
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T5	2		T14	1		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	205	1			T5	3		T14	1		T16	2
all_values[0]	auto[1]	auto[1]	auto[1]	160	1			T5	2		T14	4		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	166	1			T5	2		T14	2		T16	3
all_values[1]	auto[0]	auto[0]	auto[1]	92	1			T5	2		T14	1		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	135	1			T5	2		T14	3		T16	1
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T21	1		T161	1		T22	1
all_values[1]	auto[1]	auto[0]	auto[1]	221	1			T5	7		T14	3		T19	3
all_values[1]	auto[1]	auto[1]	auto[1]	159	1			T5	1		T14	5		T19	1
all_values[2]	auto[0]	auto[0]	auto[0]	192	1			T5	3		T14	6		T16	4
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T5	2		T14	1		T19	2
all_values[2]	auto[0]	auto[1]	auto[0]	142	1			T5	1		T14	2		T19	2
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T5	3		T19	1		T21	1
all_values[2]	auto[1]	auto[0]	auto[1]	186	1			T5	3		T14	2		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	169	1			T5	2		T14	3		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	189	1			T5	2		T14	2		T16	1
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T5	1		T16	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T5	2		T14	1		T161	4
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T5	2		T14	4		T19	2
all_values[3]	auto[1]	auto[0]	auto[1]	202	1			T5	5		T14	4		T16	1
all_values[3]	auto[1]	auto[1]	auto[1]	158	1			T5	2		T14	3		T16	1
all_values[4]	auto[0]	auto[0]	auto[0]	179	1			T5	2		T14	3		T16	1
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T5	1		T14	2		T161	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T14	2		T16	2		T19	1
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T5	4		T14	2		T19	2
all_values[4]	auto[1]	auto[0]	auto[1]	189	1			T5	5		T14	2		T19	1
all_values[4]	auto[1]	auto[1]	auto[1]	175	1			T5	2		T14	3		T16	1
all_values[5]	auto[0]	auto[0]	auto[0]	245	1			T5	4		T14	6		T16	1
all_values[5]	auto[0]	auto[1]	auto[0]	233	1			T5	5		T14	2		T16	1
all_values[5]	auto[1]	auto[0]	auto[1]	181	1			T5	2		T14	2		T16	2
all_values[5]	auto[1]	auto[1]	auto[1]	188	1			T5	3		T14	4		T19	3
all_values[6]	auto[0]	auto[0]	auto[0]	155	1			T5	2		T14	2		T19	3
all_values[6]	auto[0]	auto[0]	auto[1]	99	1			T5	3		T14	1		T16	1
all_values[6]	auto[0]	auto[1]	auto[0]	122	1			T14	1		T19	1		T21	1
all_values[6]	auto[0]	auto[1]	auto[1]	86	1			T5	2		T14	2		T16	1
all_values[6]	auto[1]	auto[0]	auto[1]	205	1			T5	4		T14	5		T16	2
all_values[6]	auto[1]	auto[1]	auto[1]	180	1			T5	3		T14	3		T19	1
all_values[7]	auto[0]	auto[0]	auto[0]	169	1			T14	5		T16	1		T19	2
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T5	2		T21	1		T161	1
all_values[7]	auto[0]	auto[1]	auto[0]	118	1			T5	4		T14	2		T16	1
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T5	2		T14	2		T19	2
all_values[7]	auto[1]	auto[0]	auto[1]	211	1			T5	3		T14	2		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	181	1			T5	3		T14	3		T19	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal