Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1669

1

T2

2

T5

2

T6

6

auto[1]

1705

1

T2

3

T3

2

T5

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1830

1

T3

2

T5

5

T6

9

auto[1]

1544

1

T2

5

T6

5

T24

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2671

1

T2

5

T3

2

T5

5

auto[1]

703

1

T6

6

T13

2

T25

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	681	1			T2	2		T5	1		T6	1
valid[1]	654	1			T2	1		T3	1		T5	1
valid[2]	685	1			T3	1		T5	1		T6	5
valid[3]	682	1			T2	1		T5	1		T6	2
valid[4]	672	1			T2	1		T5	1		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	106	1			T5	1		T25	2		T34	1
auto[0]	auto[0]	valid[0]	auto[1]	163	1			T2	1		T24	1		T82	5
auto[0]	auto[0]	valid[1]	auto[0]	103	1			T5	1		T6	1		T15	4
auto[0]	auto[0]	valid[1]	auto[1]	143	1			T24	1		T68	1		T82	1
auto[0]	auto[0]	valid[2]	auto[0]	113	1			T6	2		T25	1		T26	2
auto[0]	auto[0]	valid[2]	auto[1]	159	1			T6	1		T82	3		T314	3
auto[0]	auto[0]	valid[3]	auto[0]	121	1			T25	2		T15	2		T26	1
auto[0]	auto[0]	valid[3]	auto[1]	153	1			T2	1		T6	1		T27	2
auto[0]	auto[0]	valid[4]	auto[0]	119	1			T15	1		T26	1		T28	1
auto[0]	auto[0]	valid[4]	auto[1]	149	1			T24	1		T27	1		T73	1
auto[0]	auto[1]	valid[0]	auto[0]	121	1			T13	3		T25	2		T15	5
auto[0]	auto[1]	valid[0]	auto[1]	142	1			T2	1		T27	2		T73	1
auto[0]	auto[1]	valid[1]	auto[0]	109	1			T3	1		T25	1		T15	1
auto[0]	auto[1]	valid[1]	auto[1]	158	1			T2	1		T6	1		T24	1
auto[0]	auto[1]	valid[2]	auto[0]	115	1			T3	1		T5	1		T25	4
auto[0]	auto[1]	valid[2]	auto[1]	173	1			T6	1		T68	1		T82	1
auto[0]	auto[1]	valid[3]	auto[0]	108	1			T5	1		T25	2		T15	2
auto[0]	auto[1]	valid[3]	auto[1]	147	1			T6	1		T82	4		T314	4
auto[0]	auto[1]	valid[4]	auto[0]	112	1			T5	1		T25	1		T15	2
auto[0]	auto[1]	valid[4]	auto[1]	157	1			T2	1		T27	5		T81	1
auto[1]	auto[0]	valid[0]	auto[0]	63	1			T13	1		T25	1		T15	1
auto[1]	auto[0]	valid[1]	auto[0]	63	1			T25	1		T72	1		T304	1
auto[1]	auto[0]	valid[2]	auto[0]	61	1			T25	1		T15	4		T26	1
auto[1]	auto[0]	valid[3]	auto[0]	80	1			T13	1		T15	1		T28	1
auto[1]	auto[0]	valid[4]	auto[0]	73	1			T6	1		T15	1		T28	1
auto[1]	auto[1]	valid[0]	auto[0]	86	1			T6	1		T15	2		T26	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T6	3		T34	1		T70	1
auto[1]	auto[1]	valid[2]	auto[0]	64	1			T6	1		T26	1		T308	1
auto[1]	auto[1]	valid[3]	auto[0]	73	1			T25	1		T15	1		T72	1
auto[1]	auto[1]	valid[4]	auto[0]	62	1			T15	2		T26	1		T81	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal