Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45178

1

T3

111

T5

100

T6

278

auto[1]

15600

1

T2

5

T5

20

T6

75

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44343

1

T2

5

T3

74

T5

81

auto[1]

16435

1

T3

37

T5

39

T6

126

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31317	1			T2	5		T3	61		T5	62
others[1]	5112	1			T3	9		T5	10		T6	33
others[2]	5025	1			T3	8		T5	18		T6	29
others[3]	5752	1			T3	15		T5	9		T6	30
interest[1]	3324	1			T3	4		T5	7		T6	14
interest[4]	20461	1			T2	5		T3	40		T5	37
interest[64]	10248	1			T3	14		T5	14		T6	55

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14815	1			T3	40		T5	30		T6	84
auto[0]	auto[0]	others[1]	2433	1			T3	6		T5	5		T6	13
auto[0]	auto[0]	others[2]	2393	1			T3	6		T5	8		T6	11
auto[0]	auto[0]	others[3]	2716	1			T3	9		T5	6		T6	19
auto[0]	auto[0]	interest[1]	1569	1			T3	2		T5	5		T6	6
auto[0]	auto[0]	interest[4]	9638	1			T3	27		T5	21		T6	59
auto[0]	auto[0]	interest[64]	4817	1			T3	11		T5	7		T6	19
auto[0]	auto[1]	others[0]	8092	1			T2	5		T5	9		T6	43
auto[0]	auto[1]	others[1]	1310	1			T5	2		T6	7		T26	4
auto[0]	auto[1]	others[2]	1209	1			T5	3		T6	6		T26	3
auto[0]	auto[1]	others[3]	1492	1			T5	2		T6	4		T26	4
auto[0]	auto[1]	interest[1]	866	1			T5	2		T6	4		T26	2
auto[0]	auto[1]	interest[4]	5437	1			T2	5		T5	5		T6	32
auto[0]	auto[1]	interest[64]	2631	1			T5	2		T6	11		T26	8
auto[1]	auto[0]	others[0]	8410	1			T3	21		T5	23		T6	65
auto[1]	auto[0]	others[1]	1369	1			T3	3		T5	3		T6	13
auto[1]	auto[0]	others[2]	1423	1			T3	2		T5	7		T6	12
auto[1]	auto[0]	others[3]	1544	1			T3	6		T5	1		T6	7
auto[1]	auto[0]	interest[1]	889	1			T3	2		T6	4		T13	1
auto[1]	auto[0]	interest[4]	5386	1			T3	13		T5	11		T6	38
auto[1]	auto[0]	interest[64]	2800	1			T3	3		T5	5		T6	25

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal