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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.10 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1149
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T1033 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3980602368 Jul 05 05:55:38 PM PDT 24 Jul 05 05:55:40 PM PDT 24 37852688 ps
T112 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2976962248 Jul 05 05:55:31 PM PDT 24 Jul 05 05:55:45 PM PDT 24 819733511 ps
T101 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2877189048 Jul 05 05:55:31 PM PDT 24 Jul 05 05:55:36 PM PDT 24 265733005 ps
T78 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1000212451 Jul 05 05:55:21 PM PDT 24 Jul 05 05:55:22 PM PDT 24 516426742 ps
T102 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1223601791 Jul 05 05:55:26 PM PDT 24 Jul 05 05:55:29 PM PDT 24 30491604 ps
T141 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.545321538 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:38 PM PDT 24 289871610 ps
T151 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.436849253 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:33 PM PDT 24 302270266 ps
T142 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3248029818 Jul 05 05:55:31 PM PDT 24 Jul 05 05:55:36 PM PDT 24 59798678 ps
T1034 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.49828428 Jul 05 05:55:17 PM PDT 24 Jul 05 05:55:31 PM PDT 24 636505676 ps
T121 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.186873068 Jul 05 05:55:44 PM PDT 24 Jul 05 05:55:48 PM PDT 24 451383221 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3081545836 Jul 05 05:55:23 PM PDT 24 Jul 05 05:55:48 PM PDT 24 3642857261 ps
T1035 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.706378497 Jul 05 05:55:36 PM PDT 24 Jul 05 05:55:38 PM PDT 24 23199898 ps
T1036 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4146803213 Jul 05 05:55:34 PM PDT 24 Jul 05 05:55:39 PM PDT 24 238861803 ps
T1037 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.928102520 Jul 05 05:55:44 PM PDT 24 Jul 05 05:55:45 PM PDT 24 14274799 ps
T1038 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2415878622 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:37 PM PDT 24 38005373 ps
T1039 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4051343808 Jul 05 05:55:28 PM PDT 24 Jul 05 05:55:31 PM PDT 24 51836067 ps
T1040 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1413046276 Jul 05 05:55:37 PM PDT 24 Jul 05 05:55:38 PM PDT 24 30059330 ps
T1041 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3693176720 Jul 05 05:55:37 PM PDT 24 Jul 05 05:55:40 PM PDT 24 52312882 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.273855877 Jul 05 05:55:28 PM PDT 24 Jul 05 05:55:42 PM PDT 24 364287107 ps
T1042 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1874544879 Jul 05 05:55:27 PM PDT 24 Jul 05 05:55:36 PM PDT 24 1180726819 ps
T1043 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.142926429 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:38 PM PDT 24 285445823 ps
T105 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1964048858 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:34 PM PDT 24 129176992 ps
T1044 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1652528993 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:31 PM PDT 24 13173717 ps
T1045 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2175727113 Jul 05 05:55:47 PM PDT 24 Jul 05 05:55:48 PM PDT 24 11831593 ps
T1046 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3315920732 Jul 05 05:55:43 PM PDT 24 Jul 05 05:55:44 PM PDT 24 17366597 ps
T104 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1204859301 Jul 05 05:55:28 PM PDT 24 Jul 05 05:55:31 PM PDT 24 61916619 ps
T106 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3676627014 Jul 05 05:55:26 PM PDT 24 Jul 05 05:55:30 PM PDT 24 111020744 ps
T1047 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2087576123 Jul 05 05:55:39 PM PDT 24 Jul 05 05:55:41 PM PDT 24 17268015 ps
T124 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2670508107 Jul 05 05:55:39 PM PDT 24 Jul 05 05:55:43 PM PDT 24 343447264 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2443589616 Jul 05 05:55:30 PM PDT 24 Jul 05 05:55:34 PM PDT 24 27874122 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2981253991 Jul 05 05:55:37 PM PDT 24 Jul 05 05:55:41 PM PDT 24 50780452 ps
T170 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2018602445 Jul 05 05:55:33 PM PDT 24 Jul 05 05:55:41 PM PDT 24 416099474 ps
T1050 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1078701096 Jul 05 05:55:43 PM PDT 24 Jul 05 05:55:44 PM PDT 24 49212160 ps
T166 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2332599500 Jul 05 05:55:38 PM PDT 24 Jul 05 05:55:46 PM PDT 24 855373443 ps
T168 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2680088630 Jul 05 05:55:27 PM PDT 24 Jul 05 05:55:51 PM PDT 24 822755157 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.911261412 Jul 05 05:55:14 PM PDT 24 Jul 05 05:55:16 PM PDT 24 75859392 ps
T1052 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2682516387 Jul 05 05:55:34 PM PDT 24 Jul 05 05:55:36 PM PDT 24 16866947 ps
T1053 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1812658954 Jul 05 05:55:36 PM PDT 24 Jul 05 05:55:38 PM PDT 24 28762416 ps
T1054 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1860897954 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:37 PM PDT 24 52547080 ps
T1055 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2175962208 Jul 05 05:55:40 PM PDT 24 Jul 05 05:55:41 PM PDT 24 41303122 ps
T125 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2410300152 Jul 05 05:55:34 PM PDT 24 Jul 05 05:55:37 PM PDT 24 211633599 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3308469404 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:40 PM PDT 24 338156443 ps
T1057 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2164332761 Jul 05 05:55:50 PM PDT 24 Jul 05 05:55:52 PM PDT 24 12823988 ps
T79 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.601262473 Jul 05 05:55:18 PM PDT 24 Jul 05 05:55:20 PM PDT 24 80522477 ps
T1058 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1758288396 Jul 05 05:55:36 PM PDT 24 Jul 05 05:55:40 PM PDT 24 171893222 ps
T1059 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1837223361 Jul 05 05:55:36 PM PDT 24 Jul 05 05:55:41 PM PDT 24 243365777 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3761491971 Jul 05 05:55:16 PM PDT 24 Jul 05 05:55:18 PM PDT 24 140491095 ps
T1060 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.492828980 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:32 PM PDT 24 20366724 ps
T152 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3454070480 Jul 05 05:55:31 PM PDT 24 Jul 05 05:55:34 PM PDT 24 149555482 ps
T1061 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.756033718 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:27 PM PDT 24 29650359 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4252253782 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:28 PM PDT 24 287569709 ps
T160 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3096810734 Jul 05 05:55:34 PM PDT 24 Jul 05 05:55:38 PM PDT 24 1895529264 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3139785764 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:27 PM PDT 24 34662357 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4052586742 Jul 05 05:55:28 PM PDT 24 Jul 05 05:55:32 PM PDT 24 96804912 ps
T1065 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1208889887 Jul 05 05:55:36 PM PDT 24 Jul 05 05:55:38 PM PDT 24 28009903 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1722812576 Jul 05 05:55:23 PM PDT 24 Jul 05 05:55:26 PM PDT 24 164994652 ps
T1067 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3523034170 Jul 05 05:55:30 PM PDT 24 Jul 05 05:55:35 PM PDT 24 112374175 ps
T1068 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3989546248 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:39 PM PDT 24 139660957 ps
T1069 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2542215942 Jul 05 05:55:40 PM PDT 24 Jul 05 05:55:42 PM PDT 24 28321063 ps
T103 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3241727128 Jul 05 05:55:32 PM PDT 24 Jul 05 05:55:37 PM PDT 24 651690628 ps
T169 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1987367985 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:50 PM PDT 24 1177955391 ps
T171 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2051309704 Jul 05 05:55:37 PM PDT 24 Jul 05 05:55:44 PM PDT 24 113252342 ps
T1070 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3674369247 Jul 05 05:55:47 PM PDT 24 Jul 05 05:55:48 PM PDT 24 19053870 ps
T1071 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.525817112 Jul 05 05:55:31 PM PDT 24 Jul 05 05:55:33 PM PDT 24 50712018 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.48841179 Jul 05 05:55:12 PM PDT 24 Jul 05 05:55:15 PM PDT 24 72548610 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4066212104 Jul 05 05:55:16 PM PDT 24 Jul 05 05:55:18 PM PDT 24 11924474 ps
T1074 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.957514193 Jul 05 05:55:28 PM PDT 24 Jul 05 05:56:06 PM PDT 24 3768507624 ps
T167 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.20014212 Jul 05 05:55:30 PM PDT 24 Jul 05 05:55:45 PM PDT 24 820517616 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1913836005 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:35 PM PDT 24 1735975384 ps
T1076 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3203685216 Jul 05 05:55:43 PM PDT 24 Jul 05 05:55:45 PM PDT 24 55922723 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1699443884 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:39 PM PDT 24 288394130 ps
T1078 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4292180113 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:30 PM PDT 24 121841514 ps
T1079 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3901310352 Jul 05 05:55:40 PM PDT 24 Jul 05 05:55:42 PM PDT 24 49721676 ps
T108 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3504782954 Jul 05 05:55:44 PM PDT 24 Jul 05 05:55:46 PM PDT 24 162641815 ps
T1080 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3313649126 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:40 PM PDT 24 146679941 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2012415943 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:41 PM PDT 24 613013682 ps
T1082 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2792767224 Jul 05 05:55:34 PM PDT 24 Jul 05 05:55:44 PM PDT 24 1529249479 ps
T1083 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2272581694 Jul 05 05:55:17 PM PDT 24 Jul 05 05:55:18 PM PDT 24 30298222 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4144657847 Jul 05 05:55:19 PM PDT 24 Jul 05 05:55:34 PM PDT 24 726039344 ps
T1085 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.472975555 Jul 05 05:55:37 PM PDT 24 Jul 05 05:55:39 PM PDT 24 15427250 ps
T109 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1301756754 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:36 PM PDT 24 553783498 ps
T1086 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.758266595 Jul 05 05:55:30 PM PDT 24 Jul 05 05:55:36 PM PDT 24 163410474 ps
T1087 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.926783722 Jul 05 05:55:37 PM PDT 24 Jul 05 05:55:38 PM PDT 24 22465431 ps
T1088 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3215894527 Jul 05 05:55:31 PM PDT 24 Jul 05 05:55:34 PM PDT 24 48187150 ps
T1089 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1017458716 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:34 PM PDT 24 203423121 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.84133658 Jul 05 05:55:24 PM PDT 24 Jul 05 05:55:27 PM PDT 24 150187347 ps
T1091 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3654561577 Jul 05 05:55:38 PM PDT 24 Jul 05 05:55:42 PM PDT 24 108754829 ps
T1092 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1635686566 Jul 05 05:55:26 PM PDT 24 Jul 05 05:55:30 PM PDT 24 106083785 ps
T1093 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1799604075 Jul 05 05:55:11 PM PDT 24 Jul 05 05:55:14 PM PDT 24 63285983 ps
T1094 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1835076642 Jul 05 05:55:30 PM PDT 24 Jul 05 05:55:50 PM PDT 24 694057667 ps
T1095 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.946497278 Jul 05 05:55:26 PM PDT 24 Jul 05 05:55:29 PM PDT 24 165635103 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.323975073 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:34 PM PDT 24 530995915 ps
T107 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1527646847 Jul 05 05:55:31 PM PDT 24 Jul 05 05:55:36 PM PDT 24 561875242 ps
T1097 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.927323510 Jul 05 05:55:44 PM PDT 24 Jul 05 05:55:46 PM PDT 24 15641750 ps
T1098 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.193964967 Jul 05 05:55:23 PM PDT 24 Jul 05 05:55:27 PM PDT 24 171021530 ps
T1099 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.141019014 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:28 PM PDT 24 56750244 ps
T1100 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1562197476 Jul 05 05:55:20 PM PDT 24 Jul 05 05:55:24 PM PDT 24 152891399 ps
T172 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2998642165 Jul 05 05:55:30 PM PDT 24 Jul 05 05:55:40 PM PDT 24 541250216 ps
T1101 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2532571801 Jul 05 05:55:30 PM PDT 24 Jul 05 05:55:35 PM PDT 24 550999697 ps
T1102 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.669366761 Jul 05 05:55:36 PM PDT 24 Jul 05 05:55:41 PM PDT 24 216745205 ps
T1103 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1893729807 Jul 05 06:01:35 PM PDT 24 Jul 05 06:01:36 PM PDT 24 10828430 ps
T1104 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2655524515 Jul 05 05:55:28 PM PDT 24 Jul 05 05:55:29 PM PDT 24 10716805 ps
T1105 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1242721376 Jul 05 05:55:17 PM PDT 24 Jul 05 05:55:22 PM PDT 24 673577477 ps
T1106 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2299225282 Jul 05 05:55:19 PM PDT 24 Jul 05 05:55:32 PM PDT 24 1783628338 ps
T1107 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3704012575 Jul 05 05:55:39 PM PDT 24 Jul 05 05:55:43 PM PDT 24 403812281 ps
T1108 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1096183163 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:40 PM PDT 24 57828164 ps
T1109 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.271897076 Jul 05 05:55:38 PM PDT 24 Jul 05 05:55:47 PM PDT 24 1104630527 ps
T1110 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.798575710 Jul 05 05:55:24 PM PDT 24 Jul 05 05:55:27 PM PDT 24 115850916 ps
T1111 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1684229502 Jul 05 05:55:38 PM PDT 24 Jul 05 05:55:42 PM PDT 24 122932287 ps
T1112 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2874861013 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:31 PM PDT 24 24799496 ps
T1113 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.817859047 Jul 05 05:55:32 PM PDT 24 Jul 05 05:55:35 PM PDT 24 109602007 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1850152286 Jul 05 05:55:22 PM PDT 24 Jul 05 05:55:26 PM PDT 24 109175111 ps
T80 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3422162064 Jul 05 05:55:24 PM PDT 24 Jul 05 05:55:26 PM PDT 24 47211012 ps
T1115 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3062543076 Jul 05 05:55:17 PM PDT 24 Jul 05 05:55:18 PM PDT 24 43976571 ps
T1116 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2267299081 Jul 05 05:55:39 PM PDT 24 Jul 05 05:55:41 PM PDT 24 16416755 ps
T1117 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3174624774 Jul 05 05:55:49 PM PDT 24 Jul 05 05:55:50 PM PDT 24 23214809 ps
T1118 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3264712776 Jul 05 05:55:17 PM PDT 24 Jul 05 05:55:19 PM PDT 24 35683514 ps
T1119 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1866141065 Jul 05 05:55:49 PM PDT 24 Jul 05 05:55:51 PM PDT 24 16265373 ps
T1120 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.497016559 Jul 05 05:55:24 PM PDT 24 Jul 05 05:55:27 PM PDT 24 88040638 ps
T1121 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.582767224 Jul 05 05:55:39 PM PDT 24 Jul 05 05:55:44 PM PDT 24 633087786 ps
T1122 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3316413312 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:31 PM PDT 24 24971919 ps
T1123 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3600645545 Jul 05 05:55:32 PM PDT 24 Jul 05 05:55:34 PM PDT 24 33971309 ps
T1124 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3976484207 Jul 05 05:55:23 PM PDT 24 Jul 05 05:55:25 PM PDT 24 14226299 ps
T1125 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2200042247 Jul 05 05:55:19 PM PDT 24 Jul 05 05:55:21 PM PDT 24 89491418 ps
T1126 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3704021112 Jul 05 05:55:34 PM PDT 24 Jul 05 05:55:57 PM PDT 24 3416649369 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4175725845 Jul 05 05:55:18 PM PDT 24 Jul 05 05:55:41 PM PDT 24 948418150 ps
T1128 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1251456931 Jul 05 05:55:16 PM PDT 24 Jul 05 05:55:22 PM PDT 24 170184169 ps
T1129 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1185424647 Jul 05 05:55:27 PM PDT 24 Jul 05 05:55:29 PM PDT 24 33823374 ps
T1130 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1804229161 Jul 05 05:55:36 PM PDT 24 Jul 05 05:55:39 PM PDT 24 165892759 ps
T1131 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3143395767 Jul 05 05:55:35 PM PDT 24 Jul 05 05:55:38 PM PDT 24 43996003 ps
T1132 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2673543662 Jul 05 05:55:48 PM PDT 24 Jul 05 05:55:49 PM PDT 24 32460479 ps
T1133 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2728162915 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:29 PM PDT 24 1534388638 ps
T1134 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3488515327 Jul 05 05:55:42 PM PDT 24 Jul 05 05:55:43 PM PDT 24 15979064 ps
T1135 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.154427939 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:33 PM PDT 24 155173955 ps
T1136 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2110582007 Jul 05 05:55:37 PM PDT 24 Jul 05 05:55:40 PM PDT 24 51838080 ps
T1137 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2593981295 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:27 PM PDT 24 122589099 ps
T1138 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2877068927 Jul 05 05:55:25 PM PDT 24 Jul 05 05:55:28 PM PDT 24 12415445 ps
T165 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3768001679 Jul 05 05:55:31 PM PDT 24 Jul 05 05:55:36 PM PDT 24 2845337170 ps
T1139 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3164208607 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:42 PM PDT 24 2444993372 ps
T1140 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1454842787 Jul 05 05:55:40 PM PDT 24 Jul 05 05:55:41 PM PDT 24 15195807 ps
T1141 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1986934336 Jul 05 05:55:38 PM PDT 24 Jul 05 05:55:39 PM PDT 24 45864117 ps
T1142 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3228568904 Jul 05 05:55:40 PM PDT 24 Jul 05 05:55:42 PM PDT 24 15891576 ps
T1143 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.243904304 Jul 05 05:55:33 PM PDT 24 Jul 05 05:55:36 PM PDT 24 54501597 ps
T1144 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3267170056 Jul 05 05:55:23 PM PDT 24 Jul 05 05:55:25 PM PDT 24 13702811 ps
T1145 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.556613394 Jul 05 05:55:30 PM PDT 24 Jul 05 05:55:32 PM PDT 24 34733582 ps
T1146 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4032739047 Jul 05 05:55:54 PM PDT 24 Jul 05 05:55:56 PM PDT 24 152778564 ps
T1147 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3610454926 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:32 PM PDT 24 133383364 ps
T1148 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2424445889 Jul 05 05:55:24 PM PDT 24 Jul 05 05:55:27 PM PDT 24 72364622 ps
T1149 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3972287679 Jul 05 05:55:29 PM PDT 24 Jul 05 05:55:31 PM PDT 24 21980496 ps

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3344685432
Short name T6
Test name
Test status
Simulation time 4414999977 ps
CPU time 104.66 seconds
Started Jul 05 06:26:33 PM PDT 24
Finished Jul 05 06:28:18 PM PDT 24
Peak memory 266788 kb
Host smart-64d395d4-1a81-425d-8705-e3c22869d09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344685432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3344685432
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3179031767
Short name T5
Test name
Test status
Simulation time 5635564370 ps
CPU time 84.66 seconds
Started Jul 05 06:28:02 PM PDT 24
Finished Jul 05 06:29:27 PM PDT 24
Peak memory 256284 kb
Host smart-080085d6-e384-4893-881f-541384612b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179031767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3179031767
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.155293824
Short name T15
Test name
Test status
Simulation time 62575855277 ps
CPU time 556.47 seconds
Started Jul 05 06:28:18 PM PDT 24
Finished Jul 05 06:37:36 PM PDT 24
Peak memory 266740 kb
Host smart-3a44e2f2-59b0-474a-ae86-7be2f19093bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155293824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.155293824
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.98053003
Short name T110
Test name
Test status
Simulation time 1818032439 ps
CPU time 21.64 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:53 PM PDT 24
Peak memory 216476 kb
Host smart-75103bee-3b8c-4d0c-a892-d4f4ad300db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98053003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.98053003
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1838218459
Short name T127
Test name
Test status
Simulation time 15679884745 ps
CPU time 157.99 seconds
Started Jul 05 06:29:54 PM PDT 24
Finished Jul 05 06:32:32 PM PDT 24
Peak memory 271720 kb
Host smart-2527588a-f563-4a90-ae79-e6c57351b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838218459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1838218459
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1273369941
Short name T62
Test name
Test status
Simulation time 39510034 ps
CPU time 0.74 seconds
Started Jul 05 06:24:40 PM PDT 24
Finished Jul 05 06:24:41 PM PDT 24
Peak memory 217096 kb
Host smart-7e12c648-68ce-4b27-a63a-13a157058894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273369941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1273369941
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3932863006
Short name T184
Test name
Test status
Simulation time 136171981496 ps
CPU time 379.82 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:34:52 PM PDT 24
Peak memory 266316 kb
Host smart-64776da2-c1ab-4eee-ad28-936a93942bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932863006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3932863006
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2665975762
Short name T154
Test name
Test status
Simulation time 30921606199 ps
CPU time 191.99 seconds
Started Jul 05 06:27:23 PM PDT 24
Finished Jul 05 06:30:35 PM PDT 24
Peak memory 286108 kb
Host smart-b7b13ad3-bcdb-4d76-aaf5-f7c6f0812337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665975762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2665975762
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.462880153
Short name T3
Test name
Test status
Simulation time 28388019606 ps
CPU time 290.87 seconds
Started Jul 05 06:28:59 PM PDT 24
Finished Jul 05 06:33:51 PM PDT 24
Peak memory 254456 kb
Host smart-a5cc6218-1ebf-4b48-b035-46beeb020d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462880153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.462880153
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3079459375
Short name T163
Test name
Test status
Simulation time 125489593051 ps
CPU time 163.35 seconds
Started Jul 05 06:25:22 PM PDT 24
Finished Jul 05 06:28:06 PM PDT 24
Peak memory 266868 kb
Host smart-cb34505c-a7e3-42ca-88c3-5e4655918ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079459375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3079459375
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.479098502
Short name T17
Test name
Test status
Simulation time 306155820 ps
CPU time 0.92 seconds
Started Jul 05 06:24:54 PM PDT 24
Finished Jul 05 06:24:55 PM PDT 24
Peak memory 235400 kb
Host smart-20b33e78-c413-4ce7-8021-32eb90471b89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479098502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.479098502
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2877189048
Short name T101
Test name
Test status
Simulation time 265733005 ps
CPU time 3.26 seconds
Started Jul 05 05:55:31 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 215648 kb
Host smart-b489e83a-caa3-4396-a6bf-818be407e76f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877189048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2877189048
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1195034808
Short name T185
Test name
Test status
Simulation time 43753992254 ps
CPU time 149.3 seconds
Started Jul 05 06:29:56 PM PDT 24
Finished Jul 05 06:32:26 PM PDT 24
Peak memory 266828 kb
Host smart-80e4e744-52a4-470f-bda4-67614daf0efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195034808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1195034808
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1005072610
Short name T11
Test name
Test status
Simulation time 3518848134 ps
CPU time 44.01 seconds
Started Jul 05 06:25:22 PM PDT 24
Finished Jul 05 06:26:07 PM PDT 24
Peak memory 225668 kb
Host smart-f5f4d7d8-8f76-4801-9b00-d22417070bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005072610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1005072610
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3562699507
Short name T178
Test name
Test status
Simulation time 35127511162 ps
CPU time 385.49 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:33:07 PM PDT 24
Peak memory 257268 kb
Host smart-ee630328-89b4-41a5-94f3-3f21407cc371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562699507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3562699507
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2357307992
Short name T76
Test name
Test status
Simulation time 6173336634 ps
CPU time 87.03 seconds
Started Jul 05 06:31:05 PM PDT 24
Finished Jul 05 06:32:33 PM PDT 24
Peak memory 265464 kb
Host smart-efa1db45-5ed3-43e2-b037-403b40d9e91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357307992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2357307992
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.585092146
Short name T114
Test name
Test status
Simulation time 313213803 ps
CPU time 20.71 seconds
Started Jul 05 05:55:23 PM PDT 24
Finished Jul 05 05:55:44 PM PDT 24
Peak memory 215528 kb
Host smart-cb363036-e567-4c4f-aa25-56a98ea9d424
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585092146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.585092146
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2527365170
Short name T57
Test name
Test status
Simulation time 3677873003 ps
CPU time 92.85 seconds
Started Jul 05 06:26:59 PM PDT 24
Finished Jul 05 06:28:32 PM PDT 24
Peak memory 254844 kb
Host smart-49d22467-1c1f-48f8-9e0e-a5d74f83d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527365170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2527365170
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1072996420
Short name T273
Test name
Test status
Simulation time 51060721514 ps
CPU time 188.5 seconds
Started Jul 05 06:28:47 PM PDT 24
Finished Jul 05 06:31:56 PM PDT 24
Peak memory 271884 kb
Host smart-9cb4507f-7c35-46c7-93ff-a197e07e8797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072996420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1072996420
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1893885796
Short name T1
Test name
Test status
Simulation time 35259205 ps
CPU time 1.1 seconds
Started Jul 05 06:24:38 PM PDT 24
Finished Jul 05 06:24:40 PM PDT 24
Peak memory 217644 kb
Host smart-dc10f299-1f95-41d7-ba45-b44bc1826134
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893885796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1893885796
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2076974927
Short name T192
Test name
Test status
Simulation time 5895415028 ps
CPU time 141.59 seconds
Started Jul 05 06:30:42 PM PDT 24
Finished Jul 05 06:33:04 PM PDT 24
Peak memory 269236 kb
Host smart-8d34596b-44b6-40b6-885a-f669bb1e8772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076974927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2076974927
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.982476148
Short name T157
Test name
Test status
Simulation time 31004363734 ps
CPU time 169.33 seconds
Started Jul 05 06:29:35 PM PDT 24
Finished Jul 05 06:32:25 PM PDT 24
Peak memory 268852 kb
Host smart-1fd2d455-7b7a-4730-8144-b8566fbed1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982476148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.982476148
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.272104576
Short name T180
Test name
Test status
Simulation time 4480818991 ps
CPU time 57.28 seconds
Started Jul 05 06:30:36 PM PDT 24
Finished Jul 05 06:31:34 PM PDT 24
Peak memory 234028 kb
Host smart-6b870a06-cddc-40b9-8167-a62d1f5650e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272104576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.272104576
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3714603146
Short name T258
Test name
Test status
Simulation time 34803502642 ps
CPU time 324.79 seconds
Started Jul 05 06:28:25 PM PDT 24
Finished Jul 05 06:33:50 PM PDT 24
Peak memory 266820 kb
Host smart-7e1e777f-c15d-41ad-b9e4-82895b00cff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714603146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3714603146
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1714725512
Short name T278
Test name
Test status
Simulation time 9306111578 ps
CPU time 106.39 seconds
Started Jul 05 06:28:46 PM PDT 24
Finished Jul 05 06:30:33 PM PDT 24
Peak memory 273804 kb
Host smart-3a010fd2-0ad4-43c5-8f3b-e3f24686f1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714725512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1714725512
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1275538402
Short name T339
Test name
Test status
Simulation time 31823958 ps
CPU time 0.72 seconds
Started Jul 05 06:27:31 PM PDT 24
Finished Jul 05 06:27:32 PM PDT 24
Peak memory 206376 kb
Host smart-71ba7fec-eeb1-417a-922c-7e98940c0c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275538402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1275538402
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3241727128
Short name T103
Test name
Test status
Simulation time 651690628 ps
CPU time 4 seconds
Started Jul 05 05:55:32 PM PDT 24
Finished Jul 05 05:55:37 PM PDT 24
Peak memory 215756 kb
Host smart-44a30f4b-4a96-4c86-8179-1821a1561794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241727128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3241727128
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1667972588
Short name T96
Test name
Test status
Simulation time 5765442064 ps
CPU time 21.58 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:53 PM PDT 24
Peak memory 215752 kb
Host smart-43f52577-5e2b-469f-a805-6afcb7c7ac7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667972588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1667972588
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3173784318
Short name T205
Test name
Test status
Simulation time 3904168041 ps
CPU time 82.13 seconds
Started Jul 05 06:28:52 PM PDT 24
Finished Jul 05 06:30:14 PM PDT 24
Peak memory 265572 kb
Host smart-300610d6-bc34-47b4-8dbc-654b0557726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173784318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3173784318
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.729356065
Short name T207
Test name
Test status
Simulation time 14569543235 ps
CPU time 72.57 seconds
Started Jul 05 06:29:32 PM PDT 24
Finished Jul 05 06:30:45 PM PDT 24
Peak memory 256828 kb
Host smart-64944541-4da2-4020-a93c-d0e554ddc758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729356065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.729356065
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2978755303
Short name T295
Test name
Test status
Simulation time 17617125615 ps
CPU time 60.35 seconds
Started Jul 05 06:30:30 PM PDT 24
Finished Jul 05 06:31:30 PM PDT 24
Peak memory 233956 kb
Host smart-63ad6fc4-3a97-4de6-845f-c2d8c677be63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978755303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2978755303
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2511238445
Short name T45
Test name
Test status
Simulation time 86630999177 ps
CPU time 232.1 seconds
Started Jul 05 06:25:21 PM PDT 24
Finished Jul 05 06:29:14 PM PDT 24
Peak memory 250404 kb
Host smart-dc5b79c0-19c5-43cc-baf8-8e1d1f2bde03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511238445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2511238445
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.586468333
Short name T851
Test name
Test status
Simulation time 35275077916 ps
CPU time 306.47 seconds
Started Jul 05 06:28:55 PM PDT 24
Finished Jul 05 06:34:02 PM PDT 24
Peak memory 250572 kb
Host smart-7aba70ae-1cb3-42c4-b10b-461da0dd1e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586468333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.586468333
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3746376241
Short name T314
Test name
Test status
Simulation time 884164265 ps
CPU time 5.92 seconds
Started Jul 05 06:25:51 PM PDT 24
Finished Jul 05 06:25:57 PM PDT 24
Peak memory 217388 kb
Host smart-a3e8d4cd-a9cb-40a0-933b-b888cfb95bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746376241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3746376241
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2429363243
Short name T283
Test name
Test status
Simulation time 45348581052 ps
CPU time 311.99 seconds
Started Jul 05 06:31:20 PM PDT 24
Finished Jul 05 06:36:32 PM PDT 24
Peak memory 251660 kb
Host smart-db4b5e9b-ff1b-4e27-8ef0-cb0da13e0d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429363243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2429363243
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1546769771
Short name T214
Test name
Test status
Simulation time 121336128017 ps
CPU time 186.11 seconds
Started Jul 05 06:27:10 PM PDT 24
Finished Jul 05 06:30:16 PM PDT 24
Peak memory 266816 kb
Host smart-538665b2-6bed-4fc0-b4bc-234d565cd4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546769771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1546769771
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2762111902
Short name T266
Test name
Test status
Simulation time 971332810 ps
CPU time 22.94 seconds
Started Jul 05 06:27:55 PM PDT 24
Finished Jul 05 06:28:18 PM PDT 24
Peak memory 236916 kb
Host smart-33234382-bc59-4025-adbe-2508184a07ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762111902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2762111902
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4245081146
Short name T83
Test name
Test status
Simulation time 36335705743 ps
CPU time 68 seconds
Started Jul 05 06:24:49 PM PDT 24
Finished Jul 05 06:25:57 PM PDT 24
Peak memory 251028 kb
Host smart-23f29b19-3149-447d-8790-15edc611c400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245081146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4245081146
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1658142304
Short name T90
Test name
Test status
Simulation time 3547978646 ps
CPU time 10.35 seconds
Started Jul 05 06:30:44 PM PDT 24
Finished Jul 05 06:30:55 PM PDT 24
Peak memory 241216 kb
Host smart-944f37f6-a541-4bac-9c80-1a36795a2502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658142304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1658142304
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.464386840
Short name T16
Test name
Test status
Simulation time 30756976935 ps
CPU time 201.82 seconds
Started Jul 05 06:27:21 PM PDT 24
Finished Jul 05 06:30:43 PM PDT 24
Peak memory 258200 kb
Host smart-ab3ee36e-1ac9-48db-b6b8-4a330c5be3a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464386840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.464386840
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.115858723
Short name T97
Test name
Test status
Simulation time 1171260198 ps
CPU time 18.46 seconds
Started Jul 05 05:55:34 PM PDT 24
Finished Jul 05 05:55:54 PM PDT 24
Peak memory 217292 kb
Host smart-2a4f62af-f1fa-40c5-830c-70d6160f9937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115858723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.115858723
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3768001679
Short name T165
Test name
Test status
Simulation time 2845337170 ps
CPU time 3.45 seconds
Started Jul 05 05:55:31 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 220396 kb
Host smart-74b01839-a91d-4020-bee2-d3445dd6b073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768001679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3768001679
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1670090453
Short name T917
Test name
Test status
Simulation time 15264743456 ps
CPU time 87.29 seconds
Started Jul 05 06:27:17 PM PDT 24
Finished Jul 05 06:28:45 PM PDT 24
Peak memory 257212 kb
Host smart-92cf99e4-714d-46b3-b925-b040f2eda70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670090453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1670090453
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1745275758
Short name T247
Test name
Test status
Simulation time 20367728638 ps
CPU time 229.43 seconds
Started Jul 05 06:27:28 PM PDT 24
Finished Jul 05 06:31:18 PM PDT 24
Peak memory 256312 kb
Host smart-2897f6a4-3380-4782-ae57-69efeaff2de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745275758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1745275758
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4109085392
Short name T179
Test name
Test status
Simulation time 223519506708 ps
CPU time 701.56 seconds
Started Jul 05 06:28:18 PM PDT 24
Finished Jul 05 06:40:00 PM PDT 24
Peak memory 267236 kb
Host smart-0439e967-5721-4a23-9168-33dea4ce5420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109085392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4109085392
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3989845038
Short name T315
Test name
Test status
Simulation time 43429817731 ps
CPU time 67.59 seconds
Started Jul 05 06:30:51 PM PDT 24
Finished Jul 05 06:31:59 PM PDT 24
Peak memory 233992 kb
Host smart-a87e3323-e7a3-4391-a503-fb809e9b586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989845038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3989845038
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.601262473
Short name T79
Test name
Test status
Simulation time 80522477 ps
CPU time 1.4 seconds
Started Jul 05 05:55:18 PM PDT 24
Finished Jul 05 05:55:20 PM PDT 24
Peak memory 216508 kb
Host smart-ecdd5788-f89f-4561-940c-62cb6c4408b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601262473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.601262473
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.613518832
Short name T28
Test name
Test status
Simulation time 19495797079 ps
CPU time 81.6 seconds
Started Jul 05 06:27:34 PM PDT 24
Finished Jul 05 06:28:57 PM PDT 24
Peak memory 252896 kb
Host smart-0f6a9ae5-25d1-4ce9-9264-d94ac42ac507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613518832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.613518832
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4144657847
Short name T1084
Test name
Test status
Simulation time 726039344 ps
CPU time 14.43 seconds
Started Jul 05 05:55:19 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 215552 kb
Host smart-3cab8627-4dde-45ff-9ce8-fd4282fe09e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144657847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4144657847
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3881743733
Short name T120
Test name
Test status
Simulation time 2699387724 ps
CPU time 22.4 seconds
Started Jul 05 05:55:16 PM PDT 24
Finished Jul 05 05:55:39 PM PDT 24
Peak memory 207368 kb
Host smart-85e7da0f-a3bb-4559-bb1a-a879d546309b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881743733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3881743733
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1000212451
Short name T78
Test name
Test status
Simulation time 516426742 ps
CPU time 1.38 seconds
Started Jul 05 05:55:21 PM PDT 24
Finished Jul 05 05:55:22 PM PDT 24
Peak memory 207336 kb
Host smart-233e069c-21a1-4fea-83fd-28801ae69245
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000212451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1000212451
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2200042247
Short name T1125
Test name
Test status
Simulation time 89491418 ps
CPU time 1.63 seconds
Started Jul 05 05:55:19 PM PDT 24
Finished Jul 05 05:55:21 PM PDT 24
Peak memory 215568 kb
Host smart-b8f629d3-3664-4546-b69d-823539a39551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200042247 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2200042247
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.911261412
Short name T1051
Test name
Test status
Simulation time 75859392 ps
CPU time 1.21 seconds
Started Jul 05 05:55:14 PM PDT 24
Finished Jul 05 05:55:16 PM PDT 24
Peak memory 215496 kb
Host smart-3e5a3f6e-b924-4db5-8a7c-659e04a71b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911261412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.911261412
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2272581694
Short name T1083
Test name
Test status
Simulation time 30298222 ps
CPU time 0.72 seconds
Started Jul 05 05:55:17 PM PDT 24
Finished Jul 05 05:55:18 PM PDT 24
Peak memory 204260 kb
Host smart-c2ee0310-0c6b-41a8-bb31-9bf4aebb98cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272581694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
272581694
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.48841179
Short name T1072
Test name
Test status
Simulation time 72548610 ps
CPU time 2.26 seconds
Started Jul 05 05:55:12 PM PDT 24
Finished Jul 05 05:55:15 PM PDT 24
Peak memory 215544 kb
Host smart-c009ee50-1b57-4816-a7b8-12836a287fc4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48841179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_d
evice_mem_partial_access.48841179
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4066212104
Short name T1073
Test name
Test status
Simulation time 11924474 ps
CPU time 0.66 seconds
Started Jul 05 05:55:16 PM PDT 24
Finished Jul 05 05:55:18 PM PDT 24
Peak memory 203856 kb
Host smart-c69772d7-ce7f-4d3a-861e-261a5c0f35b7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066212104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4066212104
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1251456931
Short name T1128
Test name
Test status
Simulation time 170184169 ps
CPU time 4.57 seconds
Started Jul 05 05:55:16 PM PDT 24
Finished Jul 05 05:55:22 PM PDT 24
Peak memory 215540 kb
Host smart-8192b704-7030-472b-af1c-7429c6abcf2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251456931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1251456931
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2429141080
Short name T98
Test name
Test status
Simulation time 101706427 ps
CPU time 2.84 seconds
Started Jul 05 05:55:18 PM PDT 24
Finished Jul 05 05:55:21 PM PDT 24
Peak memory 215808 kb
Host smart-c82983bd-f391-4fdf-98b3-eec7f1c622e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429141080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
429141080
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4175725845
Short name T1127
Test name
Test status
Simulation time 948418150 ps
CPU time 22.59 seconds
Started Jul 05 05:55:18 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 215744 kb
Host smart-c5eea5ce-46c6-49c5-b0c2-aaf7fdfd5a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175725845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4175725845
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.49828428
Short name T1034
Test name
Test status
Simulation time 636505676 ps
CPU time 13.07 seconds
Started Jul 05 05:55:17 PM PDT 24
Finished Jul 05 05:55:31 PM PDT 24
Peak memory 215492 kb
Host smart-706eea69-8e23-4740-8e34-e362a4ac9471
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49828428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
bit_bash.49828428
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1563671175
Short name T99
Test name
Test status
Simulation time 78835427 ps
CPU time 2.55 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 216004 kb
Host smart-4dd9b5bf-cdd9-4812-9b4f-44e6c16240c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563671175 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1563671175
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3761491971
Short name T126
Test name
Test status
Simulation time 140491095 ps
CPU time 1.98 seconds
Started Jul 05 05:55:16 PM PDT 24
Finished Jul 05 05:55:18 PM PDT 24
Peak memory 207284 kb
Host smart-51dc6f2e-4f78-4cc2-812b-af0dfa8f28e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761491971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
761491971
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3062543076
Short name T1115
Test name
Test status
Simulation time 43976571 ps
CPU time 0.73 seconds
Started Jul 05 05:55:17 PM PDT 24
Finished Jul 05 05:55:18 PM PDT 24
Peak memory 203980 kb
Host smart-2a9e35f2-ab53-4b7d-988f-b371ee28ab6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062543076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
062543076
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1799604075
Short name T1093
Test name
Test status
Simulation time 63285983 ps
CPU time 2.41 seconds
Started Jul 05 05:55:11 PM PDT 24
Finished Jul 05 05:55:14 PM PDT 24
Peak memory 215596 kb
Host smart-a9acd47b-1266-4ff7-a564-7f8a5bb7dd7f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799604075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1799604075
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3264712776
Short name T1118
Test name
Test status
Simulation time 35683514 ps
CPU time 0.67 seconds
Started Jul 05 05:55:17 PM PDT 24
Finished Jul 05 05:55:19 PM PDT 24
Peak memory 203860 kb
Host smart-4db48eb6-84aa-4b9e-b9db-66a1ac523225
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264712776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3264712776
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2728162915
Short name T1133
Test name
Test status
Simulation time 1534388638 ps
CPU time 3.04 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:29 PM PDT 24
Peak memory 215500 kb
Host smart-e831e819-7690-428a-8e33-9906a2dd0931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728162915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2728162915
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1242721376
Short name T1105
Test name
Test status
Simulation time 673577477 ps
CPU time 4.1 seconds
Started Jul 05 05:55:17 PM PDT 24
Finished Jul 05 05:55:22 PM PDT 24
Peak memory 215668 kb
Host smart-eefce97b-18c2-46b0-9bdd-9998cdfac9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242721376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
242721376
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2299225282
Short name T1106
Test name
Test status
Simulation time 1783628338 ps
CPU time 11.68 seconds
Started Jul 05 05:55:19 PM PDT 24
Finished Jul 05 05:55:32 PM PDT 24
Peak memory 216072 kb
Host smart-2470bded-ec67-449e-a92c-287add05bc64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299225282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2299225282
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3313649126
Short name T1080
Test name
Test status
Simulation time 146679941 ps
CPU time 3.7 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:40 PM PDT 24
Peak memory 218588 kb
Host smart-fa8ac257-0007-47d8-816a-42c86534722b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313649126 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3313649126
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3989546248
Short name T1068
Test name
Test status
Simulation time 139660957 ps
CPU time 2.43 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:39 PM PDT 24
Peak memory 207272 kb
Host smart-8e2adb49-2689-4def-b9a0-f5bf305131ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989546248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3989546248
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.556613394
Short name T1145
Test name
Test status
Simulation time 34733582 ps
CPU time 0.7 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:32 PM PDT 24
Peak memory 203932 kb
Host smart-04f5874c-826c-4886-81ef-3c4cfec03875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556613394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.556613394
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2500086956
Short name T140
Test name
Test status
Simulation time 60721127 ps
CPU time 1.96 seconds
Started Jul 05 05:55:32 PM PDT 24
Finished Jul 05 05:55:35 PM PDT 24
Peak memory 215560 kb
Host smart-8da20bc3-81f8-425a-b45f-aae7a10427c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500086956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2500086956
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.758266595
Short name T1086
Test name
Test status
Simulation time 163410474 ps
CPU time 4.02 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 216960 kb
Host smart-e76269ba-729e-449a-a5e6-6c77cde6ae29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758266595 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.758266595
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3550177320
Short name T118
Test name
Test status
Simulation time 36049128 ps
CPU time 1.26 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:33 PM PDT 24
Peak memory 215596 kb
Host smart-800677a2-9d5d-4377-a8d5-f5c34b6e4ae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550177320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3550177320
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3600645545
Short name T1123
Test name
Test status
Simulation time 33971309 ps
CPU time 0.75 seconds
Started Jul 05 05:55:32 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 203936 kb
Host smart-7a1d9430-8fb0-4459-a4b5-e2027794a033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600645545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3600645545
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3248029818
Short name T142
Test name
Test status
Simulation time 59798678 ps
CPU time 3.58 seconds
Started Jul 05 05:55:31 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 215480 kb
Host smart-86a8e4de-1756-4a30-87bc-88d1bd32d0c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248029818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3248029818
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3152718685
Short name T95
Test name
Test status
Simulation time 54119229 ps
CPU time 1.92 seconds
Started Jul 05 05:55:32 PM PDT 24
Finished Jul 05 05:55:35 PM PDT 24
Peak memory 215756 kb
Host smart-344bbf49-2be1-482e-9fa5-93242fe79a65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152718685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3152718685
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3308469404
Short name T1056
Test name
Test status
Simulation time 338156443 ps
CPU time 3.65 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:40 PM PDT 24
Peak memory 217404 kb
Host smart-b2fd05dc-ddb1-4f04-aad0-72374469408b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308469404 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3308469404
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1193489358
Short name T116
Test name
Test status
Simulation time 62670078 ps
CPU time 1.94 seconds
Started Jul 05 05:55:32 PM PDT 24
Finished Jul 05 05:55:35 PM PDT 24
Peak memory 215572 kb
Host smart-07a8ceb2-dd84-489a-ba84-079493aaa4fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193489358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1193489358
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.525817112
Short name T1071
Test name
Test status
Simulation time 50712018 ps
CPU time 0.74 seconds
Started Jul 05 05:55:31 PM PDT 24
Finished Jul 05 05:55:33 PM PDT 24
Peak memory 204280 kb
Host smart-2dfc4277-b2c2-491d-b45a-5f915d807a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525817112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.525817112
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4146803213
Short name T1036
Test name
Test status
Simulation time 238861803 ps
CPU time 4.14 seconds
Started Jul 05 05:55:34 PM PDT 24
Finished Jul 05 05:55:39 PM PDT 24
Peak memory 215532 kb
Host smart-89ac4f35-6f32-486b-a16d-8f986255e853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146803213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4146803213
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2051309704
Short name T171
Test name
Test status
Simulation time 113252342 ps
CPU time 6.2 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:44 PM PDT 24
Peak memory 215428 kb
Host smart-b04da387-2c04-47f6-92bb-5269ac7300d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051309704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2051309704
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1519475535
Short name T111
Test name
Test status
Simulation time 562245363 ps
CPU time 1.59 seconds
Started Jul 05 05:55:32 PM PDT 24
Finished Jul 05 05:55:35 PM PDT 24
Peak memory 215576 kb
Host smart-c1bf820c-3c26-4fe2-9fa4-4abdd5c651a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519475535 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1519475535
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.804725188
Short name T117
Test name
Test status
Simulation time 226994512 ps
CPU time 2.59 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 215440 kb
Host smart-70423b9d-92ad-492a-84b7-2d63ee6fe7ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804725188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.804725188
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3316413312
Short name T1122
Test name
Test status
Simulation time 24971919 ps
CPU time 0.75 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:31 PM PDT 24
Peak memory 204268 kb
Host smart-3c0348b9-590a-43a7-9ce5-ae9c8cd9ef02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316413312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3316413312
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.817859047
Short name T1113
Test name
Test status
Simulation time 109602007 ps
CPU time 1.82 seconds
Started Jul 05 05:55:32 PM PDT 24
Finished Jul 05 05:55:35 PM PDT 24
Peak memory 215464 kb
Host smart-d25b7115-6ad1-42fc-8db5-9c0b56820a94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817859047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.817859047
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2110582007
Short name T1136
Test name
Test status
Simulation time 51838080 ps
CPU time 1.8 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:40 PM PDT 24
Peak memory 215692 kb
Host smart-9fe87a63-ddf5-4fe1-99c5-a0b4efe29946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110582007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2110582007
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1835076642
Short name T1094
Test name
Test status
Simulation time 694057667 ps
CPU time 15.25 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:50 PM PDT 24
Peak memory 219008 kb
Host smart-35987d2f-eef3-4376-8592-3a8f222ccc43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835076642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1835076642
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4052586742
Short name T1064
Test name
Test status
Simulation time 96804912 ps
CPU time 2.86 seconds
Started Jul 05 05:55:28 PM PDT 24
Finished Jul 05 05:55:32 PM PDT 24
Peak memory 216712 kb
Host smart-c9342638-9faf-442d-8a67-a951d6794cc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052586742 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4052586742
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.142926429
Short name T1043
Test name
Test status
Simulation time 285445823 ps
CPU time 1.99 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 215588 kb
Host smart-e86e76ea-6053-4276-ac25-2b1b9a1b1e3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142926429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.142926429
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2682516387
Short name T1052
Test name
Test status
Simulation time 16866947 ps
CPU time 0.72 seconds
Started Jul 05 05:55:34 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 204316 kb
Host smart-738871f5-f4b7-47f8-b968-5401d70e04a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682516387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2682516387
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1699443884
Short name T1077
Test name
Test status
Simulation time 288394130 ps
CPU time 2.98 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:39 PM PDT 24
Peak memory 216092 kb
Host smart-633af69c-e619-4775-9e01-2e2b8c48f59f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699443884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1699443884
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2998642165
Short name T172
Test name
Test status
Simulation time 541250216 ps
CPU time 8.29 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:40 PM PDT 24
Peak memory 223728 kb
Host smart-c87e499f-29d8-486e-b2a4-e77251708aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998642165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2998642165
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.243904304
Short name T1143
Test name
Test status
Simulation time 54501597 ps
CPU time 1.69 seconds
Started Jul 05 05:55:33 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 215608 kb
Host smart-54074ea1-8d0a-4297-be80-a2a262db60b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243904304 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.243904304
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2410300152
Short name T125
Test name
Test status
Simulation time 211633599 ps
CPU time 1.98 seconds
Started Jul 05 05:55:34 PM PDT 24
Finished Jul 05 05:55:37 PM PDT 24
Peak memory 215592 kb
Host smart-2da64392-6f31-41b7-9a95-9d36868f41ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410300152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2410300152
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.706378497
Short name T1035
Test name
Test status
Simulation time 23199898 ps
CPU time 0.78 seconds
Started Jul 05 05:55:36 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 203968 kb
Host smart-e0c7d4d1-0e9a-4822-ada0-848e35ff9cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706378497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.706378497
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1096183163
Short name T1108
Test name
Test status
Simulation time 57828164 ps
CPU time 3.79 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:40 PM PDT 24
Peak memory 215576 kb
Host smart-b89b55ef-27a8-4e25-bfdd-444b376c675b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096183163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1096183163
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1964048858
Short name T105
Test name
Test status
Simulation time 129176992 ps
CPU time 3.54 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 215656 kb
Host smart-784581d5-ec63-490a-a02a-63386c83fc0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964048858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1964048858
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2976962248
Short name T112
Test name
Test status
Simulation time 819733511 ps
CPU time 12.82 seconds
Started Jul 05 05:55:31 PM PDT 24
Finished Jul 05 05:55:45 PM PDT 24
Peak memory 215740 kb
Host smart-c79be138-f192-45b2-8658-17660b362e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976962248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2976962248
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1837223361
Short name T1059
Test name
Test status
Simulation time 243365777 ps
CPU time 3.94 seconds
Started Jul 05 05:55:36 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 217416 kb
Host smart-f81ab7c3-5a75-48b9-977d-860b7a7187b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837223361 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1837223361
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3143395767
Short name T1131
Test name
Test status
Simulation time 43996003 ps
CPU time 1.34 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 207300 kb
Host smart-b1e311f3-846c-44ef-b25a-d9f72d20cfc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143395767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3143395767
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1860897954
Short name T1054
Test name
Test status
Simulation time 52547080 ps
CPU time 0.78 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:37 PM PDT 24
Peak memory 204084 kb
Host smart-e50026a6-bf83-4905-a546-efccd7750c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860897954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1860897954
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.545321538
Short name T141
Test name
Test status
Simulation time 289871610 ps
CPU time 1.95 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 215540 kb
Host smart-63ed7397-152d-478f-8f1a-9b8ce736dcff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545321538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.545321538
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1527646847
Short name T107
Test name
Test status
Simulation time 561875242 ps
CPU time 3.3 seconds
Started Jul 05 05:55:31 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 215756 kb
Host smart-62894a4c-9e7f-4d11-a0ec-c2998bd85bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527646847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1527646847
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2018602445
Short name T170
Test name
Test status
Simulation time 416099474 ps
CPU time 7.18 seconds
Started Jul 05 05:55:33 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 216196 kb
Host smart-28867132-213c-4dae-b745-cae34c0283d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018602445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2018602445
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3704012575
Short name T1107
Test name
Test status
Simulation time 403812281 ps
CPU time 2.72 seconds
Started Jul 05 05:55:39 PM PDT 24
Finished Jul 05 05:55:43 PM PDT 24
Peak memory 217212 kb
Host smart-751eb7e2-79ef-4bdd-ba1c-c2a4e913a552
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704012575 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3704012575
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2670508107
Short name T124
Test name
Test status
Simulation time 343447264 ps
CPU time 2.68 seconds
Started Jul 05 05:55:39 PM PDT 24
Finished Jul 05 05:55:43 PM PDT 24
Peak memory 215552 kb
Host smart-9906a167-eba4-4f82-af2b-ef0f1f9faf4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670508107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2670508107
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2415878622
Short name T1038
Test name
Test status
Simulation time 38005373 ps
CPU time 0.76 seconds
Started Jul 05 05:55:35 PM PDT 24
Finished Jul 05 05:55:37 PM PDT 24
Peak memory 203924 kb
Host smart-8c96c76b-119d-45d6-83b0-8318a5348ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415878622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2415878622
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1684229502
Short name T1111
Test name
Test status
Simulation time 122932287 ps
CPU time 2.87 seconds
Started Jul 05 05:55:38 PM PDT 24
Finished Jul 05 05:55:42 PM PDT 24
Peak memory 215572 kb
Host smart-be899681-2a03-4175-bde7-d19f0e3f2870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684229502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1684229502
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3504782954
Short name T108
Test name
Test status
Simulation time 162641815 ps
CPU time 1.69 seconds
Started Jul 05 05:55:44 PM PDT 24
Finished Jul 05 05:55:46 PM PDT 24
Peak memory 215820 kb
Host smart-e8467b88-7767-4e31-99ce-b4db05e85a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504782954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3504782954
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.271897076
Short name T1109
Test name
Test status
Simulation time 1104630527 ps
CPU time 7.26 seconds
Started Jul 05 05:55:38 PM PDT 24
Finished Jul 05 05:55:47 PM PDT 24
Peak memory 222632 kb
Host smart-4333b806-eceb-424e-8100-794ceff79ea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271897076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.271897076
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.582767224
Short name T1121
Test name
Test status
Simulation time 633087786 ps
CPU time 3.69 seconds
Started Jul 05 05:55:39 PM PDT 24
Finished Jul 05 05:55:44 PM PDT 24
Peak memory 217492 kb
Host smart-8133d10d-9320-431a-b950-2e5a7c1f9677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582767224 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.582767224
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.186873068
Short name T121
Test name
Test status
Simulation time 451383221 ps
CPU time 2.65 seconds
Started Jul 05 05:55:44 PM PDT 24
Finished Jul 05 05:55:48 PM PDT 24
Peak memory 215524 kb
Host smart-a3ec670a-73d9-45e5-9fd9-f6fe1c1f55a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186873068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.186873068
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1456508963
Short name T1031
Test name
Test status
Simulation time 14191746 ps
CPU time 0.7 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:39 PM PDT 24
Peak memory 204000 kb
Host smart-5086780e-5f4b-4342-b6b6-0a04628b72b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456508963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1456508963
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.669366761
Short name T1102
Test name
Test status
Simulation time 216745205 ps
CPU time 3.96 seconds
Started Jul 05 05:55:36 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 215500 kb
Host smart-6ab0e5f9-95d1-4627-99b7-b5e92bca88f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669366761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.669366761
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3693176720
Short name T1041
Test name
Test status
Simulation time 52312882 ps
CPU time 1.79 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:40 PM PDT 24
Peak memory 215696 kb
Host smart-f38ca09b-4b7a-4353-a9c4-ff85e376e9a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693176720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3693176720
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2332599500
Short name T166
Test name
Test status
Simulation time 855373443 ps
CPU time 6.85 seconds
Started Jul 05 05:55:38 PM PDT 24
Finished Jul 05 05:55:46 PM PDT 24
Peak memory 215552 kb
Host smart-e3552db9-5254-49ee-a5dc-8c2226eb0e03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332599500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2332599500
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2510405858
Short name T94
Test name
Test status
Simulation time 631464239 ps
CPU time 3.7 seconds
Started Jul 05 05:55:38 PM PDT 24
Finished Jul 05 05:55:43 PM PDT 24
Peak memory 218176 kb
Host smart-1104a863-e520-40a5-b000-86ea79d774c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510405858 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2510405858
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3654561577
Short name T1091
Test name
Test status
Simulation time 108754829 ps
CPU time 2.7 seconds
Started Jul 05 05:55:38 PM PDT 24
Finished Jul 05 05:55:42 PM PDT 24
Peak memory 215520 kb
Host smart-f50fdbaa-b5e3-4adb-94df-adac1a6b87cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654561577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3654561577
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.928102520
Short name T1037
Test name
Test status
Simulation time 14274799 ps
CPU time 0.74 seconds
Started Jul 05 05:55:44 PM PDT 24
Finished Jul 05 05:55:45 PM PDT 24
Peak memory 203996 kb
Host smart-3e9a0ff1-23fb-49bf-8648-768d1d072244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928102520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.928102520
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2981253991
Short name T1049
Test name
Test status
Simulation time 50780452 ps
CPU time 3.03 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 215408 kb
Host smart-b09b5689-d5bd-4586-abd9-a21c37d397a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981253991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2981253991
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1804229161
Short name T1130
Test name
Test status
Simulation time 165892759 ps
CPU time 1.46 seconds
Started Jul 05 05:55:36 PM PDT 24
Finished Jul 05 05:55:39 PM PDT 24
Peak memory 215712 kb
Host smart-7a6a73bd-d7c6-4687-b002-5a13c9fb3c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804229161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1804229161
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1277661407
Short name T93
Test name
Test status
Simulation time 449955215 ps
CPU time 6.99 seconds
Started Jul 05 05:55:46 PM PDT 24
Finished Jul 05 05:55:53 PM PDT 24
Peak memory 215432 kb
Host smart-698d5ae0-1ebd-4d51-91a2-7742242a2290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277661407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1277661407
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3081545836
Short name T122
Test name
Test status
Simulation time 3642857261 ps
CPU time 23.81 seconds
Started Jul 05 05:55:23 PM PDT 24
Finished Jul 05 05:55:48 PM PDT 24
Peak memory 215488 kb
Host smart-e83d8ac4-c250-44b4-bd82-fbdb59317215
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081545836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3081545836
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.957514193
Short name T1074
Test name
Test status
Simulation time 3768507624 ps
CPU time 37.78 seconds
Started Jul 05 05:55:28 PM PDT 24
Finished Jul 05 05:56:06 PM PDT 24
Peak memory 207304 kb
Host smart-8dab34ea-cad5-4737-b402-9836c8cb62b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957514193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.957514193
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1185424647
Short name T1129
Test name
Test status
Simulation time 33823374 ps
CPU time 1.22 seconds
Started Jul 05 05:55:27 PM PDT 24
Finished Jul 05 05:55:29 PM PDT 24
Peak memory 207260 kb
Host smart-047a1470-df27-4f43-9120-4ff42518b4b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185424647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1185424647
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.968486092
Short name T92
Test name
Test status
Simulation time 55261052 ps
CPU time 1.83 seconds
Started Jul 05 05:55:26 PM PDT 24
Finished Jul 05 05:55:29 PM PDT 24
Peak memory 216624 kb
Host smart-ff6cc27c-0e70-46f4-b33b-de2629684803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968486092 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.968486092
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2593981295
Short name T1137
Test name
Test status
Simulation time 122589099 ps
CPU time 1.19 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 207272 kb
Host smart-7581fc89-d37b-47fe-b8b4-a7be992b6b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593981295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
593981295
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3139785764
Short name T1063
Test name
Test status
Simulation time 34662357 ps
CPU time 0.77 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 204280 kb
Host smart-a628b473-cae7-4a95-b967-b524091043eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139785764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
139785764
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.798575710
Short name T1110
Test name
Test status
Simulation time 115850916 ps
CPU time 2.28 seconds
Started Jul 05 05:55:24 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 215552 kb
Host smart-975de13f-08ed-4cf5-9248-b5264e111705
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798575710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.798575710
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2655524515
Short name T1104
Test name
Test status
Simulation time 10716805 ps
CPU time 0.68 seconds
Started Jul 05 05:55:28 PM PDT 24
Finished Jul 05 05:55:29 PM PDT 24
Peak memory 203864 kb
Host smart-a6dc4a08-8075-4818-9d9b-5924e7216c53
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655524515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2655524515
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1635686566
Short name T1092
Test name
Test status
Simulation time 106083785 ps
CPU time 2.86 seconds
Started Jul 05 05:55:26 PM PDT 24
Finished Jul 05 05:55:30 PM PDT 24
Peak memory 215544 kb
Host smart-49b95077-0f73-4204-b13a-227545df7566
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635686566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1635686566
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2365971167
Short name T100
Test name
Test status
Simulation time 100137402 ps
CPU time 2.69 seconds
Started Jul 05 05:55:26 PM PDT 24
Finished Jul 05 05:55:30 PM PDT 24
Peak memory 215728 kb
Host smart-20610919-5a59-4d99-9751-941eaf70d9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365971167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
365971167
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1913836005
Short name T1075
Test name
Test status
Simulation time 1735975384 ps
CPU time 8.18 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:35 PM PDT 24
Peak memory 215504 kb
Host smart-d3787bc0-0f5b-43ce-a242-13f45ef27cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913836005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1913836005
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3980602368
Short name T1033
Test name
Test status
Simulation time 37852688 ps
CPU time 0.71 seconds
Started Jul 05 05:55:38 PM PDT 24
Finished Jul 05 05:55:40 PM PDT 24
Peak memory 203828 kb
Host smart-2830bf51-6d9d-4419-ba76-11843a129706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980602368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3980602368
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1413046276
Short name T1040
Test name
Test status
Simulation time 30059330 ps
CPU time 0.7 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 204320 kb
Host smart-ca2baf64-a944-44b1-971a-674c643dd756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413046276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1413046276
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.519545770
Short name T1027
Test name
Test status
Simulation time 28810505 ps
CPU time 0.75 seconds
Started Jul 05 05:55:39 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 203988 kb
Host smart-4563723e-65ec-4a31-ab63-7e521a3e66d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519545770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.519545770
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.927323510
Short name T1097
Test name
Test status
Simulation time 15641750 ps
CPU time 0.71 seconds
Started Jul 05 05:55:44 PM PDT 24
Finished Jul 05 05:55:46 PM PDT 24
Peak memory 204264 kb
Host smart-e92a84c7-be5d-45d5-9a5e-dfc619ca727d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927323510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.927323510
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.472975555
Short name T1085
Test name
Test status
Simulation time 15427250 ps
CPU time 0.71 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:39 PM PDT 24
Peak memory 204284 kb
Host smart-c73c4bce-4f46-480d-a3ed-939d169a1ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472975555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.472975555
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1866141065
Short name T1119
Test name
Test status
Simulation time 16265373 ps
CPU time 0.81 seconds
Started Jul 05 05:55:49 PM PDT 24
Finished Jul 05 05:55:51 PM PDT 24
Peak memory 204032 kb
Host smart-f34887c2-ade5-4bde-a046-f44300620724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866141065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1866141065
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2267299081
Short name T1116
Test name
Test status
Simulation time 16416755 ps
CPU time 0.77 seconds
Started Jul 05 05:55:39 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 204048 kb
Host smart-e3642871-7183-4150-9c20-60246dfdaec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267299081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2267299081
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1812658954
Short name T1053
Test name
Test status
Simulation time 28762416 ps
CPU time 0.78 seconds
Started Jul 05 05:55:36 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 204040 kb
Host smart-f8bfef73-e54d-4535-9e1f-602fcfde3c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812658954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1812658954
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3203685216
Short name T1076
Test name
Test status
Simulation time 55922723 ps
CPU time 0.74 seconds
Started Jul 05 05:55:43 PM PDT 24
Finished Jul 05 05:55:45 PM PDT 24
Peak memory 203988 kb
Host smart-cae20a41-6722-4919-bf61-654e31a248b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203685216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3203685216
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1208889887
Short name T1065
Test name
Test status
Simulation time 28009903 ps
CPU time 0.75 seconds
Started Jul 05 05:55:36 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 204004 kb
Host smart-1bc80398-76b8-4814-b98e-746e7f3aa033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208889887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1208889887
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3289636735
Short name T119
Test name
Test status
Simulation time 463552386 ps
CPU time 7.92 seconds
Started Jul 05 05:55:27 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 215568 kb
Host smart-7629ed2b-12d6-479d-bf0d-ab6ec9ee739a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289636735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3289636735
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3164208607
Short name T1139
Test name
Test status
Simulation time 2444993372 ps
CPU time 12.55 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:42 PM PDT 24
Peak memory 215524 kb
Host smart-5f69ccc7-f610-4b56-9545-8ed0518427d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164208607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3164208607
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2165740582
Short name T77
Test name
Test status
Simulation time 20406254 ps
CPU time 1.02 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 207116 kb
Host smart-2102ad81-c3c8-480e-90f7-502a88adc6d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165740582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2165740582
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.84133658
Short name T1090
Test name
Test status
Simulation time 150187347 ps
CPU time 2.52 seconds
Started Jul 05 05:55:24 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 216656 kb
Host smart-e40615ab-8cf2-4bdc-ada8-8952028cf3d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84133658 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.84133658
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4252253782
Short name T1062
Test name
Test status
Simulation time 287569709 ps
CPU time 1.32 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:28 PM PDT 24
Peak memory 207240 kb
Host smart-84822951-29c9-46df-b278-8af18eaa3f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252253782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
252253782
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3972287679
Short name T1149
Test name
Test status
Simulation time 21980496 ps
CPU time 0.73 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:31 PM PDT 24
Peak memory 203932 kb
Host smart-b5f7827d-81e6-4d09-a327-405e23c145a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972287679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
972287679
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2443589616
Short name T1048
Test name
Test status
Simulation time 27874122 ps
CPU time 2.05 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 215472 kb
Host smart-b9b09862-eaa8-47e0-81c9-69cc9bf75e10
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443589616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2443589616
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3976484207
Short name T1124
Test name
Test status
Simulation time 14226299 ps
CPU time 0.7 seconds
Started Jul 05 05:55:23 PM PDT 24
Finished Jul 05 05:55:25 PM PDT 24
Peak memory 204248 kb
Host smart-0c73b877-2f05-4506-a148-c8c38d833a33
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976484207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3976484207
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1722812576
Short name T1066
Test name
Test status
Simulation time 164994652 ps
CPU time 2.03 seconds
Started Jul 05 05:55:23 PM PDT 24
Finished Jul 05 05:55:26 PM PDT 24
Peak memory 215376 kb
Host smart-27ac6d06-5167-4dcb-bfab-5929c061174f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722812576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1722812576
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.193964967
Short name T1098
Test name
Test status
Simulation time 171021530 ps
CPU time 3.91 seconds
Started Jul 05 05:55:23 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 215752 kb
Host smart-eebea298-2406-4426-9bec-7a84979bc188
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193964967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.193964967
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2792767224
Short name T1082
Test name
Test status
Simulation time 1529249479 ps
CPU time 8.14 seconds
Started Jul 05 05:55:34 PM PDT 24
Finished Jul 05 05:55:44 PM PDT 24
Peak memory 215680 kb
Host smart-751a4901-0744-4de4-84a5-99ad8fcae583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792767224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2792767224
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3482458050
Short name T1029
Test name
Test status
Simulation time 21978044 ps
CPU time 0.73 seconds
Started Jul 05 05:55:40 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 204296 kb
Host smart-3f369f29-3494-4a24-89af-3f3cebf311ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482458050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3482458050
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.926783722
Short name T1087
Test name
Test status
Simulation time 22465431 ps
CPU time 0.69 seconds
Started Jul 05 05:55:37 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 203976 kb
Host smart-2ca0e06f-b250-43a4-8230-6ac7a2887c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926783722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.926783722
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3315920732
Short name T1046
Test name
Test status
Simulation time 17366597 ps
CPU time 0.72 seconds
Started Jul 05 05:55:43 PM PDT 24
Finished Jul 05 05:55:44 PM PDT 24
Peak memory 203992 kb
Host smart-b16d5b17-a774-4e79-8ee2-96bc60e3a38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315920732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3315920732
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1078701096
Short name T1050
Test name
Test status
Simulation time 49212160 ps
CPU time 0.74 seconds
Started Jul 05 05:55:43 PM PDT 24
Finished Jul 05 05:55:44 PM PDT 24
Peak memory 203956 kb
Host smart-d95c9d73-f906-49f4-bead-960b70fcea8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078701096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1078701096
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1986934336
Short name T1141
Test name
Test status
Simulation time 45864117 ps
CPU time 0.67 seconds
Started Jul 05 05:55:38 PM PDT 24
Finished Jul 05 05:55:39 PM PDT 24
Peak memory 203808 kb
Host smart-1425b4d5-b3eb-483f-a7d7-3ab82ef579bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986934336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1986934336
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1454842787
Short name T1140
Test name
Test status
Simulation time 15195807 ps
CPU time 0.72 seconds
Started Jul 05 05:55:40 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 203920 kb
Host smart-f2db5b41-5b65-4f1d-8930-be900614418a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454842787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1454842787
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3228568904
Short name T1142
Test name
Test status
Simulation time 15891576 ps
CPU time 0.8 seconds
Started Jul 05 05:55:40 PM PDT 24
Finished Jul 05 05:55:42 PM PDT 24
Peak memory 204224 kb
Host smart-d3cc5796-9d6d-47db-b218-e1243cb748ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228568904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3228568904
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3774955712
Short name T1030
Test name
Test status
Simulation time 62783804 ps
CPU time 0.73 seconds
Started Jul 05 05:55:47 PM PDT 24
Finished Jul 05 05:55:49 PM PDT 24
Peak memory 204084 kb
Host smart-361db217-4690-43da-9762-3a3b324530ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774955712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3774955712
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2175727113
Short name T1045
Test name
Test status
Simulation time 11831593 ps
CPU time 0.7 seconds
Started Jul 05 05:55:47 PM PDT 24
Finished Jul 05 05:55:48 PM PDT 24
Peak memory 203868 kb
Host smart-228cc5c5-d932-48c3-ad5a-9f9cade67263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175727113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2175727113
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.367623113
Short name T1032
Test name
Test status
Simulation time 23331775 ps
CPU time 0.73 seconds
Started Jul 05 05:55:49 PM PDT 24
Finished Jul 05 05:55:50 PM PDT 24
Peak memory 203952 kb
Host smart-154b3f0f-5f8d-4da2-8f24-3900b5187bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367623113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.367623113
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2012415943
Short name T1081
Test name
Test status
Simulation time 613013682 ps
CPU time 14.63 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 215440 kb
Host smart-bf66f9c3-476a-474c-a759-f1c97a5d9f8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012415943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2012415943
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.273855877
Short name T123
Test name
Test status
Simulation time 364287107 ps
CPU time 12.45 seconds
Started Jul 05 05:55:28 PM PDT 24
Finished Jul 05 05:55:42 PM PDT 24
Peak memory 207320 kb
Host smart-612a099f-632a-4e86-b284-b4a4523d037e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273855877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.273855877
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3422162064
Short name T80
Test name
Test status
Simulation time 47211012 ps
CPU time 1.44 seconds
Started Jul 05 05:55:24 PM PDT 24
Finished Jul 05 05:55:26 PM PDT 24
Peak memory 207292 kb
Host smart-5dcd4782-05c9-4a0e-897f-80e8129aa077
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422162064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3422162064
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3610454926
Short name T1147
Test name
Test status
Simulation time 133383364 ps
CPU time 1.64 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:32 PM PDT 24
Peak memory 216592 kb
Host smart-7ecc034d-fe7e-4bdc-9fb6-4b730eb0b64c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610454926 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3610454926
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1850152286
Short name T1114
Test name
Test status
Simulation time 109175111 ps
CPU time 2.67 seconds
Started Jul 05 05:55:22 PM PDT 24
Finished Jul 05 05:55:26 PM PDT 24
Peak memory 215568 kb
Host smart-b54c4af7-3127-4188-8d62-6a35b18de972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850152286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
850152286
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2477051916
Short name T1028
Test name
Test status
Simulation time 59604238 ps
CPU time 0.72 seconds
Started Jul 05 05:55:20 PM PDT 24
Finished Jul 05 05:55:21 PM PDT 24
Peak memory 203924 kb
Host smart-9b54b739-4813-41a2-822a-502b2c37aacc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477051916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
477051916
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.501995617
Short name T115
Test name
Test status
Simulation time 63781755 ps
CPU time 2.03 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:28 PM PDT 24
Peak memory 215504 kb
Host smart-1ca4ec66-6bfa-4fb6-af6c-d008d86f6acd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501995617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.501995617
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1893729807
Short name T1103
Test name
Test status
Simulation time 10828430 ps
CPU time 0.69 seconds
Started Jul 05 06:01:35 PM PDT 24
Finished Jul 05 06:01:36 PM PDT 24
Peak memory 204276 kb
Host smart-2ea82166-b7eb-43b0-af51-2054f4a565f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893729807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1893729807
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1017458716
Short name T1089
Test name
Test status
Simulation time 203423121 ps
CPU time 4.47 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 215500 kb
Host smart-91561f90-e6f8-4821-a51e-d890ec66077c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017458716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1017458716
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3676627014
Short name T106
Test name
Test status
Simulation time 111020744 ps
CPU time 2.8 seconds
Started Jul 05 05:55:26 PM PDT 24
Finished Jul 05 05:55:30 PM PDT 24
Peak memory 215744 kb
Host smart-46b0f0a9-34e1-4f99-b5bc-f1eb2c298c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676627014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
676627014
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2680088630
Short name T168
Test name
Test status
Simulation time 822755157 ps
CPU time 23.18 seconds
Started Jul 05 05:55:27 PM PDT 24
Finished Jul 05 05:55:51 PM PDT 24
Peak memory 215568 kb
Host smart-8d56d1f6-d247-4cf4-bb27-fcbf2fe9147b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680088630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2680088630
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2673543662
Short name T1132
Test name
Test status
Simulation time 32460479 ps
CPU time 0.76 seconds
Started Jul 05 05:55:48 PM PDT 24
Finished Jul 05 05:55:49 PM PDT 24
Peak memory 204012 kb
Host smart-f884f031-9bb6-431d-878f-2ea37177bc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673543662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2673543662
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3174624774
Short name T1117
Test name
Test status
Simulation time 23214809 ps
CPU time 0.76 seconds
Started Jul 05 05:55:49 PM PDT 24
Finished Jul 05 05:55:50 PM PDT 24
Peak memory 204320 kb
Host smart-831b7094-e3c8-424d-ac34-0246b3859ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174624774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3174624774
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2164332761
Short name T1057
Test name
Test status
Simulation time 12823988 ps
CPU time 0.75 seconds
Started Jul 05 05:55:50 PM PDT 24
Finished Jul 05 05:55:52 PM PDT 24
Peak memory 204004 kb
Host smart-cd983c09-dda4-482c-8ae9-860e061336d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164332761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2164332761
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2542215942
Short name T1069
Test name
Test status
Simulation time 28321063 ps
CPU time 0.75 seconds
Started Jul 05 05:55:40 PM PDT 24
Finished Jul 05 05:55:42 PM PDT 24
Peak memory 204296 kb
Host smart-1e360e8b-9793-4d54-bd51-cd9fe2a7e7c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542215942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2542215942
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3674369247
Short name T1070
Test name
Test status
Simulation time 19053870 ps
CPU time 0.77 seconds
Started Jul 05 05:55:47 PM PDT 24
Finished Jul 05 05:55:48 PM PDT 24
Peak memory 203528 kb
Host smart-2b504ac8-fde5-4479-a60d-ccbdcb26660f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674369247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3674369247
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3488515327
Short name T1134
Test name
Test status
Simulation time 15979064 ps
CPU time 0.79 seconds
Started Jul 05 05:55:42 PM PDT 24
Finished Jul 05 05:55:43 PM PDT 24
Peak memory 203940 kb
Host smart-d239ce9d-51cf-47d8-b86b-1a49d2ee229e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488515327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3488515327
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3901310352
Short name T1079
Test name
Test status
Simulation time 49721676 ps
CPU time 0.77 seconds
Started Jul 05 05:55:40 PM PDT 24
Finished Jul 05 05:55:42 PM PDT 24
Peak memory 204008 kb
Host smart-a6c12b1b-e21e-4e20-9d46-93097160c0de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901310352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3901310352
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2087576123
Short name T1047
Test name
Test status
Simulation time 17268015 ps
CPU time 0.73 seconds
Started Jul 05 05:55:39 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 204044 kb
Host smart-dbeb8dcb-128d-4c05-b9a0-384a76c0c469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087576123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2087576123
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4032739047
Short name T1146
Test name
Test status
Simulation time 152778564 ps
CPU time 0.77 seconds
Started Jul 05 05:55:54 PM PDT 24
Finished Jul 05 05:55:56 PM PDT 24
Peak memory 204284 kb
Host smart-effd0aa4-006f-4a58-b220-6e0297b0c864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032739047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4032739047
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2175962208
Short name T1055
Test name
Test status
Simulation time 41303122 ps
CPU time 0.75 seconds
Started Jul 05 05:55:40 PM PDT 24
Finished Jul 05 05:55:41 PM PDT 24
Peak memory 204044 kb
Host smart-19d5b675-5965-4b54-bc26-4136b3b7ba29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175962208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2175962208
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4292180113
Short name T1078
Test name
Test status
Simulation time 121841514 ps
CPU time 3.55 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:30 PM PDT 24
Peak memory 218628 kb
Host smart-5cc91a8e-a3d3-44a8-a23a-b44980d38a05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292180113 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4292180113
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.141019014
Short name T1099
Test name
Test status
Simulation time 56750244 ps
CPU time 1.27 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:28 PM PDT 24
Peak memory 207360 kb
Host smart-dfba533b-65dc-4429-ae22-00cbf60c227b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141019014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.141019014
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3267170056
Short name T1144
Test name
Test status
Simulation time 13702811 ps
CPU time 0.72 seconds
Started Jul 05 05:55:23 PM PDT 24
Finished Jul 05 05:55:25 PM PDT 24
Peak memory 204000 kb
Host smart-87ed43e2-634f-441f-acb6-1553127c9493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267170056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
267170056
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.323975073
Short name T1096
Test name
Test status
Simulation time 530995915 ps
CPU time 4.19 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 215544 kb
Host smart-f180daa6-5325-4b61-9dfc-54cf4f091427
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323975073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.323975073
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1562197476
Short name T1100
Test name
Test status
Simulation time 152891399 ps
CPU time 4.25 seconds
Started Jul 05 05:55:20 PM PDT 24
Finished Jul 05 05:55:24 PM PDT 24
Peak memory 215836 kb
Host smart-6a2ca114-e6f7-474f-9e4d-9c67b1726cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562197476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
562197476
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1874544879
Short name T1042
Test name
Test status
Simulation time 1180726819 ps
CPU time 8.26 seconds
Started Jul 05 05:55:27 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 215408 kb
Host smart-3385ed64-6d50-4aef-bf00-4b9e0245246a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874544879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1874544879
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3096810734
Short name T160
Test name
Test status
Simulation time 1895529264 ps
CPU time 2.71 seconds
Started Jul 05 05:55:34 PM PDT 24
Finished Jul 05 05:55:38 PM PDT 24
Peak memory 218096 kb
Host smart-b51e7bd9-c50f-4d8b-b542-406f4f3964b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096810734 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3096810734
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.946497278
Short name T1095
Test name
Test status
Simulation time 165635103 ps
CPU time 1.42 seconds
Started Jul 05 05:55:26 PM PDT 24
Finished Jul 05 05:55:29 PM PDT 24
Peak memory 207356 kb
Host smart-98f8ec62-9333-4bc1-ad33-25949aaf413a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946497278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.946497278
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2877068927
Short name T1138
Test name
Test status
Simulation time 12415445 ps
CPU time 0.79 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:28 PM PDT 24
Peak memory 204020 kb
Host smart-c49328a7-5d77-4652-9dd2-0b489e1b0ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877068927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
877068927
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.497016559
Short name T1120
Test name
Test status
Simulation time 88040638 ps
CPU time 1.62 seconds
Started Jul 05 05:55:24 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 215484 kb
Host smart-0ce1320e-ee0f-4db5-9209-3347546c5b9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497016559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.497016559
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2424445889
Short name T1148
Test name
Test status
Simulation time 72364622 ps
CPU time 2.14 seconds
Started Jul 05 05:55:24 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 215640 kb
Host smart-06242c23-9380-434f-b11c-181a0a392d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424445889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
424445889
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1987367985
Short name T169
Test name
Test status
Simulation time 1177955391 ps
CPU time 19.57 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:50 PM PDT 24
Peak memory 216980 kb
Host smart-1d112998-94f6-40c1-a7da-41ef2410c749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987367985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1987367985
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.436849253
Short name T151
Test name
Test status
Simulation time 302270266 ps
CPU time 3.5 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:33 PM PDT 24
Peak memory 218252 kb
Host smart-61fb1f87-d60c-45db-a4a4-b216a9390196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436849253 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.436849253
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3523034170
Short name T1067
Test name
Test status
Simulation time 112374175 ps
CPU time 2.68 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:35 PM PDT 24
Peak memory 215520 kb
Host smart-12f914f0-3aa1-44f8-9faa-fbd35007ef86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523034170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
523034170
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.756033718
Short name T1061
Test name
Test status
Simulation time 29650359 ps
CPU time 0.8 seconds
Started Jul 05 05:55:25 PM PDT 24
Finished Jul 05 05:55:27 PM PDT 24
Peak memory 204004 kb
Host smart-aef5e6ae-395f-4206-ba47-e3e50f80f80b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756033718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.756033718
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4051343808
Short name T1039
Test name
Test status
Simulation time 51836067 ps
CPU time 1.75 seconds
Started Jul 05 05:55:28 PM PDT 24
Finished Jul 05 05:55:31 PM PDT 24
Peak memory 215540 kb
Host smart-a01f8a4e-7918-4b98-9627-e77fca3e14ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051343808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4051343808
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1301756754
Short name T109
Test name
Test status
Simulation time 553783498 ps
CPU time 4.74 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:36 PM PDT 24
Peak memory 216736 kb
Host smart-ac7ecfc3-1bcf-4a92-a20f-ac2565289314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301756754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
301756754
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3704021112
Short name T1126
Test name
Test status
Simulation time 3416649369 ps
CPU time 22.09 seconds
Started Jul 05 05:55:34 PM PDT 24
Finished Jul 05 05:55:57 PM PDT 24
Peak memory 215716 kb
Host smart-1f0a1636-7a4b-4b02-a35b-c26b7ed703b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704021112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3704021112
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.154427939
Short name T1135
Test name
Test status
Simulation time 155173955 ps
CPU time 2.6 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:33 PM PDT 24
Peak memory 217404 kb
Host smart-440b64b3-9108-4946-ae40-123ad94c5125
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154427939 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.154427939
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.492828980
Short name T1060
Test name
Test status
Simulation time 20366724 ps
CPU time 1.32 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:32 PM PDT 24
Peak memory 207324 kb
Host smart-d34ca8da-d843-46a0-896f-71116e76bb7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492828980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.492828980
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1652528993
Short name T1044
Test name
Test status
Simulation time 13173717 ps
CPU time 0.75 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:31 PM PDT 24
Peak memory 203956 kb
Host smart-5bfcbdb9-cd83-428a-94c8-6afbd61ccb09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652528993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
652528993
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2532571801
Short name T1101
Test name
Test status
Simulation time 550999697 ps
CPU time 3.62 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:35 PM PDT 24
Peak memory 215492 kb
Host smart-c3da6d35-2f11-4c7a-97b0-75817bb63fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532571801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2532571801
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1223601791
Short name T102
Test name
Test status
Simulation time 30491604 ps
CPU time 1.98 seconds
Started Jul 05 05:55:26 PM PDT 24
Finished Jul 05 05:55:29 PM PDT 24
Peak memory 215700 kb
Host smart-960da044-afa7-472b-8fd9-f8c01cc1bd52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223601791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
223601791
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.20014212
Short name T167
Test name
Test status
Simulation time 820517616 ps
CPU time 13.44 seconds
Started Jul 05 05:55:30 PM PDT 24
Finished Jul 05 05:55:45 PM PDT 24
Peak memory 215884 kb
Host smart-95dcb635-9319-47df-8e7a-da10eabd092f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20014212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_t
l_intg_err.20014212
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1758288396
Short name T1058
Test name
Test status
Simulation time 171893222 ps
CPU time 2.75 seconds
Started Jul 05 05:55:36 PM PDT 24
Finished Jul 05 05:55:40 PM PDT 24
Peak memory 216660 kb
Host smart-cd6ff748-51db-4d6d-9e07-7a866ea30089
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758288396 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1758288396
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3454070480
Short name T152
Test name
Test status
Simulation time 149555482 ps
CPU time 1.88 seconds
Started Jul 05 05:55:31 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 207356 kb
Host smart-d7a26274-a296-4302-8cb6-4f873b03397d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454070480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
454070480
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2874861013
Short name T1112
Test name
Test status
Simulation time 24799496 ps
CPU time 0.71 seconds
Started Jul 05 05:55:29 PM PDT 24
Finished Jul 05 05:55:31 PM PDT 24
Peak memory 204300 kb
Host smart-79579ca0-afc8-4389-9a94-8bc71974e427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874861013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
874861013
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3215894527
Short name T1088
Test name
Test status
Simulation time 48187150 ps
CPU time 1.73 seconds
Started Jul 05 05:55:31 PM PDT 24
Finished Jul 05 05:55:34 PM PDT 24
Peak memory 207356 kb
Host smart-f03bd7db-af8f-467b-a905-683f6fd9f516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215894527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3215894527
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1204859301
Short name T104
Test name
Test status
Simulation time 61916619 ps
CPU time 1.76 seconds
Started Jul 05 05:55:28 PM PDT 24
Finished Jul 05 05:55:31 PM PDT 24
Peak memory 215656 kb
Host smart-f1e3315e-3531-4004-8278-b471ce7d8e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204859301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
204859301
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1453325890
Short name T1010
Test name
Test status
Simulation time 42572059 ps
CPU time 0.71 seconds
Started Jul 05 06:24:59 PM PDT 24
Finished Jul 05 06:25:01 PM PDT 24
Peak memory 206360 kb
Host smart-513d4d0b-396e-4315-a4c0-5b007a4bf9bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453325890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
453325890
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3165000803
Short name T792
Test name
Test status
Simulation time 133200748 ps
CPU time 2.46 seconds
Started Jul 05 06:24:45 PM PDT 24
Finished Jul 05 06:24:48 PM PDT 24
Peak memory 233724 kb
Host smart-4efb8f1d-ef35-4d76-943e-e30d7c69b83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165000803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3165000803
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.672551991
Short name T343
Test name
Test status
Simulation time 18241893 ps
CPU time 0.77 seconds
Started Jul 05 06:24:40 PM PDT 24
Finished Jul 05 06:24:41 PM PDT 24
Peak memory 206532 kb
Host smart-42747da0-49af-4ea9-b931-c6469b912705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672551991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.672551991
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2914158083
Short name T909
Test name
Test status
Simulation time 17516438534 ps
CPU time 155.09 seconds
Started Jul 05 06:24:52 PM PDT 24
Finished Jul 05 06:27:27 PM PDT 24
Peak memory 255880 kb
Host smart-2e9a754d-ae02-414f-bd41-09b4f80dc5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914158083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2914158083
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.433994114
Short name T301
Test name
Test status
Simulation time 994475178 ps
CPU time 15.71 seconds
Started Jul 05 06:24:52 PM PDT 24
Finished Jul 05 06:25:08 PM PDT 24
Peak memory 218920 kb
Host smart-a0795d7b-0d02-4070-9559-aed20245a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433994114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.433994114
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3202034953
Short name T208
Test name
Test status
Simulation time 3223141652 ps
CPU time 75.97 seconds
Started Jul 05 06:24:54 PM PDT 24
Finished Jul 05 06:26:10 PM PDT 24
Peak memory 252588 kb
Host smart-01136e93-dc23-49c7-9a29-6cf0a1a2ce84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202034953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3202034953
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1866154351
Short name T674
Test name
Test status
Simulation time 4715841244 ps
CPU time 22.88 seconds
Started Jul 05 06:24:49 PM PDT 24
Finished Jul 05 06:25:12 PM PDT 24
Peak memory 250320 kb
Host smart-66c5f47b-16fd-4340-a39e-028b149136ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866154351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1866154351
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2068956638
Short name T930
Test name
Test status
Simulation time 2217829240 ps
CPU time 31.61 seconds
Started Jul 05 06:24:45 PM PDT 24
Finished Jul 05 06:25:17 PM PDT 24
Peak memory 236528 kb
Host smart-a9a94fa4-53f1-4faf-9349-729aee220f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068956638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2068956638
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1413090558
Short name T230
Test name
Test status
Simulation time 124193257 ps
CPU time 4.12 seconds
Started Jul 05 06:24:46 PM PDT 24
Finished Jul 05 06:24:50 PM PDT 24
Peak memory 233744 kb
Host smart-ebf27b14-84b7-45d7-8305-bf2a2740202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413090558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1413090558
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.128345318
Short name T252
Test name
Test status
Simulation time 13717008833 ps
CPU time 13.68 seconds
Started Jul 05 06:24:46 PM PDT 24
Finished Jul 05 06:25:00 PM PDT 24
Peak memory 233896 kb
Host smart-92d68dc0-593d-48d9-a5d0-dd1d9facb076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128345318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
128345318
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.398137166
Short name T541
Test name
Test status
Simulation time 1694029371 ps
CPU time 8.46 seconds
Started Jul 05 06:24:45 PM PDT 24
Finished Jul 05 06:24:54 PM PDT 24
Peak memory 233824 kb
Host smart-852f1d29-9e2f-46e0-8c9d-b885742523ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398137166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.398137166
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1013605218
Short name T997
Test name
Test status
Simulation time 2328051046 ps
CPU time 12.78 seconds
Started Jul 05 06:24:52 PM PDT 24
Finished Jul 05 06:25:05 PM PDT 24
Peak memory 221648 kb
Host smart-cb70725e-3ac6-4deb-8f8a-a0d88a721e21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1013605218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1013605218
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.101313828
Short name T275
Test name
Test status
Simulation time 177313437121 ps
CPU time 424.59 seconds
Started Jul 05 06:24:52 PM PDT 24
Finished Jul 05 06:31:57 PM PDT 24
Peak memory 266312 kb
Host smart-3e4cb69c-60b0-43ea-9cc3-ea7b81be3755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101313828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.101313828
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1734636962
Short name T515
Test name
Test status
Simulation time 35797086 ps
CPU time 0.73 seconds
Started Jul 05 06:24:39 PM PDT 24
Finished Jul 05 06:24:40 PM PDT 24
Peak memory 206680 kb
Host smart-a1bdf245-4d76-4af8-b0a9-7aafc99e5a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734636962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1734636962
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1970923823
Short name T322
Test name
Test status
Simulation time 13815955 ps
CPU time 0.74 seconds
Started Jul 05 06:24:38 PM PDT 24
Finished Jul 05 06:24:40 PM PDT 24
Peak memory 206676 kb
Host smart-95cb7775-3b04-49e1-93fb-1315c1341875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970923823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1970923823
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.583320956
Short name T40
Test name
Test status
Simulation time 286681463 ps
CPU time 5.17 seconds
Started Jul 05 06:24:38 PM PDT 24
Finished Jul 05 06:24:44 PM PDT 24
Peak memory 217300 kb
Host smart-655e07a6-7e41-4644-8a75-9c7c3161db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583320956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.583320956
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1809946866
Short name T922
Test name
Test status
Simulation time 96273421 ps
CPU time 0.84 seconds
Started Jul 05 06:24:40 PM PDT 24
Finished Jul 05 06:24:41 PM PDT 24
Peak memory 208028 kb
Host smart-67b0d784-dc6f-46fe-9384-c16b79afa527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809946866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1809946866
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.800728402
Short name T795
Test name
Test status
Simulation time 3310210048 ps
CPU time 11.58 seconds
Started Jul 05 06:24:46 PM PDT 24
Finished Jul 05 06:24:58 PM PDT 24
Peak memory 233932 kb
Host smart-47309f7d-d7bd-4b65-9005-1c0b3b10c51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800728402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.800728402
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.239016646
Short name T698
Test name
Test status
Simulation time 240853735 ps
CPU time 0.73 seconds
Started Jul 05 06:25:14 PM PDT 24
Finished Jul 05 06:25:15 PM PDT 24
Peak memory 206416 kb
Host smart-eda6f2a9-00f2-492f-a9dc-7a7d3d928d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239016646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.239016646
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.309759656
Short name T85
Test name
Test status
Simulation time 710936223 ps
CPU time 4.59 seconds
Started Jul 05 06:25:00 PM PDT 24
Finished Jul 05 06:25:05 PM PDT 24
Peak memory 233784 kb
Host smart-5f90bd51-6116-4e17-bd03-a1785b2c0ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309759656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.309759656
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.58729809
Short name T970
Test name
Test status
Simulation time 39059220 ps
CPU time 0.81 seconds
Started Jul 05 06:24:59 PM PDT 24
Finished Jul 05 06:25:00 PM PDT 24
Peak memory 207540 kb
Host smart-e25fc5ce-9a66-4ad4-8aeb-19ba26c52b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58729809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.58729809
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4000320058
Short name T470
Test name
Test status
Simulation time 64787849 ps
CPU time 0.8 seconds
Started Jul 05 06:25:08 PM PDT 24
Finished Jul 05 06:25:09 PM PDT 24
Peak memory 216944 kb
Host smart-b669bf8c-d595-4544-94c8-a9a62986458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000320058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4000320058
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1435844035
Short name T193
Test name
Test status
Simulation time 30238592147 ps
CPU time 370.5 seconds
Started Jul 05 06:25:07 PM PDT 24
Finished Jul 05 06:31:18 PM PDT 24
Peak memory 270408 kb
Host smart-eeb1c4d4-51c9-4160-bedc-445857c97637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435844035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1435844035
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1149433690
Short name T867
Test name
Test status
Simulation time 9462913018 ps
CPU time 42.58 seconds
Started Jul 05 06:25:08 PM PDT 24
Finished Jul 05 06:25:51 PM PDT 24
Peak memory 225844 kb
Host smart-de3a8e74-3982-4472-953b-71a39d833d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149433690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1149433690
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2017302229
Short name T293
Test name
Test status
Simulation time 4388119328 ps
CPU time 41.5 seconds
Started Jul 05 06:25:08 PM PDT 24
Finished Jul 05 06:25:49 PM PDT 24
Peak memory 242116 kb
Host smart-d137db2d-30c4-4550-8dd0-c473bda80543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017302229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2017302229
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.120282982
Short name T191
Test name
Test status
Simulation time 5443315446 ps
CPU time 78.24 seconds
Started Jul 05 06:25:09 PM PDT 24
Finished Jul 05 06:26:27 PM PDT 24
Peak memory 267620 kb
Host smart-91ef168a-2c2d-44fa-96d2-14109ba8d9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120282982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
120282982
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.807347644
Short name T379
Test name
Test status
Simulation time 449238581 ps
CPU time 4.14 seconds
Started Jul 05 06:25:00 PM PDT 24
Finished Jul 05 06:25:05 PM PDT 24
Peak memory 233760 kb
Host smart-76bde1c6-67e5-468f-adde-55b089676fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807347644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.807347644
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3723586883
Short name T659
Test name
Test status
Simulation time 920978542 ps
CPU time 4.43 seconds
Started Jul 05 06:24:59 PM PDT 24
Finished Jul 05 06:25:04 PM PDT 24
Peak memory 225576 kb
Host smart-c65f765c-c9ef-4752-b9c5-01e34e718902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723586883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3723586883
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1453958916
Short name T367
Test name
Test status
Simulation time 88307071 ps
CPU time 1.08 seconds
Started Jul 05 06:24:59 PM PDT 24
Finished Jul 05 06:25:01 PM PDT 24
Peak memory 217660 kb
Host smart-143a8f5e-cead-49fd-90c2-b11dfacd7d29
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453958916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1453958916
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3932860419
Short name T134
Test name
Test status
Simulation time 1449354678 ps
CPU time 5.95 seconds
Started Jul 05 06:24:59 PM PDT 24
Finished Jul 05 06:25:06 PM PDT 24
Peak memory 225584 kb
Host smart-90143e97-97b2-4bab-8ef1-22607277d59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932860419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3932860419
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3128584476
Short name T662
Test name
Test status
Simulation time 5889925375 ps
CPU time 5.39 seconds
Started Jul 05 06:25:00 PM PDT 24
Finished Jul 05 06:25:06 PM PDT 24
Peak memory 225704 kb
Host smart-5404fc47-aefe-47b0-992f-984bd1dd1e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128584476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3128584476
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1568920082
Short name T467
Test name
Test status
Simulation time 993112704 ps
CPU time 7.78 seconds
Started Jul 05 06:25:06 PM PDT 24
Finished Jul 05 06:25:14 PM PDT 24
Peak memory 221276 kb
Host smart-1bf38112-8bfe-4f5a-b969-8e0ac4b93c54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1568920082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1568920082
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2528551060
Short name T63
Test name
Test status
Simulation time 1690149623 ps
CPU time 1.17 seconds
Started Jul 05 06:25:09 PM PDT 24
Finished Jul 05 06:25:10 PM PDT 24
Peak memory 237408 kb
Host smart-f7746326-c51a-4654-8506-9ad983a91459
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528551060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2528551060
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3117913017
Short name T47
Test name
Test status
Simulation time 37096265388 ps
CPU time 191.37 seconds
Started Jul 05 06:25:07 PM PDT 24
Finished Jul 05 06:28:19 PM PDT 24
Peak memory 256480 kb
Host smart-cb6d76a0-2688-48ec-8cda-4b0eb97c66fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117913017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3117913017
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.767132407
Short name T860
Test name
Test status
Simulation time 7812931735 ps
CPU time 21.46 seconds
Started Jul 05 06:25:00 PM PDT 24
Finished Jul 05 06:25:22 PM PDT 24
Peak memory 217532 kb
Host smart-61e8c128-5597-4e67-93fb-b2bca37f3677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767132407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.767132407
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2368581614
Short name T907
Test name
Test status
Simulation time 365568954 ps
CPU time 3.19 seconds
Started Jul 05 06:24:59 PM PDT 24
Finished Jul 05 06:25:03 PM PDT 24
Peak memory 217408 kb
Host smart-3e43d5d5-1984-4ea5-9119-ad485c7985ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368581614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2368581614
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.116681490
Short name T310
Test name
Test status
Simulation time 229499036 ps
CPU time 1.33 seconds
Started Jul 05 06:25:00 PM PDT 24
Finished Jul 05 06:25:02 PM PDT 24
Peak memory 217448 kb
Host smart-0cb6c9fe-8f8f-4ba3-a462-800b4220c297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116681490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.116681490
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2408765105
Short name T854
Test name
Test status
Simulation time 155971261 ps
CPU time 0.93 seconds
Started Jul 05 06:25:01 PM PDT 24
Finished Jul 05 06:25:02 PM PDT 24
Peak memory 208016 kb
Host smart-be75cada-9353-46e6-804b-9512370ee36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408765105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2408765105
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1297410100
Short name T594
Test name
Test status
Simulation time 502930362 ps
CPU time 2.44 seconds
Started Jul 05 06:24:58 PM PDT 24
Finished Jul 05 06:25:01 PM PDT 24
Peak memory 218100 kb
Host smart-1a6cd03d-68fa-4fe6-8426-a33e9e575ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297410100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1297410100
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3815898877
Short name T873
Test name
Test status
Simulation time 24459685 ps
CPU time 0.73 seconds
Started Jul 05 06:26:54 PM PDT 24
Finished Jul 05 06:26:55 PM PDT 24
Peak memory 205824 kb
Host smart-30361861-ddef-48ab-abbf-23ded625ed52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815898877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3815898877
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1199785971
Short name T718
Test name
Test status
Simulation time 410227420 ps
CPU time 3.54 seconds
Started Jul 05 06:26:49 PM PDT 24
Finished Jul 05 06:26:53 PM PDT 24
Peak memory 225596 kb
Host smart-b808346f-dea6-4512-929b-f2bbcab8a56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199785971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1199785971
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1497168791
Short name T996
Test name
Test status
Simulation time 55525507 ps
CPU time 0.75 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:26:41 PM PDT 24
Peak memory 207540 kb
Host smart-2df34f0d-2350-4c5e-b032-c32f9d119e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497168791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1497168791
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3489359823
Short name T811
Test name
Test status
Simulation time 1846398856 ps
CPU time 44.89 seconds
Started Jul 05 06:26:47 PM PDT 24
Finished Jul 05 06:27:32 PM PDT 24
Peak memory 253092 kb
Host smart-c684cdc1-37ae-47b0-9771-676fe315cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489359823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3489359823
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.317216090
Short name T843
Test name
Test status
Simulation time 8192980958 ps
CPU time 65.19 seconds
Started Jul 05 06:26:50 PM PDT 24
Finished Jul 05 06:27:56 PM PDT 24
Peak memory 242256 kb
Host smart-18552c49-235b-4e73-ad05-ec312f841d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317216090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.317216090
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.14941704
Short name T615
Test name
Test status
Simulation time 18580988088 ps
CPU time 108.11 seconds
Started Jul 05 06:26:48 PM PDT 24
Finished Jul 05 06:28:37 PM PDT 24
Peak memory 258624 kb
Host smart-f8aaaac2-bf4c-4e5e-bb10-6a16e64f4bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14941704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.14941704
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1178017095
Short name T884
Test name
Test status
Simulation time 297964017 ps
CPU time 6.11 seconds
Started Jul 05 06:26:47 PM PDT 24
Finished Jul 05 06:26:54 PM PDT 24
Peak memory 225624 kb
Host smart-b3fd1d08-e326-46dc-9407-e400406f5701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178017095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1178017095
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.375774704
Short name T246
Test name
Test status
Simulation time 112622516647 ps
CPU time 103.82 seconds
Started Jul 05 06:26:49 PM PDT 24
Finished Jul 05 06:28:33 PM PDT 24
Peak memory 253368 kb
Host smart-929d9142-624e-48c5-a74a-894eef3be409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375774704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.375774704
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4005873440
Short name T181
Test name
Test status
Simulation time 282849986 ps
CPU time 3.08 seconds
Started Jul 05 06:26:47 PM PDT 24
Finished Jul 05 06:26:51 PM PDT 24
Peak memory 225532 kb
Host smart-0a480911-1d62-4a5b-83d0-0eac8f532400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005873440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4005873440
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3859313599
Short name T643
Test name
Test status
Simulation time 28762056680 ps
CPU time 86.01 seconds
Started Jul 05 06:26:46 PM PDT 24
Finished Jul 05 06:28:12 PM PDT 24
Peak memory 251184 kb
Host smart-d491295f-8686-4d98-88cf-06e32853e7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859313599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3859313599
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3592476706
Short name T787
Test name
Test status
Simulation time 28970974 ps
CPU time 1.08 seconds
Started Jul 05 06:26:48 PM PDT 24
Finished Jul 05 06:26:50 PM PDT 24
Peak memory 217700 kb
Host smart-78a41b65-8262-428f-b25c-404bb2575079
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592476706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3592476706
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3851805164
Short name T527
Test name
Test status
Simulation time 1755562496 ps
CPU time 3.78 seconds
Started Jul 05 06:26:50 PM PDT 24
Finished Jul 05 06:26:54 PM PDT 24
Peak memory 225612 kb
Host smart-da372b4a-baff-4ded-b265-5b6b488c7072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851805164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3851805164
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3741619458
Short name T362
Test name
Test status
Simulation time 110075269 ps
CPU time 2.44 seconds
Started Jul 05 06:26:47 PM PDT 24
Finished Jul 05 06:26:50 PM PDT 24
Peak memory 233524 kb
Host smart-4518cf3e-f33a-4f76-a676-a5795981b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741619458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3741619458
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.698541231
Short name T589
Test name
Test status
Simulation time 1022085911 ps
CPU time 9.44 seconds
Started Jul 05 06:26:50 PM PDT 24
Finished Jul 05 06:27:00 PM PDT 24
Peak memory 224568 kb
Host smart-1e1b9d4a-2953-46f3-8948-317d7a1790b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=698541231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.698541231
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1618617372
Short name T649
Test name
Test status
Simulation time 33874932929 ps
CPU time 197.86 seconds
Started Jul 05 06:26:49 PM PDT 24
Finished Jul 05 06:30:07 PM PDT 24
Peak memory 257376 kb
Host smart-d91c3b8f-ac03-4a19-b1e6-392ccc7af291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618617372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1618617372
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2182247692
Short name T729
Test name
Test status
Simulation time 11774506416 ps
CPU time 12.23 seconds
Started Jul 05 06:26:51 PM PDT 24
Finished Jul 05 06:27:04 PM PDT 24
Peak memory 217444 kb
Host smart-c1ad870b-4db3-4781-8bbd-a248c67d320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182247692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2182247692
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.215923751
Short name T731
Test name
Test status
Simulation time 1287380893 ps
CPU time 5.47 seconds
Started Jul 05 06:26:48 PM PDT 24
Finished Jul 05 06:26:54 PM PDT 24
Peak memory 217376 kb
Host smart-f87a023e-baa4-40a7-8f64-3f7b15cd260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215923751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.215923751
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2867500099
Short name T785
Test name
Test status
Simulation time 23689573 ps
CPU time 0.8 seconds
Started Jul 05 06:26:46 PM PDT 24
Finished Jul 05 06:26:48 PM PDT 24
Peak memory 207024 kb
Host smart-a7d5d935-aa9f-4fb7-9079-1e7ffd1e6a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867500099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2867500099
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.719022541
Short name T418
Test name
Test status
Simulation time 45869223 ps
CPU time 0.88 seconds
Started Jul 05 06:26:48 PM PDT 24
Finished Jul 05 06:26:49 PM PDT 24
Peak memory 207284 kb
Host smart-53352a3b-046b-40aa-8998-5946799d2dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719022541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.719022541
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1878158340
Short name T838
Test name
Test status
Simulation time 1307620674 ps
CPU time 6.55 seconds
Started Jul 05 06:26:46 PM PDT 24
Finished Jul 05 06:26:53 PM PDT 24
Peak memory 225524 kb
Host smart-b4f7ed2f-1988-4f72-b7f2-3b9bed17d4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878158340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1878158340
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2837828509
Short name T553
Test name
Test status
Simulation time 32109903 ps
CPU time 0.73 seconds
Started Jul 05 06:27:01 PM PDT 24
Finished Jul 05 06:27:03 PM PDT 24
Peak memory 205732 kb
Host smart-7b9d3598-2ccf-4766-b003-cbf361908896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837828509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2837828509
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.232604031
Short name T401
Test name
Test status
Simulation time 85945046 ps
CPU time 2.61 seconds
Started Jul 05 06:26:55 PM PDT 24
Finished Jul 05 06:26:58 PM PDT 24
Peak memory 225632 kb
Host smart-611668d6-c09d-4c30-97ad-2da3066dea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232604031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.232604031
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4078119246
Short name T387
Test name
Test status
Simulation time 189655999 ps
CPU time 0.82 seconds
Started Jul 05 06:26:54 PM PDT 24
Finished Jul 05 06:26:56 PM PDT 24
Peak memory 207876 kb
Host smart-fa2213b3-0a62-4344-9c94-9f24682848af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078119246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4078119246
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.532108007
Short name T190
Test name
Test status
Simulation time 4206311937 ps
CPU time 73.22 seconds
Started Jul 05 06:26:56 PM PDT 24
Finished Jul 05 06:28:09 PM PDT 24
Peak memory 272516 kb
Host smart-27d84d48-b1e9-4acb-b2a2-9c2e0a18e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532108007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.532108007
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.926048209
Short name T612
Test name
Test status
Simulation time 2628043837 ps
CPU time 48.51 seconds
Started Jul 05 06:27:00 PM PDT 24
Finished Jul 05 06:27:49 PM PDT 24
Peak memory 238440 kb
Host smart-29c19037-559f-461a-93a0-837cf3783633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926048209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.926048209
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4028767179
Short name T213
Test name
Test status
Simulation time 106784556 ps
CPU time 3.2 seconds
Started Jul 05 06:26:53 PM PDT 24
Finished Jul 05 06:26:56 PM PDT 24
Peak memory 225600 kb
Host smart-51b4d089-bdff-4aea-9cb8-3512bf73bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028767179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4028767179
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2699851095
Short name T958
Test name
Test status
Simulation time 31445705 ps
CPU time 0.74 seconds
Started Jul 05 06:26:57 PM PDT 24
Finished Jul 05 06:26:58 PM PDT 24
Peak memory 208740 kb
Host smart-a3f98f6b-47ca-4af7-a9e8-ff9ba36cb2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699851095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2699851095
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3729299867
Short name T601
Test name
Test status
Simulation time 295396976 ps
CPU time 4.98 seconds
Started Jul 05 06:26:54 PM PDT 24
Finished Jul 05 06:27:00 PM PDT 24
Peak memory 225564 kb
Host smart-64d95259-2a20-409b-a31b-f9f9864b0cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729299867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3729299867
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2985327021
Short name T952
Test name
Test status
Simulation time 2504269932 ps
CPU time 9.83 seconds
Started Jul 05 06:26:58 PM PDT 24
Finished Jul 05 06:27:09 PM PDT 24
Peak memory 225712 kb
Host smart-3c2bee3b-3685-4138-b3c9-af77a359b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985327021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2985327021
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2986158764
Short name T31
Test name
Test status
Simulation time 32604454 ps
CPU time 1.03 seconds
Started Jul 05 06:26:54 PM PDT 24
Finished Jul 05 06:26:56 PM PDT 24
Peak memory 218880 kb
Host smart-29c5fcb5-9692-41a0-82e6-a06573a3798b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986158764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2986158764
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3105296113
Short name T37
Test name
Test status
Simulation time 15980194459 ps
CPU time 18.93 seconds
Started Jul 05 06:26:56 PM PDT 24
Finished Jul 05 06:27:15 PM PDT 24
Peak memory 233880 kb
Host smart-99f0b1c9-ca79-43fe-8355-9c4b9a8491a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105296113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3105296113
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.823306551
Short name T807
Test name
Test status
Simulation time 8989048458 ps
CPU time 5.68 seconds
Started Jul 05 06:26:55 PM PDT 24
Finished Jul 05 06:27:01 PM PDT 24
Peak memory 233944 kb
Host smart-fe5fe8dc-fc38-4dd8-84bf-03e8bca47d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823306551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.823306551
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3647716931
Short name T947
Test name
Test status
Simulation time 1018421327 ps
CPU time 6.31 seconds
Started Jul 05 06:26:55 PM PDT 24
Finished Jul 05 06:27:02 PM PDT 24
Peak memory 219784 kb
Host smart-0910d239-a7e3-4a6a-86fa-ff8ea2eac7a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3647716931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3647716931
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2065146502
Short name T288
Test name
Test status
Simulation time 44503662910 ps
CPU time 204.43 seconds
Started Jul 05 06:27:03 PM PDT 24
Finished Jul 05 06:30:28 PM PDT 24
Peak memory 252564 kb
Host smart-02261c48-59a2-4b2b-bf06-5cd63db26ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065146502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2065146502
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3131940607
Short name T871
Test name
Test status
Simulation time 5778713989 ps
CPU time 13.94 seconds
Started Jul 05 06:26:58 PM PDT 24
Finished Jul 05 06:27:13 PM PDT 24
Peak memory 217540 kb
Host smart-247fcb03-f8f1-4c39-b2c8-798407f09728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131940607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3131940607
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.39906204
Short name T378
Test name
Test status
Simulation time 22755418082 ps
CPU time 16.65 seconds
Started Jul 05 06:26:56 PM PDT 24
Finished Jul 05 06:27:13 PM PDT 24
Peak memory 217560 kb
Host smart-0f71012a-3e11-4b1b-86e9-9e6490f10f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39906204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.39906204
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4187316490
Short name T733
Test name
Test status
Simulation time 32932921 ps
CPU time 0.68 seconds
Started Jul 05 06:26:55 PM PDT 24
Finished Jul 05 06:26:56 PM PDT 24
Peak memory 206540 kb
Host smart-51c76672-6826-4ce3-a681-f61c619f91eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187316490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4187316490
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2558129853
Short name T24
Test name
Test status
Simulation time 83195338 ps
CPU time 0.79 seconds
Started Jul 05 06:26:58 PM PDT 24
Finished Jul 05 06:26:59 PM PDT 24
Peak memory 206988 kb
Host smart-01cc95dc-c726-4fa8-a453-2c26f84a730c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558129853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2558129853
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1193815236
Short name T834
Test name
Test status
Simulation time 615531158 ps
CPU time 8.67 seconds
Started Jul 05 06:26:57 PM PDT 24
Finished Jul 05 06:27:06 PM PDT 24
Peak memory 241992 kb
Host smart-551f782a-b5f9-451d-a924-2e8521f772d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193815236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1193815236
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.474416890
Short name T859
Test name
Test status
Simulation time 10750684 ps
CPU time 0.71 seconds
Started Jul 05 06:27:09 PM PDT 24
Finished Jul 05 06:27:10 PM PDT 24
Peak memory 205824 kb
Host smart-be8306eb-3741-4f21-b27e-2a205a94751c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474416890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.474416890
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3725449302
Short name T734
Test name
Test status
Simulation time 1939873158 ps
CPU time 13.67 seconds
Started Jul 05 06:27:06 PM PDT 24
Finished Jul 05 06:27:20 PM PDT 24
Peak memory 233860 kb
Host smart-0bd8182b-6f25-4d99-bfe6-809e684d7657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725449302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3725449302
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3082190489
Short name T357
Test name
Test status
Simulation time 31848750 ps
CPU time 0.84 seconds
Started Jul 05 06:27:02 PM PDT 24
Finished Jul 05 06:27:04 PM PDT 24
Peak memory 207548 kb
Host smart-eba1a5c1-0054-4567-89ea-317249314f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082190489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3082190489
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.367037713
Short name T265
Test name
Test status
Simulation time 11673145977 ps
CPU time 138.6 seconds
Started Jul 05 06:27:07 PM PDT 24
Finished Jul 05 06:29:27 PM PDT 24
Peak memory 273400 kb
Host smart-62bc54be-84e0-4b81-a4c7-9f1a23404475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367037713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.367037713
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.342129852
Short name T548
Test name
Test status
Simulation time 22726376114 ps
CPU time 129.72 seconds
Started Jul 05 06:27:08 PM PDT 24
Finished Jul 05 06:29:19 PM PDT 24
Peak memory 258636 kb
Host smart-e4158746-0e5d-49c5-b56e-1706a189b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342129852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.342129852
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.736082067
Short name T456
Test name
Test status
Simulation time 3909717327 ps
CPU time 54.22 seconds
Started Jul 05 06:27:08 PM PDT 24
Finished Jul 05 06:28:03 PM PDT 24
Peak memory 241388 kb
Host smart-2cf958bc-07e4-430a-8428-f3d76a8a4619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736082067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.736082067
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1510793909
Short name T951
Test name
Test status
Simulation time 9977016921 ps
CPU time 63.83 seconds
Started Jul 05 06:27:08 PM PDT 24
Finished Jul 05 06:28:13 PM PDT 24
Peak memory 251724 kb
Host smart-79323976-92e8-4e61-9b28-18377d2f99ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510793909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1510793909
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3091926459
Short name T386
Test name
Test status
Simulation time 7598761815 ps
CPU time 17.05 seconds
Started Jul 05 06:27:01 PM PDT 24
Finished Jul 05 06:27:19 PM PDT 24
Peak memory 233948 kb
Host smart-13eacdd6-c887-4cc0-9a34-00df02fb401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091926459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3091926459
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2780879320
Short name T133
Test name
Test status
Simulation time 6788857841 ps
CPU time 25.33 seconds
Started Jul 05 06:27:02 PM PDT 24
Finished Jul 05 06:27:27 PM PDT 24
Peak memory 242048 kb
Host smart-211f33ab-297d-447e-92f8-df21c2e7ee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780879320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2780879320
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2593263264
Short name T831
Test name
Test status
Simulation time 26832747 ps
CPU time 1.09 seconds
Started Jul 05 06:27:01 PM PDT 24
Finished Jul 05 06:27:03 PM PDT 24
Peak memory 218892 kb
Host smart-93764e33-29e3-46ec-80a6-5d597e8279d9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593263264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2593263264
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4077417927
Short name T1026
Test name
Test status
Simulation time 10797897387 ps
CPU time 12.51 seconds
Started Jul 05 06:27:03 PM PDT 24
Finished Jul 05 06:27:16 PM PDT 24
Peak memory 250276 kb
Host smart-2f6a8ed4-452f-4a3b-827d-6231b074cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077417927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4077417927
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1784662123
Short name T697
Test name
Test status
Simulation time 14827552552 ps
CPU time 37.62 seconds
Started Jul 05 06:27:01 PM PDT 24
Finished Jul 05 06:27:39 PM PDT 24
Peak memory 250284 kb
Host smart-0fb889e8-14d1-4342-9e98-9db6efaf077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784662123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1784662123
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3695619424
Short name T148
Test name
Test status
Simulation time 4301918698 ps
CPU time 12.79 seconds
Started Jul 05 06:27:07 PM PDT 24
Finished Jul 05 06:27:21 PM PDT 24
Peak memory 221432 kb
Host smart-8ccfb0db-5e88-473f-90fc-8934e4c94a39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3695619424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3695619424
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3742606204
Short name T21
Test name
Test status
Simulation time 8284574561 ps
CPU time 99.48 seconds
Started Jul 05 06:27:07 PM PDT 24
Finished Jul 05 06:28:47 PM PDT 24
Peak memory 258608 kb
Host smart-eed53d86-932c-464e-adf0-a9ed01a30d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742606204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3742606204
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2647714149
Short name T299
Test name
Test status
Simulation time 35416114068 ps
CPU time 41.68 seconds
Started Jul 05 06:27:01 PM PDT 24
Finished Jul 05 06:27:43 PM PDT 24
Peak memory 217696 kb
Host smart-5233cf71-7bcf-4021-b26f-88e332e9c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647714149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2647714149
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.600934249
Short name T977
Test name
Test status
Simulation time 574586365 ps
CPU time 2.3 seconds
Started Jul 05 06:27:01 PM PDT 24
Finished Jul 05 06:27:04 PM PDT 24
Peak memory 208104 kb
Host smart-ac243706-ceb6-4acd-919e-6362f3f6c5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600934249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.600934249
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4198495740
Short name T723
Test name
Test status
Simulation time 1285635539 ps
CPU time 1.73 seconds
Started Jul 05 06:27:04 PM PDT 24
Finished Jul 05 06:27:06 PM PDT 24
Peak memory 217388 kb
Host smart-c87df001-d8ee-4f10-a9cc-eee667479a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198495740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4198495740
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3331139223
Short name T457
Test name
Test status
Simulation time 109485953 ps
CPU time 0.95 seconds
Started Jul 05 06:27:01 PM PDT 24
Finished Jul 05 06:27:03 PM PDT 24
Peak memory 207348 kb
Host smart-7de282be-e6fb-4b7a-b50f-83b3b3d23119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331139223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3331139223
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1615562589
Short name T374
Test name
Test status
Simulation time 99475194 ps
CPU time 2.19 seconds
Started Jul 05 06:27:01 PM PDT 24
Finished Jul 05 06:27:04 PM PDT 24
Peak memory 225260 kb
Host smart-f5252ddf-a2df-4151-b7c0-4bcecae41585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615562589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1615562589
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.675001201
Short name T740
Test name
Test status
Simulation time 14181100 ps
CPU time 0.72 seconds
Started Jul 05 06:27:26 PM PDT 24
Finished Jul 05 06:27:27 PM PDT 24
Peak memory 206392 kb
Host smart-17577b07-fd58-42c8-876b-9d59b200e722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675001201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.675001201
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3818950363
Short name T628
Test name
Test status
Simulation time 143030973 ps
CPU time 3.93 seconds
Started Jul 05 06:27:17 PM PDT 24
Finished Jul 05 06:27:22 PM PDT 24
Peak memory 225584 kb
Host smart-45713ffc-580e-42e9-b9e5-322c1141156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818950363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3818950363
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3235001965
Short name T345
Test name
Test status
Simulation time 48858607 ps
CPU time 0.76 seconds
Started Jul 05 06:27:07 PM PDT 24
Finished Jul 05 06:27:08 PM PDT 24
Peak memory 206856 kb
Host smart-75890b23-b526-4f0e-9481-1892560c6ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235001965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3235001965
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2171947858
Short name T816
Test name
Test status
Simulation time 73874326088 ps
CPU time 200.31 seconds
Started Jul 05 06:27:26 PM PDT 24
Finished Jul 05 06:30:47 PM PDT 24
Peak memory 254456 kb
Host smart-01e3fec0-6dcf-4281-9cf1-fd1be82edde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171947858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2171947858
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2100465797
Short name T862
Test name
Test status
Simulation time 8626569897 ps
CPU time 42.03 seconds
Started Jul 05 06:27:22 PM PDT 24
Finished Jul 05 06:28:05 PM PDT 24
Peak memory 250432 kb
Host smart-ea8c218d-e6e6-45c6-bbae-14d9cc0f0444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100465797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2100465797
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.671511709
Short name T776
Test name
Test status
Simulation time 377607012 ps
CPU time 2.7 seconds
Started Jul 05 06:27:16 PM PDT 24
Finished Jul 05 06:27:19 PM PDT 24
Peak memory 225616 kb
Host smart-6b40f7e7-cd05-4f02-afed-3f7e22ad9d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671511709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.671511709
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1803999365
Short name T264
Test name
Test status
Simulation time 364808159065 ps
CPU time 517.33 seconds
Started Jul 05 06:27:16 PM PDT 24
Finished Jul 05 06:35:54 PM PDT 24
Peak memory 269064 kb
Host smart-211202ca-1912-456c-bc69-492897bb4546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803999365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1803999365
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1851410382
Short name T826
Test name
Test status
Simulation time 16960361529 ps
CPU time 10.67 seconds
Started Jul 05 06:27:16 PM PDT 24
Finished Jul 05 06:27:27 PM PDT 24
Peak memory 225668 kb
Host smart-3afd34d7-8c67-4629-a63a-2e7efd391711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851410382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1851410382
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.603183071
Short name T883
Test name
Test status
Simulation time 13536433964 ps
CPU time 58.68 seconds
Started Jul 05 06:27:16 PM PDT 24
Finished Jul 05 06:28:15 PM PDT 24
Peak memory 233956 kb
Host smart-1c3acecb-6b55-415d-8401-ed57fb06a53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603183071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.603183071
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1839682130
Short name T376
Test name
Test status
Simulation time 51561943 ps
CPU time 1.09 seconds
Started Jul 05 06:27:16 PM PDT 24
Finished Jul 05 06:27:18 PM PDT 24
Peak memory 217676 kb
Host smart-27c04b6d-66c3-46a6-b25d-fe378973754d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839682130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1839682130
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1043530560
Short name T198
Test name
Test status
Simulation time 9944437248 ps
CPU time 7.93 seconds
Started Jul 05 06:27:17 PM PDT 24
Finished Jul 05 06:27:26 PM PDT 24
Peak memory 233900 kb
Host smart-8161507e-9afd-476f-bbcf-035f742daa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043530560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1043530560
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.829396520
Short name T507
Test name
Test status
Simulation time 30400575 ps
CPU time 2 seconds
Started Jul 05 06:27:17 PM PDT 24
Finished Jul 05 06:27:19 PM PDT 24
Peak memory 224192 kb
Host smart-0955ed3d-4616-4d2a-8426-aa15e2efbad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829396520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.829396520
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.872591673
Short name T359
Test name
Test status
Simulation time 171003066 ps
CPU time 4.53 seconds
Started Jul 05 06:27:17 PM PDT 24
Finished Jul 05 06:27:22 PM PDT 24
Peak memory 224220 kb
Host smart-21973b10-470b-411f-9ad0-fe11f16992d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=872591673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.872591673
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1938813881
Short name T13
Test name
Test status
Simulation time 9453504503 ps
CPU time 7.57 seconds
Started Jul 05 06:27:16 PM PDT 24
Finished Jul 05 06:27:24 PM PDT 24
Peak memory 217720 kb
Host smart-de978f95-b4e5-43b9-b290-8ade3187ccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938813881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1938813881
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3054280302
Short name T874
Test name
Test status
Simulation time 1976495652 ps
CPU time 10.88 seconds
Started Jul 05 06:27:18 PM PDT 24
Finished Jul 05 06:27:29 PM PDT 24
Peak memory 217376 kb
Host smart-bb1c6722-14a8-47cd-a0a0-186ea1407d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054280302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3054280302
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.929836201
Short name T616
Test name
Test status
Simulation time 235887718 ps
CPU time 1.16 seconds
Started Jul 05 06:27:17 PM PDT 24
Finished Jul 05 06:27:18 PM PDT 24
Peak memory 217316 kb
Host smart-e0be64af-c5ea-4173-9b95-7dbdd4c91a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929836201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.929836201
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.305774041
Short name T892
Test name
Test status
Simulation time 43974840 ps
CPU time 0.86 seconds
Started Jul 05 06:27:17 PM PDT 24
Finished Jul 05 06:27:18 PM PDT 24
Peak memory 206904 kb
Host smart-cc7feda2-905c-49a6-b396-ee70327f85ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305774041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.305774041
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3262759708
Short name T575
Test name
Test status
Simulation time 3662161046 ps
CPU time 6.87 seconds
Started Jul 05 06:27:16 PM PDT 24
Finished Jul 05 06:27:23 PM PDT 24
Peak memory 233936 kb
Host smart-41461df2-cce2-440d-80e7-c1b0b97fd592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262759708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3262759708
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1666110974
Short name T502
Test name
Test status
Simulation time 734555545 ps
CPU time 4.62 seconds
Started Jul 05 06:27:25 PM PDT 24
Finished Jul 05 06:27:30 PM PDT 24
Peak memory 233760 kb
Host smart-31933350-0226-4eb6-953f-43acaf5436e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666110974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1666110974
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3943586334
Short name T58
Test name
Test status
Simulation time 23233086 ps
CPU time 0.82 seconds
Started Jul 05 06:27:22 PM PDT 24
Finished Jul 05 06:27:23 PM PDT 24
Peak memory 207552 kb
Host smart-aca55efd-6f72-4782-8afa-0fed1cc69824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943586334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3943586334
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.836175237
Short name T786
Test name
Test status
Simulation time 5065161544 ps
CPU time 36.03 seconds
Started Jul 05 06:27:26 PM PDT 24
Finished Jul 05 06:28:03 PM PDT 24
Peak memory 250672 kb
Host smart-c6966298-edfd-4e49-8d2e-a8d4ca7cee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836175237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.836175237
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3220978070
Short name T491
Test name
Test status
Simulation time 2692254999 ps
CPU time 22.56 seconds
Started Jul 05 06:27:23 PM PDT 24
Finished Jul 05 06:27:45 PM PDT 24
Peak memory 250628 kb
Host smart-49bd8167-c5a8-4487-b14a-03ecbd2ec281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220978070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3220978070
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2943634770
Short name T624
Test name
Test status
Simulation time 3965226100 ps
CPU time 44.75 seconds
Started Jul 05 06:27:23 PM PDT 24
Finished Jul 05 06:28:08 PM PDT 24
Peak memory 250308 kb
Host smart-c663bdb8-6637-4234-a010-c755a55d6831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943634770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2943634770
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3319786906
Short name T781
Test name
Test status
Simulation time 2526164513 ps
CPU time 13.19 seconds
Started Jul 05 06:27:23 PM PDT 24
Finished Jul 05 06:27:37 PM PDT 24
Peak memory 225696 kb
Host smart-da8562f1-05c2-4c77-8d10-2f5cb110f177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319786906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3319786906
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.4017957610
Short name T879
Test name
Test status
Simulation time 41721452 ps
CPU time 0.79 seconds
Started Jul 05 06:27:25 PM PDT 24
Finished Jul 05 06:27:26 PM PDT 24
Peak memory 216932 kb
Host smart-8b3b4f58-a663-4e4e-ad39-824df04765a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017957610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.4017957610
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.562626332
Short name T195
Test name
Test status
Simulation time 1484108148 ps
CPU time 10.63 seconds
Started Jul 05 06:27:23 PM PDT 24
Finished Jul 05 06:27:34 PM PDT 24
Peak memory 233832 kb
Host smart-dca786a1-4b41-4eee-bc96-92acd878fbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562626332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.562626332
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.98835921
Short name T998
Test name
Test status
Simulation time 156624934 ps
CPU time 4.5 seconds
Started Jul 05 06:27:26 PM PDT 24
Finished Jul 05 06:27:31 PM PDT 24
Peak memory 225600 kb
Host smart-006170ae-7358-4816-aeeb-11a29d39d906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98835921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.98835921
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3595758264
Short name T437
Test name
Test status
Simulation time 106482963 ps
CPU time 1.12 seconds
Started Jul 05 06:27:24 PM PDT 24
Finished Jul 05 06:27:25 PM PDT 24
Peak memory 218920 kb
Host smart-13429dfb-3f56-4305-a92d-92762d939925
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595758264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3595758264
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4115245419
Short name T531
Test name
Test status
Simulation time 2736921870 ps
CPU time 8.68 seconds
Started Jul 05 06:27:20 PM PDT 24
Finished Jul 05 06:27:29 PM PDT 24
Peak memory 241504 kb
Host smart-ebd7c0f5-3f3d-497f-a48a-8a3e371b2f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115245419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4115245419
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.325417050
Short name T841
Test name
Test status
Simulation time 239294039 ps
CPU time 5.58 seconds
Started Jul 05 06:27:24 PM PDT 24
Finished Jul 05 06:27:30 PM PDT 24
Peak memory 233780 kb
Host smart-36181481-ed81-43db-ba16-08e0efedffda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325417050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.325417050
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3326173528
Short name T833
Test name
Test status
Simulation time 242254460 ps
CPU time 4.87 seconds
Started Jul 05 06:27:26 PM PDT 24
Finished Jul 05 06:27:31 PM PDT 24
Peak memory 223972 kb
Host smart-156330c9-e9fd-4a5b-a3b6-7fb65380a3b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3326173528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3326173528
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4213498906
Short name T824
Test name
Test status
Simulation time 1257524949 ps
CPU time 5.25 seconds
Started Jul 05 06:27:21 PM PDT 24
Finished Jul 05 06:27:26 PM PDT 24
Peak memory 217684 kb
Host smart-8037eb6c-ca45-49a8-8277-62480cabd87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213498906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4213498906
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.691736890
Short name T658
Test name
Test status
Simulation time 10642561734 ps
CPU time 23.22 seconds
Started Jul 05 06:27:29 PM PDT 24
Finished Jul 05 06:27:53 PM PDT 24
Peak memory 217464 kb
Host smart-eaa0adb7-1514-4943-adee-84f88e2fa9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691736890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.691736890
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1006786162
Short name T383
Test name
Test status
Simulation time 47564255 ps
CPU time 0.89 seconds
Started Jul 05 06:27:26 PM PDT 24
Finished Jul 05 06:27:28 PM PDT 24
Peak memory 207752 kb
Host smart-9ad247d2-dcdd-455a-b04b-a19f28b87c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006786162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1006786162
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.395416141
Short name T415
Test name
Test status
Simulation time 42970981 ps
CPU time 0.78 seconds
Started Jul 05 06:27:23 PM PDT 24
Finished Jul 05 06:27:24 PM PDT 24
Peak memory 206996 kb
Host smart-d38c9ae9-d0dc-4ab8-bd96-0514b85c5eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395416141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.395416141
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.134935591
Short name T261
Test name
Test status
Simulation time 11846977285 ps
CPU time 20.11 seconds
Started Jul 05 06:27:23 PM PDT 24
Finished Jul 05 06:27:43 PM PDT 24
Peak memory 245108 kb
Host smart-ed1b4d5d-ddd9-4a22-9118-f3221ab56d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134935591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.134935591
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.265256074
Short name T978
Test name
Test status
Simulation time 23883493 ps
CPU time 0.69 seconds
Started Jul 05 06:27:38 PM PDT 24
Finished Jul 05 06:27:39 PM PDT 24
Peak memory 206336 kb
Host smart-2b1ca1e0-7a81-44b8-8752-7669844ce462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265256074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.265256074
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4024825876
Short name T130
Test name
Test status
Simulation time 7962750946 ps
CPU time 17.73 seconds
Started Jul 05 06:27:31 PM PDT 24
Finished Jul 05 06:27:49 PM PDT 24
Peak memory 233892 kb
Host smart-3d477e5e-c1e8-40c8-9598-b77839c3586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024825876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4024825876
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1854748800
Short name T783
Test name
Test status
Simulation time 77565795 ps
CPU time 0.75 seconds
Started Jul 05 06:27:28 PM PDT 24
Finished Jul 05 06:27:29 PM PDT 24
Peak memory 206516 kb
Host smart-bb0e7667-5bac-4ca6-8cb8-8fe443da773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854748800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1854748800
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.853794833
Short name T23
Test name
Test status
Simulation time 32687109329 ps
CPU time 106.72 seconds
Started Jul 05 06:27:33 PM PDT 24
Finished Jul 05 06:29:20 PM PDT 24
Peak memory 250328 kb
Host smart-08830bee-7364-4567-b839-cd4fd2aa39c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853794833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.853794833
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1652317070
Short name T519
Test name
Test status
Simulation time 473529719 ps
CPU time 3.47 seconds
Started Jul 05 06:27:28 PM PDT 24
Finished Jul 05 06:27:32 PM PDT 24
Peak memory 233800 kb
Host smart-6ff913fc-3878-442e-90f6-2afb99148551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652317070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1652317070
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3314439022
Short name T255
Test name
Test status
Simulation time 24112334538 ps
CPU time 82.08 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:29:00 PM PDT 24
Peak memory 233876 kb
Host smart-8ff983ec-507c-4249-9233-ed6267cc4f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314439022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3314439022
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3121991929
Short name T906
Test name
Test status
Simulation time 61593457 ps
CPU time 2.3 seconds
Started Jul 05 06:27:28 PM PDT 24
Finished Jul 05 06:27:31 PM PDT 24
Peak memory 233504 kb
Host smart-ffe96293-6d6f-462f-a8e7-d388a087d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121991929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3121991929
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4178511794
Short name T636
Test name
Test status
Simulation time 436742753 ps
CPU time 2.49 seconds
Started Jul 05 06:27:30 PM PDT 24
Finished Jul 05 06:27:33 PM PDT 24
Peak memory 225412 kb
Host smart-f8788e57-e56a-4d81-92f2-2c4857ef1d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178511794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4178511794
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.784875274
Short name T493
Test name
Test status
Simulation time 28029849 ps
CPU time 1.12 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:27:39 PM PDT 24
Peak memory 217624 kb
Host smart-ef695d40-f2d4-40ab-a1b5-9d9f4acf1df1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784875274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.784875274
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.25382993
Short name T577
Test name
Test status
Simulation time 191590103 ps
CPU time 4.29 seconds
Started Jul 05 06:27:31 PM PDT 24
Finished Jul 05 06:27:35 PM PDT 24
Peak memory 225572 kb
Host smart-b06b60f2-fd3c-4f01-9c61-6e0446756886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25382993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.25382993
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3533706392
Short name T469
Test name
Test status
Simulation time 1067915417 ps
CPU time 9.73 seconds
Started Jul 05 06:27:33 PM PDT 24
Finished Jul 05 06:27:43 PM PDT 24
Peak memory 241512 kb
Host smart-c61b3491-aacb-42a6-9e21-b2018e3393e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533706392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3533706392
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2175602818
Short name T609
Test name
Test status
Simulation time 3867841787 ps
CPU time 12.42 seconds
Started Jul 05 06:27:31 PM PDT 24
Finished Jul 05 06:27:44 PM PDT 24
Peak memory 223316 kb
Host smart-365d5e2e-4cc8-4727-a1ea-aeadd0c701c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2175602818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2175602818
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3562002019
Short name T865
Test name
Test status
Simulation time 215705301828 ps
CPU time 510.06 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:36:07 PM PDT 24
Peak memory 254292 kb
Host smart-96297530-25cb-4fe3-ba92-3b6d049d8cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562002019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3562002019
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2130498233
Short name T453
Test name
Test status
Simulation time 13825853163 ps
CPU time 26.37 seconds
Started Jul 05 06:27:28 PM PDT 24
Finished Jul 05 06:27:55 PM PDT 24
Peak memory 221060 kb
Host smart-9bbb4be3-03a8-4819-b89b-7d450f810b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130498233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2130498233
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1789704151
Short name T737
Test name
Test status
Simulation time 407230477 ps
CPU time 3.76 seconds
Started Jul 05 06:27:30 PM PDT 24
Finished Jul 05 06:27:34 PM PDT 24
Peak memory 217384 kb
Host smart-2c472113-2219-41c3-887f-00d8fde7167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789704151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1789704151
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.671274841
Short name T356
Test name
Test status
Simulation time 101832571 ps
CPU time 2.6 seconds
Started Jul 05 06:27:29 PM PDT 24
Finished Jul 05 06:27:32 PM PDT 24
Peak memory 217416 kb
Host smart-9888a04b-c0dc-4806-b3a4-2a71a2a7655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671274841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.671274841
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3786200151
Short name T402
Test name
Test status
Simulation time 50893108 ps
CPU time 0.82 seconds
Started Jul 05 06:27:30 PM PDT 24
Finished Jul 05 06:27:31 PM PDT 24
Peak memory 206988 kb
Host smart-19ef78a5-1302-4f6a-aa6b-8db0b1593497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786200151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3786200151
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.419220979
Short name T9
Test name
Test status
Simulation time 73573204310 ps
CPU time 47.92 seconds
Started Jul 05 06:27:35 PM PDT 24
Finished Jul 05 06:28:23 PM PDT 24
Peak memory 233832 kb
Host smart-986d8a22-7a68-4729-bd9a-f2e9c05b5a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419220979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.419220979
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.497563393
Short name T392
Test name
Test status
Simulation time 12375015 ps
CPU time 0.72 seconds
Started Jul 05 06:27:42 PM PDT 24
Finished Jul 05 06:27:43 PM PDT 24
Peak memory 205816 kb
Host smart-b778dc29-abd6-40ad-a3a1-7ae745c304ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497563393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.497563393
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2253064344
Short name T338
Test name
Test status
Simulation time 1946442104 ps
CPU time 12.57 seconds
Started Jul 05 06:27:38 PM PDT 24
Finished Jul 05 06:27:51 PM PDT 24
Peak memory 225620 kb
Host smart-028e4d15-a0c8-4db4-85da-e934f2e68fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253064344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2253064344
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.32626558
Short name T934
Test name
Test status
Simulation time 72238015 ps
CPU time 0.79 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:27:38 PM PDT 24
Peak memory 207564 kb
Host smart-423884c5-cf9b-469a-87bf-deae7d9d3ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32626558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.32626558
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1283208772
Short name T688
Test name
Test status
Simulation time 11797097 ps
CPU time 0.76 seconds
Started Jul 05 06:27:39 PM PDT 24
Finished Jul 05 06:27:40 PM PDT 24
Peak memory 216948 kb
Host smart-27b4a805-56b7-4747-acd1-c903ec113054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283208772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1283208772
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3672933870
Short name T287
Test name
Test status
Simulation time 180249747630 ps
CPU time 474.43 seconds
Started Jul 05 06:27:39 PM PDT 24
Finished Jul 05 06:35:34 PM PDT 24
Peak memory 254680 kb
Host smart-2c8da8a6-acf2-4246-b4ff-93105f9a3349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672933870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3672933870
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1237834954
Short name T81
Test name
Test status
Simulation time 5155729224 ps
CPU time 98.71 seconds
Started Jul 05 06:27:38 PM PDT 24
Finished Jul 05 06:29:17 PM PDT 24
Peak memory 257856 kb
Host smart-2a086ece-1c97-41ba-a5ec-c936c40583c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237834954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1237834954
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2059806339
Short name T143
Test name
Test status
Simulation time 3919046211 ps
CPU time 25.28 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:28:03 PM PDT 24
Peak memory 244264 kb
Host smart-7b14d3be-2d8e-43f0-87f6-b0cb523ecfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059806339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2059806339
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2560173325
Short name T683
Test name
Test status
Simulation time 102079586405 ps
CPU time 154.08 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:30:12 PM PDT 24
Peak memory 251316 kb
Host smart-c12f920c-0e54-4e1e-9384-452dcf30f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560173325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2560173325
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.479561586
Short name T194
Test name
Test status
Simulation time 245155883 ps
CPU time 4.15 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:27:41 PM PDT 24
Peak memory 225536 kb
Host smart-646d1b0c-8549-4054-bf47-19c5bd911b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479561586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.479561586
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3093226114
Short name T593
Test name
Test status
Simulation time 810633039 ps
CPU time 13.25 seconds
Started Jul 05 06:27:35 PM PDT 24
Finished Jul 05 06:27:48 PM PDT 24
Peak memory 225576 kb
Host smart-b28f28f2-d860-4b3d-9a06-9168602fa4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093226114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3093226114
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1192715800
Short name T434
Test name
Test status
Simulation time 18331732 ps
CPU time 1.03 seconds
Started Jul 05 06:27:36 PM PDT 24
Finished Jul 05 06:27:37 PM PDT 24
Peak memory 217704 kb
Host smart-f2eab000-5082-46b2-942c-2ee02c6f5a79
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192715800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1192715800
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1083100472
Short name T950
Test name
Test status
Simulation time 17817144692 ps
CPU time 25.24 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:28:03 PM PDT 24
Peak memory 233972 kb
Host smart-e35f3f33-e938-4d51-8a58-749a84a42057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083100472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1083100472
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1851613265
Short name T680
Test name
Test status
Simulation time 426888982 ps
CPU time 6.94 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:27:44 PM PDT 24
Peak memory 236424 kb
Host smart-38968a75-b4e0-4387-b091-521b575ca258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851613265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1851613265
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1267114133
Short name T677
Test name
Test status
Simulation time 2349485524 ps
CPU time 15.55 seconds
Started Jul 05 06:27:36 PM PDT 24
Finished Jul 05 06:27:52 PM PDT 24
Peak memory 223148 kb
Host smart-a54f349e-b323-40ab-b464-842d402cfd19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1267114133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1267114133
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.113738403
Short name T159
Test name
Test status
Simulation time 202904606 ps
CPU time 1.14 seconds
Started Jul 05 06:27:43 PM PDT 24
Finished Jul 05 06:27:44 PM PDT 24
Peak memory 208860 kb
Host smart-322241f0-aa6b-420a-a645-f46245157bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113738403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.113738403
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2160462018
Short name T407
Test name
Test status
Simulation time 20814681113 ps
CPU time 34.93 seconds
Started Jul 05 06:27:36 PM PDT 24
Finished Jul 05 06:28:11 PM PDT 24
Peak memory 217508 kb
Host smart-fb299964-5aef-4376-9af3-6a7e8594c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160462018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2160462018
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3692959152
Short name T630
Test name
Test status
Simulation time 9303004397 ps
CPU time 10.97 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:27:49 PM PDT 24
Peak memory 217436 kb
Host smart-0b570c47-3829-4a82-b846-9d8109a8371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692959152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3692959152
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1408501795
Short name T830
Test name
Test status
Simulation time 1387854424 ps
CPU time 2.09 seconds
Started Jul 05 06:27:36 PM PDT 24
Finished Jul 05 06:27:38 PM PDT 24
Peak memory 217360 kb
Host smart-6cf9e384-878e-4d08-8ab4-6a7ca98fa4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408501795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1408501795
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1979160160
Short name T373
Test name
Test status
Simulation time 100387324 ps
CPU time 0.81 seconds
Started Jul 05 06:27:36 PM PDT 24
Finished Jul 05 06:27:37 PM PDT 24
Peak memory 207024 kb
Host smart-9ba0506d-f9ef-404e-8561-dac5efa50659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979160160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1979160160
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1780928253
Short name T390
Test name
Test status
Simulation time 442294161 ps
CPU time 4.21 seconds
Started Jul 05 06:27:37 PM PDT 24
Finished Jul 05 06:27:42 PM PDT 24
Peak memory 225528 kb
Host smart-40dc45a5-f647-4ea4-b401-8acaa201261e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780928253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1780928253
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.14679805
Short name T501
Test name
Test status
Simulation time 12444482 ps
CPU time 0.71 seconds
Started Jul 05 06:27:50 PM PDT 24
Finished Jul 05 06:27:51 PM PDT 24
Peak memory 206360 kb
Host smart-2e5174df-b7b4-4048-bae3-e9d1a6097014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14679805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.14679805
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1080205366
Short name T944
Test name
Test status
Simulation time 28673102185 ps
CPU time 20.67 seconds
Started Jul 05 06:27:48 PM PDT 24
Finished Jul 05 06:28:09 PM PDT 24
Peak memory 233916 kb
Host smart-db21c3e1-5eee-43ad-9ada-a04f8aeb01d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080205366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1080205366
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3196029791
Short name T574
Test name
Test status
Simulation time 20990820 ps
CPU time 0.77 seconds
Started Jul 05 06:27:48 PM PDT 24
Finished Jul 05 06:27:49 PM PDT 24
Peak memory 206516 kb
Host smart-9f4065de-ead9-4899-90da-460470f2fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196029791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3196029791
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.549521097
Short name T75
Test name
Test status
Simulation time 77939953519 ps
CPU time 115.49 seconds
Started Jul 05 06:27:50 PM PDT 24
Finished Jul 05 06:29:46 PM PDT 24
Peak memory 253196 kb
Host smart-101f97b3-383c-4f4c-aa2e-8dbb4789384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549521097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.549521097
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3427839525
Short name T823
Test name
Test status
Simulation time 41945211557 ps
CPU time 105.95 seconds
Started Jul 05 06:27:52 PM PDT 24
Finished Jul 05 06:29:38 PM PDT 24
Peak memory 250436 kb
Host smart-1b1c5408-6e1a-47fa-a9cc-66d580848a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427839525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3427839525
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2627764908
Short name T596
Test name
Test status
Simulation time 10988267495 ps
CPU time 145.09 seconds
Started Jul 05 06:27:50 PM PDT 24
Finished Jul 05 06:30:16 PM PDT 24
Peak memory 255944 kb
Host smart-5c147c94-467a-4ccd-ae55-d97d53240320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627764908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2627764908
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1759937978
Short name T966
Test name
Test status
Simulation time 353969836 ps
CPU time 3.74 seconds
Started Jul 05 06:27:42 PM PDT 24
Finished Jul 05 06:27:47 PM PDT 24
Peak memory 233976 kb
Host smart-43b2cd62-aaba-4280-a608-5d539ca32845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759937978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1759937978
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1612456504
Short name T89
Test name
Test status
Simulation time 148034896412 ps
CPU time 158.1 seconds
Started Jul 05 06:27:43 PM PDT 24
Finished Jul 05 06:30:22 PM PDT 24
Peak memory 255384 kb
Host smart-df5511e8-55bf-4b14-bf29-ab3e4979c20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612456504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1612456504
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3356474639
Short name T583
Test name
Test status
Simulation time 2030829520 ps
CPU time 10.43 seconds
Started Jul 05 06:27:48 PM PDT 24
Finished Jul 05 06:27:59 PM PDT 24
Peak memory 225612 kb
Host smart-1d75581e-7f0f-492c-80b7-b8c13b6ceeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356474639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3356474639
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4049213430
Short name T316
Test name
Test status
Simulation time 107799498 ps
CPU time 2.24 seconds
Started Jul 05 06:27:41 PM PDT 24
Finished Jul 05 06:27:44 PM PDT 24
Peak memory 223944 kb
Host smart-dd7ad104-50c6-4454-8938-54f49568ec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049213430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4049213430
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4288669908
Short name T796
Test name
Test status
Simulation time 53856633 ps
CPU time 1.08 seconds
Started Jul 05 06:27:43 PM PDT 24
Finished Jul 05 06:27:44 PM PDT 24
Peak memory 218940 kb
Host smart-d234331d-3e73-41fa-8ca6-124119cf8901
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288669908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4288669908
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.790670431
Short name T480
Test name
Test status
Simulation time 1157504649 ps
CPU time 8.32 seconds
Started Jul 05 06:27:42 PM PDT 24
Finished Jul 05 06:27:50 PM PDT 24
Peak memory 225600 kb
Host smart-224295d8-1f02-4866-99a7-56627d32f886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790670431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.790670431
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3753540938
Short name T707
Test name
Test status
Simulation time 716198893 ps
CPU time 5.57 seconds
Started Jul 05 06:27:45 PM PDT 24
Finished Jul 05 06:27:51 PM PDT 24
Peak memory 241660 kb
Host smart-acb59013-953f-4e04-8cce-8b031709142e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753540938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3753540938
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3853599772
Short name T900
Test name
Test status
Simulation time 389196383 ps
CPU time 3.73 seconds
Started Jul 05 06:27:49 PM PDT 24
Finished Jul 05 06:27:53 PM PDT 24
Peak memory 221452 kb
Host smart-31aedc69-30e1-4b80-8390-e08d41c4ffe7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3853599772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3853599772
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2328078488
Short name T648
Test name
Test status
Simulation time 34610767320 ps
CPU time 89.85 seconds
Started Jul 05 06:27:52 PM PDT 24
Finished Jul 05 06:29:22 PM PDT 24
Peak memory 238772 kb
Host smart-b89ccd79-aa37-4007-870f-f697aef1d90a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328078488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2328078488
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3591496883
Short name T769
Test name
Test status
Simulation time 2184197908 ps
CPU time 28.79 seconds
Started Jul 05 06:27:42 PM PDT 24
Finished Jul 05 06:28:11 PM PDT 24
Peak memory 217532 kb
Host smart-7e42dbb9-3d24-4f38-b85a-d602fa709e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591496883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3591496883
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.380033085
Short name T828
Test name
Test status
Simulation time 5618702986 ps
CPU time 3.35 seconds
Started Jul 05 06:27:42 PM PDT 24
Finished Jul 05 06:27:45 PM PDT 24
Peak memory 217540 kb
Host smart-35ee941d-e6a1-42c4-89ac-021b14e01a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380033085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.380033085
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1885427927
Short name T926
Test name
Test status
Simulation time 671464463 ps
CPU time 7.41 seconds
Started Jul 05 06:27:44 PM PDT 24
Finished Jul 05 06:27:51 PM PDT 24
Peak memory 217412 kb
Host smart-afec8fa7-6824-4906-8d28-eeaf423b560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885427927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1885427927
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.92557760
Short name T330
Test name
Test status
Simulation time 96987150 ps
CPU time 0.84 seconds
Started Jul 05 06:27:41 PM PDT 24
Finished Jul 05 06:27:43 PM PDT 24
Peak memory 207484 kb
Host smart-9458ec6f-812f-4fa4-b4c1-fab2393078f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92557760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.92557760
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2388652280
Short name T848
Test name
Test status
Simulation time 624907366 ps
CPU time 4.59 seconds
Started Jul 05 06:27:44 PM PDT 24
Finished Jul 05 06:27:49 PM PDT 24
Peak memory 233768 kb
Host smart-0c6b032c-44df-4fa5-928d-44e44cc5296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388652280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2388652280
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3433094004
Short name T323
Test name
Test status
Simulation time 36024993 ps
CPU time 0.74 seconds
Started Jul 05 06:28:08 PM PDT 24
Finished Jul 05 06:28:09 PM PDT 24
Peak memory 206396 kb
Host smart-3ce03b5a-c5d1-4e9a-be49-acfd050a80d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433094004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3433094004
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1455912680
Short name T318
Test name
Test status
Simulation time 31928722 ps
CPU time 2.63 seconds
Started Jul 05 06:27:56 PM PDT 24
Finished Jul 05 06:28:00 PM PDT 24
Peak memory 233520 kb
Host smart-80385748-4eef-4ff6-b099-cd9c7a290994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455912680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1455912680
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2341163674
Short name T539
Test name
Test status
Simulation time 14578938 ps
CPU time 0.82 seconds
Started Jul 05 06:27:49 PM PDT 24
Finished Jul 05 06:27:50 PM PDT 24
Peak memory 207428 kb
Host smart-ca3b4dc2-7dbf-490b-8bc9-29b87b43ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341163674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2341163674
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3499985717
Short name T202
Test name
Test status
Simulation time 28743566568 ps
CPU time 195.44 seconds
Started Jul 05 06:27:56 PM PDT 24
Finished Jul 05 06:31:12 PM PDT 24
Peak memory 253700 kb
Host smart-46d69b60-f6fc-4d8b-a01f-2193a58ff46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499985717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3499985717
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.426124248
Short name T454
Test name
Test status
Simulation time 6179477296 ps
CPU time 23.98 seconds
Started Jul 05 06:28:09 PM PDT 24
Finished Jul 05 06:28:33 PM PDT 24
Peak memory 250452 kb
Host smart-a858429e-3c37-477d-8e30-5484685fbeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426124248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.426124248
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2861718571
Short name T300
Test name
Test status
Simulation time 15004647055 ps
CPU time 20.54 seconds
Started Jul 05 06:28:09 PM PDT 24
Finished Jul 05 06:28:30 PM PDT 24
Peak memory 218864 kb
Host smart-3622d125-6cf5-45d4-8eeb-bbf3441f7d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861718571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2861718571
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3232150080
Short name T296
Test name
Test status
Simulation time 3347961829 ps
CPU time 16.56 seconds
Started Jul 05 06:27:57 PM PDT 24
Finished Jul 05 06:28:14 PM PDT 24
Peak memory 242100 kb
Host smart-04107f0f-4f08-41f3-a7a5-86beddd016af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232150080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3232150080
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3972546768
Short name T319
Test name
Test status
Simulation time 1369816232 ps
CPU time 13.92 seconds
Started Jul 05 06:27:57 PM PDT 24
Finished Jul 05 06:28:11 PM PDT 24
Peak memory 225512 kb
Host smart-aee637cb-5b12-45ab-99c5-1180f082bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972546768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3972546768
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4222348283
Short name T474
Test name
Test status
Simulation time 8920029683 ps
CPU time 46.13 seconds
Started Jul 05 06:27:56 PM PDT 24
Finished Jul 05 06:28:43 PM PDT 24
Peak memory 240660 kb
Host smart-afbbd4f0-ffde-4f08-a3c4-15d70c0d1c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222348283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4222348283
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.484891368
Short name T543
Test name
Test status
Simulation time 92601811 ps
CPU time 1.09 seconds
Started Jul 05 06:27:50 PM PDT 24
Finished Jul 05 06:27:52 PM PDT 24
Peak memory 217652 kb
Host smart-e4dda936-64a8-453e-a020-42b7c46646da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484891368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.484891368
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.723841126
Short name T135
Test name
Test status
Simulation time 890125049 ps
CPU time 6.74 seconds
Started Jul 05 06:27:57 PM PDT 24
Finished Jul 05 06:28:04 PM PDT 24
Peak memory 241964 kb
Host smart-49f76ce0-ff44-4ba0-a2a0-33fc077448f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723841126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.723841126
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3782616993
Short name T669
Test name
Test status
Simulation time 373413562 ps
CPU time 2.47 seconds
Started Jul 05 06:27:59 PM PDT 24
Finished Jul 05 06:28:01 PM PDT 24
Peak memory 233776 kb
Host smart-4d7dc4e2-482f-4feb-9718-0bc5307a8800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782616993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3782616993
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2863039366
Short name T625
Test name
Test status
Simulation time 794535581 ps
CPU time 8.26 seconds
Started Jul 05 06:27:56 PM PDT 24
Finished Jul 05 06:28:05 PM PDT 24
Peak memory 222572 kb
Host smart-87a82ac1-f446-425d-b8f4-f9a0a01158f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2863039366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2863039366
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3805659313
Short name T920
Test name
Test status
Simulation time 1563841948 ps
CPU time 20 seconds
Started Jul 05 06:27:54 PM PDT 24
Finished Jul 05 06:28:14 PM PDT 24
Peak memory 217524 kb
Host smart-d3e61def-fe34-427d-bf7d-d0f4865dfdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805659313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3805659313
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2627071166
Short name T340
Test name
Test status
Simulation time 27894176 ps
CPU time 0.72 seconds
Started Jul 05 06:27:50 PM PDT 24
Finished Jul 05 06:27:51 PM PDT 24
Peak memory 206664 kb
Host smart-8557b61e-ad73-4fbd-a2b2-caea9cdb7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627071166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2627071166
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1170011349
Short name T375
Test name
Test status
Simulation time 50571442 ps
CPU time 1.95 seconds
Started Jul 05 06:27:57 PM PDT 24
Finished Jul 05 06:27:59 PM PDT 24
Peak memory 217384 kb
Host smart-9a441842-8c12-422b-bd4b-f1b0714ae3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170011349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1170011349
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1088595511
Short name T969
Test name
Test status
Simulation time 372042939 ps
CPU time 0.99 seconds
Started Jul 05 06:27:57 PM PDT 24
Finished Jul 05 06:27:58 PM PDT 24
Peak memory 206900 kb
Host smart-01842324-d229-47b9-a180-9aeae6c20987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088595511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1088595511
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4235629430
Short name T675
Test name
Test status
Simulation time 946304863 ps
CPU time 3.46 seconds
Started Jul 05 06:27:57 PM PDT 24
Finished Jul 05 06:28:01 PM PDT 24
Peak memory 225568 kb
Host smart-30af3155-2cf7-4b2e-b1a8-19e10d5fc7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235629430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4235629430
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2011339045
Short name T755
Test name
Test status
Simulation time 12084254 ps
CPU time 0.76 seconds
Started Jul 05 06:28:19 PM PDT 24
Finished Jul 05 06:28:21 PM PDT 24
Peak memory 205792 kb
Host smart-c1322b1d-1c25-4b49-b5c4-b25de8507b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011339045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2011339045
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.259567054
Short name T411
Test name
Test status
Simulation time 33831266 ps
CPU time 2.46 seconds
Started Jul 05 06:28:19 PM PDT 24
Finished Jul 05 06:28:22 PM PDT 24
Peak memory 233512 kb
Host smart-0b5f581f-41df-4d7b-b01b-a69d612f526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259567054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.259567054
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1160845422
Short name T890
Test name
Test status
Simulation time 66313101 ps
CPU time 0.78 seconds
Started Jul 05 06:28:03 PM PDT 24
Finished Jul 05 06:28:04 PM PDT 24
Peak memory 207548 kb
Host smart-52082a59-0162-45c3-aed3-9740135ba79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160845422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1160845422
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3937928024
Short name T225
Test name
Test status
Simulation time 2403191170 ps
CPU time 54.93 seconds
Started Jul 05 06:28:11 PM PDT 24
Finished Jul 05 06:29:07 PM PDT 24
Peak memory 251068 kb
Host smart-47396212-fc70-4dcd-afdf-a12d6ad45dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937928024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3937928024
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1579410004
Short name T990
Test name
Test status
Simulation time 4554052624 ps
CPU time 58.25 seconds
Started Jul 05 06:28:11 PM PDT 24
Finished Jul 05 06:29:10 PM PDT 24
Peak memory 250596 kb
Host smart-8ae75159-e995-4e89-9b64-fde178fddbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579410004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1579410004
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1078838632
Short name T821
Test name
Test status
Simulation time 2946351707 ps
CPU time 63.28 seconds
Started Jul 05 06:28:10 PM PDT 24
Finished Jul 05 06:29:13 PM PDT 24
Peak memory 263416 kb
Host smart-2f4bd97f-1103-46b0-85e0-2cc180943d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078838632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1078838632
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1006172943
Short name T290
Test name
Test status
Simulation time 3976237661 ps
CPU time 16.82 seconds
Started Jul 05 06:28:11 PM PDT 24
Finished Jul 05 06:28:28 PM PDT 24
Peak memory 250348 kb
Host smart-61678221-d2c2-4ac4-9cf4-3b48eb36d06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006172943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1006172943
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3992744601
Short name T88
Test name
Test status
Simulation time 35258922877 ps
CPU time 236.31 seconds
Started Jul 05 06:28:13 PM PDT 24
Finished Jul 05 06:32:10 PM PDT 24
Peak memory 258484 kb
Host smart-36234927-762c-4902-b725-25146a952231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992744601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3992744601
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.978648243
Short name T582
Test name
Test status
Simulation time 159359770 ps
CPU time 2.47 seconds
Started Jul 05 06:28:03 PM PDT 24
Finished Jul 05 06:28:06 PM PDT 24
Peak memory 233836 kb
Host smart-68d5c948-80b7-4d79-874c-fa4892af1d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978648243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.978648243
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1047231980
Short name T980
Test name
Test status
Simulation time 1075026648 ps
CPU time 19.2 seconds
Started Jul 05 06:28:03 PM PDT 24
Finished Jul 05 06:28:22 PM PDT 24
Peak memory 233828 kb
Host smart-878c0707-8c76-46fd-a0db-40e7c13a0299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047231980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1047231980
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.807707779
Short name T380
Test name
Test status
Simulation time 138417215 ps
CPU time 1.05 seconds
Started Jul 05 06:28:09 PM PDT 24
Finished Jul 05 06:28:11 PM PDT 24
Peak memory 218936 kb
Host smart-17beb915-11a5-414d-832c-f0abccf5bd81
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807707779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.807707779
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2571008423
Short name T250
Test name
Test status
Simulation time 35785667296 ps
CPU time 15.98 seconds
Started Jul 05 06:28:09 PM PDT 24
Finished Jul 05 06:28:25 PM PDT 24
Peak memory 225776 kb
Host smart-dab55d02-3211-4912-9c45-9ee010f47dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571008423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2571008423
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3725633128
Short name T222
Test name
Test status
Simulation time 336771607 ps
CPU time 2.76 seconds
Started Jul 05 06:28:06 PM PDT 24
Finished Jul 05 06:28:09 PM PDT 24
Peak memory 225600 kb
Host smart-55294397-4032-4e9f-bcad-bc7b393ef95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725633128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3725633128
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3022545034
Short name T146
Test name
Test status
Simulation time 637985931 ps
CPU time 9.62 seconds
Started Jul 05 06:28:10 PM PDT 24
Finished Jul 05 06:28:20 PM PDT 24
Peak memory 224256 kb
Host smart-3518f4e6-b1bd-48e3-8947-b26b4b0bdb50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3022545034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3022545034
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.906156635
Short name T68
Test name
Test status
Simulation time 8141898109 ps
CPU time 6.92 seconds
Started Jul 05 06:28:01 PM PDT 24
Finished Jul 05 06:28:08 PM PDT 24
Peak memory 217428 kb
Host smart-6774cfee-df25-42c3-87bc-6126cf7af790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906156635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.906156635
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3418370513
Short name T388
Test name
Test status
Simulation time 8627999892 ps
CPU time 13.12 seconds
Started Jul 05 06:28:01 PM PDT 24
Finished Jul 05 06:28:15 PM PDT 24
Peak memory 217536 kb
Host smart-9b90186c-b99c-4427-8b98-9a099593211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418370513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3418370513
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.257400452
Short name T872
Test name
Test status
Simulation time 20437358 ps
CPU time 0.72 seconds
Started Jul 05 06:28:03 PM PDT 24
Finished Jul 05 06:28:04 PM PDT 24
Peak memory 206608 kb
Host smart-bfdfcc6d-fce9-4510-9321-4e89b01c15b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257400452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.257400452
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3606297753
Short name T812
Test name
Test status
Simulation time 119474562 ps
CPU time 0.98 seconds
Started Jul 05 06:28:03 PM PDT 24
Finished Jul 05 06:28:05 PM PDT 24
Peak memory 208008 kb
Host smart-e2650d64-9a4f-47f6-8af9-347a62273587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606297753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3606297753
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1307142003
Short name T850
Test name
Test status
Simulation time 5926627728 ps
CPU time 20.38 seconds
Started Jul 05 06:28:13 PM PDT 24
Finished Jul 05 06:28:34 PM PDT 24
Peak memory 234880 kb
Host smart-9e31ebd7-6c09-43de-8d57-da99c67abd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307142003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1307142003
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.399921729
Short name T766
Test name
Test status
Simulation time 20701771 ps
CPU time 0.72 seconds
Started Jul 05 06:25:28 PM PDT 24
Finished Jul 05 06:25:29 PM PDT 24
Peak memory 206740 kb
Host smart-9f802c4b-aff7-4f61-ab84-d18a2840ab0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399921729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.399921729
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2638613123
Short name T87
Test name
Test status
Simulation time 12301190829 ps
CPU time 8.37 seconds
Started Jul 05 06:25:21 PM PDT 24
Finished Jul 05 06:25:30 PM PDT 24
Peak memory 233880 kb
Host smart-c10c835a-f327-4a1a-ae28-ffd195d44ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638613123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2638613123
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2379211079
Short name T422
Test name
Test status
Simulation time 16478075 ps
CPU time 0.83 seconds
Started Jul 05 06:25:13 PM PDT 24
Finished Jul 05 06:25:14 PM PDT 24
Peak memory 207544 kb
Host smart-6d8c7d9a-2022-4a96-9c8a-9c74ff75d7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379211079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2379211079
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1751607046
Short name T1022
Test name
Test status
Simulation time 5603712081 ps
CPU time 37.53 seconds
Started Jul 05 06:25:21 PM PDT 24
Finished Jul 05 06:25:59 PM PDT 24
Peak memory 242072 kb
Host smart-e5da4d4f-88fd-4564-9d01-9b4aeb0a4ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751607046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1751607046
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.848122412
Short name T581
Test name
Test status
Simulation time 12649544827 ps
CPU time 62.59 seconds
Started Jul 05 06:25:21 PM PDT 24
Finished Jul 05 06:26:24 PM PDT 24
Peak memory 250352 kb
Host smart-edfa06f2-ee36-4fc7-bd17-8e5e0ef20472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848122412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
848122412
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.95057105
Short name T400
Test name
Test status
Simulation time 585611306 ps
CPU time 2.55 seconds
Started Jul 05 06:25:14 PM PDT 24
Finished Jul 05 06:25:17 PM PDT 24
Peak memory 233772 kb
Host smart-73af8d55-eb72-4d98-b0b6-fcc23a2ab498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95057105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.95057105
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1058355659
Short name T570
Test name
Test status
Simulation time 2618681786 ps
CPU time 3.88 seconds
Started Jul 05 06:25:23 PM PDT 24
Finished Jul 05 06:25:27 PM PDT 24
Peak memory 229916 kb
Host smart-7e390ef5-3cbb-4462-999b-9cd8cc95666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058355659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1058355659
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.968814646
Short name T893
Test name
Test status
Simulation time 121360713 ps
CPU time 1.04 seconds
Started Jul 05 06:25:14 PM PDT 24
Finished Jul 05 06:25:15 PM PDT 24
Peak memory 217688 kb
Host smart-a3870e53-fbf8-4ce3-96f3-7223741af53f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968814646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.968814646
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.930949766
Short name T55
Test name
Test status
Simulation time 8510349108 ps
CPU time 10.68 seconds
Started Jul 05 06:25:14 PM PDT 24
Finished Jul 05 06:25:25 PM PDT 24
Peak memory 241028 kb
Host smart-ac13181c-8128-4461-83fe-f9f1318d5a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930949766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
930949766
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1778547558
Short name T738
Test name
Test status
Simulation time 4150325526 ps
CPU time 17.88 seconds
Started Jul 05 06:25:14 PM PDT 24
Finished Jul 05 06:25:32 PM PDT 24
Peak memory 233980 kb
Host smart-19a41fe5-662a-4efb-b9b2-97dd01aeb523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778547558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1778547558
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2402622035
Short name T144
Test name
Test status
Simulation time 2755568012 ps
CPU time 7.86 seconds
Started Jul 05 06:25:21 PM PDT 24
Finished Jul 05 06:25:30 PM PDT 24
Peak memory 220416 kb
Host smart-62f93fa6-3f65-4fdb-911f-6c03e1b16239
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2402622035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2402622035
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2328837802
Short name T66
Test name
Test status
Simulation time 37128761 ps
CPU time 1 seconds
Started Jul 05 06:25:29 PM PDT 24
Finished Jul 05 06:25:30 PM PDT 24
Peak memory 236792 kb
Host smart-1474a3c4-4c25-46c6-86ec-3a158e962d64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328837802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2328837802
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3566465109
Short name T156
Test name
Test status
Simulation time 55953297 ps
CPU time 1 seconds
Started Jul 05 06:25:27 PM PDT 24
Finished Jul 05 06:25:29 PM PDT 24
Peak memory 207880 kb
Host smart-07821047-ad34-4b1e-9e7d-72a345af5432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566465109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3566465109
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2535139408
Short name T861
Test name
Test status
Simulation time 2807185116 ps
CPU time 10.42 seconds
Started Jul 05 06:25:14 PM PDT 24
Finished Jul 05 06:25:25 PM PDT 24
Peak memory 221140 kb
Host smart-b911bc2f-7395-4ac5-a205-650c96b984a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535139408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2535139408
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2962248321
Short name T608
Test name
Test status
Simulation time 93675856 ps
CPU time 1.35 seconds
Started Jul 05 06:25:14 PM PDT 24
Finished Jul 05 06:25:16 PM PDT 24
Peak memory 208316 kb
Host smart-179ee8ae-a24f-40b0-a218-9db910237f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962248321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2962248321
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3737292875
Short name T605
Test name
Test status
Simulation time 96489013 ps
CPU time 1.82 seconds
Started Jul 05 06:25:13 PM PDT 24
Finished Jul 05 06:25:15 PM PDT 24
Peak memory 217388 kb
Host smart-3521603e-09b0-4c60-92b5-481ec68811ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737292875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3737292875
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1832751511
Short name T602
Test name
Test status
Simulation time 49385590 ps
CPU time 0.9 seconds
Started Jul 05 06:25:14 PM PDT 24
Finished Jul 05 06:25:16 PM PDT 24
Peak memory 206976 kb
Host smart-c213b3b6-06ae-45f1-b4b7-09ebeeda2cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832751511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1832751511
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2781003119
Short name T534
Test name
Test status
Simulation time 238497677 ps
CPU time 3.55 seconds
Started Jul 05 06:25:22 PM PDT 24
Finished Jul 05 06:25:25 PM PDT 24
Peak memory 225556 kb
Host smart-9afc668f-2e03-4880-8a29-566767082b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781003119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2781003119
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.179476213
Short name T360
Test name
Test status
Simulation time 47738280 ps
CPU time 0.71 seconds
Started Jul 05 06:28:18 PM PDT 24
Finished Jul 05 06:28:19 PM PDT 24
Peak memory 205800 kb
Host smart-31f62aab-1419-4322-b388-19938e66fd45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179476213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.179476213
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2961071441
Short name T779
Test name
Test status
Simulation time 2200368964 ps
CPU time 13.32 seconds
Started Jul 05 06:28:10 PM PDT 24
Finished Jul 05 06:28:24 PM PDT 24
Peak memory 225692 kb
Host smart-505553d2-2722-4e3b-a0c0-afb6348c475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961071441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2961071441
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2074170501
Short name T576
Test name
Test status
Simulation time 46630140 ps
CPU time 0.83 seconds
Started Jul 05 06:28:11 PM PDT 24
Finished Jul 05 06:28:12 PM PDT 24
Peak memory 207436 kb
Host smart-99009378-c5f0-4d46-bea2-b934970f326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074170501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2074170501
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3092200078
Short name T526
Test name
Test status
Simulation time 80011112157 ps
CPU time 132.22 seconds
Started Jul 05 06:28:11 PM PDT 24
Finished Jul 05 06:30:24 PM PDT 24
Peak memory 258516 kb
Host smart-26b2778c-e6b0-48a9-82ff-e297f1228841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092200078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3092200078
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2417872959
Short name T46
Test name
Test status
Simulation time 6213896391 ps
CPU time 91.66 seconds
Started Jul 05 06:28:17 PM PDT 24
Finished Jul 05 06:29:49 PM PDT 24
Peak memory 251588 kb
Host smart-44823b6b-9001-4441-b827-be6266416018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417872959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2417872959
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1611314169
Short name T487
Test name
Test status
Simulation time 113210089425 ps
CPU time 276.08 seconds
Started Jul 05 06:28:17 PM PDT 24
Finished Jul 05 06:32:54 PM PDT 24
Peak memory 254244 kb
Host smart-cd20f808-a97a-40e1-8481-a44f1d23443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611314169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1611314169
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1877407330
Short name T691
Test name
Test status
Simulation time 69089431 ps
CPU time 3.08 seconds
Started Jul 05 06:28:10 PM PDT 24
Finished Jul 05 06:28:14 PM PDT 24
Peak memory 233788 kb
Host smart-fca2e0a1-a6aa-4d40-a861-640e4cd8c98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877407330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1877407330
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3367123403
Short name T721
Test name
Test status
Simulation time 43592563676 ps
CPU time 59.16 seconds
Started Jul 05 06:28:10 PM PDT 24
Finished Jul 05 06:29:09 PM PDT 24
Peak memory 250364 kb
Host smart-2032f50b-9d51-44d8-9d78-5852a82b9a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367123403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3367123403
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2184739683
Short name T451
Test name
Test status
Simulation time 3308734444 ps
CPU time 29.33 seconds
Started Jul 05 06:28:11 PM PDT 24
Finished Jul 05 06:28:41 PM PDT 24
Peak memory 233880 kb
Host smart-a509d536-51cf-4779-b861-484bdec329f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184739683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2184739683
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.542128546
Short name T908
Test name
Test status
Simulation time 95234627 ps
CPU time 2.2 seconds
Started Jul 05 06:28:19 PM PDT 24
Finished Jul 05 06:28:22 PM PDT 24
Peak memory 224884 kb
Host smart-3cba6663-f704-4dd5-9a0e-ce7ab0f64c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542128546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.542128546
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.273610482
Short name T458
Test name
Test status
Simulation time 3317283586 ps
CPU time 11.22 seconds
Started Jul 05 06:28:12 PM PDT 24
Finished Jul 05 06:28:23 PM PDT 24
Peak memory 233864 kb
Host smart-6bfa90a0-f8c9-49fe-a483-e1f8ba8ef62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273610482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.273610482
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3927190063
Short name T820
Test name
Test status
Simulation time 1188022940 ps
CPU time 9.17 seconds
Started Jul 05 06:28:12 PM PDT 24
Finished Jul 05 06:28:21 PM PDT 24
Peak memory 236764 kb
Host smart-81483c5a-2aee-4576-97da-cfdfde9e329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927190063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3927190063
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3166869058
Short name T736
Test name
Test status
Simulation time 3684395363 ps
CPU time 12.65 seconds
Started Jul 05 06:28:09 PM PDT 24
Finished Jul 05 06:28:22 PM PDT 24
Peak memory 224200 kb
Host smart-a2f78e4c-36b6-4067-9da0-810ca3ca05f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3166869058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3166869058
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3749399205
Short name T158
Test name
Test status
Simulation time 237493430 ps
CPU time 1.12 seconds
Started Jul 05 06:28:16 PM PDT 24
Finished Jul 05 06:28:18 PM PDT 24
Peak memory 207912 kb
Host smart-a5a28882-881f-4f2c-8c4e-6c5ae9c41d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749399205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3749399205
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.914864199
Short name T919
Test name
Test status
Simulation time 15857352332 ps
CPU time 16.67 seconds
Started Jul 05 06:28:10 PM PDT 24
Finished Jul 05 06:28:27 PM PDT 24
Peak memory 217492 kb
Host smart-44c77762-f7c4-412a-a7c8-1a4910aaa518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914864199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.914864199
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2475204489
Short name T968
Test name
Test status
Simulation time 27067815098 ps
CPU time 10.57 seconds
Started Jul 05 06:28:11 PM PDT 24
Finished Jul 05 06:28:22 PM PDT 24
Peak memory 218608 kb
Host smart-a8cd7f66-6c2d-4c8a-8998-3523f4cd4995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475204489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2475204489
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2766948115
Short name T676
Test name
Test status
Simulation time 143816981 ps
CPU time 1.22 seconds
Started Jul 05 06:28:09 PM PDT 24
Finished Jul 05 06:28:11 PM PDT 24
Peak memory 209180 kb
Host smart-ef65e71d-25f9-4252-a02b-ad423a4d2869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766948115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2766948115
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2454202059
Short name T546
Test name
Test status
Simulation time 47968351 ps
CPU time 0.76 seconds
Started Jul 05 06:28:10 PM PDT 24
Finished Jul 05 06:28:11 PM PDT 24
Peak memory 207004 kb
Host smart-d0cff06f-ed60-44bf-b249-278d55297c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454202059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2454202059
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1710787444
Short name T717
Test name
Test status
Simulation time 398384612 ps
CPU time 2.87 seconds
Started Jul 05 06:28:11 PM PDT 24
Finished Jul 05 06:28:14 PM PDT 24
Peak memory 233764 kb
Host smart-25d1cf66-68ca-4b5a-9cc9-c7dfeffaa731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710787444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1710787444
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3254409278
Short name T562
Test name
Test status
Simulation time 33032146 ps
CPU time 0.68 seconds
Started Jul 05 06:28:27 PM PDT 24
Finished Jul 05 06:28:29 PM PDT 24
Peak memory 205828 kb
Host smart-fb18adf5-d7bf-4f14-bd25-e03741a64aa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254409278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3254409278
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.414572932
Short name T461
Test name
Test status
Simulation time 108341728 ps
CPU time 2.12 seconds
Started Jul 05 06:28:22 PM PDT 24
Finished Jul 05 06:28:25 PM PDT 24
Peak memory 225604 kb
Host smart-7c3438d7-2346-474e-8887-a7198287e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414572932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.414572932
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1136856252
Short name T759
Test name
Test status
Simulation time 21803523 ps
CPU time 0.76 seconds
Started Jul 05 06:28:17 PM PDT 24
Finished Jul 05 06:28:19 PM PDT 24
Peak memory 207848 kb
Host smart-b2ac75f3-8dc3-4f4c-b639-c96f3a243990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136856252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1136856252
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.28739571
Short name T49
Test name
Test status
Simulation time 111309192754 ps
CPU time 547.69 seconds
Started Jul 05 06:28:20 PM PDT 24
Finished Jul 05 06:37:29 PM PDT 24
Peak memory 271348 kb
Host smart-ecea5ac6-7b0b-4cc9-8291-edb3870fdb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28739571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.28739571
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1032899931
Short name T809
Test name
Test status
Simulation time 1207966691 ps
CPU time 9.18 seconds
Started Jul 05 06:28:17 PM PDT 24
Finished Jul 05 06:28:27 PM PDT 24
Peak memory 255352 kb
Host smart-ec7e41b9-82c7-4863-ae92-ac1bf33440ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032899931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1032899931
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3243804898
Short name T241
Test name
Test status
Simulation time 230511831891 ps
CPU time 224.38 seconds
Started Jul 05 06:28:17 PM PDT 24
Finished Jul 05 06:32:01 PM PDT 24
Peak memory 250316 kb
Host smart-4b3fea6d-8cde-45d2-b18e-cfb790d811a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243804898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3243804898
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3237836583
Short name T259
Test name
Test status
Simulation time 1964756055 ps
CPU time 7.35 seconds
Started Jul 05 06:28:21 PM PDT 24
Finished Jul 05 06:28:29 PM PDT 24
Peak memory 225568 kb
Host smart-2abc68d7-bd22-4750-a5f6-3d73e396da96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237836583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3237836583
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1628301747
Short name T656
Test name
Test status
Simulation time 16735117129 ps
CPU time 124.03 seconds
Started Jul 05 06:28:18 PM PDT 24
Finished Jul 05 06:30:23 PM PDT 24
Peak memory 233856 kb
Host smart-36bb95c1-0c5e-4ddc-92f9-5184fe9a5095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628301747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1628301747
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.951018449
Short name T349
Test name
Test status
Simulation time 386204760 ps
CPU time 3.19 seconds
Started Jul 05 06:28:18 PM PDT 24
Finished Jul 05 06:28:22 PM PDT 24
Peak memory 233752 kb
Host smart-a67bcaf2-f83a-4dbd-b21f-a6eee522df1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951018449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.951018449
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2625933006
Short name T509
Test name
Test status
Simulation time 95953487 ps
CPU time 2.15 seconds
Started Jul 05 06:28:17 PM PDT 24
Finished Jul 05 06:28:20 PM PDT 24
Peak memory 224164 kb
Host smart-73d73222-1c78-4fcb-a8f2-0f06f96a9740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625933006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2625933006
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3713412636
Short name T500
Test name
Test status
Simulation time 218579362 ps
CPU time 5.97 seconds
Started Jul 05 06:28:18 PM PDT 24
Finished Jul 05 06:28:26 PM PDT 24
Peak memory 223640 kb
Host smart-1af9d5a0-0f3e-4c1f-aac1-82773bb932d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3713412636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3713412636
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1004271275
Short name T923
Test name
Test status
Simulation time 2703959999 ps
CPU time 51.31 seconds
Started Jul 05 06:28:27 PM PDT 24
Finished Jul 05 06:29:19 PM PDT 24
Peak memory 250504 kb
Host smart-c78b5668-8efe-49a3-828a-47514291f7eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004271275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1004271275
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3150567681
Short name T598
Test name
Test status
Simulation time 6578752683 ps
CPU time 10.9 seconds
Started Jul 05 06:28:18 PM PDT 24
Finished Jul 05 06:28:30 PM PDT 24
Peak memory 217512 kb
Host smart-d1bf5d52-c9ee-4f30-a4ac-21845ffcdd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150567681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3150567681
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2007380868
Short name T935
Test name
Test status
Simulation time 33097914942 ps
CPU time 24.56 seconds
Started Jul 05 06:28:21 PM PDT 24
Finished Jul 05 06:28:46 PM PDT 24
Peak memory 217476 kb
Host smart-e8ad8472-3534-472c-9f62-fc2c1f8a94b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007380868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2007380868
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.182752600
Short name T391
Test name
Test status
Simulation time 825666253 ps
CPU time 2.26 seconds
Started Jul 05 06:28:16 PM PDT 24
Finished Jul 05 06:28:19 PM PDT 24
Peak memory 217388 kb
Host smart-7aad8a2a-7619-4faf-aa67-23d76071931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182752600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.182752600
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3923199868
Short name T682
Test name
Test status
Simulation time 42893876 ps
CPU time 0.92 seconds
Started Jul 05 06:28:17 PM PDT 24
Finished Jul 05 06:28:19 PM PDT 24
Peak memory 207988 kb
Host smart-ee890764-6bd7-4a3a-beea-84ad1cef29ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923199868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3923199868
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4193819062
Short name T699
Test name
Test status
Simulation time 88151118 ps
CPU time 2.7 seconds
Started Jul 05 06:28:18 PM PDT 24
Finished Jul 05 06:28:22 PM PDT 24
Peak memory 233768 kb
Host smart-ab2bda56-2a45-43ec-96cb-2bed4604e9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193819062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4193819062
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1399984270
Short name T555
Test name
Test status
Simulation time 75772130 ps
CPU time 0.78 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:28:33 PM PDT 24
Peak memory 205796 kb
Host smart-47758d4f-f6ae-46df-b117-1bf4f77e197a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399984270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1399984270
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3113862715
Short name T1012
Test name
Test status
Simulation time 149071297 ps
CPU time 3.08 seconds
Started Jul 05 06:28:26 PM PDT 24
Finished Jul 05 06:28:30 PM PDT 24
Peak memory 225608 kb
Host smart-859336c8-2e0e-4af3-8acd-9e2ce40ee6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113862715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3113862715
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4065772870
Short name T384
Test name
Test status
Simulation time 27229744 ps
CPU time 0.82 seconds
Started Jul 05 06:28:25 PM PDT 24
Finished Jul 05 06:28:27 PM PDT 24
Peak memory 207532 kb
Host smart-ca0ce7f1-4820-4c70-95fd-6665db42e7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065772870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4065772870
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2962557245
Short name T578
Test name
Test status
Simulation time 290751276866 ps
CPU time 283.11 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:33:15 PM PDT 24
Peak memory 250292 kb
Host smart-d764d0f3-e22b-4ad4-a73e-da5254e9a789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962557245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2962557245
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2200503146
Short name T657
Test name
Test status
Simulation time 181807437096 ps
CPU time 97.98 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:30:12 PM PDT 24
Peak memory 250404 kb
Host smart-58d5f9b6-0b58-4253-9a2d-e0645f1a3a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200503146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2200503146
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.121086335
Short name T34
Test name
Test status
Simulation time 70293904327 ps
CPU time 166.26 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:31:17 PM PDT 24
Peak memory 252104 kb
Host smart-e2e1e28b-18fb-4452-8505-0f823c38aeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121086335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.121086335
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.208833681
Short name T520
Test name
Test status
Simulation time 6807152988 ps
CPU time 25.67 seconds
Started Jul 05 06:28:24 PM PDT 24
Finished Jul 05 06:28:51 PM PDT 24
Peak memory 238128 kb
Host smart-cce2835b-e6e9-4bd1-88fd-4259bd80a83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208833681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.208833681
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3935053968
Short name T35
Test name
Test status
Simulation time 1307754404 ps
CPU time 37.12 seconds
Started Jul 05 06:28:26 PM PDT 24
Finished Jul 05 06:29:04 PM PDT 24
Peak memory 253832 kb
Host smart-12f8c35c-4649-473f-a1ae-b02d1fc660f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935053968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3935053968
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.324198670
Short name T7
Test name
Test status
Simulation time 4009775532 ps
CPU time 9.19 seconds
Started Jul 05 06:28:25 PM PDT 24
Finished Jul 05 06:28:35 PM PDT 24
Peak memory 225716 kb
Host smart-999f6cd7-be93-4350-bf18-c5db051c0fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324198670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.324198670
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4168819808
Short name T238
Test name
Test status
Simulation time 21229089327 ps
CPU time 58.22 seconds
Started Jul 05 06:28:25 PM PDT 24
Finished Jul 05 06:29:25 PM PDT 24
Peak memory 233940 kb
Host smart-d0afe3f2-02fb-4ff4-9afb-c97e5b0b33c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168819808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4168819808
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3538484099
Short name T244
Test name
Test status
Simulation time 2258847441 ps
CPU time 4.11 seconds
Started Jul 05 06:28:23 PM PDT 24
Finished Jul 05 06:28:28 PM PDT 24
Peak memory 225720 kb
Host smart-5d064645-037c-4480-9679-04596bc460ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538484099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3538484099
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2622467468
Short name T563
Test name
Test status
Simulation time 405879595 ps
CPU time 8.34 seconds
Started Jul 05 06:28:25 PM PDT 24
Finished Jul 05 06:28:34 PM PDT 24
Peak memory 250428 kb
Host smart-a6179982-33a3-4f10-bbb4-961b35fa6beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622467468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2622467468
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3742696045
Short name T622
Test name
Test status
Simulation time 231287130 ps
CPU time 5.2 seconds
Started Jul 05 06:28:25 PM PDT 24
Finished Jul 05 06:28:31 PM PDT 24
Peak memory 223944 kb
Host smart-64a3af0b-96f8-4d0b-940b-fb6fe63de5d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742696045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3742696045
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2510063554
Short name T855
Test name
Test status
Simulation time 15487537750 ps
CPU time 155.64 seconds
Started Jul 05 06:28:33 PM PDT 24
Finished Jul 05 06:31:10 PM PDT 24
Peak memory 264012 kb
Host smart-7765916f-dac8-4701-8dab-cd6adaf61fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510063554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2510063554
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2898517107
Short name T875
Test name
Test status
Simulation time 27977036964 ps
CPU time 18.34 seconds
Started Jul 05 06:28:25 PM PDT 24
Finished Jul 05 06:28:44 PM PDT 24
Peak memory 217484 kb
Host smart-6574841d-ded4-47f7-af0b-c53c0f80585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898517107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2898517107
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.306074666
Short name T711
Test name
Test status
Simulation time 12923673738 ps
CPU time 13.06 seconds
Started Jul 05 06:28:26 PM PDT 24
Finished Jul 05 06:28:40 PM PDT 24
Peak memory 217504 kb
Host smart-d5692c7f-0809-47c2-9f11-88f51389eca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306074666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.306074666
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.111845793
Short name T413
Test name
Test status
Simulation time 72176138 ps
CPU time 0.94 seconds
Started Jul 05 06:28:24 PM PDT 24
Finished Jul 05 06:28:26 PM PDT 24
Peak memory 208180 kb
Host smart-38fbd607-2956-4845-b567-7015473310a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111845793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.111845793
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2310392272
Short name T399
Test name
Test status
Simulation time 51675839 ps
CPU time 0.84 seconds
Started Jul 05 06:28:24 PM PDT 24
Finished Jul 05 06:28:26 PM PDT 24
Peak memory 207004 kb
Host smart-514cc06d-df00-4328-92df-0b9ca594a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310392272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2310392272
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2126662041
Short name T586
Test name
Test status
Simulation time 45256171459 ps
CPU time 31.87 seconds
Started Jul 05 06:28:26 PM PDT 24
Finished Jul 05 06:28:59 PM PDT 24
Peak memory 233832 kb
Host smart-be38c57a-e3b8-437e-8061-b3e44329e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126662041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2126662041
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.512133260
Short name T447
Test name
Test status
Simulation time 15262857 ps
CPU time 0.76 seconds
Started Jul 05 06:28:39 PM PDT 24
Finished Jul 05 06:28:40 PM PDT 24
Peak memory 206396 kb
Host smart-96b01b19-487d-440f-ba4d-77e951ce92f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512133260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.512133260
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3296836976
Short name T673
Test name
Test status
Simulation time 41320027 ps
CPU time 2.6 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:28:35 PM PDT 24
Peak memory 233780 kb
Host smart-e93672b2-487a-4a0c-af84-b137023f5e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296836976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3296836976
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2623544323
Short name T985
Test name
Test status
Simulation time 12845945 ps
CPU time 0.77 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:28:33 PM PDT 24
Peak memory 206516 kb
Host smart-7fac5815-cb49-45f6-871a-e1f8001974b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623544323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2623544323
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2390907656
Short name T956
Test name
Test status
Simulation time 5970456485 ps
CPU time 55.63 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:29:28 PM PDT 24
Peak memory 242124 kb
Host smart-ccf05b2c-99c9-4556-a1db-cf49badb1afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390907656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2390907656
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.432772631
Short name T837
Test name
Test status
Simulation time 10771128504 ps
CPU time 107.05 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:30:19 PM PDT 24
Peak memory 250528 kb
Host smart-efe5d663-d4fb-455b-b195-e2d061593a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432772631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.432772631
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2595072881
Short name T1018
Test name
Test status
Simulation time 410271160 ps
CPU time 5.36 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:28:37 PM PDT 24
Peak memory 225608 kb
Host smart-8d294430-dd9a-48ef-9411-9cbf251b343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595072881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2595072881
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2168456525
Short name T164
Test name
Test status
Simulation time 202392233350 ps
CPU time 311.45 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:33:44 PM PDT 24
Peak memory 256260 kb
Host smart-420196de-91bd-49eb-b3c5-22ad9e34201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168456525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2168456525
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4047935728
Short name T889
Test name
Test status
Simulation time 2064965785 ps
CPU time 12.1 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:28:45 PM PDT 24
Peak memory 225552 kb
Host smart-b63c5395-3890-41bb-937d-8510c0d45e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047935728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4047935728
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1656742757
Short name T927
Test name
Test status
Simulation time 40747430035 ps
CPU time 25.5 seconds
Started Jul 05 06:28:34 PM PDT 24
Finished Jul 05 06:29:00 PM PDT 24
Peak memory 233856 kb
Host smart-face3be2-821d-4a2e-9449-80e83aaa88be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656742757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1656742757
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2300607984
Short name T932
Test name
Test status
Simulation time 1026501694 ps
CPU time 4.74 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:28:36 PM PDT 24
Peak memory 225572 kb
Host smart-3481d967-68de-41af-b550-83ce3acc875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300607984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2300607984
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3829349375
Short name T162
Test name
Test status
Simulation time 11772971427 ps
CPU time 8.26 seconds
Started Jul 05 06:28:30 PM PDT 24
Finished Jul 05 06:28:39 PM PDT 24
Peak memory 238288 kb
Host smart-335472c7-70a5-4f62-8f65-af2c97376d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829349375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3829349375
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3304413647
Short name T758
Test name
Test status
Simulation time 6128491152 ps
CPU time 14.74 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:28:47 PM PDT 24
Peak memory 223248 kb
Host smart-be84fb5e-f164-4caa-a342-0a507d349f10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3304413647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3304413647
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1087667133
Short name T1021
Test name
Test status
Simulation time 74638622236 ps
CPU time 183.75 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:31:37 PM PDT 24
Peak memory 257516 kb
Host smart-3f2b89dc-9933-4bce-9182-4af0bfa788d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087667133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1087667133
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2947173079
Short name T604
Test name
Test status
Simulation time 13461741436 ps
CPU time 23.6 seconds
Started Jul 05 06:28:33 PM PDT 24
Finished Jul 05 06:28:58 PM PDT 24
Peak memory 217680 kb
Host smart-c8508f70-3cf5-4ca9-97b3-110df9d38081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947173079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2947173079
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1527994377
Short name T798
Test name
Test status
Simulation time 838073646 ps
CPU time 3.2 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:28:37 PM PDT 24
Peak memory 217228 kb
Host smart-4c3e9b09-7f11-4cbe-a469-21bd71db48d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527994377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1527994377
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3139157860
Short name T476
Test name
Test status
Simulation time 55785164 ps
CPU time 1.5 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:28:33 PM PDT 24
Peak memory 217352 kb
Host smart-4789e8b9-2a5d-4373-8c5f-321c1fdde85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139157860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3139157860
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2654235603
Short name T591
Test name
Test status
Simulation time 91447001 ps
CPU time 0.92 seconds
Started Jul 05 06:28:31 PM PDT 24
Finished Jul 05 06:28:33 PM PDT 24
Peak memory 207044 kb
Host smart-1fbe9500-4af5-4833-8675-ed529d550d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654235603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2654235603
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1001316292
Short name T994
Test name
Test status
Simulation time 58580858 ps
CPU time 2.79 seconds
Started Jul 05 06:28:32 PM PDT 24
Finished Jul 05 06:28:36 PM PDT 24
Peak memory 225396 kb
Host smart-62143a17-9357-45bc-ac8b-32a5c936d7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001316292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1001316292
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2384578278
Short name T791
Test name
Test status
Simulation time 12087783 ps
CPU time 0.7 seconds
Started Jul 05 06:28:45 PM PDT 24
Finished Jul 05 06:28:46 PM PDT 24
Peak memory 205796 kb
Host smart-fe58692d-662b-41e5-b28a-c5ae3159bce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384578278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2384578278
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1401352744
Short name T84
Test name
Test status
Simulation time 2776285362 ps
CPU time 11.1 seconds
Started Jul 05 06:28:49 PM PDT 24
Finished Jul 05 06:29:00 PM PDT 24
Peak memory 225704 kb
Host smart-ac4170fc-15a4-4991-bfaf-a84a938cf9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401352744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1401352744
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1802115921
Short name T354
Test name
Test status
Simulation time 60627280 ps
CPU time 0.81 seconds
Started Jul 05 06:28:40 PM PDT 24
Finished Jul 05 06:28:41 PM PDT 24
Peak memory 206512 kb
Host smart-d98c1738-68c5-4f07-9e66-ed9e3c3327bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802115921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1802115921
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.879084670
Short name T866
Test name
Test status
Simulation time 2379690294 ps
CPU time 46.97 seconds
Started Jul 05 06:28:50 PM PDT 24
Finished Jul 05 06:29:38 PM PDT 24
Peak memory 240904 kb
Host smart-dda2810b-4f0a-48c0-9c94-b97584b88284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879084670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.879084670
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4069566198
Short name T888
Test name
Test status
Simulation time 5725251400 ps
CPU time 43.93 seconds
Started Jul 05 06:28:48 PM PDT 24
Finished Jul 05 06:29:32 PM PDT 24
Peak memory 242116 kb
Host smart-8ac0cdb5-b345-4459-9347-00a3986d85c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069566198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4069566198
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1953455843
Short name T44
Test name
Test status
Simulation time 3191743681 ps
CPU time 28.51 seconds
Started Jul 05 06:28:50 PM PDT 24
Finished Jul 05 06:29:18 PM PDT 24
Peak memory 254296 kb
Host smart-2c200140-07f2-42d0-8541-90fb6e6ab123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953455843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1953455843
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3635355586
Short name T704
Test name
Test status
Simulation time 246003419 ps
CPU time 4.78 seconds
Started Jul 05 06:28:47 PM PDT 24
Finished Jul 05 06:28:52 PM PDT 24
Peak memory 233820 kb
Host smart-6e2d449b-91c8-4da5-9f37-7a0eefedddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635355586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3635355586
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.909250710
Short name T489
Test name
Test status
Simulation time 962563781 ps
CPU time 18.31 seconds
Started Jul 05 06:28:48 PM PDT 24
Finished Jul 05 06:29:07 PM PDT 24
Peak memory 249992 kb
Host smart-eff997be-89a8-4337-abb6-f8f14c6f85d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909250710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.909250710
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4159272509
Short name T713
Test name
Test status
Simulation time 3039636093 ps
CPU time 9.75 seconds
Started Jul 05 06:28:37 PM PDT 24
Finished Jul 05 06:28:47 PM PDT 24
Peak memory 225732 kb
Host smart-3795035f-bb89-43e8-b740-7241d7124cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159272509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4159272509
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.774342533
Short name T355
Test name
Test status
Simulation time 31384589 ps
CPU time 2.21 seconds
Started Jul 05 06:28:38 PM PDT 24
Finished Jul 05 06:28:40 PM PDT 24
Peak memory 233524 kb
Host smart-a4fda4ad-ef48-4aa6-ab6a-8fed741baaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774342533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.774342533
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3930633124
Short name T478
Test name
Test status
Simulation time 322924179 ps
CPU time 3.88 seconds
Started Jul 05 06:28:48 PM PDT 24
Finished Jul 05 06:28:52 PM PDT 24
Peak memory 224388 kb
Host smart-f9c6ffd0-1248-4097-8da0-dea4ac91d5e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3930633124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3930633124
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1707332858
Short name T155
Test name
Test status
Simulation time 24763907298 ps
CPU time 50.36 seconds
Started Jul 05 06:28:46 PM PDT 24
Finished Jul 05 06:29:36 PM PDT 24
Peak memory 236352 kb
Host smart-ba6fceb9-ffe6-4f70-85d6-12ed358f1875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707332858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1707332858
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1725785333
Short name T302
Test name
Test status
Simulation time 1512630690 ps
CPU time 21.21 seconds
Started Jul 05 06:28:39 PM PDT 24
Finished Jul 05 06:29:01 PM PDT 24
Peak memory 217456 kb
Host smart-ed5f2031-7355-47b2-b13e-95d8dcf1fb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725785333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1725785333
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2368153042
Short name T1015
Test name
Test status
Simulation time 86652155975 ps
CPU time 20.41 seconds
Started Jul 05 06:28:37 PM PDT 24
Finished Jul 05 06:28:58 PM PDT 24
Peak memory 217028 kb
Host smart-a6dee7e6-8ea4-47d3-99df-dee7745347e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368153042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2368153042
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2702884821
Short name T724
Test name
Test status
Simulation time 98003686 ps
CPU time 1.74 seconds
Started Jul 05 06:28:37 PM PDT 24
Finished Jul 05 06:28:40 PM PDT 24
Peak memory 217436 kb
Host smart-84c8fdea-42db-417b-aa82-2eca50d34c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702884821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2702884821
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3794974440
Short name T328
Test name
Test status
Simulation time 115155839 ps
CPU time 0.83 seconds
Started Jul 05 06:28:42 PM PDT 24
Finished Jul 05 06:28:43 PM PDT 24
Peak memory 207040 kb
Host smart-ba7cfb12-271a-47fb-abea-a0ce1ef2d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794974440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3794974440
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.874646016
Short name T942
Test name
Test status
Simulation time 1187978511 ps
CPU time 4.95 seconds
Started Jul 05 06:28:48 PM PDT 24
Finished Jul 05 06:28:53 PM PDT 24
Peak memory 233760 kb
Host smart-ce5db84b-6f71-4353-8056-68ffc29035c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874646016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.874646016
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2083060575
Short name T61
Test name
Test status
Simulation time 84775101 ps
CPU time 0.71 seconds
Started Jul 05 06:28:57 PM PDT 24
Finished Jul 05 06:28:58 PM PDT 24
Peak memory 205796 kb
Host smart-57373f4f-f3b7-47cc-be33-7776a0639fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083060575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2083060575
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2649602955
Short name T761
Test name
Test status
Simulation time 232100329 ps
CPU time 4.39 seconds
Started Jul 05 06:28:49 PM PDT 24
Finished Jul 05 06:28:54 PM PDT 24
Peak memory 225632 kb
Host smart-9dbd8e50-7a68-4027-a823-6115b9b25c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649602955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2649602955
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1856718854
Short name T590
Test name
Test status
Simulation time 16343577 ps
CPU time 0.79 seconds
Started Jul 05 06:28:47 PM PDT 24
Finished Jul 05 06:28:49 PM PDT 24
Peak memory 207560 kb
Host smart-360a0415-3ff8-4cd0-a568-ddef23006d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856718854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1856718854
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.221785302
Short name T129
Test name
Test status
Simulation time 3592370016 ps
CPU time 46.39 seconds
Started Jul 05 06:28:53 PM PDT 24
Finished Jul 05 06:29:40 PM PDT 24
Peak memory 258488 kb
Host smart-2c8e2106-0380-4fa0-a5d8-401a440a3fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221785302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.221785302
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1585081629
Short name T26
Test name
Test status
Simulation time 8935397236 ps
CPU time 17.26 seconds
Started Jul 05 06:28:57 PM PDT 24
Finished Jul 05 06:29:14 PM PDT 24
Peak memory 218912 kb
Host smart-f6f4791a-55a3-4ef8-aed5-52e3e1db83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585081629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1585081629
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2431117548
Short name T940
Test name
Test status
Simulation time 842007360 ps
CPU time 11.92 seconds
Started Jul 05 06:28:47 PM PDT 24
Finished Jul 05 06:28:59 PM PDT 24
Peak memory 241988 kb
Host smart-b3c1f74f-6a74-4902-bc6d-9a905f5cd455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431117548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2431117548
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2687016133
Short name T634
Test name
Test status
Simulation time 22904763045 ps
CPU time 56.85 seconds
Started Jul 05 06:28:52 PM PDT 24
Finished Jul 05 06:29:49 PM PDT 24
Peak memory 250616 kb
Host smart-f72868f3-b73b-464a-b8b8-6e46a56dfd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687016133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2687016133
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2450910404
Short name T839
Test name
Test status
Simulation time 147339443 ps
CPU time 3.33 seconds
Started Jul 05 06:28:48 PM PDT 24
Finished Jul 05 06:28:52 PM PDT 24
Peak memory 225304 kb
Host smart-eab01051-50dc-43ac-9ae2-72b289080581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450910404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2450910404
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.663581775
Short name T896
Test name
Test status
Simulation time 3192415727 ps
CPU time 22.73 seconds
Started Jul 05 06:28:47 PM PDT 24
Finished Jul 05 06:29:10 PM PDT 24
Peak memory 233928 kb
Host smart-4212db21-7bf0-4b71-a941-805ca357d264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663581775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.663581775
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2859567257
Short name T836
Test name
Test status
Simulation time 632470426 ps
CPU time 6.51 seconds
Started Jul 05 06:28:45 PM PDT 24
Finished Jul 05 06:28:52 PM PDT 24
Peak memory 241540 kb
Host smart-98fb54f8-acdc-40e6-be2a-cce5e9364b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859567257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2859567257
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1773810499
Short name T187
Test name
Test status
Simulation time 3190469564 ps
CPU time 9.2 seconds
Started Jul 05 06:28:49 PM PDT 24
Finished Jul 05 06:28:58 PM PDT 24
Peak memory 225712 kb
Host smart-e187473b-b0cc-4f22-a4f2-001f8433a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773810499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1773810499
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1868852710
Short name T716
Test name
Test status
Simulation time 2556978394 ps
CPU time 8.16 seconds
Started Jul 05 06:28:54 PM PDT 24
Finished Jul 05 06:29:02 PM PDT 24
Peak memory 221264 kb
Host smart-b73d5d69-087b-4bf1-aa86-a65e62e1036c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1868852710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1868852710
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2720310917
Short name T726
Test name
Test status
Simulation time 11479137 ps
CPU time 0.73 seconds
Started Jul 05 06:28:46 PM PDT 24
Finished Jul 05 06:28:47 PM PDT 24
Peak memory 206896 kb
Host smart-51bfa225-7290-4150-91a1-5bf385e5ae1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720310917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2720310917
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.683790623
Short name T435
Test name
Test status
Simulation time 1052451618 ps
CPU time 1.56 seconds
Started Jul 05 06:28:45 PM PDT 24
Finished Jul 05 06:28:47 PM PDT 24
Peak memory 208080 kb
Host smart-917a7ef1-99bf-4ccb-a792-c42571d0b5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683790623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.683790623
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3549390727
Short name T441
Test name
Test status
Simulation time 133242571 ps
CPU time 0.96 seconds
Started Jul 05 06:28:46 PM PDT 24
Finished Jul 05 06:28:48 PM PDT 24
Peak memory 208032 kb
Host smart-e94d7eb1-8c1d-46b9-a2c3-8b0b2561d497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549390727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3549390727
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2145557038
Short name T631
Test name
Test status
Simulation time 107880799 ps
CPU time 0.89 seconds
Started Jul 05 06:28:48 PM PDT 24
Finished Jul 05 06:28:50 PM PDT 24
Peak memory 208048 kb
Host smart-7bb910dd-bfd2-4339-9174-95324cc6039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145557038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2145557038
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1269890352
Short name T219
Test name
Test status
Simulation time 17302009550 ps
CPU time 18.46 seconds
Started Jul 05 06:28:49 PM PDT 24
Finished Jul 05 06:29:08 PM PDT 24
Peak memory 242040 kb
Host smart-d5ac7b54-591f-4f2a-be4f-8be0a1179f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269890352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1269890352
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1927353313
Short name T385
Test name
Test status
Simulation time 21463174 ps
CPU time 0.73 seconds
Started Jul 05 06:28:59 PM PDT 24
Finished Jul 05 06:29:00 PM PDT 24
Peak memory 206416 kb
Host smart-adafdb60-9b78-4d15-ae17-0647c983472c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927353313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1927353313
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3849517380
Short name T756
Test name
Test status
Simulation time 774364561 ps
CPU time 3.18 seconds
Started Jul 05 06:28:53 PM PDT 24
Finished Jul 05 06:28:57 PM PDT 24
Peak memory 233792 kb
Host smart-ab2d5b33-3469-45ab-b933-e478be11156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849517380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3849517380
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3387235048
Short name T784
Test name
Test status
Simulation time 132175894 ps
CPU time 0.79 seconds
Started Jul 05 06:28:56 PM PDT 24
Finished Jul 05 06:28:57 PM PDT 24
Peak memory 206848 kb
Host smart-c1378717-fda7-4f55-b8f3-18a3954d9671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387235048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3387235048
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1139736480
Short name T346
Test name
Test status
Simulation time 22453954674 ps
CPU time 71.93 seconds
Started Jul 05 06:28:53 PM PDT 24
Finished Jul 05 06:30:05 PM PDT 24
Peak memory 242028 kb
Host smart-a1851508-207d-4784-bbd8-e15a155085bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139736480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1139736480
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3951599311
Short name T880
Test name
Test status
Simulation time 19083941473 ps
CPU time 184.21 seconds
Started Jul 05 06:28:52 PM PDT 24
Finished Jul 05 06:31:56 PM PDT 24
Peak memory 252920 kb
Host smart-01de7656-b5ed-4829-aad7-f2051cba495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951599311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3951599311
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.441981553
Short name T870
Test name
Test status
Simulation time 74077882244 ps
CPU time 346.11 seconds
Started Jul 05 06:28:59 PM PDT 24
Finished Jul 05 06:34:45 PM PDT 24
Peak memory 255076 kb
Host smart-2432184b-995a-431d-92fd-f30ae10974cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441981553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.441981553
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.400055071
Short name T450
Test name
Test status
Simulation time 911448143 ps
CPU time 6.2 seconds
Started Jul 05 06:28:54 PM PDT 24
Finished Jul 05 06:29:00 PM PDT 24
Peak memory 233776 kb
Host smart-6090e3c3-5c64-4f3c-9e56-6d394befc81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400055071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.400055071
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.214593959
Short name T715
Test name
Test status
Simulation time 33506111053 ps
CPU time 67.79 seconds
Started Jul 05 06:28:52 PM PDT 24
Finished Jul 05 06:30:01 PM PDT 24
Peak memory 250672 kb
Host smart-1678dffd-a284-47b6-82a6-ad4c8be47b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214593959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.214593959
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2328849198
Short name T757
Test name
Test status
Simulation time 3412949145 ps
CPU time 9.05 seconds
Started Jul 05 06:28:56 PM PDT 24
Finished Jul 05 06:29:05 PM PDT 24
Peak memory 225752 kb
Host smart-8a50c3f9-efd1-43e7-97e4-a99775ad02a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328849198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2328849198
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1584816740
Short name T637
Test name
Test status
Simulation time 1905317936 ps
CPU time 7.31 seconds
Started Jul 05 06:28:52 PM PDT 24
Finished Jul 05 06:29:00 PM PDT 24
Peak memory 241712 kb
Host smart-13c2fe6c-b66f-405a-acba-86e5e1d20238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584816740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1584816740
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.413936788
Short name T220
Test name
Test status
Simulation time 2718347559 ps
CPU time 14.73 seconds
Started Jul 05 06:28:54 PM PDT 24
Finished Jul 05 06:29:09 PM PDT 24
Peak memory 233932 kb
Host smart-aaf1d586-b0e7-4b89-8005-1c91f30511d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413936788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.413936788
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1727750967
Short name T488
Test name
Test status
Simulation time 373108108 ps
CPU time 5.38 seconds
Started Jul 05 06:28:52 PM PDT 24
Finished Jul 05 06:28:58 PM PDT 24
Peak memory 233704 kb
Host smart-d036a1f1-b06a-4e8a-b210-747bed7d6d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727750967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1727750967
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.310428459
Short name T650
Test name
Test status
Simulation time 411845909 ps
CPU time 4.37 seconds
Started Jul 05 06:28:56 PM PDT 24
Finished Jul 05 06:29:01 PM PDT 24
Peak memory 223976 kb
Host smart-e76bbab2-3d85-4bb1-91d9-f54e2a9feb71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=310428459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.310428459
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2595668153
Short name T29
Test name
Test status
Simulation time 187294011720 ps
CPU time 281.3 seconds
Started Jul 05 06:29:01 PM PDT 24
Finished Jul 05 06:33:43 PM PDT 24
Peak memory 257656 kb
Host smart-faf1a553-9e46-4e9c-b0ae-9f0b42ef64d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595668153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2595668153
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2943219589
Short name T1002
Test name
Test status
Simulation time 11559208639 ps
CPU time 14.84 seconds
Started Jul 05 06:28:53 PM PDT 24
Finished Jul 05 06:29:09 PM PDT 24
Peak memory 221212 kb
Host smart-a850039c-8208-4668-81e1-c3b1519a50de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943219589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2943219589
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.770855585
Short name T568
Test name
Test status
Simulation time 19404704912 ps
CPU time 14.37 seconds
Started Jul 05 06:28:55 PM PDT 24
Finished Jul 05 06:29:10 PM PDT 24
Peak memory 217416 kb
Host smart-3693b18b-a42e-4041-9b79-b3850e5cd918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770855585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.770855585
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3612190335
Short name T660
Test name
Test status
Simulation time 50566896 ps
CPU time 1.34 seconds
Started Jul 05 06:28:52 PM PDT 24
Finished Jul 05 06:28:54 PM PDT 24
Peak memory 209212 kb
Host smart-8c314815-3bad-49e4-88c5-eb29cbb9e684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612190335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3612190335
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2616604396
Short name T954
Test name
Test status
Simulation time 36171850 ps
CPU time 0.84 seconds
Started Jul 05 06:28:53 PM PDT 24
Finished Jul 05 06:28:55 PM PDT 24
Peak memory 206996 kb
Host smart-772bc33e-241e-493b-bc4f-580361746805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616604396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2616604396
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3090563061
Short name T393
Test name
Test status
Simulation time 284195856 ps
CPU time 5.34 seconds
Started Jul 05 06:28:53 PM PDT 24
Finished Jul 05 06:28:59 PM PDT 24
Peak memory 233764 kb
Host smart-5a5e7f46-78f9-42c0-afc1-28513e055326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090563061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3090563061
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1304076029
Short name T351
Test name
Test status
Simulation time 20529323 ps
CPU time 0.78 seconds
Started Jul 05 06:28:59 PM PDT 24
Finished Jul 05 06:29:01 PM PDT 24
Peak memory 205804 kb
Host smart-86f35d80-074d-40b3-9257-385d20d30138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304076029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1304076029
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3429492709
Short name T518
Test name
Test status
Simulation time 709025563 ps
CPU time 6.63 seconds
Started Jul 05 06:29:00 PM PDT 24
Finished Jul 05 06:29:07 PM PDT 24
Peak memory 225600 kb
Host smart-55f7cd7d-c0f7-40f4-b34b-904414c34da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429492709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3429492709
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1880569656
Short name T377
Test name
Test status
Simulation time 34562708 ps
CPU time 0.8 seconds
Started Jul 05 06:29:01 PM PDT 24
Finished Jul 05 06:29:02 PM PDT 24
Peak memory 207544 kb
Host smart-ed3153f1-7fb7-4540-b092-c04c14ff91ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880569656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1880569656
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.472880190
Short name T174
Test name
Test status
Simulation time 3033420608 ps
CPU time 61.28 seconds
Started Jul 05 06:29:00 PM PDT 24
Finished Jul 05 06:30:02 PM PDT 24
Peak memory 258264 kb
Host smart-a0696f14-4ba4-43d1-aab9-963193c4d003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472880190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.472880190
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3707557922
Short name T641
Test name
Test status
Simulation time 7351310201 ps
CPU time 85.03 seconds
Started Jul 05 06:29:01 PM PDT 24
Finished Jul 05 06:30:26 PM PDT 24
Peak memory 250340 kb
Host smart-b67b2ac4-11f7-4151-9248-cbd2241dc3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707557922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3707557922
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.603159603
Short name T741
Test name
Test status
Simulation time 97956832 ps
CPU time 4.1 seconds
Started Jul 05 06:28:59 PM PDT 24
Finished Jul 05 06:29:03 PM PDT 24
Peak memory 225564 kb
Host smart-2d9829ae-380f-4d8b-a77e-01919f06d5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603159603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.603159603
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.199041060
Short name T233
Test name
Test status
Simulation time 54781642343 ps
CPU time 37.49 seconds
Started Jul 05 06:29:00 PM PDT 24
Finished Jul 05 06:29:38 PM PDT 24
Peak memory 242116 kb
Host smart-a84d6b91-3afa-4e7c-af77-90831b4beccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199041060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.199041060
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1769160290
Short name T989
Test name
Test status
Simulation time 1686811860 ps
CPU time 17.83 seconds
Started Jul 05 06:29:03 PM PDT 24
Finished Jul 05 06:29:21 PM PDT 24
Peak memory 233764 kb
Host smart-fee7f648-8942-41ce-953a-400f025f4fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769160290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1769160290
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.645195819
Short name T394
Test name
Test status
Simulation time 9514698769 ps
CPU time 28.51 seconds
Started Jul 05 06:29:02 PM PDT 24
Finished Jul 05 06:29:31 PM PDT 24
Peak memory 233944 kb
Host smart-9099aa0c-cc2b-40c8-bf5e-71d429f38258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645195819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.645195819
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1981810882
Short name T249
Test name
Test status
Simulation time 367838987 ps
CPU time 6.01 seconds
Started Jul 05 06:29:00 PM PDT 24
Finished Jul 05 06:29:07 PM PDT 24
Peak memory 233832 kb
Host smart-495665b0-5573-4d2c-abd7-db0e7bc1b6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981810882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1981810882
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2591769177
Short name T508
Test name
Test status
Simulation time 935355185 ps
CPU time 3.18 seconds
Started Jul 05 06:28:58 PM PDT 24
Finished Jul 05 06:29:02 PM PDT 24
Peak memory 233688 kb
Host smart-bb5cfc5a-aa5c-41e5-9924-ebbb5fa69a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591769177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2591769177
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.287756448
Short name T695
Test name
Test status
Simulation time 4554836738 ps
CPU time 11.55 seconds
Started Jul 05 06:29:01 PM PDT 24
Finished Jul 05 06:29:13 PM PDT 24
Peak memory 222696 kb
Host smart-9bead550-c7e0-4be7-97ec-474a9f32e46e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=287756448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.287756448
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.116008842
Short name T239
Test name
Test status
Simulation time 89649562854 ps
CPU time 398.09 seconds
Started Jul 05 06:29:00 PM PDT 24
Finished Jul 05 06:35:39 PM PDT 24
Peak memory 267784 kb
Host smart-dcdfc336-cdc7-4f8c-95ff-44662d632889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116008842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.116008842
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1552973160
Short name T326
Test name
Test status
Simulation time 17827434 ps
CPU time 0.72 seconds
Started Jul 05 06:28:58 PM PDT 24
Finished Jul 05 06:28:59 PM PDT 24
Peak memory 206668 kb
Host smart-6954b875-139d-49e0-9a52-8ae92ce56371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552973160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1552973160
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1849778516
Short name T793
Test name
Test status
Simulation time 56550523 ps
CPU time 0.7 seconds
Started Jul 05 06:28:59 PM PDT 24
Finished Jul 05 06:29:01 PM PDT 24
Peak memory 206628 kb
Host smart-d38cbba6-5a5a-46a7-b004-ace95cc4ef26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849778516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1849778516
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4242675471
Short name T41
Test name
Test status
Simulation time 566623857 ps
CPU time 3.33 seconds
Started Jul 05 06:29:02 PM PDT 24
Finished Jul 05 06:29:06 PM PDT 24
Peak memory 217436 kb
Host smart-b19ea679-07be-4b99-84ff-fb43b8674a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242675471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4242675471
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3944099781
Short name T827
Test name
Test status
Simulation time 43396353 ps
CPU time 0.8 seconds
Started Jul 05 06:29:00 PM PDT 24
Finished Jul 05 06:29:01 PM PDT 24
Peak memory 206968 kb
Host smart-2162324a-cd60-4139-81f2-43c9952c0e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944099781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3944099781
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.992107762
Short name T257
Test name
Test status
Simulation time 2967293602 ps
CPU time 13.28 seconds
Started Jul 05 06:28:59 PM PDT 24
Finished Jul 05 06:29:13 PM PDT 24
Peak memory 233920 kb
Host smart-76af3417-ad12-4dec-af81-1c8f2d7da860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992107762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.992107762
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.512143687
Short name T587
Test name
Test status
Simulation time 13649310 ps
CPU time 0.74 seconds
Started Jul 05 06:29:06 PM PDT 24
Finished Jul 05 06:29:07 PM PDT 24
Peak memory 206696 kb
Host smart-3beffdd3-d40b-4fdd-b0cb-a2939ab8483a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512143687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.512143687
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3039737500
Short name T974
Test name
Test status
Simulation time 262535191 ps
CPU time 3.91 seconds
Started Jul 05 06:29:10 PM PDT 24
Finished Jul 05 06:29:14 PM PDT 24
Peak memory 233796 kb
Host smart-64ef96ef-e72d-4206-91dd-1041e86cc47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039737500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3039737500
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4236001933
Short name T334
Test name
Test status
Simulation time 23580614 ps
CPU time 0.79 seconds
Started Jul 05 06:29:09 PM PDT 24
Finished Jul 05 06:29:10 PM PDT 24
Peak memory 207528 kb
Host smart-23588d25-032f-4efe-8b5b-aeef7f8c005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236001933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4236001933
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3419609560
Short name T600
Test name
Test status
Simulation time 8620564607 ps
CPU time 31.08 seconds
Started Jul 05 06:29:05 PM PDT 24
Finished Jul 05 06:29:37 PM PDT 24
Peak memory 233936 kb
Host smart-4fab3b17-98c6-4342-89fa-9a11bddc7401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419609560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3419609560
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1886179411
Short name T54
Test name
Test status
Simulation time 11407694799 ps
CPU time 105.37 seconds
Started Jul 05 06:29:07 PM PDT 24
Finished Jul 05 06:30:53 PM PDT 24
Peak memory 242248 kb
Host smart-686bab8a-1562-4daf-a3ff-613ff59e0d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886179411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1886179411
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3267803123
Short name T139
Test name
Test status
Simulation time 33457422646 ps
CPU time 178.79 seconds
Started Jul 05 06:29:13 PM PDT 24
Finished Jul 05 06:32:12 PM PDT 24
Peak memory 250796 kb
Host smart-15acecff-4b02-4ed0-9fc2-4961f2809b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267803123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3267803123
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1273615462
Short name T492
Test name
Test status
Simulation time 160891924 ps
CPU time 4.42 seconds
Started Jul 05 06:29:07 PM PDT 24
Finished Jul 05 06:29:12 PM PDT 24
Peak memory 233788 kb
Host smart-22a9b0f4-0e89-443b-b5e3-3a9afcc91645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273615462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1273615462
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1976401609
Short name T817
Test name
Test status
Simulation time 60258520276 ps
CPU time 256.14 seconds
Started Jul 05 06:29:09 PM PDT 24
Finished Jul 05 06:33:26 PM PDT 24
Peak memory 258504 kb
Host smart-3789b117-0ec6-4b6a-b8b7-12a75a7fb018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976401609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1976401609
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4258881908
Short name T406
Test name
Test status
Simulation time 1276757454 ps
CPU time 7.9 seconds
Started Jul 05 06:29:06 PM PDT 24
Finished Jul 05 06:29:14 PM PDT 24
Peak memory 233768 kb
Host smart-cb892d17-7442-4b45-b9ea-f43811ab20ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258881908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4258881908
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.328785622
Short name T592
Test name
Test status
Simulation time 13427293955 ps
CPU time 33.2 seconds
Started Jul 05 06:29:09 PM PDT 24
Finished Jul 05 06:29:42 PM PDT 24
Peak memory 225728 kb
Host smart-f960806d-2316-4bb3-9eb0-311d08ae347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328785622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.328785622
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2942350133
Short name T1005
Test name
Test status
Simulation time 35550233 ps
CPU time 2.32 seconds
Started Jul 05 06:29:07 PM PDT 24
Finished Jul 05 06:29:10 PM PDT 24
Peak memory 233780 kb
Host smart-edb0bbf4-689b-417f-a718-d5dcca23e4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942350133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2942350133
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.387355309
Short name T778
Test name
Test status
Simulation time 2339868592 ps
CPU time 8.38 seconds
Started Jul 05 06:29:13 PM PDT 24
Finished Jul 05 06:29:22 PM PDT 24
Peak memory 225660 kb
Host smart-2ad09908-da35-4551-a0c3-3e81d1762bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387355309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.387355309
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2719537636
Short name T327
Test name
Test status
Simulation time 223666767 ps
CPU time 4.74 seconds
Started Jul 05 06:29:07 PM PDT 24
Finished Jul 05 06:29:12 PM PDT 24
Peak memory 223068 kb
Host smart-6361dd71-53f5-4cb9-955f-98a01ae95174
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2719537636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2719537636
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3742244364
Short name T263
Test name
Test status
Simulation time 47884584415 ps
CPU time 405.43 seconds
Started Jul 05 06:29:07 PM PDT 24
Finished Jul 05 06:35:53 PM PDT 24
Peak memory 262800 kb
Host smart-b8ccc082-9a5a-47e4-a82d-1a9e9962b341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742244364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3742244364
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3359632965
Short name T1001
Test name
Test status
Simulation time 7060584297 ps
CPU time 22.5 seconds
Started Jul 05 06:29:08 PM PDT 24
Finished Jul 05 06:29:31 PM PDT 24
Peak memory 220812 kb
Host smart-c763ae03-d6ec-4bb1-adcc-955645b6941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359632965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3359632965
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1740388253
Short name T613
Test name
Test status
Simulation time 942993225 ps
CPU time 3.87 seconds
Started Jul 05 06:29:08 PM PDT 24
Finished Jul 05 06:29:12 PM PDT 24
Peak memory 217396 kb
Host smart-be6b3023-406e-4529-955e-8abf9a350f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740388253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1740388253
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4253151161
Short name T50
Test name
Test status
Simulation time 309378058 ps
CPU time 1.67 seconds
Started Jul 05 06:29:13 PM PDT 24
Finished Jul 05 06:29:15 PM PDT 24
Peak memory 217380 kb
Host smart-94ffdb1a-323c-4272-aa19-27926860f2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253151161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4253151161
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2962782122
Short name T324
Test name
Test status
Simulation time 62255477 ps
CPU time 0.88 seconds
Started Jul 05 06:29:09 PM PDT 24
Finished Jul 05 06:29:11 PM PDT 24
Peak memory 206988 kb
Host smart-b7307ba2-8944-4996-9eb2-663a19bd0d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962782122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2962782122
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2566923716
Short name T210
Test name
Test status
Simulation time 2278651347 ps
CPU time 6.32 seconds
Started Jul 05 06:29:06 PM PDT 24
Finished Jul 05 06:29:12 PM PDT 24
Peak memory 225688 kb
Host smart-af0b3049-e82d-4255-9a94-fe5c5e872550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566923716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2566923716
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3661934340
Short name T370
Test name
Test status
Simulation time 12203018 ps
CPU time 0.72 seconds
Started Jul 05 06:29:19 PM PDT 24
Finished Jul 05 06:29:20 PM PDT 24
Peak memory 206412 kb
Host smart-70e34300-8b06-4c11-aa80-3b91b3a7faa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661934340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3661934340
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.794990624
Short name T369
Test name
Test status
Simulation time 2907858292 ps
CPU time 8.31 seconds
Started Jul 05 06:29:16 PM PDT 24
Finished Jul 05 06:29:24 PM PDT 24
Peak memory 225704 kb
Host smart-39eb2c6d-5692-4734-8494-65550d74dd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794990624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.794990624
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2352473266
Short name T69
Test name
Test status
Simulation time 16229411 ps
CPU time 0.81 seconds
Started Jul 05 06:29:14 PM PDT 24
Finished Jul 05 06:29:15 PM PDT 24
Peak memory 206536 kb
Host smart-81647c28-d6ac-44c0-8776-94e906c8c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352473266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2352473266
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2623375608
Short name T203
Test name
Test status
Simulation time 25792037214 ps
CPU time 92.08 seconds
Started Jul 05 06:29:13 PM PDT 24
Finished Jul 05 06:30:46 PM PDT 24
Peak memory 267464 kb
Host smart-ff5bc0ae-e10d-494d-af95-0231491d8240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623375608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2623375608
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.301497055
Short name T307
Test name
Test status
Simulation time 127090681549 ps
CPU time 98.61 seconds
Started Jul 05 06:29:12 PM PDT 24
Finished Jul 05 06:30:51 PM PDT 24
Peak memory 250452 kb
Host smart-9c3df138-c3b6-4576-8228-4af170a1754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301497055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.301497055
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.996209241
Short name T822
Test name
Test status
Simulation time 83982847 ps
CPU time 0.84 seconds
Started Jul 05 06:29:14 PM PDT 24
Finished Jul 05 06:29:16 PM PDT 24
Peak memory 218160 kb
Host smart-b416e8b0-7155-4987-9566-de07521df1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996209241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.996209241
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1489424045
Short name T910
Test name
Test status
Simulation time 749971852 ps
CPU time 4.07 seconds
Started Jul 05 06:29:14 PM PDT 24
Finished Jul 05 06:29:18 PM PDT 24
Peak memory 225568 kb
Host smart-3559c69f-3e2e-4ab9-95c7-fbe7a757e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489424045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1489424045
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.4186996497
Short name T281
Test name
Test status
Simulation time 233501346341 ps
CPU time 207.27 seconds
Started Jul 05 06:29:13 PM PDT 24
Finished Jul 05 06:32:41 PM PDT 24
Peak memory 251344 kb
Host smart-23643148-0680-478a-b5d0-5ddb292d65a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186996497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.4186996497
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1851881097
Short name T749
Test name
Test status
Simulation time 434826725 ps
CPU time 4.41 seconds
Started Jul 05 06:29:13 PM PDT 24
Finished Jul 05 06:29:18 PM PDT 24
Peak memory 233816 kb
Host smart-1c08e6c0-e160-4dc7-9d12-32c7c61c3d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851881097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1851881097
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.925028665
Short name T517
Test name
Test status
Simulation time 60763192507 ps
CPU time 127.34 seconds
Started Jul 05 06:29:14 PM PDT 24
Finished Jul 05 06:31:22 PM PDT 24
Peak memory 241916 kb
Host smart-a77debbc-339a-4314-85ab-d347555db49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925028665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.925028665
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2995053029
Short name T521
Test name
Test status
Simulation time 156478229 ps
CPU time 4.09 seconds
Started Jul 05 06:29:16 PM PDT 24
Finished Jul 05 06:29:21 PM PDT 24
Peak memory 225584 kb
Host smart-481836bc-2a9f-4bd4-819e-ecd44a4017e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995053029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2995053029
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2205545337
Short name T714
Test name
Test status
Simulation time 814517951 ps
CPU time 4.68 seconds
Started Jul 05 06:29:13 PM PDT 24
Finished Jul 05 06:29:18 PM PDT 24
Peak memory 236004 kb
Host smart-4d24c1d2-e03d-452a-b9b6-7cd420d980a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205545337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2205545337
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2701887701
Short name T414
Test name
Test status
Simulation time 744761922 ps
CPU time 9.6 seconds
Started Jul 05 06:29:14 PM PDT 24
Finished Jul 05 06:29:24 PM PDT 24
Peak memory 223292 kb
Host smart-867fe29a-ba45-4e17-897d-39875b76230f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2701887701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2701887701
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4011358795
Short name T573
Test name
Test status
Simulation time 12500111252 ps
CPU time 80.23 seconds
Started Jul 05 06:29:21 PM PDT 24
Finished Jul 05 06:30:41 PM PDT 24
Peak memory 225800 kb
Host smart-ff9494fe-8a1b-4b6a-9daa-d33af0201358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011358795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4011358795
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.473114332
Short name T559
Test name
Test status
Simulation time 8500057254 ps
CPU time 9.95 seconds
Started Jul 05 06:29:15 PM PDT 24
Finished Jul 05 06:29:25 PM PDT 24
Peak memory 217528 kb
Host smart-49faddcf-eafb-449d-aaee-16f04a4075c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473114332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.473114332
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1029713161
Short name T27
Test name
Test status
Simulation time 3177372098 ps
CPU time 4.96 seconds
Started Jul 05 06:29:12 PM PDT 24
Finished Jul 05 06:29:17 PM PDT 24
Peak memory 217536 kb
Host smart-b9fe3ad2-4593-4e55-b75e-3528e7fc6537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029713161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1029713161
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4096261092
Short name T663
Test name
Test status
Simulation time 186392691 ps
CPU time 0.99 seconds
Started Jul 05 06:29:14 PM PDT 24
Finished Jul 05 06:29:15 PM PDT 24
Peak memory 207996 kb
Host smart-4535fc34-799d-48e7-b558-5107e780aea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096261092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4096261092
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2426152440
Short name T709
Test name
Test status
Simulation time 147503643 ps
CPU time 0.79 seconds
Started Jul 05 06:29:14 PM PDT 24
Finished Jul 05 06:29:15 PM PDT 24
Peak memory 206988 kb
Host smart-f02ef159-6c45-4f84-bb6c-fd7c2acc55b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426152440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2426152440
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3169941109
Short name T366
Test name
Test status
Simulation time 533648352 ps
CPU time 2.66 seconds
Started Jul 05 06:29:15 PM PDT 24
Finished Jul 05 06:29:18 PM PDT 24
Peak memory 225580 kb
Host smart-6a707695-873b-4940-9509-7e39e635e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169941109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3169941109
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1387233132
Short name T532
Test name
Test status
Simulation time 11258620 ps
CPU time 0.67 seconds
Started Jul 05 06:25:50 PM PDT 24
Finished Jul 05 06:25:51 PM PDT 24
Peak memory 206288 kb
Host smart-6c7cb74a-d80c-4752-93a4-51116d8c2d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387233132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
387233132
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1185604386
Short name T797
Test name
Test status
Simulation time 317109453 ps
CPU time 2.21 seconds
Started Jul 05 06:25:35 PM PDT 24
Finished Jul 05 06:25:37 PM PDT 24
Peak memory 225536 kb
Host smart-973caf02-f476-469d-91cc-5945014e8e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185604386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1185604386
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3188883205
Short name T325
Test name
Test status
Simulation time 17698962 ps
CPU time 0.78 seconds
Started Jul 05 06:25:28 PM PDT 24
Finished Jul 05 06:25:29 PM PDT 24
Peak memory 207864 kb
Host smart-57086ae3-a7b4-4ff5-88ac-21feb601bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188883205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3188883205
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3131745330
Short name T700
Test name
Test status
Simulation time 787504256 ps
CPU time 3.58 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:53 PM PDT 24
Peak memory 219840 kb
Host smart-1a42ea8a-3131-43cc-ad44-0cc3dc3dd148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131745330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3131745330
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3504567553
Short name T1003
Test name
Test status
Simulation time 12797295598 ps
CPU time 124.81 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:27:54 PM PDT 24
Peak memory 236792 kb
Host smart-d341d100-e1a2-4b92-afb1-c1b2c3883bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504567553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3504567553
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1157157416
Short name T915
Test name
Test status
Simulation time 3345710537 ps
CPU time 72.42 seconds
Started Jul 05 06:25:47 PM PDT 24
Finished Jul 05 06:27:00 PM PDT 24
Peak memory 263312 kb
Host smart-a1ddd71d-f873-4a6d-a486-1a4e37a0b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157157416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1157157416
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.436655604
Short name T317
Test name
Test status
Simulation time 483341863 ps
CPU time 4.8 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:55 PM PDT 24
Peak memory 225568 kb
Host smart-66ea6936-fb7f-45bf-8e40-7bf41507fe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436655604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.436655604
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2039759067
Short name T752
Test name
Test status
Simulation time 332776185 ps
CPU time 8.11 seconds
Started Jul 05 06:25:48 PM PDT 24
Finished Jul 05 06:25:57 PM PDT 24
Peak memory 225648 kb
Host smart-34a67e73-023e-4ee8-a7cc-a73604165d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039759067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2039759067
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.678419738
Short name T236
Test name
Test status
Simulation time 275077690 ps
CPU time 6.14 seconds
Started Jul 05 06:25:36 PM PDT 24
Finished Jul 05 06:25:42 PM PDT 24
Peak memory 233784 kb
Host smart-89b55e87-7bbd-4c92-974e-abf8a09139ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678419738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.678419738
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2706662756
Short name T482
Test name
Test status
Simulation time 952650190 ps
CPU time 13.72 seconds
Started Jul 05 06:25:32 PM PDT 24
Finished Jul 05 06:25:46 PM PDT 24
Peak memory 249876 kb
Host smart-8ef55da8-61fe-494d-b1a3-0574146f1610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706662756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2706662756
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.4032804570
Short name T702
Test name
Test status
Simulation time 48628960 ps
CPU time 1.08 seconds
Started Jul 05 06:25:29 PM PDT 24
Finished Jul 05 06:25:31 PM PDT 24
Peak memory 217684 kb
Host smart-e360cfa3-f224-4748-8d6a-f4b790e8405a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032804570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.4032804570
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1745677225
Short name T913
Test name
Test status
Simulation time 9516771927 ps
CPU time 9.32 seconds
Started Jul 05 06:25:34 PM PDT 24
Finished Jul 05 06:25:43 PM PDT 24
Peak memory 240280 kb
Host smart-9013170e-acf3-41f2-90c0-09425990639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745677225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1745677225
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3695090541
Short name T933
Test name
Test status
Simulation time 1115624587 ps
CPU time 8.36 seconds
Started Jul 05 06:25:35 PM PDT 24
Finished Jul 05 06:25:43 PM PDT 24
Peak memory 241924 kb
Host smart-5a599a01-8a02-4c58-afc5-e68c2e9e10c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695090541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3695090541
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1858594772
Short name T647
Test name
Test status
Simulation time 982622251 ps
CPU time 8.6 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:58 PM PDT 24
Peak memory 222684 kb
Host smart-49ab025a-52f6-4594-a128-7c90b650adab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1858594772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1858594772
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3763648947
Short name T65
Test name
Test status
Simulation time 117762555 ps
CPU time 0.99 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:50 PM PDT 24
Peak memory 236620 kb
Host smart-dae48fbe-a0f7-49ab-9139-25ba78cfd100
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763648947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3763648947
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1952618898
Short name T137
Test name
Test status
Simulation time 105944661786 ps
CPU time 332.32 seconds
Started Jul 05 06:25:48 PM PDT 24
Finished Jul 05 06:31:20 PM PDT 24
Peak memory 283220 kb
Host smart-b9b1ee5a-5ac9-41be-8704-c60215b1b420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952618898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1952618898
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4097135958
Short name T53
Test name
Test status
Simulation time 81781890215 ps
CPU time 63.01 seconds
Started Jul 05 06:25:27 PM PDT 24
Finished Jul 05 06:26:30 PM PDT 24
Peak memory 217388 kb
Host smart-14ccd189-6b32-4cc7-8276-498e597d964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097135958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4097135958
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2866678354
Short name T436
Test name
Test status
Simulation time 6267858021 ps
CPU time 10.34 seconds
Started Jul 05 06:25:28 PM PDT 24
Finished Jul 05 06:25:39 PM PDT 24
Peak memory 217460 kb
Host smart-f53e0f94-90e5-4a81-96f1-496616d3819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866678354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2866678354
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2296683712
Short name T342
Test name
Test status
Simulation time 480157299 ps
CPU time 3.57 seconds
Started Jul 05 06:25:35 PM PDT 24
Finished Jul 05 06:25:39 PM PDT 24
Peak memory 217400 kb
Host smart-abe5fc04-9f91-46cc-8e2b-ec47605e0053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296683712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2296683712
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2293811126
Short name T442
Test name
Test status
Simulation time 45242950 ps
CPU time 0.76 seconds
Started Jul 05 06:25:35 PM PDT 24
Finished Jul 05 06:25:36 PM PDT 24
Peak memory 206988 kb
Host smart-40e09cbb-afed-4c63-a9b1-2a7e5d111857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293811126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2293811126
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4166038094
Short name T511
Test name
Test status
Simulation time 18628456961 ps
CPU time 26.23 seconds
Started Jul 05 06:25:35 PM PDT 24
Finished Jul 05 06:26:01 PM PDT 24
Peak memory 237692 kb
Host smart-315a4524-52be-4386-907e-4f50e04e8429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166038094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4166038094
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.688844429
Short name T773
Test name
Test status
Simulation time 11215505 ps
CPU time 0.74 seconds
Started Jul 05 06:29:27 PM PDT 24
Finished Jul 05 06:29:28 PM PDT 24
Peak memory 205708 kb
Host smart-7fecbaaa-6b70-4b51-a3ce-641675ec67f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688844429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.688844429
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3547868150
Short name T344
Test name
Test status
Simulation time 1299682215 ps
CPU time 12.49 seconds
Started Jul 05 06:29:20 PM PDT 24
Finished Jul 05 06:29:33 PM PDT 24
Peak memory 225616 kb
Host smart-b6ef92b1-5e41-4303-bb08-46e17343bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547868150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3547868150
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2184845088
Short name T957
Test name
Test status
Simulation time 88949818 ps
CPU time 0.84 seconds
Started Jul 05 06:29:19 PM PDT 24
Finished Jul 05 06:29:20 PM PDT 24
Peak memory 207880 kb
Host smart-b52a6e87-1243-4713-bb53-e756dd4a31a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184845088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2184845088
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.326640457
Short name T701
Test name
Test status
Simulation time 25563634553 ps
CPU time 187.62 seconds
Started Jul 05 06:29:28 PM PDT 24
Finished Jul 05 06:32:36 PM PDT 24
Peak memory 257056 kb
Host smart-f5a93c13-92b6-4579-96e8-7dd2cdc02d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326640457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.326640457
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.888496227
Short name T70
Test name
Test status
Simulation time 2988828436 ps
CPU time 22.26 seconds
Started Jul 05 06:29:28 PM PDT 24
Finished Jul 05 06:29:51 PM PDT 24
Peak memory 255344 kb
Host smart-dc35ca7c-80ca-48f5-b81e-4923b9b8228c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888496227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.888496227
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2409766617
Short name T200
Test name
Test status
Simulation time 40221433457 ps
CPU time 249.04 seconds
Started Jul 05 06:29:31 PM PDT 24
Finished Jul 05 06:33:40 PM PDT 24
Peak memory 252300 kb
Host smart-c4e6aef6-f10b-4adb-bea7-688d3f162a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409766617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2409766617
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3733556027
Short name T535
Test name
Test status
Simulation time 3077266626 ps
CPU time 18.79 seconds
Started Jul 05 06:29:27 PM PDT 24
Finished Jul 05 06:29:46 PM PDT 24
Peak memory 225720 kb
Host smart-691cde14-9750-4a60-912e-de4d6103ef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733556027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3733556027
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.824434791
Short name T218
Test name
Test status
Simulation time 109259757242 ps
CPU time 98.08 seconds
Started Jul 05 06:29:29 PM PDT 24
Finished Jul 05 06:31:07 PM PDT 24
Peak memory 250352 kb
Host smart-b953a976-d9d2-480a-8a67-c1d44aeca3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824434791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.824434791
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.506669974
Short name T565
Test name
Test status
Simulation time 46187774 ps
CPU time 2.91 seconds
Started Jul 05 06:29:20 PM PDT 24
Finished Jul 05 06:29:23 PM PDT 24
Peak memory 233836 kb
Host smart-d49847ec-f552-4154-9c1f-edb8bea46251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506669974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.506669974
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2360426734
Short name T91
Test name
Test status
Simulation time 103869659423 ps
CPU time 186.83 seconds
Started Jul 05 06:29:20 PM PDT 24
Finished Jul 05 06:32:28 PM PDT 24
Peak memory 236884 kb
Host smart-1ad7c128-0cb3-43ef-b939-376bb087b2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360426734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2360426734
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1544299115
Short name T438
Test name
Test status
Simulation time 1610316818 ps
CPU time 6.11 seconds
Started Jul 05 06:29:19 PM PDT 24
Finished Jul 05 06:29:25 PM PDT 24
Peak memory 225556 kb
Host smart-deba67b8-322a-4b2e-8bad-fbbfdd2be339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544299115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1544299115
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1061102271
Short name T722
Test name
Test status
Simulation time 4714589669 ps
CPU time 9.19 seconds
Started Jul 05 06:29:20 PM PDT 24
Finished Jul 05 06:29:29 PM PDT 24
Peak memory 233896 kb
Host smart-7661de14-ff91-44b3-a01b-bc569cefd298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061102271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1061102271
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2643559880
Short name T371
Test name
Test status
Simulation time 3499856845 ps
CPU time 11.49 seconds
Started Jul 05 06:29:31 PM PDT 24
Finished Jul 05 06:29:42 PM PDT 24
Peak memory 223220 kb
Host smart-5ed0453b-27d8-49ff-b32f-46ef01b89a91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2643559880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2643559880
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2002264934
Short name T725
Test name
Test status
Simulation time 77512569375 ps
CPU time 225.64 seconds
Started Jul 05 06:29:26 PM PDT 24
Finished Jul 05 06:33:12 PM PDT 24
Peak memory 257020 kb
Host smart-b50f5bdb-1905-43f8-bc17-bb207ed5156d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002264934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2002264934
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1140160879
Short name T331
Test name
Test status
Simulation time 33465997 ps
CPU time 0.75 seconds
Started Jul 05 06:29:21 PM PDT 24
Finished Jul 05 06:29:22 PM PDT 24
Peak memory 206640 kb
Host smart-f9c8a74c-8418-49ff-a63a-8b539c121601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140160879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1140160879
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1962445652
Short name T395
Test name
Test status
Simulation time 3570414636 ps
CPU time 6.55 seconds
Started Jul 05 06:29:19 PM PDT 24
Finished Jul 05 06:29:26 PM PDT 24
Peak memory 217516 kb
Host smart-aca4ba0e-fccf-4159-93c4-d7f94d388c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962445652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1962445652
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3724633219
Short name T610
Test name
Test status
Simulation time 23972526 ps
CPU time 0.96 seconds
Started Jul 05 06:29:21 PM PDT 24
Finished Jul 05 06:29:22 PM PDT 24
Peak memory 208204 kb
Host smart-c5475252-1325-4bb2-9d8c-281edf560264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724633219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3724633219
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.644088438
Short name T352
Test name
Test status
Simulation time 98004033 ps
CPU time 0.81 seconds
Started Jul 05 06:29:21 PM PDT 24
Finished Jul 05 06:29:22 PM PDT 24
Peak memory 207024 kb
Host smart-7c8353c7-e9b0-4300-8f79-859005d686a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644088438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.644088438
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4116495953
Short name T506
Test name
Test status
Simulation time 3061973016 ps
CPU time 6.56 seconds
Started Jul 05 06:29:22 PM PDT 24
Finished Jul 05 06:29:29 PM PDT 24
Peak memory 241976 kb
Host smart-940a0871-beca-4e20-83cf-45ef034c13cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116495953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4116495953
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1977624219
Short name T770
Test name
Test status
Simulation time 24400646 ps
CPU time 0.72 seconds
Started Jul 05 06:29:34 PM PDT 24
Finished Jul 05 06:29:35 PM PDT 24
Peak memory 206716 kb
Host smart-6be8b3d7-5d21-41ee-8a1a-5bd226e0ef55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977624219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1977624219
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.505772619
Short name T774
Test name
Test status
Simulation time 195310072 ps
CPU time 2.55 seconds
Started Jul 05 06:29:33 PM PDT 24
Finished Jul 05 06:29:36 PM PDT 24
Peak memory 225560 kb
Host smart-8071f943-17ad-42e3-93cf-64c92661235e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505772619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.505772619
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1015320647
Short name T845
Test name
Test status
Simulation time 28860898 ps
CPU time 0.77 seconds
Started Jul 05 06:29:28 PM PDT 24
Finished Jul 05 06:29:29 PM PDT 24
Peak memory 207888 kb
Host smart-ac720a9f-cc2c-4b9d-b92a-d6d2aef1bf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015320647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1015320647
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.872526040
Short name T891
Test name
Test status
Simulation time 35984280507 ps
CPU time 245.88 seconds
Started Jul 05 06:29:34 PM PDT 24
Finished Jul 05 06:33:40 PM PDT 24
Peak memory 255348 kb
Host smart-0dfc0ebe-ddc9-4999-9843-db86a20183d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872526040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.872526040
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2618269900
Short name T728
Test name
Test status
Simulation time 23661895149 ps
CPU time 67.6 seconds
Started Jul 05 06:29:39 PM PDT 24
Finished Jul 05 06:30:47 PM PDT 24
Peak memory 239272 kb
Host smart-afbc70ad-c121-4180-8b31-4652ec4a7215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618269900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2618269900
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1550746792
Short name T51
Test name
Test status
Simulation time 179136131 ps
CPU time 6.07 seconds
Started Jul 05 06:29:35 PM PDT 24
Finished Jul 05 06:29:41 PM PDT 24
Peak memory 236032 kb
Host smart-fda07022-7c73-49bc-b4e5-67b03e0ecd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550746792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1550746792
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4218227089
Short name T1023
Test name
Test status
Simulation time 391624665 ps
CPU time 2.32 seconds
Started Jul 05 06:29:34 PM PDT 24
Finished Jul 05 06:29:37 PM PDT 24
Peak memory 225324 kb
Host smart-1861cba4-cee9-4593-9fb2-587ad4c9143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218227089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4218227089
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1822447695
Short name T1000
Test name
Test status
Simulation time 4511844169 ps
CPU time 54.6 seconds
Started Jul 05 06:29:36 PM PDT 24
Finished Jul 05 06:30:31 PM PDT 24
Peak memory 225760 kb
Host smart-c512674d-f6a2-45ce-ac0f-983d37685e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822447695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1822447695
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.397075684
Short name T382
Test name
Test status
Simulation time 1523141452 ps
CPU time 12.63 seconds
Started Jul 05 06:29:28 PM PDT 24
Finished Jul 05 06:29:41 PM PDT 24
Peak memory 233808 kb
Host smart-e8ef0c14-7148-448e-9c68-211660705935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397075684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.397075684
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3668427501
Short name T620
Test name
Test status
Simulation time 4993062057 ps
CPU time 19.07 seconds
Started Jul 05 06:29:27 PM PDT 24
Finished Jul 05 06:29:47 PM PDT 24
Peak memory 242068 kb
Host smart-63bdc2b9-3ee5-4ceb-b014-e5b5e90926f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668427501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3668427501
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2810058386
Short name T992
Test name
Test status
Simulation time 4885696157 ps
CPU time 12.09 seconds
Started Jul 05 06:29:34 PM PDT 24
Finished Jul 05 06:29:47 PM PDT 24
Peak memory 220484 kb
Host smart-a07f3a41-4f3c-4c81-8e9f-0cb2ca6406d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810058386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2810058386
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3616647110
Short name T644
Test name
Test status
Simulation time 1509668817 ps
CPU time 20.63 seconds
Started Jul 05 06:29:27 PM PDT 24
Finished Jul 05 06:29:48 PM PDT 24
Peak memory 217448 kb
Host smart-533becc4-f67a-4e5b-b489-768b28838603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616647110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3616647110
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2922547702
Short name T747
Test name
Test status
Simulation time 18632712686 ps
CPU time 14.68 seconds
Started Jul 05 06:29:29 PM PDT 24
Finished Jul 05 06:29:44 PM PDT 24
Peak memory 217452 kb
Host smart-f2ac8542-c243-4379-943e-aa596d599995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922547702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2922547702
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1182626622
Short name T42
Test name
Test status
Simulation time 1222572925 ps
CPU time 2.01 seconds
Started Jul 05 06:29:27 PM PDT 24
Finished Jul 05 06:29:29 PM PDT 24
Peak memory 217360 kb
Host smart-905b1bbc-bbba-4b1e-80a4-acedc64a6f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182626622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1182626622
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.688837882
Short name T73
Test name
Test status
Simulation time 67051588 ps
CPU time 0.74 seconds
Started Jul 05 06:29:28 PM PDT 24
Finished Jul 05 06:29:29 PM PDT 24
Peak memory 207016 kb
Host smart-1e77f7ed-99b9-4684-9bc7-df983af36581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688837882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.688837882
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2010139754
Short name T775
Test name
Test status
Simulation time 36740279515 ps
CPU time 31.09 seconds
Started Jul 05 06:29:34 PM PDT 24
Finished Jul 05 06:30:06 PM PDT 24
Peak memory 250316 kb
Host smart-2478bc32-518b-4e68-bded-7ff19d4f312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010139754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2010139754
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2273335479
Short name T849
Test name
Test status
Simulation time 39998835 ps
CPU time 0.74 seconds
Started Jul 05 06:29:40 PM PDT 24
Finished Jul 05 06:29:41 PM PDT 24
Peak memory 205776 kb
Host smart-fb77b6fa-e24c-4578-bbbd-4ab913c3604b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273335479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2273335479
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3270566997
Short name T805
Test name
Test status
Simulation time 913243405 ps
CPU time 4.77 seconds
Started Jul 05 06:29:42 PM PDT 24
Finished Jul 05 06:29:47 PM PDT 24
Peak memory 233768 kb
Host smart-e8df0733-75f0-4a15-8c97-c7337ebc45e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270566997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3270566997
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2435153283
Short name T48
Test name
Test status
Simulation time 15463976 ps
CPU time 0.8 seconds
Started Jul 05 06:29:34 PM PDT 24
Finished Jul 05 06:29:35 PM PDT 24
Peak memory 207568 kb
Host smart-958ca066-288d-4b64-83ae-170f386db217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435153283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2435153283
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2588166501
Short name T921
Test name
Test status
Simulation time 37304591122 ps
CPU time 114.79 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:31:37 PM PDT 24
Peak memory 255808 kb
Host smart-a6ada01a-771a-421c-82e0-2123e7402756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588166501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2588166501
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1334780941
Short name T308
Test name
Test status
Simulation time 3264962207 ps
CPU time 22.01 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:30:03 PM PDT 24
Peak memory 220848 kb
Host smart-dff8302e-45e2-4acf-8c0c-c1fb3c531148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334780941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1334780941
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1892733365
Short name T1004
Test name
Test status
Simulation time 1019344292 ps
CPU time 7.72 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:49 PM PDT 24
Peak memory 224008 kb
Host smart-22232679-1992-4edc-8e2f-c6c15eda918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892733365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1892733365
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3898528764
Short name T484
Test name
Test status
Simulation time 2876794726 ps
CPU time 53.28 seconds
Started Jul 05 06:29:40 PM PDT 24
Finished Jul 05 06:30:34 PM PDT 24
Peak memory 233936 kb
Host smart-fa031930-d12a-4d7f-bbbe-8547f4a60791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898528764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3898528764
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.4100097151
Short name T188
Test name
Test status
Simulation time 125643443098 ps
CPU time 233.94 seconds
Started Jul 05 06:29:42 PM PDT 24
Finished Jul 05 06:33:37 PM PDT 24
Peak memory 254200 kb
Host smart-0456013c-727d-4bc8-a57b-22af11cb60f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100097151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.4100097151
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3481252105
Short name T818
Test name
Test status
Simulation time 77416074 ps
CPU time 2.17 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:43 PM PDT 24
Peak memory 224900 kb
Host smart-33720ed6-c5a4-4634-99a4-f52be2b603cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481252105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3481252105
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.363190294
Short name T993
Test name
Test status
Simulation time 1921102705 ps
CPU time 5.14 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:47 PM PDT 24
Peak memory 233856 kb
Host smart-b3919e8f-4141-40fc-ba47-c0651f9720e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363190294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.363190294
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.569360626
Short name T953
Test name
Test status
Simulation time 1150722248 ps
CPU time 5.35 seconds
Started Jul 05 06:29:36 PM PDT 24
Finished Jul 05 06:29:41 PM PDT 24
Peak memory 225568 kb
Host smart-a556132f-d097-48e7-b317-ca7f5d7ab053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569360626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.569360626
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.709087517
Short name T983
Test name
Test status
Simulation time 718362201 ps
CPU time 3.83 seconds
Started Jul 05 06:29:34 PM PDT 24
Finished Jul 05 06:29:38 PM PDT 24
Peak memory 225616 kb
Host smart-36e1a920-eba0-4987-b8a9-9dd1b342d071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709087517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.709087517
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1560337419
Short name T929
Test name
Test status
Simulation time 570422568 ps
CPU time 4.74 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:46 PM PDT 24
Peak memory 220308 kb
Host smart-9e75e273-a075-4c7b-8414-8ff5ac908b6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1560337419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1560337419
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.124434786
Short name T1017
Test name
Test status
Simulation time 11699952211 ps
CPU time 257.48 seconds
Started Jul 05 06:29:42 PM PDT 24
Finished Jul 05 06:34:00 PM PDT 24
Peak memory 280308 kb
Host smart-4f1a1fc3-6dee-487a-b3c8-99d0ecd70090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124434786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.124434786
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1025434415
Short name T304
Test name
Test status
Simulation time 750633883 ps
CPU time 9.36 seconds
Started Jul 05 06:29:38 PM PDT 24
Finished Jul 05 06:29:48 PM PDT 24
Peak memory 217456 kb
Host smart-e70b9b6b-0c8d-485f-a40e-fae0975b6f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025434415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1025434415
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3902321679
Short name T485
Test name
Test status
Simulation time 1612900496 ps
CPU time 1.59 seconds
Started Jul 05 06:29:39 PM PDT 24
Finished Jul 05 06:29:41 PM PDT 24
Peak memory 208952 kb
Host smart-8d434425-4fd9-4a42-8576-f5b186ae6650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902321679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3902321679
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2735445965
Short name T751
Test name
Test status
Simulation time 97343354 ps
CPU time 3.77 seconds
Started Jul 05 06:29:34 PM PDT 24
Finished Jul 05 06:29:38 PM PDT 24
Peak memory 217444 kb
Host smart-2e5c9214-6f25-4837-b57f-031bf747d92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735445965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2735445965
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3698641421
Short name T1011
Test name
Test status
Simulation time 45694129 ps
CPU time 0.7 seconds
Started Jul 05 06:29:33 PM PDT 24
Finished Jul 05 06:29:34 PM PDT 24
Peak memory 206604 kb
Host smart-63e0bf23-84bb-46a7-84fc-60ad8f89e99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698641421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3698641421
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3742124448
Short name T670
Test name
Test status
Simulation time 12175434377 ps
CPU time 13.68 seconds
Started Jul 05 06:29:39 PM PDT 24
Finished Jul 05 06:29:53 PM PDT 24
Peak memory 242080 kb
Host smart-fb71338c-bb05-4a2e-a5ba-4b539fd21d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742124448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3742124448
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2643999909
Short name T788
Test name
Test status
Simulation time 12609779 ps
CPU time 0.72 seconds
Started Jul 05 06:29:49 PM PDT 24
Finished Jul 05 06:29:50 PM PDT 24
Peak memory 206428 kb
Host smart-93366fd7-fc0b-460a-9ca5-8d7ed9e826af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643999909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2643999909
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.945012334
Short name T479
Test name
Test status
Simulation time 1142411562 ps
CPU time 17.11 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:59 PM PDT 24
Peak memory 225592 kb
Host smart-8d957a6c-3b75-497f-8c15-d495cacdbaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945012334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.945012334
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.555268611
Short name T332
Test name
Test status
Simulation time 16025118 ps
CPU time 0.75 seconds
Started Jul 05 06:29:42 PM PDT 24
Finished Jul 05 06:29:43 PM PDT 24
Peak memory 206832 kb
Host smart-db060164-a5af-4085-a77a-49b02613aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555268611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.555268611
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2927389781
Short name T282
Test name
Test status
Simulation time 152368142049 ps
CPU time 281.27 seconds
Started Jul 05 06:29:47 PM PDT 24
Finished Jul 05 06:34:29 PM PDT 24
Peak memory 256292 kb
Host smart-894243ea-6c61-49cd-ab78-03d3a7583d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927389781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2927389781
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1736007869
Short name T209
Test name
Test status
Simulation time 7308337366 ps
CPU time 28.45 seconds
Started Jul 05 06:29:49 PM PDT 24
Finished Jul 05 06:30:17 PM PDT 24
Peak memory 250596 kb
Host smart-b4a001ef-37c4-4be2-88ff-d10c3e298268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736007869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1736007869
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3592521223
Short name T262
Test name
Test status
Simulation time 35035473771 ps
CPU time 380.74 seconds
Started Jul 05 06:29:47 PM PDT 24
Finished Jul 05 06:36:08 PM PDT 24
Peak memory 264400 kb
Host smart-be9f25f9-176c-446b-9a68-6ff23f3b15cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592521223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3592521223
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3483169080
Short name T764
Test name
Test status
Simulation time 1139337457 ps
CPU time 14.47 seconds
Started Jul 05 06:29:48 PM PDT 24
Finished Jul 05 06:30:02 PM PDT 24
Peak memory 241644 kb
Host smart-32dd5b40-6c0a-4972-a216-07b04821800c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483169080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3483169080
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2677531689
Short name T510
Test name
Test status
Simulation time 2854519736 ps
CPU time 24.04 seconds
Started Jul 05 06:29:48 PM PDT 24
Finished Jul 05 06:30:12 PM PDT 24
Peak memory 242124 kb
Host smart-9d7af528-6928-4753-a7d3-922a58596aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677531689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2677531689
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.445833610
Short name T705
Test name
Test status
Simulation time 60976427 ps
CPU time 2.54 seconds
Started Jul 05 06:29:42 PM PDT 24
Finished Jul 05 06:29:45 PM PDT 24
Peak memory 233584 kb
Host smart-42a01c0a-15d3-4f65-960a-e83644a9d812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445833610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.445833610
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2625714270
Short name T595
Test name
Test status
Simulation time 2285713987 ps
CPU time 26.78 seconds
Started Jul 05 06:29:42 PM PDT 24
Finished Jul 05 06:30:09 PM PDT 24
Peak memory 239652 kb
Host smart-afb8bfb1-d0e6-4d0d-98a8-46053c009c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625714270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2625714270
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.40328224
Short name T277
Test name
Test status
Simulation time 373585055 ps
CPU time 2.84 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:44 PM PDT 24
Peak memory 225628 kb
Host smart-380cd83d-40d8-4173-94db-6a5ccd538a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40328224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.40328224
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.192478238
Short name T1020
Test name
Test status
Simulation time 29976227862 ps
CPU time 43.79 seconds
Started Jul 05 06:29:40 PM PDT 24
Finished Jul 05 06:30:24 PM PDT 24
Peak memory 250312 kb
Host smart-dbaa1f84-c23e-4fbc-a063-b627591660d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192478238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.192478238
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2130744620
Short name T396
Test name
Test status
Simulation time 912573943 ps
CPU time 10.45 seconds
Started Jul 05 06:29:46 PM PDT 24
Finished Jul 05 06:29:57 PM PDT 24
Peak memory 223368 kb
Host smart-b050a0c3-4443-4cbb-a43f-5468b75955af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2130744620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2130744620
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.75043656
Short name T876
Test name
Test status
Simulation time 20986804532 ps
CPU time 211.13 seconds
Started Jul 05 06:29:49 PM PDT 24
Finished Jul 05 06:33:21 PM PDT 24
Peak memory 266868 kb
Host smart-4020da29-54d0-4962-87cc-661f01323e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75043656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress
_all.75043656
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3551921000
Short name T471
Test name
Test status
Simulation time 1401629532 ps
CPU time 5.36 seconds
Started Jul 05 06:29:42 PM PDT 24
Finished Jul 05 06:29:48 PM PDT 24
Peak memory 217360 kb
Host smart-ff5ad2e7-ef23-494e-b7fa-48a71ad547fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551921000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3551921000
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2256145640
Short name T672
Test name
Test status
Simulation time 1909315001 ps
CPU time 4.24 seconds
Started Jul 05 06:29:40 PM PDT 24
Finished Jul 05 06:29:45 PM PDT 24
Peak memory 217388 kb
Host smart-dfac1a16-bd95-4367-bcf0-6f55ef47da4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256145640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2256145640
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1438179970
Short name T882
Test name
Test status
Simulation time 869319631 ps
CPU time 0.87 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:42 PM PDT 24
Peak memory 207572 kb
Host smart-a5d047c1-3e15-4493-85a4-fc5a73326b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438179970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1438179970
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.900757245
Short name T409
Test name
Test status
Simulation time 45863049 ps
CPU time 0.73 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:42 PM PDT 24
Peak memory 207016 kb
Host smart-8dbf6a92-625b-443e-b8b6-116d5371846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900757245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.900757245
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2143816703
Short name T221
Test name
Test status
Simulation time 8597411959 ps
CPU time 11.44 seconds
Started Jul 05 06:29:41 PM PDT 24
Finished Jul 05 06:29:53 PM PDT 24
Peak memory 233844 kb
Host smart-d14a91c9-936e-4248-969b-741708db9a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143816703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2143816703
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1083605080
Short name T727
Test name
Test status
Simulation time 23488132 ps
CPU time 0.73 seconds
Started Jul 05 06:29:55 PM PDT 24
Finished Jul 05 06:29:56 PM PDT 24
Peak memory 206312 kb
Host smart-17e7b479-57c0-4c8e-9afa-0adbb323b2bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083605080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1083605080
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3699320342
Short name T971
Test name
Test status
Simulation time 126105615 ps
CPU time 2.81 seconds
Started Jul 05 06:29:48 PM PDT 24
Finished Jul 05 06:29:51 PM PDT 24
Peak memory 225656 kb
Host smart-2f0fa947-8c69-4fc2-b65a-f509d0409db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699320342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3699320342
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2393482197
Short name T572
Test name
Test status
Simulation time 188394281 ps
CPU time 0.78 seconds
Started Jul 05 06:29:48 PM PDT 24
Finished Jul 05 06:29:49 PM PDT 24
Peak memory 207532 kb
Host smart-34393db3-ba22-44f2-a69b-d5b8169f66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393482197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2393482197
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3433795773
Short name T645
Test name
Test status
Simulation time 915027049 ps
CPU time 12.16 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:30:10 PM PDT 24
Peak memory 242016 kb
Host smart-26d86297-d13e-44d1-9c1c-4c7bba7370da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433795773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3433795773
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1711323603
Short name T272
Test name
Test status
Simulation time 15524607754 ps
CPU time 109.14 seconds
Started Jul 05 06:29:58 PM PDT 24
Finished Jul 05 06:31:47 PM PDT 24
Peak memory 271768 kb
Host smart-045df936-59c5-420a-9549-e80e2c26968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711323603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1711323603
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2008696662
Short name T298
Test name
Test status
Simulation time 69007891249 ps
CPU time 46.93 seconds
Started Jul 05 06:29:58 PM PDT 24
Finished Jul 05 06:30:45 PM PDT 24
Peak memory 250344 kb
Host smart-e178d9b4-d43c-46e9-9062-52e398374318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008696662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2008696662
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1880763609
Short name T580
Test name
Test status
Simulation time 38530958 ps
CPU time 0.76 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:29:58 PM PDT 24
Peak memory 216912 kb
Host smart-24aa6f48-2287-40cd-b198-ab64caaee399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880763609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1880763609
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1419125767
Short name T260
Test name
Test status
Simulation time 4784983748 ps
CPU time 20.06 seconds
Started Jul 05 06:29:50 PM PDT 24
Finished Jul 05 06:30:11 PM PDT 24
Peak memory 233888 kb
Host smart-3524d97a-5cd0-4849-82a2-cecae4faa74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419125767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1419125767
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1034786732
Short name T254
Test name
Test status
Simulation time 6196939958 ps
CPU time 37.98 seconds
Started Jul 05 06:29:48 PM PDT 24
Finished Jul 05 06:30:27 PM PDT 24
Peak memory 225732 kb
Host smart-2ef01d46-0a4b-4984-986e-a1230b841f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034786732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1034786732
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.597349419
Short name T251
Test name
Test status
Simulation time 442289503 ps
CPU time 3.45 seconds
Started Jul 05 06:29:48 PM PDT 24
Finished Jul 05 06:29:52 PM PDT 24
Peak memory 225592 kb
Host smart-1dc612c9-726e-430f-8bfd-a440fed1636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597349419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.597349419
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3736944596
Short name T895
Test name
Test status
Simulation time 62814112535 ps
CPU time 13.32 seconds
Started Jul 05 06:29:50 PM PDT 24
Finished Jul 05 06:30:03 PM PDT 24
Peak memory 225672 kb
Host smart-f6d1b529-9be4-4585-babe-a21b22ae0708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736944596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3736944596
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.33762906
Short name T858
Test name
Test status
Simulation time 1517787569 ps
CPU time 9.11 seconds
Started Jul 05 06:29:56 PM PDT 24
Finished Jul 05 06:30:05 PM PDT 24
Peak memory 221408 kb
Host smart-14ea0d35-1dfb-42cd-8a6e-d679e59a2e9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=33762906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direc
t.33762906
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3597442704
Short name T984
Test name
Test status
Simulation time 65566161476 ps
CPU time 342.61 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:35:40 PM PDT 24
Peak memory 283268 kb
Host smart-692f0425-c918-4d4c-a0f1-752967f331c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597442704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3597442704
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3574661424
Short name T912
Test name
Test status
Simulation time 1923429918 ps
CPU time 25.61 seconds
Started Jul 05 06:29:51 PM PDT 24
Finished Jul 05 06:30:17 PM PDT 24
Peak memory 217408 kb
Host smart-daf6cda3-c5a1-4455-a084-76f501033f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574661424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3574661424
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3659680399
Short name T561
Test name
Test status
Simulation time 2961639960 ps
CPU time 4.87 seconds
Started Jul 05 06:29:50 PM PDT 24
Finished Jul 05 06:29:55 PM PDT 24
Peak memory 217472 kb
Host smart-20941bca-4c7d-406e-bb7a-eddc414635f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659680399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3659680399
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1272493362
Short name T483
Test name
Test status
Simulation time 235919622 ps
CPU time 2.4 seconds
Started Jul 05 06:29:48 PM PDT 24
Finished Jul 05 06:29:50 PM PDT 24
Peak memory 217384 kb
Host smart-6770bd4e-5a0c-4c09-bed0-f58fcccf53d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272493362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1272493362
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3541455400
Short name T829
Test name
Test status
Simulation time 396660259 ps
CPU time 0.83 seconds
Started Jul 05 06:29:49 PM PDT 24
Finished Jul 05 06:29:50 PM PDT 24
Peak memory 207012 kb
Host smart-dc6681f5-925d-4be0-abf2-f6d21b69a5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541455400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3541455400
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3599269480
Short name T946
Test name
Test status
Simulation time 147290779 ps
CPU time 2.33 seconds
Started Jul 05 06:29:47 PM PDT 24
Finished Jul 05 06:29:50 PM PDT 24
Peak memory 225308 kb
Host smart-f0b87aed-66ff-4106-b879-33fcbb213bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599269480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3599269480
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2399714364
Short name T405
Test name
Test status
Simulation time 85736027 ps
CPU time 0.69 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:29:58 PM PDT 24
Peak memory 205788 kb
Host smart-bd3080d0-3c29-42bb-8f2e-866b8358dfaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399714364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2399714364
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.254503417
Short name T256
Test name
Test status
Simulation time 734316591 ps
CPU time 4.2 seconds
Started Jul 05 06:29:54 PM PDT 24
Finished Jul 05 06:29:58 PM PDT 24
Peak memory 225584 kb
Host smart-5a0f986e-4e88-4bf1-afd1-6e3c1a6cf8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254503417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.254503417
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.837882565
Short name T903
Test name
Test status
Simulation time 27058503 ps
CPU time 0.82 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:29:58 PM PDT 24
Peak memory 207516 kb
Host smart-08d32360-0668-4cdf-b900-b9e3fd4382b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837882565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.837882565
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.525483344
Short name T269
Test name
Test status
Simulation time 160827047856 ps
CPU time 301.71 seconds
Started Jul 05 06:29:56 PM PDT 24
Finished Jul 05 06:34:58 PM PDT 24
Peak memory 257820 kb
Host smart-857c5229-ae4b-49c3-896b-f629d139603e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525483344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.525483344
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3294053300
Short name T274
Test name
Test status
Simulation time 74658493255 ps
CPU time 734.18 seconds
Started Jul 05 06:29:56 PM PDT 24
Finished Jul 05 06:42:11 PM PDT 24
Peak memory 274972 kb
Host smart-6546b6ed-22e6-44a8-a400-9447217a42dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294053300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3294053300
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3623184784
Short name T292
Test name
Test status
Simulation time 3144322282 ps
CPU time 9.87 seconds
Started Jul 05 06:29:54 PM PDT 24
Finished Jul 05 06:30:04 PM PDT 24
Peak memory 225708 kb
Host smart-a9538647-007f-4bb6-820d-c931dcf32d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623184784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3623184784
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.144108365
Short name T618
Test name
Test status
Simulation time 220989695 ps
CPU time 0.98 seconds
Started Jul 05 06:29:55 PM PDT 24
Finished Jul 05 06:29:56 PM PDT 24
Peak memory 217172 kb
Host smart-3eb87de2-95af-47fb-bc76-a784cb1afdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144108365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.144108365
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3503931853
Short name T794
Test name
Test status
Simulation time 104190735 ps
CPU time 2.19 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:30:00 PM PDT 24
Peak memory 233512 kb
Host smart-dc4120cd-0740-4396-adaa-a032955b0e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503931853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3503931853
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1813855470
Short name T961
Test name
Test status
Simulation time 8312400621 ps
CPU time 34.87 seconds
Started Jul 05 06:29:54 PM PDT 24
Finished Jul 05 06:30:29 PM PDT 24
Peak memory 225692 kb
Host smart-cad3dc82-057c-46f4-b6c6-162c0574ebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813855470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1813855470
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1963896994
Short name T216
Test name
Test status
Simulation time 292169376 ps
CPU time 5.6 seconds
Started Jul 05 06:29:54 PM PDT 24
Finished Jul 05 06:29:59 PM PDT 24
Peak memory 233760 kb
Host smart-8c38cfe4-7cd9-4b95-9431-0d316d54c620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963896994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1963896994
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3962378298
Short name T71
Test name
Test status
Simulation time 1798275037 ps
CPU time 4.62 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:30:02 PM PDT 24
Peak memory 233712 kb
Host smart-d5ef3ee4-6eb9-4d30-971a-b9c4a2581728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962378298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3962378298
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3414578766
Short name T931
Test name
Test status
Simulation time 348571468 ps
CPU time 3.94 seconds
Started Jul 05 06:29:55 PM PDT 24
Finished Jul 05 06:29:59 PM PDT 24
Peak memory 223668 kb
Host smart-a2d427ca-aa0c-4043-af21-a93904b3acac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3414578766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3414578766
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2401279333
Short name T18
Test name
Test status
Simulation time 8452933826 ps
CPU time 56.69 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:30:54 PM PDT 24
Peak memory 250428 kb
Host smart-985c8e40-d36a-4d8f-a8c7-ae8ba1c28530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401279333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2401279333
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.37894612
Short name T621
Test name
Test status
Simulation time 7650779043 ps
CPU time 12.83 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:30:11 PM PDT 24
Peak memory 217456 kb
Host smart-83eb411c-b16c-4614-8c30-e9eefc715980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37894612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.37894612
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1841440907
Short name T965
Test name
Test status
Simulation time 7834143090 ps
CPU time 8.45 seconds
Started Jul 05 06:29:56 PM PDT 24
Finished Jul 05 06:30:05 PM PDT 24
Peak memory 217512 kb
Host smart-c0a34763-d1fb-44d3-85de-a190c2e8625c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841440907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1841440907
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2249146815
Short name T347
Test name
Test status
Simulation time 82096580 ps
CPU time 2.34 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:29:59 PM PDT 24
Peak memory 217380 kb
Host smart-8a2234b8-fecc-40a7-9720-d2cafebd157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249146815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2249146815
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1778454927
Short name T1009
Test name
Test status
Simulation time 606748849 ps
CPU time 0.92 seconds
Started Jul 05 06:29:55 PM PDT 24
Finished Jul 05 06:29:56 PM PDT 24
Peak memory 206988 kb
Host smart-52c811d6-0e49-4344-96cb-54dc2b0a206b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778454927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1778454927
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.376609792
Short name T588
Test name
Test status
Simulation time 10891484032 ps
CPU time 10.02 seconds
Started Jul 05 06:29:57 PM PDT 24
Finished Jul 05 06:30:08 PM PDT 24
Peak memory 233976 kb
Host smart-e0f98bcc-fb9f-4401-858a-4f611fedbb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376609792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.376609792
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.217528501
Short name T404
Test name
Test status
Simulation time 11395214 ps
CPU time 0.72 seconds
Started Jul 05 06:30:12 PM PDT 24
Finished Jul 05 06:30:13 PM PDT 24
Peak memory 205808 kb
Host smart-4a9f2166-1ba7-486e-b768-0ed94dbe1a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217528501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.217528501
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3267494236
Short name T1025
Test name
Test status
Simulation time 842095761 ps
CPU time 3.21 seconds
Started Jul 05 06:30:02 PM PDT 24
Finished Jul 05 06:30:06 PM PDT 24
Peak memory 225572 kb
Host smart-50980359-fb75-4c09-b239-37dfbee866de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267494236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3267494236
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2363116212
Short name T389
Test name
Test status
Simulation time 49759821 ps
CPU time 0.83 seconds
Started Jul 05 06:30:03 PM PDT 24
Finished Jul 05 06:30:05 PM PDT 24
Peak memory 207568 kb
Host smart-2ff5696b-ad71-4bad-9b53-7463696fd28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363116212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2363116212
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.665431312
Short name T646
Test name
Test status
Simulation time 28616494399 ps
CPU time 246.04 seconds
Started Jul 05 06:30:05 PM PDT 24
Finished Jul 05 06:34:11 PM PDT 24
Peak memory 266596 kb
Host smart-7f02f7e7-faeb-43d1-a28e-649c83b9460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665431312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.665431312
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3992172355
Short name T1013
Test name
Test status
Simulation time 24582593722 ps
CPU time 155.58 seconds
Started Jul 05 06:30:02 PM PDT 24
Finished Jul 05 06:32:38 PM PDT 24
Peak memory 257964 kb
Host smart-a4202d3a-f015-4703-a6ae-c93c5527a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992172355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3992172355
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.10221536
Short name T692
Test name
Test status
Simulation time 15627262096 ps
CPU time 70.98 seconds
Started Jul 05 06:30:03 PM PDT 24
Finished Jul 05 06:31:15 PM PDT 24
Peak memory 265796 kb
Host smart-eb0c0d8c-59fc-47e3-9696-f7867822bd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10221536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.10221536
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3978674785
Short name T569
Test name
Test status
Simulation time 231465455 ps
CPU time 3.31 seconds
Started Jul 05 06:30:03 PM PDT 24
Finished Jul 05 06:30:08 PM PDT 24
Peak memory 233788 kb
Host smart-4b9cdd6d-8530-4eb8-840c-5918c67e2032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978674785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3978674785
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4194811543
Short name T280
Test name
Test status
Simulation time 2696299349 ps
CPU time 35.07 seconds
Started Jul 05 06:30:04 PM PDT 24
Finished Jul 05 06:30:39 PM PDT 24
Peak memory 250344 kb
Host smart-b8d59552-6d21-45b5-b736-1c181fdba332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194811543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4194811543
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4291094141
Short name T762
Test name
Test status
Simulation time 1049103412 ps
CPU time 10.62 seconds
Started Jul 05 06:30:05 PM PDT 24
Finished Jul 05 06:30:16 PM PDT 24
Peak memory 233740 kb
Host smart-23e4fdd1-5697-4ebf-be6e-0ef6bbc9fed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291094141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4291094141
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3919478480
Short name T887
Test name
Test status
Simulation time 6805897591 ps
CPU time 63.42 seconds
Started Jul 05 06:30:03 PM PDT 24
Finished Jul 05 06:31:06 PM PDT 24
Peak memory 238520 kb
Host smart-5ba03de4-e093-43f2-9ed2-d0b5b11815bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919478480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3919478480
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2339098701
Short name T633
Test name
Test status
Simulation time 6957349172 ps
CPU time 8.06 seconds
Started Jul 05 06:30:01 PM PDT 24
Finished Jul 05 06:30:09 PM PDT 24
Peak memory 233908 kb
Host smart-b6421ef9-7b5b-47ec-b687-239d7ff23442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339098701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2339098701
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2078874905
Short name T397
Test name
Test status
Simulation time 7659881848 ps
CPU time 6.65 seconds
Started Jul 05 06:30:03 PM PDT 24
Finished Jul 05 06:30:10 PM PDT 24
Peak memory 233888 kb
Host smart-8723c937-81f6-482a-b1d3-3d438ee8e563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078874905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2078874905
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.254167790
Short name T364
Test name
Test status
Simulation time 2929405476 ps
CPU time 8.22 seconds
Started Jul 05 06:30:02 PM PDT 24
Finished Jul 05 06:30:10 PM PDT 24
Peak memory 220348 kb
Host smart-4623cb7e-1cbb-48cb-b2cc-00a07bea38d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=254167790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.254167790
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2984466432
Short name T986
Test name
Test status
Simulation time 51008167 ps
CPU time 1.22 seconds
Started Jul 05 06:30:02 PM PDT 24
Finished Jul 05 06:30:04 PM PDT 24
Peak memory 208040 kb
Host smart-7c0fe40a-7d27-46a5-8599-86a915acfcb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984466432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2984466432
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3001200126
Short name T832
Test name
Test status
Simulation time 26159153 ps
CPU time 0.75 seconds
Started Jul 05 06:30:02 PM PDT 24
Finished Jul 05 06:30:03 PM PDT 24
Peak memory 206652 kb
Host smart-dd218758-d832-4ab5-aff0-0b24af88080d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001200126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3001200126
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1406721012
Short name T801
Test name
Test status
Simulation time 34748739 ps
CPU time 0.73 seconds
Started Jul 05 06:31:02 PM PDT 24
Finished Jul 05 06:31:03 PM PDT 24
Peak memory 206652 kb
Host smart-3ac05419-9afc-4e82-af5b-d792b46f71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406721012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1406721012
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3156629566
Short name T639
Test name
Test status
Simulation time 123016959 ps
CPU time 1.02 seconds
Started Jul 05 06:30:03 PM PDT 24
Finished Jul 05 06:30:05 PM PDT 24
Peak memory 208092 kb
Host smart-1bc51633-989c-4e4a-b886-836e8f8dd0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156629566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3156629566
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1513338049
Short name T410
Test name
Test status
Simulation time 415136147 ps
CPU time 1.02 seconds
Started Jul 05 06:30:02 PM PDT 24
Finished Jul 05 06:30:04 PM PDT 24
Peak memory 208028 kb
Host smart-40fcc1a4-9ce9-41dd-ba9c-f8f18ac3c1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513338049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1513338049
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4151265165
Short name T530
Test name
Test status
Simulation time 8160964051 ps
CPU time 10.52 seconds
Started Jul 05 06:30:02 PM PDT 24
Finished Jul 05 06:30:13 PM PDT 24
Peak memory 233888 kb
Host smart-8e7c2975-cb48-406d-82a9-e61a4e765fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151265165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4151265165
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2697177437
Short name T664
Test name
Test status
Simulation time 29338949 ps
CPU time 0.76 seconds
Started Jul 05 06:30:29 PM PDT 24
Finished Jul 05 06:30:30 PM PDT 24
Peak memory 206396 kb
Host smart-45e991bc-1aa4-4018-b098-d1647e9879bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697177437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2697177437
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2169710280
Short name T176
Test name
Test status
Simulation time 2272997155 ps
CPU time 10.38 seconds
Started Jul 05 06:30:10 PM PDT 24
Finished Jul 05 06:30:21 PM PDT 24
Peak memory 225652 kb
Host smart-d00c03fb-ef23-4b19-8991-eedfd6bc387c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169710280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2169710280
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2579253936
Short name T417
Test name
Test status
Simulation time 26339489 ps
CPU time 0.79 seconds
Started Jul 05 06:30:09 PM PDT 24
Finished Jul 05 06:30:10 PM PDT 24
Peak memory 207544 kb
Host smart-1699d01f-a251-4e83-b2dc-777959440db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579253936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2579253936
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2765058682
Short name T229
Test name
Test status
Simulation time 100564204735 ps
CPU time 215.87 seconds
Started Jul 05 06:30:19 PM PDT 24
Finished Jul 05 06:33:56 PM PDT 24
Peak memory 266308 kb
Host smart-17efdc32-7a9a-4fde-9aa7-0d8391fd0dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765058682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2765058682
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3413760086
Short name T685
Test name
Test status
Simulation time 611550991471 ps
CPU time 217.65 seconds
Started Jul 05 06:30:20 PM PDT 24
Finished Jul 05 06:33:58 PM PDT 24
Peak memory 254284 kb
Host smart-dc8154da-78d8-4eaa-b993-0c180cdd3363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413760086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3413760086
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4165926928
Short name T138
Test name
Test status
Simulation time 49353654889 ps
CPU time 560.63 seconds
Started Jul 05 06:30:29 PM PDT 24
Finished Jul 05 06:39:50 PM PDT 24
Peak memory 274336 kb
Host smart-f783bea2-3355-486f-98b9-847d1046b940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165926928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4165926928
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3592042648
Short name T976
Test name
Test status
Simulation time 3525468358 ps
CPU time 14.48 seconds
Started Jul 05 06:30:09 PM PDT 24
Finished Jul 05 06:30:24 PM PDT 24
Peak memory 252680 kb
Host smart-46679b58-fa43-4297-887d-7c68c82cdb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592042648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3592042648
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3735936725
Short name T655
Test name
Test status
Simulation time 37884313588 ps
CPU time 277.22 seconds
Started Jul 05 06:30:09 PM PDT 24
Finished Jul 05 06:34:46 PM PDT 24
Peak memory 252636 kb
Host smart-8ffb497f-1120-4641-ab67-2e49adffdc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735936725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3735936725
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4213728627
Short name T513
Test name
Test status
Simulation time 222207811 ps
CPU time 5.84 seconds
Started Jul 05 06:30:12 PM PDT 24
Finished Jul 05 06:30:18 PM PDT 24
Peak memory 225604 kb
Host smart-dec0c499-5ef1-4c42-b006-31fad4675e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213728627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4213728627
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3915442608
Short name T967
Test name
Test status
Simulation time 34915770482 ps
CPU time 55.55 seconds
Started Jul 05 06:30:08 PM PDT 24
Finished Jul 05 06:31:04 PM PDT 24
Peak memory 225712 kb
Host smart-b9ee6f3e-3541-476c-880f-a76440107f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915442608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3915442608
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2438606713
Short name T635
Test name
Test status
Simulation time 14488569928 ps
CPU time 11.59 seconds
Started Jul 05 06:30:09 PM PDT 24
Finished Jul 05 06:30:21 PM PDT 24
Peak memory 233912 kb
Host smart-6062dc14-b056-4b86-8ccd-5fe90780d4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438606713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2438606713
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1331180487
Short name T232
Test name
Test status
Simulation time 296324355 ps
CPU time 3.93 seconds
Started Jul 05 06:30:11 PM PDT 24
Finished Jul 05 06:30:15 PM PDT 24
Peak memory 225620 kb
Host smart-80ec4ea0-c831-42aa-9b58-cc15ab25f0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331180487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1331180487
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2503397491
Short name T335
Test name
Test status
Simulation time 157545692 ps
CPU time 4.22 seconds
Started Jul 05 06:30:20 PM PDT 24
Finished Jul 05 06:30:25 PM PDT 24
Peak memory 224224 kb
Host smart-c196ba4a-04d4-47fc-ac6a-ea0993b8389a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503397491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2503397491
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1612782322
Short name T735
Test name
Test status
Simulation time 12140639851 ps
CPU time 103.13 seconds
Started Jul 05 06:30:29 PM PDT 24
Finished Jul 05 06:32:12 PM PDT 24
Peak memory 253504 kb
Host smart-03b04882-1990-4ca2-86af-62fa2d887cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612782322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1612782322
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.758116019
Short name T72
Test name
Test status
Simulation time 2770886780 ps
CPU time 25.08 seconds
Started Jul 05 06:30:11 PM PDT 24
Finished Jul 05 06:30:36 PM PDT 24
Peak memory 217680 kb
Host smart-dbc8126c-46e9-42f0-be84-285f3687d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758116019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.758116019
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2688920050
Short name T551
Test name
Test status
Simulation time 60637639 ps
CPU time 0.71 seconds
Started Jul 05 06:30:11 PM PDT 24
Finished Jul 05 06:30:12 PM PDT 24
Peak memory 206668 kb
Host smart-70ff287e-7a11-4a40-93ac-35607d4c096e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688920050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2688920050
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4089701016
Short name T312
Test name
Test status
Simulation time 740707901 ps
CPU time 2.09 seconds
Started Jul 05 06:30:10 PM PDT 24
Finished Jul 05 06:30:13 PM PDT 24
Peak memory 217408 kb
Host smart-c8390829-361c-42e8-963e-b27b940263a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089701016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4089701016
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2636258948
Short name T780
Test name
Test status
Simulation time 93199049 ps
CPU time 0.82 seconds
Started Jul 05 06:30:10 PM PDT 24
Finished Jul 05 06:30:11 PM PDT 24
Peak memory 207340 kb
Host smart-d9b1ffd6-f0d5-4954-a59d-017f8e415fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636258948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2636258948
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.820443680
Short name T556
Test name
Test status
Simulation time 5099628358 ps
CPU time 20.67 seconds
Started Jul 05 06:30:10 PM PDT 24
Finished Jul 05 06:30:31 PM PDT 24
Peak memory 233952 kb
Host smart-1fa6da5d-2cb4-44f4-85e1-f7c0c73030b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820443680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.820443680
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2811972069
Short name T525
Test name
Test status
Simulation time 48966353 ps
CPU time 0.72 seconds
Started Jul 05 06:30:27 PM PDT 24
Finished Jul 05 06:30:28 PM PDT 24
Peak memory 205816 kb
Host smart-38760684-1db4-4ae8-8509-6320e1c17e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811972069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2811972069
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1724739980
Short name T806
Test name
Test status
Simulation time 144854889 ps
CPU time 2.25 seconds
Started Jul 05 06:30:16 PM PDT 24
Finished Jul 05 06:30:19 PM PDT 24
Peak memory 224200 kb
Host smart-5d020b94-0b4c-4162-86d5-f43311a666c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724739980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1724739980
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2739049500
Short name T368
Test name
Test status
Simulation time 32701288 ps
CPU time 0.82 seconds
Started Jul 05 06:30:24 PM PDT 24
Finished Jul 05 06:30:25 PM PDT 24
Peak memory 207536 kb
Host smart-2b67c146-77c6-4f25-8cf0-8e039ca838fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739049500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2739049500
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3223450858
Short name T189
Test name
Test status
Simulation time 14041605592 ps
CPU time 137.22 seconds
Started Jul 05 06:30:20 PM PDT 24
Finished Jul 05 06:32:38 PM PDT 24
Peak memory 258464 kb
Host smart-343b7433-ae3f-49d2-87ff-b810a734bd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223450858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3223450858
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.188959093
Short name T810
Test name
Test status
Simulation time 148309222228 ps
CPU time 320.97 seconds
Started Jul 05 06:30:26 PM PDT 24
Finished Jul 05 06:35:48 PM PDT 24
Peak memory 271560 kb
Host smart-492b7564-2ee2-48bf-a61f-3a1e2eda158a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188959093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.188959093
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3591140909
Short name T211
Test name
Test status
Simulation time 1051893130 ps
CPU time 14.1 seconds
Started Jul 05 06:30:28 PM PDT 24
Finished Jul 05 06:30:43 PM PDT 24
Peak memory 239680 kb
Host smart-31deeec9-519c-4b89-b251-4bc0ddeffe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591140909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3591140909
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1868064218
Short name T708
Test name
Test status
Simulation time 440078134 ps
CPU time 10.47 seconds
Started Jul 05 06:30:16 PM PDT 24
Finished Jul 05 06:30:26 PM PDT 24
Peak memory 233748 kb
Host smart-05e77dc7-206d-4540-905a-66e5f4593154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868064218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1868064218
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3202218592
Short name T924
Test name
Test status
Simulation time 32809618462 ps
CPU time 241 seconds
Started Jul 05 06:30:16 PM PDT 24
Finished Jul 05 06:34:18 PM PDT 24
Peak memory 258504 kb
Host smart-c52e1e3a-8edf-4d7f-825c-145661157507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202218592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3202218592
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1212546827
Short name T802
Test name
Test status
Simulation time 1586354010 ps
CPU time 7.08 seconds
Started Jul 05 06:30:18 PM PDT 24
Finished Jul 05 06:30:26 PM PDT 24
Peak memory 233768 kb
Host smart-8aff0c3d-cb0d-4e1a-9bd8-8a9d1e18e9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212546827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1212546827
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2361646455
Short name T905
Test name
Test status
Simulation time 15285775463 ps
CPU time 106.26 seconds
Started Jul 05 06:30:20 PM PDT 24
Finished Jul 05 06:32:06 PM PDT 24
Peak memory 233896 kb
Host smart-5f1342d5-6c17-4cd1-9788-a2ed0f33bbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361646455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2361646455
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.420180079
Short name T696
Test name
Test status
Simulation time 74606508 ps
CPU time 2.1 seconds
Started Jul 05 06:30:21 PM PDT 24
Finished Jul 05 06:30:24 PM PDT 24
Peak memory 225052 kb
Host smart-25570c29-eb28-4ba3-9bb0-ace399d0889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420180079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.420180079
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1919404569
Short name T975
Test name
Test status
Simulation time 1785501195 ps
CPU time 4.95 seconds
Started Jul 05 06:30:19 PM PDT 24
Finished Jul 05 06:30:24 PM PDT 24
Peak memory 225616 kb
Host smart-29ed2410-8f59-4a42-bae1-2542811d7d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919404569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1919404569
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1134853133
Short name T745
Test name
Test status
Simulation time 3425955051 ps
CPU time 5.81 seconds
Started Jul 05 06:30:21 PM PDT 24
Finished Jul 05 06:30:27 PM PDT 24
Peak memory 220860 kb
Host smart-5bc4749d-1900-4809-98c1-079e69e2ec02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1134853133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1134853133
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3586996219
Short name T948
Test name
Test status
Simulation time 1109819099 ps
CPU time 30.03 seconds
Started Jul 05 06:30:27 PM PDT 24
Finished Jul 05 06:30:58 PM PDT 24
Peak memory 242000 kb
Host smart-fc8ad11c-d70a-4214-b3f0-c4c470d06e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586996219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3586996219
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4156107244
Short name T597
Test name
Test status
Simulation time 554000457 ps
CPU time 5.66 seconds
Started Jul 05 06:30:19 PM PDT 24
Finished Jul 05 06:30:25 PM PDT 24
Peak memory 217420 kb
Host smart-d4d163f3-899d-4762-993a-8a7a795e29a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156107244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4156107244
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2453076026
Short name T936
Test name
Test status
Simulation time 434130310 ps
CPU time 2.75 seconds
Started Jul 05 06:30:18 PM PDT 24
Finished Jul 05 06:30:21 PM PDT 24
Peak memory 217312 kb
Host smart-8d61095a-fde7-451b-a690-a2b37a0240d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453076026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2453076026
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.692113650
Short name T313
Test name
Test status
Simulation time 246144566 ps
CPU time 1.1 seconds
Started Jul 05 06:30:23 PM PDT 24
Finished Jul 05 06:30:25 PM PDT 24
Peak memory 208120 kb
Host smart-8b6c896b-e329-46e3-b29c-d500069e7a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692113650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.692113650
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.115627203
Short name T424
Test name
Test status
Simulation time 69857669 ps
CPU time 0.73 seconds
Started Jul 05 06:30:17 PM PDT 24
Finished Jul 05 06:30:19 PM PDT 24
Peak memory 206992 kb
Host smart-e1da9f03-c665-4429-8a0b-84d500204ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115627203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.115627203
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2651098073
Short name T799
Test name
Test status
Simulation time 1626014764 ps
CPU time 6.14 seconds
Started Jul 05 06:30:20 PM PDT 24
Finished Jul 05 06:30:26 PM PDT 24
Peak memory 241916 kb
Host smart-6ce9f987-3d1f-4bf5-9851-8f868c00e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651098073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2651098073
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3488985596
Short name T350
Test name
Test status
Simulation time 46553214 ps
CPU time 0.72 seconds
Started Jul 05 06:30:31 PM PDT 24
Finished Jul 05 06:30:32 PM PDT 24
Peak memory 205820 kb
Host smart-b67283a6-72b4-48fd-b61e-210a3bf61b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488985596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3488985596
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3935324508
Short name T835
Test name
Test status
Simulation time 565857002 ps
CPU time 6.03 seconds
Started Jul 05 06:30:26 PM PDT 24
Finished Jul 05 06:30:32 PM PDT 24
Peak memory 233740 kb
Host smart-1258876c-c5ed-431a-a443-dab98cd67a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935324508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3935324508
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3747914973
Short name T750
Test name
Test status
Simulation time 34954570 ps
CPU time 0.75 seconds
Started Jul 05 06:30:26 PM PDT 24
Finished Jul 05 06:30:27 PM PDT 24
Peak memory 207536 kb
Host smart-5041aded-7665-444e-9d4a-2c3087093360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747914973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3747914973
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.406812863
Short name T248
Test name
Test status
Simulation time 3670330448 ps
CPU time 49.69 seconds
Started Jul 05 06:30:30 PM PDT 24
Finished Jul 05 06:31:20 PM PDT 24
Peak memory 251168 kb
Host smart-a9dcbdca-cf49-4bb1-a641-0e49b56fef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406812863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.406812863
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1412270804
Short name T886
Test name
Test status
Simulation time 12117682745 ps
CPU time 60.67 seconds
Started Jul 05 06:30:30 PM PDT 24
Finished Jul 05 06:31:31 PM PDT 24
Peak memory 260496 kb
Host smart-f3a538a8-f71c-43fa-aaea-2b5694c0a3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412270804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1412270804
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3415865086
Short name T182
Test name
Test status
Simulation time 22486504591 ps
CPU time 129.98 seconds
Started Jul 05 06:30:29 PM PDT 24
Finished Jul 05 06:32:39 PM PDT 24
Peak memory 266848 kb
Host smart-6ab1f503-2817-471a-a98d-56b216a4b43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415865086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3415865086
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2305592794
Short name T286
Test name
Test status
Simulation time 101123534456 ps
CPU time 171.49 seconds
Started Jul 05 06:30:28 PM PDT 24
Finished Jul 05 06:33:20 PM PDT 24
Peak memory 251296 kb
Host smart-8daad667-b069-4664-a80b-8381c0145bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305592794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2305592794
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3198190660
Short name T113
Test name
Test status
Simulation time 21198628699 ps
CPU time 14.11 seconds
Started Jul 05 06:30:25 PM PDT 24
Finished Jul 05 06:30:39 PM PDT 24
Peak memory 233936 kb
Host smart-30183b65-31be-4a4e-87bc-222069246e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198190660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3198190660
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.822186089
Short name T856
Test name
Test status
Simulation time 1260724512 ps
CPU time 17.97 seconds
Started Jul 05 06:30:28 PM PDT 24
Finished Jul 05 06:30:46 PM PDT 24
Peak memory 238920 kb
Host smart-23bfd1bc-2fcf-4f67-888b-506b5d756587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822186089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.822186089
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2097400770
Short name T36
Test name
Test status
Simulation time 1540338044 ps
CPU time 7.88 seconds
Started Jul 05 06:30:27 PM PDT 24
Finished Jul 05 06:30:36 PM PDT 24
Peak memory 233780 kb
Host smart-2f0ec760-3f91-40a9-92c7-be64a47468aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097400770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2097400770
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.424020525
Short name T197
Test name
Test status
Simulation time 636419235 ps
CPU time 3.82 seconds
Started Jul 05 06:30:28 PM PDT 24
Finished Jul 05 06:30:32 PM PDT 24
Peak memory 225608 kb
Host smart-493ee30a-aaf2-449e-b0ac-86e428cf4c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424020525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.424020525
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2663828782
Short name T732
Test name
Test status
Simulation time 2061344023 ps
CPU time 20.54 seconds
Started Jul 05 06:30:32 PM PDT 24
Finished Jul 05 06:30:53 PM PDT 24
Peak memory 221676 kb
Host smart-f1da97db-9b30-43e4-9ac7-3e3ab6c8cef0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2663828782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2663828782
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2796505615
Short name T285
Test name
Test status
Simulation time 181775212633 ps
CPU time 225.52 seconds
Started Jul 05 06:30:23 PM PDT 24
Finished Jul 05 06:34:09 PM PDT 24
Peak memory 250360 kb
Host smart-198c3e63-8dbb-4b92-a2fc-3421a79ef17f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796505615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2796505615
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3560253275
Short name T309
Test name
Test status
Simulation time 14868167157 ps
CPU time 28.41 seconds
Started Jul 05 06:30:26 PM PDT 24
Finished Jul 05 06:30:55 PM PDT 24
Peak memory 217800 kb
Host smart-71c03973-b43d-4689-a2e7-90a547e86fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560253275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3560253275
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1314616923
Short name T381
Test name
Test status
Simulation time 345139080 ps
CPU time 1.64 seconds
Started Jul 05 06:30:28 PM PDT 24
Finished Jul 05 06:30:30 PM PDT 24
Peak memory 208848 kb
Host smart-6665c4b8-37f8-4ff7-bc51-2ea4cfa1b8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314616923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1314616923
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.347266039
Short name T547
Test name
Test status
Simulation time 96375513 ps
CPU time 2.15 seconds
Started Jul 05 06:30:28 PM PDT 24
Finished Jul 05 06:30:31 PM PDT 24
Peak memory 217412 kb
Host smart-4e6b39e2-ec25-4719-b956-8ceab2946f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347266039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.347266039
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2871528570
Short name T550
Test name
Test status
Simulation time 13354990 ps
CPU time 0.67 seconds
Started Jul 05 06:30:26 PM PDT 24
Finished Jul 05 06:30:28 PM PDT 24
Peak memory 206584 kb
Host smart-ebdec17e-634d-4191-a51e-f8f89e416b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871528570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2871528570
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4022255186
Short name T468
Test name
Test status
Simulation time 115125475 ps
CPU time 2.7 seconds
Started Jul 05 06:30:26 PM PDT 24
Finished Jul 05 06:30:29 PM PDT 24
Peak memory 233788 kb
Host smart-96d28bb0-d6c5-44cd-9241-d35aa4831da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022255186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4022255186
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.910640303
Short name T629
Test name
Test status
Simulation time 29132760 ps
CPU time 0.75 seconds
Started Jul 05 06:25:50 PM PDT 24
Finished Jul 05 06:25:51 PM PDT 24
Peak memory 205816 kb
Host smart-570f2a3b-912c-4b81-bfff-827c254c4bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910640303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.910640303
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.761289382
Short name T529
Test name
Test status
Simulation time 376347567 ps
CPU time 5.64 seconds
Started Jul 05 06:25:52 PM PDT 24
Finished Jul 05 06:25:58 PM PDT 24
Peak memory 233752 kb
Host smart-1ec5dc01-c6de-4894-8d17-f535521a8a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761289382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.761289382
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1233038881
Short name T772
Test name
Test status
Simulation time 57928732 ps
CPU time 0.77 seconds
Started Jul 05 06:25:48 PM PDT 24
Finished Jul 05 06:25:49 PM PDT 24
Peak memory 207528 kb
Host smart-d912f38e-68f7-4fe7-9633-745892e8e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233038881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1233038881
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1909884496
Short name T175
Test name
Test status
Simulation time 260686945 ps
CPU time 6.54 seconds
Started Jul 05 06:25:50 PM PDT 24
Finished Jul 05 06:25:57 PM PDT 24
Peak memory 225576 kb
Host smart-ce056748-8f16-48ba-8b13-b8f74f080e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909884496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1909884496
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4012923065
Short name T284
Test name
Test status
Simulation time 79971265587 ps
CPU time 252.9 seconds
Started Jul 05 06:25:51 PM PDT 24
Finished Jul 05 06:30:04 PM PDT 24
Peak memory 266528 kb
Host smart-2de7e0a9-aa32-4e61-886d-7006b74ced14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012923065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4012923065
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1409854831
Short name T199
Test name
Test status
Simulation time 24134128552 ps
CPU time 104.78 seconds
Started Jul 05 06:25:51 PM PDT 24
Finished Jul 05 06:27:36 PM PDT 24
Peak memory 251116 kb
Host smart-0514d24d-195f-43d1-9989-5e3ec398b75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409854831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1409854831
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2556463584
Short name T665
Test name
Test status
Simulation time 940841833 ps
CPU time 24.54 seconds
Started Jul 05 06:25:50 PM PDT 24
Finished Jul 05 06:26:15 PM PDT 24
Peak memory 233816 kb
Host smart-960aeed7-e998-4e8d-82be-19c1d0190506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556463584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2556463584
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.367188689
Short name T899
Test name
Test status
Simulation time 21244642593 ps
CPU time 77.31 seconds
Started Jul 05 06:25:50 PM PDT 24
Finished Jul 05 06:27:08 PM PDT 24
Peak memory 253008 kb
Host smart-01116212-331b-4e22-8c06-9c93e1dd3b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367188689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
367188689
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3782496051
Short name T430
Test name
Test status
Simulation time 14319697614 ps
CPU time 21.95 seconds
Started Jul 05 06:25:48 PM PDT 24
Finished Jul 05 06:26:11 PM PDT 24
Peak memory 233940 kb
Host smart-b5c2b310-f7d9-44a3-9e55-1e23a41a28c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782496051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3782496051
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1179243025
Short name T916
Test name
Test status
Simulation time 120357445 ps
CPU time 2.68 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:53 PM PDT 24
Peak memory 233532 kb
Host smart-01dfd0eb-6cb5-4630-9f6b-c96c533b2dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179243025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1179243025
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1989265434
Short name T790
Test name
Test status
Simulation time 15331007 ps
CPU time 1.07 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:50 PM PDT 24
Peak memory 217684 kb
Host smart-b225abf2-ef7e-4e7b-8e24-808ef543ccc2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989265434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1989265434
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4010738023
Short name T918
Test name
Test status
Simulation time 2247541272 ps
CPU time 4.68 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:54 PM PDT 24
Peak memory 242036 kb
Host smart-f5b8e645-bd40-464e-86bb-ce225b31f201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010738023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4010738023
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1724419189
Short name T74
Test name
Test status
Simulation time 3592339880 ps
CPU time 4.49 seconds
Started Jul 05 06:25:51 PM PDT 24
Finished Jul 05 06:25:56 PM PDT 24
Peak memory 233952 kb
Host smart-20446cf4-6286-47b5-9d7b-c9ab578c14bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724419189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1724419189
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1828697198
Short name T771
Test name
Test status
Simulation time 218832519 ps
CPU time 3.87 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:53 PM PDT 24
Peak memory 223680 kb
Host smart-c8210ef7-85ef-46c7-b868-febbbecb41d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828697198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1828697198
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4177666668
Short name T64
Test name
Test status
Simulation time 562643017 ps
CPU time 1.24 seconds
Started Jul 05 06:25:50 PM PDT 24
Finished Jul 05 06:25:52 PM PDT 24
Peak memory 237860 kb
Host smart-2cca6b4a-c2a2-425d-afdc-5b0d4bcc5587
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177666668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4177666668
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1076996464
Short name T20
Test name
Test status
Simulation time 179389830480 ps
CPU time 406.58 seconds
Started Jul 05 06:25:50 PM PDT 24
Finished Jul 05 06:32:37 PM PDT 24
Peak memory 266844 kb
Host smart-79854602-9d4b-4e61-bdff-d420d717ee3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076996464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1076996464
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1226692721
Short name T486
Test name
Test status
Simulation time 870563877 ps
CPU time 7.53 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:58 PM PDT 24
Peak memory 217464 kb
Host smart-ab083617-c560-47b3-b4b5-634a6477f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226692721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1226692721
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.678401756
Short name T981
Test name
Test status
Simulation time 301381969 ps
CPU time 2.21 seconds
Started Jul 05 06:25:48 PM PDT 24
Finished Jul 05 06:25:51 PM PDT 24
Peak memory 217388 kb
Host smart-355303d0-4abd-41ee-b719-603c649ff8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678401756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.678401756
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3959770091
Short name T853
Test name
Test status
Simulation time 178629436 ps
CPU time 0.85 seconds
Started Jul 05 06:25:48 PM PDT 24
Finished Jul 05 06:25:49 PM PDT 24
Peak memory 206908 kb
Host smart-f666ac66-b548-4c09-a543-274bca9f6600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959770091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3959770091
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2545407749
Short name T465
Test name
Test status
Simulation time 2600987181 ps
CPU time 6.37 seconds
Started Jul 05 06:25:48 PM PDT 24
Finished Jul 05 06:25:55 PM PDT 24
Peak memory 233892 kb
Host smart-a0aebe6e-9b5b-4362-893c-7d9f8ea72277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545407749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2545407749
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1130042453
Short name T427
Test name
Test status
Simulation time 41934380 ps
CPU time 0.72 seconds
Started Jul 05 06:30:42 PM PDT 24
Finished Jul 05 06:30:43 PM PDT 24
Peak memory 206732 kb
Host smart-81d946e8-de63-42c2-a00f-134cb4f10b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130042453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1130042453
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1757906071
Short name T240
Test name
Test status
Simulation time 319206756 ps
CPU time 2.1 seconds
Started Jul 05 06:30:36 PM PDT 24
Finished Jul 05 06:30:38 PM PDT 24
Peak memory 225648 kb
Host smart-ce12266d-25e1-4263-adc6-910d3da9d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757906071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1757906071
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1430043477
Short name T361
Test name
Test status
Simulation time 141002568 ps
CPU time 0.76 seconds
Started Jul 05 06:30:23 PM PDT 24
Finished Jul 05 06:30:24 PM PDT 24
Peak memory 207552 kb
Host smart-02e588bc-4449-4b10-bdb8-ec7f1e16d761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430043477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1430043477
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.836506537
Short name T10
Test name
Test status
Simulation time 126331673622 ps
CPU time 200.12 seconds
Started Jul 05 06:30:36 PM PDT 24
Finished Jul 05 06:33:57 PM PDT 24
Peak memory 274896 kb
Host smart-331810ba-7c3f-40f0-ba05-e53db05fb858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836506537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.836506537
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3975049546
Short name T995
Test name
Test status
Simulation time 28178621353 ps
CPU time 144.61 seconds
Started Jul 05 06:30:39 PM PDT 24
Finished Jul 05 06:33:04 PM PDT 24
Peak memory 256512 kb
Host smart-23867d9b-82d5-4c50-b93f-04435b895989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975049546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3975049546
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3919139542
Short name T145
Test name
Test status
Simulation time 1016070506 ps
CPU time 9.94 seconds
Started Jul 05 06:30:35 PM PDT 24
Finished Jul 05 06:30:46 PM PDT 24
Peak memory 225628 kb
Host smart-bde6f452-18dc-4a4c-8665-52ee45583656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919139542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3919139542
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3480259402
Short name T505
Test name
Test status
Simulation time 54172610529 ps
CPU time 180.35 seconds
Started Jul 05 06:30:37 PM PDT 24
Finished Jul 05 06:33:38 PM PDT 24
Peak memory 251772 kb
Host smart-aaf8d382-35b5-4c97-a1a1-9bd0c3eec035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480259402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3480259402
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.861652003
Short name T204
Test name
Test status
Simulation time 148284673 ps
CPU time 4.73 seconds
Started Jul 05 06:30:38 PM PDT 24
Finished Jul 05 06:30:43 PM PDT 24
Peak memory 233788 kb
Host smart-5d4c7265-62f5-4aca-ac8b-6bf75d1eb33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861652003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.861652003
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2028269314
Short name T607
Test name
Test status
Simulation time 127518944 ps
CPU time 2.54 seconds
Started Jul 05 06:30:34 PM PDT 24
Finished Jul 05 06:30:37 PM PDT 24
Peak memory 233584 kb
Host smart-a54a6be1-b9ee-4ae3-a103-9526edbf06c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028269314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2028269314
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.471989346
Short name T789
Test name
Test status
Simulation time 23464921028 ps
CPU time 17.01 seconds
Started Jul 05 06:30:40 PM PDT 24
Finished Jul 05 06:30:57 PM PDT 24
Peak memory 233880 kb
Host smart-d44c03c0-f5b6-4e9f-9b69-a17aa8794d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471989346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.471989346
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3470630823
Short name T8
Test name
Test status
Simulation time 24829417511 ps
CPU time 14.93 seconds
Started Jul 05 06:30:37 PM PDT 24
Finished Jul 05 06:30:52 PM PDT 24
Peak memory 233924 kb
Host smart-1bc818da-8f26-40b5-b3a2-425113fcadec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470630823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3470630823
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1494266134
Short name T12
Test name
Test status
Simulation time 2231240310 ps
CPU time 20.13 seconds
Started Jul 05 06:30:33 PM PDT 24
Finished Jul 05 06:30:54 PM PDT 24
Peak memory 223880 kb
Host smart-afbb0c1b-2249-4773-b9e4-86fe4229a843
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1494266134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1494266134
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2014475725
Short name T710
Test name
Test status
Simulation time 5272652621 ps
CPU time 20.3 seconds
Started Jul 05 06:30:42 PM PDT 24
Finished Jul 05 06:31:03 PM PDT 24
Peak memory 225812 kb
Host smart-eae24408-c227-474a-a671-465cc6e09c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014475725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2014475725
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4192778787
Short name T306
Test name
Test status
Simulation time 1567908694 ps
CPU time 19.09 seconds
Started Jul 05 06:30:33 PM PDT 24
Finished Jul 05 06:30:53 PM PDT 24
Peak memory 217396 kb
Host smart-6e70af2b-1824-41be-8182-4f44d75369c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192778787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4192778787
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2953892120
Short name T864
Test name
Test status
Simulation time 980454875 ps
CPU time 7.73 seconds
Started Jul 05 06:30:29 PM PDT 24
Finished Jul 05 06:30:37 PM PDT 24
Peak memory 217360 kb
Host smart-6279ae38-6e99-4542-a9bf-2b92529710ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953892120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2953892120
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.455731800
Short name T440
Test name
Test status
Simulation time 272365313 ps
CPU time 6.86 seconds
Started Jul 05 06:30:36 PM PDT 24
Finished Jul 05 06:30:43 PM PDT 24
Peak memory 217420 kb
Host smart-d804560c-383b-47a9-a44b-5fc9261289ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455731800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.455731800
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3712821683
Short name T475
Test name
Test status
Simulation time 28578201 ps
CPU time 0.77 seconds
Started Jul 05 06:30:37 PM PDT 24
Finished Jul 05 06:30:39 PM PDT 24
Peak memory 207004 kb
Host smart-538072a3-e134-45bf-983e-5fb8065b0d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712821683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3712821683
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3414839979
Short name T988
Test name
Test status
Simulation time 1812816220 ps
CPU time 8.76 seconds
Started Jul 05 06:30:36 PM PDT 24
Finished Jul 05 06:30:45 PM PDT 24
Peak memory 233744 kb
Host smart-84158b09-3fe1-4b71-a941-54d9723e8db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414839979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3414839979
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.120825908
Short name T523
Test name
Test status
Simulation time 13941060 ps
CPU time 0.74 seconds
Started Jul 05 06:30:50 PM PDT 24
Finished Jul 05 06:30:51 PM PDT 24
Peak memory 206752 kb
Host smart-ac4b3378-40bf-4524-a161-4e949832d515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120825908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.120825908
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1662535687
Short name T748
Test name
Test status
Simulation time 422679197 ps
CPU time 2.51 seconds
Started Jul 05 06:30:44 PM PDT 24
Finished Jul 05 06:30:46 PM PDT 24
Peak memory 225536 kb
Host smart-147a1fdd-4c49-4cbd-8f3a-3f0561dff6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662535687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1662535687
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3713121005
Short name T955
Test name
Test status
Simulation time 39424972 ps
CPU time 0.81 seconds
Started Jul 05 06:30:41 PM PDT 24
Finished Jul 05 06:30:42 PM PDT 24
Peak memory 206492 kb
Host smart-89a17a94-bc65-49f3-9a6b-92fd74b5bdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713121005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3713121005
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3467221170
Short name T584
Test name
Test status
Simulation time 12076350 ps
CPU time 0.79 seconds
Started Jul 05 06:30:41 PM PDT 24
Finished Jul 05 06:30:42 PM PDT 24
Peak memory 216908 kb
Host smart-d60e3a07-aa64-4d54-a2e5-6bd7936ab19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467221170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3467221170
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.948892609
Short name T678
Test name
Test status
Simulation time 6712827801 ps
CPU time 111.83 seconds
Started Jul 05 06:30:42 PM PDT 24
Finished Jul 05 06:32:34 PM PDT 24
Peak memory 256216 kb
Host smart-bee6ec9c-a9e7-4d1d-8ede-d7bd013bd259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948892609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.948892609
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3057806527
Short name T808
Test name
Test status
Simulation time 405623591 ps
CPU time 10.9 seconds
Started Jul 05 06:30:45 PM PDT 24
Finished Jul 05 06:30:56 PM PDT 24
Peak memory 237956 kb
Host smart-77f57503-0b40-41a2-b6e8-c4d0acd15aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057806527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3057806527
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.978107424
Short name T1007
Test name
Test status
Simulation time 50836092511 ps
CPU time 95.13 seconds
Started Jul 05 06:30:42 PM PDT 24
Finished Jul 05 06:32:18 PM PDT 24
Peak memory 252792 kb
Host smart-2ee9b04a-5ae8-4f9f-9525-eebb3b4c206b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978107424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.978107424
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4033392548
Short name T495
Test name
Test status
Simulation time 1883282163 ps
CPU time 17.49 seconds
Started Jul 05 06:30:41 PM PDT 24
Finished Jul 05 06:30:59 PM PDT 24
Peak memory 233764 kb
Host smart-7a268eeb-3b8d-4271-ae02-76fb2269f356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033392548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4033392548
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3909903241
Short name T227
Test name
Test status
Simulation time 3324623918 ps
CPU time 18.44 seconds
Started Jul 05 06:30:42 PM PDT 24
Finished Jul 05 06:31:01 PM PDT 24
Peak memory 233884 kb
Host smart-25740c40-6f61-45bb-a682-c52cc539cab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909903241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3909903241
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1138673299
Short name T852
Test name
Test status
Simulation time 4110007407 ps
CPU time 15.78 seconds
Started Jul 05 06:30:37 PM PDT 24
Finished Jul 05 06:30:54 PM PDT 24
Peak memory 225620 kb
Host smart-5de60393-4954-462b-85da-efb6dfe00cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138673299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1138673299
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.955876048
Short name T617
Test name
Test status
Simulation time 1946283571 ps
CPU time 7.41 seconds
Started Jul 05 06:30:44 PM PDT 24
Finished Jul 05 06:30:52 PM PDT 24
Peak memory 222536 kb
Host smart-c5a333eb-ef10-4e94-9be5-f313e59e6189
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=955876048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.955876048
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2959374045
Short name T215
Test name
Test status
Simulation time 10065644965 ps
CPU time 145.98 seconds
Started Jul 05 06:30:50 PM PDT 24
Finished Jul 05 06:33:16 PM PDT 24
Peak memory 274788 kb
Host smart-d908287d-8f63-436e-8c36-9a35e16b06eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959374045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2959374045
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1655217756
Short name T579
Test name
Test status
Simulation time 831189727 ps
CPU time 4.47 seconds
Started Jul 05 06:30:44 PM PDT 24
Finished Jul 05 06:30:49 PM PDT 24
Peak memory 217428 kb
Host smart-2704949f-d745-4355-8212-a4415085cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655217756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1655217756
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2984426967
Short name T363
Test name
Test status
Simulation time 1763136518 ps
CPU time 5.2 seconds
Started Jul 05 06:30:42 PM PDT 24
Finished Jul 05 06:30:48 PM PDT 24
Peak memory 217308 kb
Host smart-6ccbfe9c-0361-4ee2-a7e7-33b2ff3bcbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984426967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2984426967
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1382337106
Short name T321
Test name
Test status
Simulation time 11432553 ps
CPU time 0.68 seconds
Started Jul 05 06:34:11 PM PDT 24
Finished Jul 05 06:34:12 PM PDT 24
Peak memory 206616 kb
Host smart-8ab2acc6-def2-47a8-8ac0-f1599b3522dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382337106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1382337106
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1471839872
Short name T813
Test name
Test status
Simulation time 84325975 ps
CPU time 0.94 seconds
Started Jul 05 06:30:44 PM PDT 24
Finished Jul 05 06:30:45 PM PDT 24
Peak memory 206936 kb
Host smart-5a178bf8-e05f-4eb1-b34d-cf6566c6cea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471839872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1471839872
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1113490967
Short name T687
Test name
Test status
Simulation time 7288077647 ps
CPU time 33.45 seconds
Started Jul 05 06:30:41 PM PDT 24
Finished Jul 05 06:31:15 PM PDT 24
Peak memory 250348 kb
Host smart-d38d0b4c-b8fa-4be2-9fce-fbe1f9ee67bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113490967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1113490967
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1938271278
Short name T904
Test name
Test status
Simulation time 14086131 ps
CPU time 0.72 seconds
Started Jul 05 06:30:50 PM PDT 24
Finished Jul 05 06:30:51 PM PDT 24
Peak memory 205824 kb
Host smart-65e0846d-cb2a-4605-a412-ca204dc1289f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938271278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1938271278
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1817686956
Short name T412
Test name
Test status
Simulation time 2625640530 ps
CPU time 14.98 seconds
Started Jul 05 06:30:49 PM PDT 24
Finished Jul 05 06:31:05 PM PDT 24
Peak memory 225704 kb
Host smart-09761498-4b97-497c-a3c3-e0629e755d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817686956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1817686956
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1043265691
Short name T599
Test name
Test status
Simulation time 17833770 ps
CPU time 0.74 seconds
Started Jul 05 06:30:48 PM PDT 24
Finished Jul 05 06:30:49 PM PDT 24
Peak memory 206828 kb
Host smart-a47ea85b-766e-4060-88ce-bac1183e0157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043265691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1043265691
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.984523464
Short name T626
Test name
Test status
Simulation time 3791937719 ps
CPU time 51.77 seconds
Started Jul 05 06:30:50 PM PDT 24
Finished Jul 05 06:31:43 PM PDT 24
Peak memory 250632 kb
Host smart-6c229c68-4474-45a9-ba47-e9f68b43e028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984523464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.984523464
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.206529914
Short name T289
Test name
Test status
Simulation time 1056521576 ps
CPU time 15.95 seconds
Started Jul 05 06:30:49 PM PDT 24
Finished Jul 05 06:31:05 PM PDT 24
Peak memory 233776 kb
Host smart-958c4c15-2795-4508-b7b4-edb9ef293902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206529914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.206529914
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.350259813
Short name T276
Test name
Test status
Simulation time 4667371917 ps
CPU time 94.18 seconds
Started Jul 05 06:30:49 PM PDT 24
Finished Jul 05 06:32:24 PM PDT 24
Peak memory 274136 kb
Host smart-0758c3ea-f8ee-4fe1-ae30-19a396c005d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350259813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.350259813
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1928447906
Short name T877
Test name
Test status
Simulation time 584842121 ps
CPU time 5.24 seconds
Started Jul 05 06:30:48 PM PDT 24
Finished Jul 05 06:30:53 PM PDT 24
Peak memory 233840 kb
Host smart-0fe53b01-fbb4-4887-b40c-6cab14b2c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928447906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1928447906
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3508747595
Short name T86
Test name
Test status
Simulation time 1836805282 ps
CPU time 27.01 seconds
Started Jul 05 06:30:51 PM PDT 24
Finished Jul 05 06:31:18 PM PDT 24
Peak memory 249928 kb
Host smart-90686468-c5bc-4873-a4a3-0b5cc2e095ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508747595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3508747595
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.810009117
Short name T661
Test name
Test status
Simulation time 11012291216 ps
CPU time 4.36 seconds
Started Jul 05 06:30:49 PM PDT 24
Finished Jul 05 06:30:54 PM PDT 24
Peak memory 225700 kb
Host smart-2467be28-c36e-4e4e-983f-9451fdb6f3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810009117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.810009117
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.612678493
Short name T768
Test name
Test status
Simulation time 798934688 ps
CPU time 6.7 seconds
Started Jul 05 06:30:51 PM PDT 24
Finished Jul 05 06:30:58 PM PDT 24
Peak memory 241712 kb
Host smart-1b941b8b-4752-4f8d-a610-a2c88ff2c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612678493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.612678493
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2702299252
Short name T804
Test name
Test status
Simulation time 275548163 ps
CPU time 4.65 seconds
Started Jul 05 06:30:49 PM PDT 24
Finished Jul 05 06:30:54 PM PDT 24
Peak memory 224140 kb
Host smart-1ab51e00-10bd-404b-8ad9-29928c9a4bb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2702299252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2702299252
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1023312052
Short name T206
Test name
Test status
Simulation time 247235627177 ps
CPU time 619.32 seconds
Started Jul 05 06:30:50 PM PDT 24
Finished Jul 05 06:41:10 PM PDT 24
Peak memory 283280 kb
Host smart-934a9f21-a274-4ac6-8658-09c1cd80c118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023312052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1023312052
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1302851145
Short name T894
Test name
Test status
Simulation time 202002893 ps
CPU time 2.21 seconds
Started Jul 05 06:30:49 PM PDT 24
Finished Jul 05 06:30:51 PM PDT 24
Peak memory 217528 kb
Host smart-29a1b7cc-bf46-46be-b1c6-88d7039f38e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302851145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1302851145
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3058231282
Short name T972
Test name
Test status
Simulation time 8180069590 ps
CPU time 12.38 seconds
Started Jul 05 06:30:47 PM PDT 24
Finished Jul 05 06:31:00 PM PDT 24
Peak memory 217444 kb
Host smart-12ce7e0e-c02c-4fec-9236-b56dea5635e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058231282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3058231282
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1709453365
Short name T606
Test name
Test status
Simulation time 60423038 ps
CPU time 1.73 seconds
Started Jul 05 06:30:52 PM PDT 24
Finished Jul 05 06:30:54 PM PDT 24
Peak memory 217440 kb
Host smart-a41bf141-993d-4524-a01d-53a53f9629b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709453365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1709453365
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1122812528
Short name T348
Test name
Test status
Simulation time 75258939 ps
CPU time 0.91 seconds
Started Jul 05 06:30:51 PM PDT 24
Finished Jul 05 06:30:53 PM PDT 24
Peak memory 206964 kb
Host smart-22b0f2da-b2d7-4f5d-b1f0-878d9395cf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122812528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1122812528
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2211431623
Short name T464
Test name
Test status
Simulation time 32541874 ps
CPU time 2.15 seconds
Started Jul 05 06:30:49 PM PDT 24
Finished Jul 05 06:30:52 PM PDT 24
Peak memory 225052 kb
Host smart-372ac696-6af5-4a54-88fa-e79894e67f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211431623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2211431623
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3933820951
Short name T902
Test name
Test status
Simulation time 13959688 ps
CPU time 0.73 seconds
Started Jul 05 06:30:59 PM PDT 24
Finished Jul 05 06:31:00 PM PDT 24
Peak memory 206328 kb
Host smart-94e664e5-854a-4497-82df-d26f38a1483d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933820951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3933820951
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1267952194
Short name T914
Test name
Test status
Simulation time 14573490990 ps
CPU time 12.61 seconds
Started Jul 05 06:30:59 PM PDT 24
Finished Jul 05 06:31:12 PM PDT 24
Peak memory 233876 kb
Host smart-17ae323e-64a6-4958-89e4-e57113a91723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267952194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1267952194
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1388331856
Short name T472
Test name
Test status
Simulation time 33679626 ps
CPU time 0.8 seconds
Started Jul 05 06:30:48 PM PDT 24
Finished Jul 05 06:30:50 PM PDT 24
Peak memory 207544 kb
Host smart-5215b8f2-851b-475f-a8f3-0a816f02c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388331856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1388331856
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.624494708
Short name T654
Test name
Test status
Simulation time 5420510380 ps
CPU time 77.72 seconds
Started Jul 05 06:30:58 PM PDT 24
Finished Jul 05 06:32:16 PM PDT 24
Peak memory 250268 kb
Host smart-8cce9276-64b8-4b7b-874d-1e73c2eb5604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624494708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.624494708
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2793139312
Short name T803
Test name
Test status
Simulation time 63635155665 ps
CPU time 163.28 seconds
Started Jul 05 06:30:59 PM PDT 24
Finished Jul 05 06:33:43 PM PDT 24
Peak memory 250440 kb
Host smart-466f6495-3844-4f8d-a5b7-7ff729e073ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793139312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2793139312
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2882862046
Short name T868
Test name
Test status
Simulation time 201573403492 ps
CPU time 311.82 seconds
Started Jul 05 06:31:01 PM PDT 24
Finished Jul 05 06:36:13 PM PDT 24
Peak memory 269236 kb
Host smart-30491ab3-f369-48a2-bf30-b7b5effbe9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882862046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2882862046
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3077063171
Short name T147
Test name
Test status
Simulation time 35636005 ps
CPU time 2.75 seconds
Started Jul 05 06:30:56 PM PDT 24
Finished Jul 05 06:30:59 PM PDT 24
Peak memory 233796 kb
Host smart-e5974be4-9532-4631-85ab-fd3945dfccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077063171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3077063171
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1529282768
Short name T549
Test name
Test status
Simulation time 1024928621 ps
CPU time 6.48 seconds
Started Jul 05 06:30:57 PM PDT 24
Finished Jul 05 06:31:04 PM PDT 24
Peak memory 225536 kb
Host smart-380d857e-5ca6-4f2c-9604-f75159e036ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529282768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1529282768
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1305647334
Short name T689
Test name
Test status
Simulation time 770139157 ps
CPU time 11.04 seconds
Started Jul 05 06:30:57 PM PDT 24
Finished Jul 05 06:31:09 PM PDT 24
Peak memory 239140 kb
Host smart-233a3dea-0692-4100-b526-ed09a3c2b489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305647334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1305647334
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3923848870
Short name T341
Test name
Test status
Simulation time 30474663 ps
CPU time 2.5 seconds
Started Jul 05 06:30:58 PM PDT 24
Finished Jul 05 06:31:01 PM PDT 24
Peak memory 233584 kb
Host smart-8c25d81f-e98c-41f5-b9c9-45b935544b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923848870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3923848870
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3948083406
Short name T459
Test name
Test status
Simulation time 10061853136 ps
CPU time 11.79 seconds
Started Jul 05 06:30:57 PM PDT 24
Finished Jul 05 06:31:10 PM PDT 24
Peak memory 233872 kb
Host smart-3a83f799-613f-4a32-8f6a-1e1568cd6466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948083406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3948083406
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3547716062
Short name T337
Test name
Test status
Simulation time 4880412489 ps
CPU time 10.39 seconds
Started Jul 05 06:31:02 PM PDT 24
Finished Jul 05 06:31:12 PM PDT 24
Peak memory 220508 kb
Host smart-e08e25eb-dc44-40f3-9ef5-ea34d4d3e633
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3547716062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3547716062
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.735452749
Short name T842
Test name
Test status
Simulation time 49271487 ps
CPU time 0.99 seconds
Started Jul 05 06:30:57 PM PDT 24
Finished Jul 05 06:30:59 PM PDT 24
Peak memory 208812 kb
Host smart-415bb83a-2190-41c8-b760-2adb2952cf53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735452749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.735452749
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1696227636
Short name T623
Test name
Test status
Simulation time 3612836317 ps
CPU time 23.08 seconds
Started Jul 05 06:30:57 PM PDT 24
Finished Jul 05 06:31:21 PM PDT 24
Peak memory 217568 kb
Host smart-d3097d8e-2ef3-48dc-af56-eab5087ee82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696227636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1696227636
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1533505777
Short name T516
Test name
Test status
Simulation time 423071598 ps
CPU time 1.64 seconds
Started Jul 05 06:30:50 PM PDT 24
Finished Jul 05 06:30:53 PM PDT 24
Peak memory 208880 kb
Host smart-fa41eb1c-b8a5-454d-8434-1a760da67e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533505777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1533505777
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2583835835
Short name T358
Test name
Test status
Simulation time 42996907 ps
CPU time 1.59 seconds
Started Jul 05 06:30:56 PM PDT 24
Finished Jul 05 06:30:59 PM PDT 24
Peak memory 217356 kb
Host smart-fd4c4de9-11cb-4d89-8486-4aec82352626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583835835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2583835835
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1594230329
Short name T2
Test name
Test status
Simulation time 28744377 ps
CPU time 0.82 seconds
Started Jul 05 06:30:56 PM PDT 24
Finished Jul 05 06:30:58 PM PDT 24
Peak memory 206988 kb
Host smart-d0d370db-3b13-4dd1-8502-467b2bab19bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594230329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1594230329
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1192041856
Short name T533
Test name
Test status
Simulation time 5404178959 ps
CPU time 7.69 seconds
Started Jul 05 06:31:00 PM PDT 24
Finished Jul 05 06:31:08 PM PDT 24
Peak memory 225716 kb
Host smart-7b8a31f5-f859-4f26-99d4-775c1c367a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192041856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1192041856
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.210143770
Short name T706
Test name
Test status
Simulation time 13657324 ps
CPU time 0.71 seconds
Started Jul 05 06:31:03 PM PDT 24
Finished Jul 05 06:31:04 PM PDT 24
Peak memory 206384 kb
Host smart-3d9e6833-aa26-4373-8f8b-5db41ca95be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210143770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.210143770
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3443115256
Short name T1016
Test name
Test status
Simulation time 587012895 ps
CPU time 5.12 seconds
Started Jul 05 06:31:04 PM PDT 24
Finished Jul 05 06:31:10 PM PDT 24
Peak memory 233776 kb
Host smart-39c0f63f-2ae6-4991-a8e6-dee251c1ec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443115256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3443115256
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3357213128
Short name T452
Test name
Test status
Simulation time 17670290 ps
CPU time 0.81 seconds
Started Jul 05 06:32:22 PM PDT 24
Finished Jul 05 06:32:23 PM PDT 24
Peak memory 206860 kb
Host smart-35c19f72-f507-4c8a-b62f-d39e480c18b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357213128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3357213128
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2319071766
Short name T39
Test name
Test status
Simulation time 1851688001 ps
CPU time 44.29 seconds
Started Jul 05 06:31:03 PM PDT 24
Finished Jul 05 06:31:49 PM PDT 24
Peak memory 239756 kb
Host smart-6c92e09e-7366-4878-9a0e-89863170ab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319071766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2319071766
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.772183812
Short name T566
Test name
Test status
Simulation time 21770672759 ps
CPU time 54.98 seconds
Started Jul 05 06:31:04 PM PDT 24
Finished Jul 05 06:32:00 PM PDT 24
Peak memory 254388 kb
Host smart-6462ab89-2429-46a0-85c7-d709c4a2f333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772183812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.772183812
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4233510443
Short name T224
Test name
Test status
Simulation time 6673852753 ps
CPU time 79.55 seconds
Started Jul 05 06:31:03 PM PDT 24
Finished Jul 05 06:32:24 PM PDT 24
Peak memory 258620 kb
Host smart-b19424ea-89a5-48c0-bd87-dd1cdd11da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233510443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4233510443
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.575375270
Short name T448
Test name
Test status
Simulation time 1825104584 ps
CPU time 26.77 seconds
Started Jul 05 06:31:03 PM PDT 24
Finished Jul 05 06:31:30 PM PDT 24
Peak memory 233816 kb
Host smart-d8396914-af9f-48ad-8abe-a15330935ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575375270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.575375270
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.282677332
Short name T38
Test name
Test status
Simulation time 22009641212 ps
CPU time 146.54 seconds
Started Jul 05 06:31:06 PM PDT 24
Finished Jul 05 06:33:33 PM PDT 24
Peak memory 250324 kb
Host smart-e5d01067-e667-43fe-b3ca-19d4b4412d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282677332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.282677332
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.924368192
Short name T196
Test name
Test status
Simulation time 808437939 ps
CPU time 6.31 seconds
Started Jul 05 06:30:58 PM PDT 24
Finished Jul 05 06:31:05 PM PDT 24
Peak memory 225580 kb
Host smart-3aa528ed-8324-4edf-b7b2-9ef74310df42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924368192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.924368192
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.698650042
Short name T959
Test name
Test status
Simulation time 901615203 ps
CPU time 16.14 seconds
Started Jul 05 06:31:00 PM PDT 24
Finished Jul 05 06:31:16 PM PDT 24
Peak memory 225596 kb
Host smart-a33e4cb3-03f5-4ce8-bd8a-5a5bb6bd898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698650042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.698650042
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3248844174
Short name T490
Test name
Test status
Simulation time 2023557742 ps
CPU time 8.46 seconds
Started Jul 05 06:31:00 PM PDT 24
Finished Jul 05 06:31:09 PM PDT 24
Peak memory 233736 kb
Host smart-70bc115a-1970-45fd-b449-e875b0e348cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248844174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3248844174
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.730185799
Short name T497
Test name
Test status
Simulation time 6045298367 ps
CPU time 28 seconds
Started Jul 05 06:30:59 PM PDT 24
Finished Jul 05 06:31:28 PM PDT 24
Peak memory 230772 kb
Host smart-fc2f7654-3236-4d89-ae25-80daeba5537b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730185799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.730185799
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.18367045
Short name T545
Test name
Test status
Simulation time 2377999051 ps
CPU time 5.96 seconds
Started Jul 05 06:31:25 PM PDT 24
Finished Jul 05 06:31:31 PM PDT 24
Peak memory 223856 kb
Host smart-1f2ac816-a733-4610-a463-d6547968fecf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=18367045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direc
t.18367045
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2893523201
Short name T14
Test name
Test status
Simulation time 64063579 ps
CPU time 1.11 seconds
Started Jul 05 06:31:09 PM PDT 24
Finished Jul 05 06:31:11 PM PDT 24
Peak memory 207928 kb
Host smart-960982aa-a445-4199-bba7-8c1f79a9928f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893523201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2893523201
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.573320453
Short name T466
Test name
Test status
Simulation time 715790463 ps
CPU time 14.19 seconds
Started Jul 05 06:30:58 PM PDT 24
Finished Jul 05 06:31:13 PM PDT 24
Peak memory 217352 kb
Host smart-c1efd178-1cf1-4e51-aa4c-a610a3eb7cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573320453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.573320453
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2019862531
Short name T943
Test name
Test status
Simulation time 832754528 ps
CPU time 5.71 seconds
Started Jul 05 06:31:00 PM PDT 24
Finished Jul 05 06:31:06 PM PDT 24
Peak memory 217296 kb
Host smart-f9e18155-b696-455f-9325-5a16eaed3be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019862531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2019862531
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2109346188
Short name T632
Test name
Test status
Simulation time 193074959 ps
CPU time 3.24 seconds
Started Jul 05 06:30:59 PM PDT 24
Finished Jul 05 06:31:03 PM PDT 24
Peak memory 217260 kb
Host smart-9cdb6703-b667-4756-bf53-d2fd291bb35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109346188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2109346188
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4065480078
Short name T419
Test name
Test status
Simulation time 39483999 ps
CPU time 0.82 seconds
Started Jul 05 06:30:58 PM PDT 24
Finished Jul 05 06:30:59 PM PDT 24
Peak memory 207004 kb
Host smart-28952d4f-a8ac-4f42-aed8-377cc6581648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065480078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4065480078
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1414009226
Short name T503
Test name
Test status
Simulation time 75832271777 ps
CPU time 13.23 seconds
Started Jul 05 06:31:09 PM PDT 24
Finished Jul 05 06:31:23 PM PDT 24
Peak memory 233864 kb
Host smart-bdff066d-99e2-4ae1-bb1b-f0bd02086862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414009226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1414009226
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3759899966
Short name T558
Test name
Test status
Simulation time 75103811 ps
CPU time 0.73 seconds
Started Jul 05 06:31:12 PM PDT 24
Finished Jul 05 06:31:13 PM PDT 24
Peak memory 205816 kb
Host smart-2f311523-3670-4964-9f90-5ea0a5101cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759899966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3759899966
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4093154512
Short name T964
Test name
Test status
Simulation time 681098982 ps
CPU time 3.45 seconds
Started Jul 05 06:31:04 PM PDT 24
Finished Jul 05 06:31:09 PM PDT 24
Peak memory 225584 kb
Host smart-a22b00da-b2fe-405f-8313-36b722e391d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093154512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4093154512
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3809492967
Short name T544
Test name
Test status
Simulation time 72194377 ps
CPU time 0.81 seconds
Started Jul 05 06:31:05 PM PDT 24
Finished Jul 05 06:31:06 PM PDT 24
Peak memory 207544 kb
Host smart-a8583101-4cf3-4ba0-ac07-fe0ebea29300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809492967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3809492967
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.995807643
Short name T712
Test name
Test status
Simulation time 2879002153 ps
CPU time 19.13 seconds
Started Jul 05 06:31:11 PM PDT 24
Finished Jul 05 06:31:31 PM PDT 24
Peak memory 242124 kb
Host smart-8d07cc58-8ab2-4b95-821c-4d378a33d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995807643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.995807643
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.187257185
Short name T720
Test name
Test status
Simulation time 16763679783 ps
CPU time 161.6 seconds
Started Jul 05 06:31:10 PM PDT 24
Finished Jul 05 06:33:52 PM PDT 24
Peak memory 250396 kb
Host smart-5ff46728-ddf4-43d8-a4ef-2fad674cce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187257185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.187257185
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3115378045
Short name T754
Test name
Test status
Simulation time 3856762815 ps
CPU time 57.91 seconds
Started Jul 05 06:31:13 PM PDT 24
Finished Jul 05 06:32:12 PM PDT 24
Peak memory 258116 kb
Host smart-5f7f7b3d-f983-4f65-ac8d-cd0cc9750442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115378045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3115378045
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1728099603
Short name T294
Test name
Test status
Simulation time 3569383261 ps
CPU time 14.53 seconds
Started Jul 05 06:31:05 PM PDT 24
Finished Jul 05 06:31:20 PM PDT 24
Peak memory 225644 kb
Host smart-b5060132-f8a4-41e8-b643-156558c99f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728099603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1728099603
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.461542628
Short name T901
Test name
Test status
Simulation time 3475092032 ps
CPU time 47.41 seconds
Started Jul 05 06:31:04 PM PDT 24
Finished Jul 05 06:31:53 PM PDT 24
Peak memory 252104 kb
Host smart-36b6136b-dcb8-410c-9521-bec959928a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461542628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.461542628
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.880699887
Short name T614
Test name
Test status
Simulation time 1169509475 ps
CPU time 4.65 seconds
Started Jul 05 06:31:05 PM PDT 24
Finished Jul 05 06:31:10 PM PDT 24
Peak memory 225564 kb
Host smart-e4e47352-e00c-4bd0-a84f-365fafa804e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880699887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.880699887
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3540166825
Short name T433
Test name
Test status
Simulation time 1749750999 ps
CPU time 22.06 seconds
Started Jul 05 06:31:03 PM PDT 24
Finished Jul 05 06:31:27 PM PDT 24
Peak memory 233804 kb
Host smart-9523df92-217a-4925-b47d-6104381c9ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540166825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3540166825
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2221466572
Short name T217
Test name
Test status
Simulation time 4344466577 ps
CPU time 14.81 seconds
Started Jul 05 06:31:03 PM PDT 24
Finished Jul 05 06:31:19 PM PDT 24
Peak memory 233904 kb
Host smart-bd6bca6f-112b-495d-8711-f23b3bd2a2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221466572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2221466572
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2867624349
Short name T746
Test name
Test status
Simulation time 18663224017 ps
CPU time 17.26 seconds
Started Jul 05 06:31:06 PM PDT 24
Finished Jul 05 06:31:23 PM PDT 24
Peak memory 241920 kb
Host smart-2e520604-1da4-448b-96cd-c9b2029585e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867624349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2867624349
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1644396235
Short name T149
Test name
Test status
Simulation time 2655343171 ps
CPU time 19.95 seconds
Started Jul 05 06:31:03 PM PDT 24
Finished Jul 05 06:31:25 PM PDT 24
Peak memory 223276 kb
Host smart-909ba785-64a2-479f-8fa0-9626cb0a1f0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1644396235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1644396235
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2140577740
Short name T22
Test name
Test status
Simulation time 39796565867 ps
CPU time 388.76 seconds
Started Jul 05 06:31:11 PM PDT 24
Finished Jul 05 06:37:40 PM PDT 24
Peak memory 266772 kb
Host smart-f5387f2a-13f0-49a6-9388-66d91696a5de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140577740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2140577740
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1188513566
Short name T311
Test name
Test status
Simulation time 1867072715 ps
CPU time 12.59 seconds
Started Jul 05 06:31:04 PM PDT 24
Finished Jul 05 06:31:18 PM PDT 24
Peak memory 217384 kb
Host smart-a8cfdc01-937f-4cb5-a3a8-f998e0f38c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188513566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1188513566
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3030235855
Short name T420
Test name
Test status
Simulation time 5770936012 ps
CPU time 16.61 seconds
Started Jul 05 06:31:09 PM PDT 24
Finished Jul 05 06:31:26 PM PDT 24
Peak memory 217364 kb
Host smart-88998523-64b4-46eb-9fdf-5834f76dbd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030235855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3030235855
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1136670632
Short name T619
Test name
Test status
Simulation time 91728951 ps
CPU time 0.92 seconds
Started Jul 05 06:31:03 PM PDT 24
Finished Jul 05 06:31:06 PM PDT 24
Peak memory 208024 kb
Host smart-5f82d270-d92d-46e5-ba3d-97df820ba526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136670632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1136670632
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.584664181
Short name T329
Test name
Test status
Simulation time 85217458 ps
CPU time 0.92 seconds
Started Jul 05 06:31:04 PM PDT 24
Finished Jul 05 06:31:06 PM PDT 24
Peak memory 207000 kb
Host smart-b710b1ff-3582-4cad-aa21-7d92f7aa6d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584664181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.584664181
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3086676801
Short name T494
Test name
Test status
Simulation time 98781779 ps
CPU time 2.77 seconds
Started Jul 05 06:31:02 PM PDT 24
Finished Jul 05 06:31:06 PM PDT 24
Peak memory 233788 kb
Host smart-510dca1f-65f0-41f9-aa61-837f88e2de9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086676801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3086676801
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.136180591
Short name T1024
Test name
Test status
Simulation time 53301426 ps
CPU time 0.72 seconds
Started Jul 05 06:31:19 PM PDT 24
Finished Jul 05 06:31:21 PM PDT 24
Peak memory 206732 kb
Host smart-8fb83cde-d96f-480e-bba5-6d63b4ddfac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136180591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.136180591
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3864392305
Short name T242
Test name
Test status
Simulation time 428322504 ps
CPU time 2.46 seconds
Started Jul 05 06:31:19 PM PDT 24
Finished Jul 05 06:31:22 PM PDT 24
Peak memory 225636 kb
Host smart-6174a1d9-75fe-41a9-ac93-c16c49f370ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864392305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3864392305
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.551972432
Short name T462
Test name
Test status
Simulation time 27936731 ps
CPU time 0.78 seconds
Started Jul 05 06:31:12 PM PDT 24
Finished Jul 05 06:31:13 PM PDT 24
Peak memory 207448 kb
Host smart-a0d1697c-357e-4d0c-97ce-ffcbfc06cc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551972432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.551972432
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3617103291
Short name T739
Test name
Test status
Simulation time 10705878002 ps
CPU time 96.34 seconds
Started Jul 05 06:31:20 PM PDT 24
Finished Jul 05 06:32:57 PM PDT 24
Peak memory 250424 kb
Host smart-2bb095cc-c442-4291-afa8-c6e728019ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617103291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3617103291
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2926672256
Short name T765
Test name
Test status
Simulation time 12996861663 ps
CPU time 137.54 seconds
Started Jul 05 06:31:19 PM PDT 24
Finished Jul 05 06:33:37 PM PDT 24
Peak memory 250420 kb
Host smart-120d5c82-b645-48c1-b0b7-f1e9c4398bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926672256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2926672256
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1054639997
Short name T455
Test name
Test status
Simulation time 133996959 ps
CPU time 3.51 seconds
Started Jul 05 06:31:18 PM PDT 24
Finished Jul 05 06:31:22 PM PDT 24
Peak memory 225568 kb
Host smart-dec692f3-f99a-4f93-9eb9-6b17f89c0485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054639997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1054639997
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1179337475
Short name T439
Test name
Test status
Simulation time 1438975848 ps
CPU time 18.71 seconds
Started Jul 05 06:31:21 PM PDT 24
Finished Jul 05 06:31:40 PM PDT 24
Peak memory 236264 kb
Host smart-ac30c639-c054-47f1-b515-8c08b52cd739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179337475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1179337475
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1183838124
Short name T432
Test name
Test status
Simulation time 529763080 ps
CPU time 5.64 seconds
Started Jul 05 06:31:12 PM PDT 24
Finished Jul 05 06:31:19 PM PDT 24
Peak memory 233852 kb
Host smart-96733488-a6a9-4030-99de-b9305cee4509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183838124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1183838124
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.195240703
Short name T504
Test name
Test status
Simulation time 17209417292 ps
CPU time 186.32 seconds
Started Jul 05 06:31:11 PM PDT 24
Finished Jul 05 06:34:17 PM PDT 24
Peak memory 250212 kb
Host smart-e5bafc1b-ffea-428f-8a32-b6a567d14a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195240703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.195240703
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1865232981
Short name T223
Test name
Test status
Simulation time 2924878095 ps
CPU time 9.69 seconds
Started Jul 05 06:31:12 PM PDT 24
Finished Jul 05 06:31:23 PM PDT 24
Peak memory 225692 kb
Host smart-d9e11a48-dec9-410e-b108-c405caf36268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865232981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1865232981
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1616507910
Short name T703
Test name
Test status
Simulation time 338137619 ps
CPU time 6.15 seconds
Started Jul 05 06:31:13 PM PDT 24
Finished Jul 05 06:31:19 PM PDT 24
Peak memory 240236 kb
Host smart-24ff3ad2-8e00-4b5c-a862-ddf5214313b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616507910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1616507910
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2185999224
Short name T857
Test name
Test status
Simulation time 2934030048 ps
CPU time 10.09 seconds
Started Jul 05 06:31:19 PM PDT 24
Finished Jul 05 06:31:30 PM PDT 24
Peak memory 221416 kb
Host smart-847d806b-edc9-48d2-8e07-15ac0c08d68f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2185999224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2185999224
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3106632802
Short name T153
Test name
Test status
Simulation time 72011944234 ps
CPU time 174.13 seconds
Started Jul 05 06:31:19 PM PDT 24
Finished Jul 05 06:34:13 PM PDT 24
Peak memory 250340 kb
Host smart-0420f375-5666-4703-a34b-e757a63877ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106632802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3106632802
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1028524459
Short name T777
Test name
Test status
Simulation time 1419700151 ps
CPU time 2.81 seconds
Started Jul 05 06:31:12 PM PDT 24
Finished Jul 05 06:31:16 PM PDT 24
Peak memory 217584 kb
Host smart-5e5dccb3-67b2-4d8c-8640-2d688928996b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028524459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1028524459
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1289159454
Short name T627
Test name
Test status
Simulation time 1550548117 ps
CPU time 2.13 seconds
Started Jul 05 06:31:11 PM PDT 24
Finished Jul 05 06:31:14 PM PDT 24
Peak memory 208792 kb
Host smart-205d057a-beb5-4cc4-b590-5e26b1586081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289159454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1289159454
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2581892448
Short name T320
Test name
Test status
Simulation time 743528317 ps
CPU time 3.57 seconds
Started Jul 05 06:31:12 PM PDT 24
Finished Jul 05 06:31:16 PM PDT 24
Peak memory 217416 kb
Host smart-d5dc0fc2-8123-424c-9371-15ffe4fd329c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581892448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2581892448
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1305501335
Short name T421
Test name
Test status
Simulation time 77281865 ps
CPU time 0.77 seconds
Started Jul 05 06:31:10 PM PDT 24
Finished Jul 05 06:31:12 PM PDT 24
Peak memory 207000 kb
Host smart-d0681054-2b6c-484c-9e7e-bc601bf1490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305501335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1305501335
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1620123143
Short name T228
Test name
Test status
Simulation time 1015740130 ps
CPU time 3.43 seconds
Started Jul 05 06:31:12 PM PDT 24
Finished Jul 05 06:31:15 PM PDT 24
Peak memory 225564 kb
Host smart-f08df586-f4d0-4991-a22a-186a008f925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620123143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1620123143
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1363016738
Short name T911
Test name
Test status
Simulation time 12417593 ps
CPU time 0.72 seconds
Started Jul 05 06:31:27 PM PDT 24
Finished Jul 05 06:31:28 PM PDT 24
Peak memory 206704 kb
Host smart-2bb121fe-7818-4dc5-9e24-057f38da69cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363016738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1363016738
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3839748752
Short name T611
Test name
Test status
Simulation time 325486535 ps
CPU time 3.28 seconds
Started Jul 05 06:31:27 PM PDT 24
Finished Jul 05 06:31:31 PM PDT 24
Peak memory 233836 kb
Host smart-5fc2362c-d8a0-4026-a869-592e3dd44f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839748752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3839748752
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2193531040
Short name T473
Test name
Test status
Simulation time 15837726 ps
CPU time 0.74 seconds
Started Jul 05 06:31:19 PM PDT 24
Finished Jul 05 06:31:21 PM PDT 24
Peak memory 207536 kb
Host smart-62e879c2-6447-4213-9914-7b762d83e6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193531040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2193531040
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1059589080
Short name T270
Test name
Test status
Simulation time 223463718016 ps
CPU time 392.46 seconds
Started Jul 05 06:31:27 PM PDT 24
Finished Jul 05 06:38:00 PM PDT 24
Peak memory 258488 kb
Host smart-42f53535-e884-4b96-803a-b081ec6cbb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059589080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1059589080
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2073356713
Short name T212
Test name
Test status
Simulation time 3405680530 ps
CPU time 69.57 seconds
Started Jul 05 06:31:25 PM PDT 24
Finished Jul 05 06:32:35 PM PDT 24
Peak memory 251120 kb
Host smart-fc696105-5797-4982-b3ed-f047938402da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073356713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2073356713
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3334827922
Short name T897
Test name
Test status
Simulation time 130366490636 ps
CPU time 229.58 seconds
Started Jul 05 06:31:29 PM PDT 24
Finished Jul 05 06:35:19 PM PDT 24
Peak memory 256440 kb
Host smart-2aae3b09-b8a2-4976-8e77-6fed08f5fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334827922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3334827922
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1565757836
Short name T449
Test name
Test status
Simulation time 191361561 ps
CPU time 2.76 seconds
Started Jul 05 06:31:29 PM PDT 24
Finished Jul 05 06:31:32 PM PDT 24
Peak memory 225620 kb
Host smart-36a8529f-6f58-4a7a-81bb-4395ab2349b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565757836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1565757836
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.759678579
Short name T514
Test name
Test status
Simulation time 10271446404 ps
CPU time 40.85 seconds
Started Jul 05 06:31:26 PM PDT 24
Finished Jul 05 06:32:07 PM PDT 24
Peak memory 250448 kb
Host smart-0e3f42a9-518b-4cd5-ac55-71bdda7c8ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759678579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.759678579
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2354589079
Short name T567
Test name
Test status
Simulation time 4234046138 ps
CPU time 17.66 seconds
Started Jul 05 06:31:27 PM PDT 24
Finished Jul 05 06:31:45 PM PDT 24
Peak memory 233884 kb
Host smart-9667dd65-c795-4809-ac4a-11ddcc23c2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354589079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2354589079
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.465442989
Short name T477
Test name
Test status
Simulation time 1003156187 ps
CPU time 4.74 seconds
Started Jul 05 06:31:27 PM PDT 24
Finished Jul 05 06:31:32 PM PDT 24
Peak memory 225576 kb
Host smart-ec8cddec-7c44-4375-a573-a7d3f6cf45ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465442989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.465442989
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1635090273
Short name T667
Test name
Test status
Simulation time 106667995 ps
CPU time 2.57 seconds
Started Jul 05 06:31:29 PM PDT 24
Finished Jul 05 06:31:32 PM PDT 24
Peak memory 224284 kb
Host smart-7a424ec9-ac1b-4215-99d8-b46046d38dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635090273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1635090273
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3353014690
Short name T403
Test name
Test status
Simulation time 549349856 ps
CPU time 5 seconds
Started Jul 05 06:31:29 PM PDT 24
Finished Jul 05 06:31:34 PM PDT 24
Peak memory 241560 kb
Host smart-45701b12-8ea3-4492-9ee0-a0eeac051fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353014690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3353014690
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.155317706
Short name T33
Test name
Test status
Simulation time 12037341482 ps
CPU time 9.24 seconds
Started Jul 05 06:31:27 PM PDT 24
Finished Jul 05 06:31:36 PM PDT 24
Peak memory 224292 kb
Host smart-1b5cbc54-1b07-4659-9d5a-54db2cc5cad5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=155317706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.155317706
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1274268373
Short name T925
Test name
Test status
Simulation time 214024286 ps
CPU time 1.01 seconds
Started Jul 05 06:31:26 PM PDT 24
Finished Jul 05 06:31:27 PM PDT 24
Peak memory 207960 kb
Host smart-e6bb1954-8969-4f8a-805d-9c5307eac61d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274268373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1274268373
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2777329633
Short name T949
Test name
Test status
Simulation time 1729306825 ps
CPU time 9.43 seconds
Started Jul 05 06:31:19 PM PDT 24
Finished Jul 05 06:31:29 PM PDT 24
Peak memory 217412 kb
Host smart-39565a55-be38-462f-b8c1-75509c59e1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777329633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2777329633
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2800979751
Short name T365
Test name
Test status
Simulation time 3146102371 ps
CPU time 7.86 seconds
Started Jul 05 06:31:18 PM PDT 24
Finished Jul 05 06:31:26 PM PDT 24
Peak memory 217504 kb
Host smart-2679bb64-82a3-4b79-b59b-e2ab77efda36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800979751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2800979751
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.622890498
Short name T668
Test name
Test status
Simulation time 46323363 ps
CPU time 1.66 seconds
Started Jul 05 06:31:30 PM PDT 24
Finished Jul 05 06:31:32 PM PDT 24
Peak memory 217336 kb
Host smart-6a69c494-1555-40b1-98e2-ffc6fc7b9d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622890498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.622890498
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2863809464
Short name T560
Test name
Test status
Simulation time 121997304 ps
CPU time 0.85 seconds
Started Jul 05 06:31:26 PM PDT 24
Finished Jul 05 06:31:27 PM PDT 24
Peak memory 208020 kb
Host smart-7e195044-c061-4e61-9df0-67a0f7dd2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863809464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2863809464
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1484232987
Short name T869
Test name
Test status
Simulation time 87447333 ps
CPU time 2.51 seconds
Started Jul 05 06:31:29 PM PDT 24
Finished Jul 05 06:31:32 PM PDT 24
Peak memory 233852 kb
Host smart-65412b20-52b8-4efd-81ea-6006cb39d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484232987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1484232987
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3268521094
Short name T60
Test name
Test status
Simulation time 102950697 ps
CPU time 0.75 seconds
Started Jul 05 06:31:35 PM PDT 24
Finished Jul 05 06:31:36 PM PDT 24
Peak memory 206384 kb
Host smart-ea7ad885-e7f6-476a-baf2-39a902ff514f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268521094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3268521094
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1616863203
Short name T237
Test name
Test status
Simulation time 1696049095 ps
CPU time 5.91 seconds
Started Jul 05 06:31:33 PM PDT 24
Finished Jul 05 06:31:39 PM PDT 24
Peak memory 233772 kb
Host smart-9489bb44-04e5-44b0-97bf-84daf00438af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616863203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1616863203
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2336722830
Short name T1006
Test name
Test status
Simulation time 20092182 ps
CPU time 0.76 seconds
Started Jul 05 06:31:27 PM PDT 24
Finished Jul 05 06:31:28 PM PDT 24
Peak memory 206452 kb
Host smart-5a10922b-8888-4078-afac-7b4ddb6d58e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336722830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2336722830
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3713626048
Short name T231
Test name
Test status
Simulation time 2012431738 ps
CPU time 39.62 seconds
Started Jul 05 06:31:35 PM PDT 24
Finished Jul 05 06:32:15 PM PDT 24
Peak memory 250164 kb
Host smart-85209889-b5b4-4417-86c8-23cce0a9c708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713626048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3713626048
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.954640569
Short name T847
Test name
Test status
Simulation time 52423444629 ps
CPU time 150.34 seconds
Started Jul 05 06:31:34 PM PDT 24
Finished Jul 05 06:34:05 PM PDT 24
Peak memory 250432 kb
Host smart-4544b90e-14db-4c78-826e-5cfe537ca911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954640569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.954640569
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1930760146
Short name T719
Test name
Test status
Simulation time 3807798158 ps
CPU time 24.02 seconds
Started Jul 05 06:31:32 PM PDT 24
Finished Jul 05 06:31:57 PM PDT 24
Peak memory 218936 kb
Host smart-8703128f-160e-4149-8afe-373d082036ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930760146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1930760146
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1317244789
Short name T428
Test name
Test status
Simulation time 1078967762 ps
CPU time 5.23 seconds
Started Jul 05 06:31:35 PM PDT 24
Finished Jul 05 06:31:41 PM PDT 24
Peak memory 234868 kb
Host smart-327b1280-d3fe-4ed1-b14c-7bf9841a1ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317244789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1317244789
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1397156920
Short name T268
Test name
Test status
Simulation time 64396540320 ps
CPU time 135.92 seconds
Started Jul 05 06:31:34 PM PDT 24
Finished Jul 05 06:33:50 PM PDT 24
Peak memory 250388 kb
Host smart-2e03d04e-9ef5-4eb0-8020-de7a476a60aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397156920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1397156920
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2467698321
Short name T234
Test name
Test status
Simulation time 7111562808 ps
CPU time 20.86 seconds
Started Jul 05 06:31:36 PM PDT 24
Finished Jul 05 06:31:57 PM PDT 24
Peak memory 225752 kb
Host smart-d2fa5f59-8191-4bd7-928b-8c46afe9e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467698321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2467698321
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2477631105
Short name T554
Test name
Test status
Simulation time 2028017480 ps
CPU time 11.47 seconds
Started Jul 05 06:31:32 PM PDT 24
Finished Jul 05 06:31:44 PM PDT 24
Peak memory 240084 kb
Host smart-b98066c1-c204-40be-ba27-aa1abfe53a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477631105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2477631105
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3945280823
Short name T651
Test name
Test status
Simulation time 3840507816 ps
CPU time 6.56 seconds
Started Jul 05 06:31:33 PM PDT 24
Finished Jul 05 06:31:40 PM PDT 24
Peak memory 225708 kb
Host smart-24778980-51ec-4972-b376-2fa55e1b4df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945280823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3945280823
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1389274089
Short name T844
Test name
Test status
Simulation time 281985780 ps
CPU time 2.39 seconds
Started Jul 05 06:31:26 PM PDT 24
Finished Jul 05 06:31:29 PM PDT 24
Peak memory 225324 kb
Host smart-501f1106-b763-48f3-a465-7f4a2984a6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389274089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1389274089
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2778693617
Short name T898
Test name
Test status
Simulation time 72567460 ps
CPU time 3.97 seconds
Started Jul 05 06:31:33 PM PDT 24
Finished Jul 05 06:31:37 PM PDT 24
Peak memory 224172 kb
Host smart-82eabb7d-2282-4b0b-9b44-47cf60843669
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2778693617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2778693617
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1425313860
Short name T161
Test name
Test status
Simulation time 38658107 ps
CPU time 0.96 seconds
Started Jul 05 06:31:33 PM PDT 24
Finished Jul 05 06:31:35 PM PDT 24
Peak memory 208548 kb
Host smart-e8ce3193-ca7d-4d1d-a381-67f22a35fbd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425313860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1425313860
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3596602071
Short name T671
Test name
Test status
Simulation time 7370888109 ps
CPU time 38.77 seconds
Started Jul 05 06:31:26 PM PDT 24
Finished Jul 05 06:32:06 PM PDT 24
Peak memory 217480 kb
Host smart-527843e8-99ab-4f97-b180-33ff467a0687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596602071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3596602071
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3287912954
Short name T481
Test name
Test status
Simulation time 2247463348 ps
CPU time 8.46 seconds
Started Jul 05 06:31:26 PM PDT 24
Finished Jul 05 06:31:35 PM PDT 24
Peak memory 217504 kb
Host smart-cab35fd8-2d71-4bbc-8e7c-c8c5143209cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287912954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3287912954
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1733459595
Short name T336
Test name
Test status
Simulation time 737185696 ps
CPU time 4.99 seconds
Started Jul 05 06:31:29 PM PDT 24
Finished Jul 05 06:31:34 PM PDT 24
Peak memory 217388 kb
Host smart-0787fba7-af33-4036-860b-7b01dc1cdf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733459595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1733459595
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1050928044
Short name T686
Test name
Test status
Simulation time 42749106 ps
CPU time 0.7 seconds
Started Jul 05 06:31:25 PM PDT 24
Finished Jul 05 06:31:26 PM PDT 24
Peak memory 207008 kb
Host smart-51eef550-f87e-4b37-9ea7-e471fbcd3fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050928044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1050928044
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2829768664
Short name T43
Test name
Test status
Simulation time 5039335396 ps
CPU time 9.72 seconds
Started Jul 05 06:31:33 PM PDT 24
Finished Jul 05 06:31:43 PM PDT 24
Peak memory 233940 kb
Host smart-532ff28b-bfc0-4642-958b-23855968bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829768664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2829768664
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3657060267
Short name T444
Test name
Test status
Simulation time 15305218 ps
CPU time 0.7 seconds
Started Jul 05 06:31:46 PM PDT 24
Finished Jul 05 06:31:47 PM PDT 24
Peak memory 206368 kb
Host smart-4609f78a-9da4-431d-a700-d5fa9db097c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657060267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3657060267
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2812120534
Short name T536
Test name
Test status
Simulation time 1438093603 ps
CPU time 4.9 seconds
Started Jul 05 06:31:43 PM PDT 24
Finished Jul 05 06:31:48 PM PDT 24
Peak memory 233744 kb
Host smart-5351455a-ba32-4e69-9122-7d9da059a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812120534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2812120534
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1197607271
Short name T67
Test name
Test status
Simulation time 35093141 ps
CPU time 0.79 seconds
Started Jul 05 06:31:32 PM PDT 24
Finished Jul 05 06:31:33 PM PDT 24
Peak memory 207568 kb
Host smart-3c3ef46b-6bed-41ad-a779-37d6c4437c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197607271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1197607271
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2769439886
Short name T557
Test name
Test status
Simulation time 15073386930 ps
CPU time 91.31 seconds
Started Jul 05 06:35:56 PM PDT 24
Finished Jul 05 06:37:28 PM PDT 24
Peak memory 266256 kb
Host smart-5083fb1d-e710-48ad-b8b9-4c5a1b61cc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769439886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2769439886
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.936288952
Short name T25
Test name
Test status
Simulation time 4662903359 ps
CPU time 28.27 seconds
Started Jul 05 06:31:44 PM PDT 24
Finished Jul 05 06:32:13 PM PDT 24
Peak memory 225812 kb
Host smart-7c5621a9-b5da-4168-892d-109e7d923751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936288952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.936288952
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4026936171
Short name T538
Test name
Test status
Simulation time 4436705776 ps
CPU time 82.87 seconds
Started Jul 05 06:31:46 PM PDT 24
Finished Jul 05 06:33:09 PM PDT 24
Peak memory 250440 kb
Host smart-7ef8a3e8-1f62-42d0-adc6-e73db99827af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026936171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4026936171
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.105080777
Short name T840
Test name
Test status
Simulation time 1889165295 ps
CPU time 6.11 seconds
Started Jul 05 06:31:43 PM PDT 24
Finished Jul 05 06:31:50 PM PDT 24
Peak memory 234020 kb
Host smart-2d53ef17-82fb-45b7-ba8f-a81d017789f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105080777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.105080777
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3030141943
Short name T177
Test name
Test status
Simulation time 13732335603 ps
CPU time 84.88 seconds
Started Jul 05 06:31:44 PM PDT 24
Finished Jul 05 06:33:10 PM PDT 24
Peak memory 267740 kb
Host smart-3839bd05-dbb8-42b6-9dfe-0ab0e5fd34b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030141943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3030141943
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3645719966
Short name T416
Test name
Test status
Simulation time 120180990 ps
CPU time 2.6 seconds
Started Jul 05 06:31:36 PM PDT 24
Finished Jul 05 06:31:39 PM PDT 24
Peak memory 227900 kb
Host smart-d6a5bab2-6b1f-4bfb-87b6-c5815ceaa985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645719966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3645719966
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1613996715
Short name T1019
Test name
Test status
Simulation time 5262185322 ps
CPU time 18.23 seconds
Started Jul 05 06:31:34 PM PDT 24
Finished Jul 05 06:31:52 PM PDT 24
Peak memory 233936 kb
Host smart-78b23ef9-7054-447d-91f5-5b18f4d693dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613996715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1613996715
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3582164902
Short name T679
Test name
Test status
Simulation time 5548695674 ps
CPU time 11.79 seconds
Started Jul 05 06:31:34 PM PDT 24
Finished Jul 05 06:31:46 PM PDT 24
Peak memory 225648 kb
Host smart-8d71ef68-adbf-4cbf-801c-6a7a7b4bc6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582164902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3582164902
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3970819392
Short name T333
Test name
Test status
Simulation time 55379751 ps
CPU time 2.09 seconds
Started Jul 05 06:31:33 PM PDT 24
Finished Jul 05 06:31:35 PM PDT 24
Peak memory 233508 kb
Host smart-075e3d5f-89b7-4ffa-b00c-18bdca99cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970819392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3970819392
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1273927734
Short name T941
Test name
Test status
Simulation time 1993798815 ps
CPU time 7.02 seconds
Started Jul 05 06:31:45 PM PDT 24
Finished Jul 05 06:31:52 PM PDT 24
Peak memory 221428 kb
Host smart-d3767abb-b85f-44f3-8b01-866a2853f93d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273927734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1273927734
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.367138978
Short name T429
Test name
Test status
Simulation time 57733889 ps
CPU time 1.07 seconds
Started Jul 05 06:31:44 PM PDT 24
Finished Jul 05 06:31:46 PM PDT 24
Peak memory 207672 kb
Host smart-938ecaa8-a401-4144-804b-7a8a1fcec239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367138978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.367138978
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3649809000
Short name T303
Test name
Test status
Simulation time 3946574882 ps
CPU time 20.6 seconds
Started Jul 05 06:31:34 PM PDT 24
Finished Jul 05 06:31:55 PM PDT 24
Peak memory 217540 kb
Host smart-ee28d319-3c52-40f7-99d0-16c77543dad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649809000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3649809000
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.453774936
Short name T638
Test name
Test status
Simulation time 785797564 ps
CPU time 3.35 seconds
Started Jul 05 06:31:35 PM PDT 24
Finished Jul 05 06:31:38 PM PDT 24
Peak memory 217404 kb
Host smart-74d3b9de-3361-4bb6-8b3d-12269eeb74c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453774936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.453774936
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.480516305
Short name T742
Test name
Test status
Simulation time 285136847 ps
CPU time 9.31 seconds
Started Jul 05 06:31:44 PM PDT 24
Finished Jul 05 06:31:53 PM PDT 24
Peak memory 217340 kb
Host smart-589e7962-1ec2-46ee-b9bb-541e79272e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480516305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.480516305
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1272885555
Short name T730
Test name
Test status
Simulation time 131459273 ps
CPU time 0.9 seconds
Started Jul 05 06:31:36 PM PDT 24
Finished Jul 05 06:31:37 PM PDT 24
Peak memory 208032 kb
Host smart-03d4f7ea-4015-4053-b0bc-77e40422ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272885555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1272885555
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.343591
Short name T537
Test name
Test status
Simulation time 1367853148 ps
CPU time 9.3 seconds
Started Jul 05 06:31:34 PM PDT 24
Finished Jul 05 06:31:44 PM PDT 24
Peak memory 240412 kb
Host smart-f84cc1ab-4afc-4adc-9a54-ac69f005da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.343591
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1054984625
Short name T825
Test name
Test status
Simulation time 24961963 ps
CPU time 0.74 seconds
Started Jul 05 06:25:55 PM PDT 24
Finished Jul 05 06:25:56 PM PDT 24
Peak memory 205812 kb
Host smart-cdf34100-3790-47a0-a201-a166d2eff1fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054984625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
054984625
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3298861555
Short name T243
Test name
Test status
Simulation time 7702554532 ps
CPU time 7.65 seconds
Started Jul 05 06:25:55 PM PDT 24
Finished Jul 05 06:26:03 PM PDT 24
Peak memory 233892 kb
Host smart-b9bdbb4e-1855-47f3-8333-d6ed8e440fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298861555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3298861555
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.532225097
Short name T540
Test name
Test status
Simulation time 54924263 ps
CPU time 0.77 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:50 PM PDT 24
Peak memory 207572 kb
Host smart-d496104d-4033-4047-a697-3734e391ead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532225097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.532225097
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1499642890
Short name T132
Test name
Test status
Simulation time 177668260 ps
CPU time 0.74 seconds
Started Jul 05 06:25:55 PM PDT 24
Finished Jul 05 06:25:56 PM PDT 24
Peak memory 216960 kb
Host smart-25731fb1-6662-4bde-8dea-db9c08bfb540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499642890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1499642890
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2413485434
Short name T585
Test name
Test status
Simulation time 12133976063 ps
CPU time 84.75 seconds
Started Jul 05 06:25:56 PM PDT 24
Finished Jul 05 06:27:21 PM PDT 24
Peak memory 240008 kb
Host smart-5bb10620-1e9d-47c3-a04b-c4a939b1d354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413485434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2413485434
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2174864290
Short name T945
Test name
Test status
Simulation time 9356517939 ps
CPU time 45.95 seconds
Started Jul 05 06:25:58 PM PDT 24
Finished Jul 05 06:26:44 PM PDT 24
Peak memory 234076 kb
Host smart-23c74581-3186-4d20-b09f-87d337d5dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174864290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2174864290
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1143151056
Short name T128
Test name
Test status
Simulation time 301893488 ps
CPU time 7.9 seconds
Started Jul 05 06:25:56 PM PDT 24
Finished Jul 05 06:26:04 PM PDT 24
Peak memory 233776 kb
Host smart-43d2da66-f4c8-4d01-9ec4-8de39f84d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143151056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1143151056
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2391547992
Short name T460
Test name
Test status
Simulation time 16206559542 ps
CPU time 42.43 seconds
Started Jul 05 06:25:57 PM PDT 24
Finished Jul 05 06:26:39 PM PDT 24
Peak memory 242120 kb
Host smart-314a1313-0211-4e5d-bde0-dc685f8bb1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391547992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2391547992
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1413484499
Short name T201
Test name
Test status
Simulation time 284354609 ps
CPU time 5.43 seconds
Started Jul 05 06:25:54 PM PDT 24
Finished Jul 05 06:26:00 PM PDT 24
Peak memory 233832 kb
Host smart-6ffa1588-ac72-4491-a703-7d40f881f46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413484499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1413484499
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.663438379
Short name T52
Test name
Test status
Simulation time 28909038645 ps
CPU time 56.61 seconds
Started Jul 05 06:25:56 PM PDT 24
Finished Jul 05 06:26:53 PM PDT 24
Peak memory 239228 kb
Host smart-d25d45a5-38eb-4af7-9f68-d31ae656d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663438379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.663438379
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3339643254
Short name T681
Test name
Test status
Simulation time 342686039 ps
CPU time 1.05 seconds
Started Jul 05 06:25:49 PM PDT 24
Finished Jul 05 06:25:51 PM PDT 24
Peak memory 217692 kb
Host smart-b89e20bc-a46d-43d2-8d00-1c9c2cb55776
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339643254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3339643254
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2764724257
Short name T928
Test name
Test status
Simulation time 316191754 ps
CPU time 3.2 seconds
Started Jul 05 06:25:56 PM PDT 24
Finished Jul 05 06:25:59 PM PDT 24
Peak memory 233756 kb
Host smart-760fe182-61f8-4e09-a7ea-802859329988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764724257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2764724257
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.41217705
Short name T999
Test name
Test status
Simulation time 262389670 ps
CPU time 4.51 seconds
Started Jul 05 06:25:56 PM PDT 24
Finished Jul 05 06:26:01 PM PDT 24
Peak memory 233772 kb
Host smart-afd97136-8edf-4396-9a52-758b6ea23e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41217705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.41217705
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1312696669
Short name T960
Test name
Test status
Simulation time 432019918 ps
CPU time 4.51 seconds
Started Jul 05 06:25:55 PM PDT 24
Finished Jul 05 06:25:59 PM PDT 24
Peak memory 224040 kb
Host smart-6dde731f-3685-460d-b028-dfc1cc31f137
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1312696669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1312696669
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1834516792
Short name T19
Test name
Test status
Simulation time 182276480 ps
CPU time 1.06 seconds
Started Jul 05 06:25:58 PM PDT 24
Finished Jul 05 06:25:59 PM PDT 24
Peak memory 207732 kb
Host smart-ad0caf1f-89cd-43ce-af2d-df92ecaac5c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834516792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1834516792
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.138736052
Short name T571
Test name
Test status
Simulation time 2066478395 ps
CPU time 8.63 seconds
Started Jul 05 06:25:54 PM PDT 24
Finished Jul 05 06:26:03 PM PDT 24
Peak memory 217424 kb
Host smart-3f531823-4745-42dd-a39a-481095b7b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138736052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.138736052
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.731405813
Short name T991
Test name
Test status
Simulation time 9234880666 ps
CPU time 7.2 seconds
Started Jul 05 06:25:58 PM PDT 24
Finished Jul 05 06:26:05 PM PDT 24
Peak memory 217536 kb
Host smart-299ea05d-0098-45dc-8905-0032ce20d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731405813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.731405813
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.342303255
Short name T305
Test name
Test status
Simulation time 129586183 ps
CPU time 1.79 seconds
Started Jul 05 06:25:58 PM PDT 24
Finished Jul 05 06:26:00 PM PDT 24
Peak memory 217416 kb
Host smart-dbae61b3-b093-4452-9828-2881f72488bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342303255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.342303255
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1230057262
Short name T987
Test name
Test status
Simulation time 366284761 ps
CPU time 0.96 seconds
Started Jul 05 06:25:55 PM PDT 24
Finished Jul 05 06:25:57 PM PDT 24
Peak memory 207996 kb
Host smart-20330d09-3223-45bb-a94e-1c77a099bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230057262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1230057262
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3287696476
Short name T814
Test name
Test status
Simulation time 166077375 ps
CPU time 3.77 seconds
Started Jul 05 06:25:56 PM PDT 24
Finished Jul 05 06:26:00 PM PDT 24
Peak memory 225580 kb
Host smart-fd670990-3872-451a-be0e-5e8ee0c820b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287696476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3287696476
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2729542146
Short name T653
Test name
Test status
Simulation time 27563604 ps
CPU time 0.72 seconds
Started Jul 05 06:26:10 PM PDT 24
Finished Jul 05 06:26:11 PM PDT 24
Peak memory 206396 kb
Host smart-4fa956c6-b866-4a0c-94d1-32b164880a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729542146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
729542146
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1277939657
Short name T800
Test name
Test status
Simulation time 800375003 ps
CPU time 3.54 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:26:13 PM PDT 24
Peak memory 233768 kb
Host smart-3a51a03d-ba1d-453f-9f55-83350c3d6854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277939657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1277939657
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3713420939
Short name T443
Test name
Test status
Simulation time 24671234 ps
CPU time 0.79 seconds
Started Jul 05 06:26:02 PM PDT 24
Finished Jul 05 06:26:03 PM PDT 24
Peak memory 207544 kb
Host smart-517292b1-b2b0-471a-a1f6-a7d17a616f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713420939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3713420939
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3996005631
Short name T32
Test name
Test status
Simulation time 16569346980 ps
CPU time 126.71 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:28:16 PM PDT 24
Peak memory 258156 kb
Host smart-b1414e25-af37-4b6b-b9ab-c9f16c7e23d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996005631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3996005631
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1497993117
Short name T937
Test name
Test status
Simulation time 6664245216 ps
CPU time 105.25 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:27:54 PM PDT 24
Peak memory 250464 kb
Host smart-b6f1a1b0-1d18-4715-b951-8bdd3e9e6f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497993117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1497993117
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3132484249
Short name T245
Test name
Test status
Simulation time 12221757611 ps
CPU time 40.48 seconds
Started Jul 05 06:26:08 PM PDT 24
Finished Jul 05 06:26:48 PM PDT 24
Peak memory 225852 kb
Host smart-ab7deb47-e2fe-4eea-a4c2-235f9c0b23c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132484249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3132484249
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2861105455
Short name T885
Test name
Test status
Simulation time 127465156 ps
CPU time 4.79 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:26:14 PM PDT 24
Peak memory 234872 kb
Host smart-a79ea6a1-ae02-4996-962f-f5a680ea7863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861105455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2861105455
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1090598432
Short name T938
Test name
Test status
Simulation time 16626281098 ps
CPU time 115.49 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:28:04 PM PDT 24
Peak memory 252348 kb
Host smart-6cce2d0e-5d69-4790-bf6b-cf2d2271d676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090598432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1090598432
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3342679514
Short name T186
Test name
Test status
Simulation time 474660948 ps
CPU time 4.13 seconds
Started Jul 05 06:26:10 PM PDT 24
Finished Jul 05 06:26:15 PM PDT 24
Peak memory 225528 kb
Host smart-f8a0015e-b32d-4a30-a110-889872c008f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342679514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3342679514
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.158125460
Short name T684
Test name
Test status
Simulation time 1089784568 ps
CPU time 12.44 seconds
Started Jul 05 06:26:10 PM PDT 24
Finished Jul 05 06:26:22 PM PDT 24
Peak memory 225548 kb
Host smart-7d43d568-ef4e-49c0-82fb-0f1cd6d1bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158125460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.158125460
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3176751070
Short name T30
Test name
Test status
Simulation time 196821239 ps
CPU time 1.02 seconds
Started Jul 05 06:26:02 PM PDT 24
Finished Jul 05 06:26:03 PM PDT 24
Peak memory 217684 kb
Host smart-bb5f7378-760a-4f42-9739-5f20ad140421
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176751070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3176751070
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.657224190
Short name T642
Test name
Test status
Simulation time 9040589417 ps
CPU time 10.76 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:26:21 PM PDT 24
Peak memory 225744 kb
Host smart-178b874e-4ae4-421e-bf13-8567312ef005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657224190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
657224190
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.118564537
Short name T4
Test name
Test status
Simulation time 1723637778 ps
CPU time 5.03 seconds
Started Jul 05 06:26:11 PM PDT 24
Finished Jul 05 06:26:16 PM PDT 24
Peak memory 233776 kb
Host smart-ea39bd78-5634-492c-8dcb-54bcb1814eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118564537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.118564537
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.843247244
Short name T1008
Test name
Test status
Simulation time 4680639082 ps
CPU time 11.35 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:26:21 PM PDT 24
Peak memory 221684 kb
Host smart-f5e6c2b7-b3ba-400f-8131-ad73fccb79b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=843247244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.843247244
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2643342641
Short name T979
Test name
Test status
Simulation time 401060214934 ps
CPU time 441.13 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:33:31 PM PDT 24
Peak memory 266776 kb
Host smart-4992ec7b-86dd-4697-9f83-9eba256e35c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643342641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2643342641
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3342956417
Short name T425
Test name
Test status
Simulation time 1982886379 ps
CPU time 26.74 seconds
Started Jul 05 06:26:01 PM PDT 24
Finished Jul 05 06:26:28 PM PDT 24
Peak memory 217468 kb
Host smart-365e1481-334c-45af-a174-f398154b82c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342956417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3342956417
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1642276285
Short name T603
Test name
Test status
Simulation time 2736991210 ps
CPU time 8.35 seconds
Started Jul 05 06:26:01 PM PDT 24
Finished Jul 05 06:26:10 PM PDT 24
Peak memory 217556 kb
Host smart-cfb4eb07-2999-4ba6-9cca-78b203d800d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642276285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1642276285
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2917401011
Short name T939
Test name
Test status
Simulation time 100023788 ps
CPU time 1.36 seconds
Started Jul 05 06:26:09 PM PDT 24
Finished Jul 05 06:26:11 PM PDT 24
Peak memory 217368 kb
Host smart-dc58aab7-45b7-41aa-9398-51a361b2ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917401011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2917401011
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4050980756
Short name T640
Test name
Test status
Simulation time 274187201 ps
CPU time 0.81 seconds
Started Jul 05 06:26:02 PM PDT 24
Finished Jul 05 06:26:03 PM PDT 24
Peak memory 206936 kb
Host smart-a4638686-b361-46a4-88f3-631b436ab100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050980756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4050980756
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1288401901
Short name T652
Test name
Test status
Simulation time 277333630 ps
CPU time 2.69 seconds
Started Jul 05 06:26:10 PM PDT 24
Finished Jul 05 06:26:13 PM PDT 24
Peak memory 225596 kb
Host smart-84afe1da-cc02-446c-88f5-dbd4d78c5d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288401901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1288401901
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1603212473
Short name T512
Test name
Test status
Simulation time 15496420 ps
CPU time 0.75 seconds
Started Jul 05 06:26:31 PM PDT 24
Finished Jul 05 06:26:32 PM PDT 24
Peak memory 206716 kb
Host smart-cd331e47-6a90-4a3d-bf22-01aea04bac49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603212473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
603212473
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2750344831
Short name T226
Test name
Test status
Simulation time 141142908 ps
CPU time 2.56 seconds
Started Jul 05 06:26:25 PM PDT 24
Finished Jul 05 06:26:28 PM PDT 24
Peak memory 233724 kb
Host smart-bcba9014-da39-4de9-817e-6bdbb93c7184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750344831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2750344831
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.872906075
Short name T863
Test name
Test status
Simulation time 56604136 ps
CPU time 0.79 seconds
Started Jul 05 06:26:10 PM PDT 24
Finished Jul 05 06:26:11 PM PDT 24
Peak memory 207568 kb
Host smart-0974343a-dfc7-4dac-80fe-a0f94b24c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872906075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.872906075
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.111861211
Short name T463
Test name
Test status
Simulation time 7038793602 ps
CPU time 52.33 seconds
Started Jul 05 06:26:24 PM PDT 24
Finished Jul 05 06:27:17 PM PDT 24
Peak memory 250620 kb
Host smart-6b5351f0-9d01-4315-835a-c91592c4423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111861211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.111861211
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4105164077
Short name T498
Test name
Test status
Simulation time 4803654547 ps
CPU time 20.77 seconds
Started Jul 05 06:26:37 PM PDT 24
Finished Jul 05 06:26:58 PM PDT 24
Peak memory 242156 kb
Host smart-fa5cb2de-8e26-4266-ab7a-f81f14bf8913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105164077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4105164077
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2601683202
Short name T815
Test name
Test status
Simulation time 17228731534 ps
CPU time 56.26 seconds
Started Jul 05 06:26:32 PM PDT 24
Finished Jul 05 06:27:29 PM PDT 24
Peak memory 266820 kb
Host smart-613591c9-75e2-4ca4-a2b6-b2290fcb4e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601683202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2601683202
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1370469039
Short name T297
Test name
Test status
Simulation time 681670694 ps
CPU time 15.03 seconds
Started Jul 05 06:26:25 PM PDT 24
Finished Jul 05 06:26:41 PM PDT 24
Peak memory 250232 kb
Host smart-b71506d4-079b-43f4-9d24-b3668b3ba307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370469039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1370469039
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2154310165
Short name T982
Test name
Test status
Simulation time 67745611952 ps
CPU time 139.45 seconds
Started Jul 05 06:26:26 PM PDT 24
Finished Jul 05 06:28:46 PM PDT 24
Peak memory 257076 kb
Host smart-b9719557-b012-4b35-8459-5f218ec12ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154310165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2154310165
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2311767339
Short name T881
Test name
Test status
Simulation time 723687791 ps
CPU time 2.69 seconds
Started Jul 05 06:26:15 PM PDT 24
Finished Jul 05 06:26:18 PM PDT 24
Peak memory 225596 kb
Host smart-3281efe8-3e1c-4df9-b0dc-bfda0acc3be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311767339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2311767339
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2749408873
Short name T564
Test name
Test status
Simulation time 1824811975 ps
CPU time 27.17 seconds
Started Jul 05 06:26:27 PM PDT 24
Finished Jul 05 06:26:54 PM PDT 24
Peak memory 233772 kb
Host smart-64941af7-7af2-49a1-ac53-7907b79422a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749408873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2749408873
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.696117454
Short name T693
Test name
Test status
Simulation time 65784373 ps
CPU time 1.18 seconds
Started Jul 05 06:26:08 PM PDT 24
Finished Jul 05 06:26:10 PM PDT 24
Peak memory 217704 kb
Host smart-16557b3b-9565-40a1-b296-d3b13d4ed94f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696117454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.696117454
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.561418266
Short name T782
Test name
Test status
Simulation time 39206222 ps
CPU time 2.26 seconds
Started Jul 05 06:26:17 PM PDT 24
Finished Jul 05 06:26:20 PM PDT 24
Peak memory 233512 kb
Host smart-7e2c123b-3004-4492-8361-044acad0f3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561418266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
561418266
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3849581166
Short name T522
Test name
Test status
Simulation time 53015129 ps
CPU time 2.4 seconds
Started Jul 05 06:26:17 PM PDT 24
Finished Jul 05 06:26:20 PM PDT 24
Peak memory 233580 kb
Host smart-4c6e3bba-bb68-4052-9461-9b11a00e857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849581166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3849581166
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3868516098
Short name T763
Test name
Test status
Simulation time 4559074858 ps
CPU time 20.21 seconds
Started Jul 05 06:26:25 PM PDT 24
Finished Jul 05 06:26:46 PM PDT 24
Peak memory 221832 kb
Host smart-4396087b-b4a0-4b65-8cd6-2c8b1a47cadc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3868516098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3868516098
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2342322302
Short name T694
Test name
Test status
Simulation time 27801474750 ps
CPU time 148.2 seconds
Started Jul 05 06:26:32 PM PDT 24
Finished Jul 05 06:29:00 PM PDT 24
Peak memory 250504 kb
Host smart-54fa0a10-980d-4397-8756-86b01cc97edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342322302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2342322302
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1321698099
Short name T372
Test name
Test status
Simulation time 2237555895 ps
CPU time 4.9 seconds
Started Jul 05 06:26:17 PM PDT 24
Finished Jul 05 06:26:22 PM PDT 24
Peak memory 217600 kb
Host smart-86394f6d-4bcc-4790-8a07-b143217c911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321698099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1321698099
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3253526160
Short name T82
Test name
Test status
Simulation time 6790156024 ps
CPU time 9.98 seconds
Started Jul 05 06:26:15 PM PDT 24
Finished Jul 05 06:26:26 PM PDT 24
Peak memory 217536 kb
Host smart-caa12442-64bd-472f-b2fd-849cbf94e135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253526160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3253526160
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3102695372
Short name T542
Test name
Test status
Simulation time 61377437 ps
CPU time 1.89 seconds
Started Jul 05 06:26:16 PM PDT 24
Finished Jul 05 06:26:18 PM PDT 24
Peak memory 217428 kb
Host smart-2f6f5b82-c423-406e-8d4d-d310b979c089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102695372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3102695372
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2514998421
Short name T666
Test name
Test status
Simulation time 21006390 ps
CPU time 0.77 seconds
Started Jul 05 06:26:17 PM PDT 24
Finished Jul 05 06:26:18 PM PDT 24
Peak memory 207004 kb
Host smart-b1393962-eb71-4aee-bed9-8ea111055de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514998421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2514998421
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.765897591
Short name T962
Test name
Test status
Simulation time 486554073 ps
CPU time 2.4 seconds
Started Jul 05 06:26:26 PM PDT 24
Finished Jul 05 06:26:28 PM PDT 24
Peak memory 225620 kb
Host smart-db019972-01d1-49db-81b4-1e2f8503d4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765897591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.765897591
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3828265691
Short name T431
Test name
Test status
Simulation time 73879600 ps
CPU time 0.75 seconds
Started Jul 05 06:26:42 PM PDT 24
Finished Jul 05 06:26:43 PM PDT 24
Peak memory 206740 kb
Host smart-237da858-de36-4705-b9ed-6a84f7cc30a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828265691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
828265691
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.595390740
Short name T173
Test name
Test status
Simulation time 287277637 ps
CPU time 2.25 seconds
Started Jul 05 06:26:37 PM PDT 24
Finished Jul 05 06:26:40 PM PDT 24
Peak memory 225492 kb
Host smart-e214e742-adb2-4918-ac59-38af9e8d791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595390740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.595390740
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1890353271
Short name T56
Test name
Test status
Simulation time 17221456 ps
CPU time 0.79 seconds
Started Jul 05 06:26:37 PM PDT 24
Finished Jul 05 06:26:38 PM PDT 24
Peak memory 206452 kb
Host smart-3697dc7e-7b96-4c2a-9807-c52f93ebe3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890353271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1890353271
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3322904841
Short name T279
Test name
Test status
Simulation time 247866664571 ps
CPU time 330.76 seconds
Started Jul 05 06:26:33 PM PDT 24
Finished Jul 05 06:32:04 PM PDT 24
Peak memory 258416 kb
Host smart-5be5b472-eba0-4d20-8a5e-af7af9ce3fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322904841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3322904841
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1738424677
Short name T267
Test name
Test status
Simulation time 92220992042 ps
CPU time 203.86 seconds
Started Jul 05 06:26:35 PM PDT 24
Finished Jul 05 06:29:59 PM PDT 24
Peak memory 274512 kb
Host smart-c8b5087c-a780-4dbf-b4ca-31ba7448e216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738424677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1738424677
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4148356289
Short name T150
Test name
Test status
Simulation time 14029401415 ps
CPU time 26.54 seconds
Started Jul 05 06:26:36 PM PDT 24
Finished Jul 05 06:27:03 PM PDT 24
Peak memory 225784 kb
Host smart-d9cafacb-a8a1-4d2c-9b38-ba8f722e826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148356289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4148356289
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2702053598
Short name T963
Test name
Test status
Simulation time 530227646 ps
CPU time 4.84 seconds
Started Jul 05 06:26:32 PM PDT 24
Finished Jul 05 06:26:37 PM PDT 24
Peak memory 234916 kb
Host smart-38d3d047-2b1b-4651-842e-84a71b05f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702053598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2702053598
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.131616135
Short name T183
Test name
Test status
Simulation time 563139086 ps
CPU time 6.58 seconds
Started Jul 05 06:26:33 PM PDT 24
Finished Jul 05 06:26:40 PM PDT 24
Peak memory 225568 kb
Host smart-6f699315-08d5-43eb-8082-d27acdc51f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131616135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.131616135
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.26941487
Short name T235
Test name
Test status
Simulation time 6086204399 ps
CPU time 21.88 seconds
Started Jul 05 06:26:32 PM PDT 24
Finished Jul 05 06:26:54 PM PDT 24
Peak memory 233980 kb
Host smart-699d361d-0601-40ef-9b0d-52b7935f39f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26941487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.26941487
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1144563262
Short name T398
Test name
Test status
Simulation time 84509179 ps
CPU time 1.09 seconds
Started Jul 05 06:26:31 PM PDT 24
Finished Jul 05 06:26:32 PM PDT 24
Peak memory 217692 kb
Host smart-efa06ac1-53ee-4fa7-88c7-5ad8b410cc4e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144563262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1144563262
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1353308931
Short name T253
Test name
Test status
Simulation time 1329700807 ps
CPU time 5.24 seconds
Started Jul 05 06:26:33 PM PDT 24
Finished Jul 05 06:26:38 PM PDT 24
Peak memory 233772 kb
Host smart-395d8a24-6efe-4cd2-96f6-c85fe786db95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353308931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1353308931
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3747109408
Short name T767
Test name
Test status
Simulation time 201251333 ps
CPU time 3.25 seconds
Started Jul 05 06:26:32 PM PDT 24
Finished Jul 05 06:26:36 PM PDT 24
Peak memory 233720 kb
Host smart-db5599c2-ffc5-4409-845e-3aa7a9326643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747109408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3747109408
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.202002578
Short name T846
Test name
Test status
Simulation time 1241463357 ps
CPU time 5 seconds
Started Jul 05 06:26:31 PM PDT 24
Finished Jul 05 06:26:37 PM PDT 24
Peak memory 220804 kb
Host smart-84ab8ed8-3c2f-43df-8c3d-4a8e913ce559
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202002578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.202002578
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3068283825
Short name T690
Test name
Test status
Simulation time 43182426 ps
CPU time 0.98 seconds
Started Jul 05 06:26:38 PM PDT 24
Finished Jul 05 06:26:39 PM PDT 24
Peak memory 207900 kb
Host smart-463f2954-0542-41a3-bdc5-13ac0532a4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068283825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3068283825
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3221365705
Short name T973
Test name
Test status
Simulation time 31726974 ps
CPU time 0.71 seconds
Started Jul 05 06:26:31 PM PDT 24
Finished Jul 05 06:26:32 PM PDT 24
Peak memory 206696 kb
Host smart-01478373-32ce-44b6-9367-c39ea7c36c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221365705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3221365705
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1314282534
Short name T499
Test name
Test status
Simulation time 822941839 ps
CPU time 5.76 seconds
Started Jul 05 06:26:30 PM PDT 24
Finished Jul 05 06:26:37 PM PDT 24
Peak memory 217252 kb
Host smart-423add37-e4ca-47da-8576-a730faa111cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314282534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1314282534
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1623539400
Short name T753
Test name
Test status
Simulation time 129669789 ps
CPU time 0.67 seconds
Started Jul 05 06:26:31 PM PDT 24
Finished Jul 05 06:26:32 PM PDT 24
Peak memory 206556 kb
Host smart-c3749cf4-ee9b-4c9f-be02-74d873b1ac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623539400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1623539400
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1219511805
Short name T408
Test name
Test status
Simulation time 37071662 ps
CPU time 0.89 seconds
Started Jul 05 06:26:32 PM PDT 24
Finished Jul 05 06:26:33 PM PDT 24
Peak memory 208044 kb
Host smart-b9d46463-b429-4cfa-b3c0-c13ea7a9b9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219511805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1219511805
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.519333265
Short name T426
Test name
Test status
Simulation time 1284294559 ps
CPU time 5.09 seconds
Started Jul 05 06:26:33 PM PDT 24
Finished Jul 05 06:26:39 PM PDT 24
Peak memory 225516 kb
Host smart-3ee366bd-0ca7-49eb-b109-a9b31a8e19d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519333265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.519333265
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1708285215
Short name T59
Test name
Test status
Simulation time 12100471 ps
CPU time 0.71 seconds
Started Jul 05 06:26:41 PM PDT 24
Finished Jul 05 06:26:42 PM PDT 24
Peak memory 206420 kb
Host smart-602ed9ad-8ba3-4606-b2e5-c4616f8ae77b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708285215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
708285215
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3342386944
Short name T528
Test name
Test status
Simulation time 162541350 ps
CPU time 4.05 seconds
Started Jul 05 06:26:41 PM PDT 24
Finished Jul 05 06:26:45 PM PDT 24
Peak memory 233788 kb
Host smart-11fa43a4-7e47-42f0-941a-0d85b4506c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342386944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3342386944
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3702915823
Short name T446
Test name
Test status
Simulation time 31784006 ps
CPU time 0.77 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:26:41 PM PDT 24
Peak memory 206860 kb
Host smart-b2aa5063-26f1-4e83-b680-ec29bde1782b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702915823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3702915823
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3603060580
Short name T445
Test name
Test status
Simulation time 458931011 ps
CPU time 6.39 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:26:47 PM PDT 24
Peak memory 250184 kb
Host smart-6789360f-6294-4756-bb7d-d138619b9e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603060580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3603060580
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.345605972
Short name T1014
Test name
Test status
Simulation time 35143034853 ps
CPU time 134.49 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:28:54 PM PDT 24
Peak memory 254528 kb
Host smart-813961a2-8649-4781-83e9-5aa7a06dd852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345605972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.345605972
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1574149458
Short name T291
Test name
Test status
Simulation time 6289465710 ps
CPU time 30.27 seconds
Started Jul 05 06:26:42 PM PDT 24
Finished Jul 05 06:27:13 PM PDT 24
Peak memory 242124 kb
Host smart-05420936-15da-44f2-8180-62f3a3829787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574149458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1574149458
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.4292032157
Short name T423
Test name
Test status
Simulation time 11003207685 ps
CPU time 85.07 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:28:06 PM PDT 24
Peak memory 264116 kb
Host smart-e9962d92-9f72-45b6-a537-4cf73b9054c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292032157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.4292032157
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2117718332
Short name T744
Test name
Test status
Simulation time 14652149765 ps
CPU time 10.39 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:26:51 PM PDT 24
Peak memory 233896 kb
Host smart-8f702489-abae-450b-9d65-04fcaa50d101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117718332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2117718332
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4065762861
Short name T743
Test name
Test status
Simulation time 6509730000 ps
CPU time 53.14 seconds
Started Jul 05 06:26:42 PM PDT 24
Finished Jul 05 06:27:35 PM PDT 24
Peak memory 236836 kb
Host smart-73b508d4-9a51-42fa-96d6-0765550b7575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065762861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4065762861
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.15715283
Short name T131
Test name
Test status
Simulation time 106555114 ps
CPU time 1.09 seconds
Started Jul 05 06:26:38 PM PDT 24
Finished Jul 05 06:26:40 PM PDT 24
Peak memory 217712 kb
Host smart-ec88b3bd-c05e-4fa4-bd83-51945d21cd0d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15715283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.15715283
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1907983839
Short name T819
Test name
Test status
Simulation time 379628612 ps
CPU time 5.32 seconds
Started Jul 05 06:26:41 PM PDT 24
Finished Jul 05 06:26:47 PM PDT 24
Peak memory 241028 kb
Host smart-13c2cd79-b55d-4182-8248-38182e95e5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907983839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1907983839
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1792179783
Short name T552
Test name
Test status
Simulation time 220478691 ps
CPU time 3.96 seconds
Started Jul 05 06:26:41 PM PDT 24
Finished Jul 05 06:26:46 PM PDT 24
Peak memory 233812 kb
Host smart-90bb880e-8f23-4eff-89b1-cb1d44a2e343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792179783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1792179783
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1801457382
Short name T524
Test name
Test status
Simulation time 1135910305 ps
CPU time 6.83 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:26:47 PM PDT 24
Peak memory 223188 kb
Host smart-a28d34e0-0176-4ca1-a712-0665b8ad3ea4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1801457382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1801457382
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1861920605
Short name T271
Test name
Test status
Simulation time 52370491312 ps
CPU time 510.1 seconds
Started Jul 05 06:26:40 PM PDT 24
Finished Jul 05 06:35:11 PM PDT 24
Peak memory 284400 kb
Host smart-6d34abcb-e9ad-4c8e-a0ff-7d03087123d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861920605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1861920605
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3044144026
Short name T496
Test name
Test status
Simulation time 41907353927 ps
CPU time 52.79 seconds
Started Jul 05 06:26:42 PM PDT 24
Finished Jul 05 06:27:35 PM PDT 24
Peak memory 217516 kb
Host smart-62aca20c-3d82-4294-a55b-d9cec4eb7cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044144026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3044144026
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3009818799
Short name T136
Test name
Test status
Simulation time 13373503 ps
CPU time 0.72 seconds
Started Jul 05 06:26:41 PM PDT 24
Finished Jul 05 06:26:42 PM PDT 24
Peak memory 206672 kb
Host smart-6b237594-b7d9-4ef5-920f-8edac745d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009818799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3009818799
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2518316854
Short name T353
Test name
Test status
Simulation time 23664937 ps
CPU time 0.92 seconds
Started Jul 05 06:26:44 PM PDT 24
Finished Jul 05 06:26:45 PM PDT 24
Peak memory 208028 kb
Host smart-8a4869d0-1381-43bc-b352-f4425e61343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518316854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2518316854
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.606342890
Short name T878
Test name
Test status
Simulation time 207885000 ps
CPU time 1.04 seconds
Started Jul 05 06:26:39 PM PDT 24
Finished Jul 05 06:26:41 PM PDT 24
Peak memory 208028 kb
Host smart-4f600b18-0813-42f4-8a48-831e4c47804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606342890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.606342890
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4102444812
Short name T760
Test name
Test status
Simulation time 19520399364 ps
CPU time 17 seconds
Started Jul 05 06:26:39 PM PDT 24
Finished Jul 05 06:26:57 PM PDT 24
Peak memory 240580 kb
Host smart-057ad0dc-b24a-406d-9850-c99fd7084bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102444812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4102444812
Directory /workspace/9.spi_device_upload/latest
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