Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2563874	1			T1	3604		T2	1		T3	1
all_values[1]	2563874	1			T1	3604		T2	1		T3	1
all_values[2]	2563874	1			T1	3604		T2	1		T3	1
all_values[3]	2563874	1			T1	3604		T2	1		T3	1
all_values[4]	2563874	1			T1	3604		T2	1		T3	1
all_values[5]	2563874	1			T1	3604		T2	1		T3	1
all_values[6]	2563874	1			T1	3604		T2	1		T3	1
all_values[7]	2563874	1			T1	3604		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20299280

1

T1

28832

T2

8

T3

8

auto[1]

211712

1

T15

139

T17

93

T18

2590

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20482393

1

T1

28832

T2

8

T3

8

auto[1]

28599

1

T7

76

T12

250

T15

101

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2544517	1			T1	3604		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13249	1			T7	38		T12	98		T15	3
all_values[0]	auto[1]	auto[0]	5688	1			T15	13		T17	4		T18	1
all_values[0]	auto[1]	auto[1]	420	1			T15	8		T17	7		T19	2
all_values[1]	auto[0]	auto[0]	2550397	1			T1	3604		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	9044	1			T7	38		T12	97		T15	8
all_values[1]	auto[1]	auto[0]	4142	1			T15	10		T17	6		T18	1
all_values[1]	auto[1]	auto[1]	291	1			T15	5		T17	4		T19	2
all_values[2]	auto[0]	auto[0]	2555481	1			T1	3604		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3347	1			T12	55		T15	5		T57	40
all_values[2]	auto[1]	auto[0]	4818	1			T15	9		T17	7		T18	641
all_values[2]	auto[1]	auto[1]	228	1			T15	7		T17	2		T18	6
all_values[3]	auto[0]	auto[0]	2543197	1			T1	3604		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	238	1			T15	7		T17	13		T19	3
all_values[3]	auto[1]	auto[0]	20246	1			T15	13		T17	4		T18	645
all_values[3]	auto[1]	auto[1]	193	1			T15	9		T17	3		T18	1
all_values[4]	auto[0]	auto[0]	2527878	1			T1	3604		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	194	1			T15	4		T17	4		T19	3
all_values[4]	auto[1]	auto[0]	35590	1			T15	10		T17	11		T18	646
all_values[4]	auto[1]	auto[1]	212	1			T15	10		T17	4		T19	2
all_values[5]	auto[0]	auto[0]	2560554	1			T1	3604		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	184	1			T15	5		T17	6		T19	2
all_values[5]	auto[1]	auto[0]	2958	1			T15	7		T17	10		T18	646
all_values[5]	auto[1]	auto[1]	178	1			T15	6		T17	4		T19	3
all_values[6]	auto[0]	auto[0]	2449072	1			T1	3604		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	195	1			T15	2		T17	1		T18	1
all_values[6]	auto[1]	auto[0]	114386	1			T15	13		T17	4		T18	1
all_values[6]	auto[1]	auto[1]	221	1			T15	5		T17	11		T19	2
all_values[7]	auto[0]	auto[0]	2541513	1			T1	3604		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	220	1			T15	10		T17	7		T19	2
all_values[7]	auto[1]	auto[0]	21956	1			T15	7		T17	6		T18	2
all_values[7]	auto[1]	auto[1]	185	1			T15	7		T17	6		T19	4