Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35018	1			T1	75		T4	70		T5	6
auto[SpiFlashAddrCfg]	7630	1			T1	30		T4	36		T5	4
auto[SpiFlashAddr3b]	9372	1			T1	54		T4	41		T5	4
auto[SpiFlashAddr4b]	7924	1			T1	41		T4	33		T5	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33649

1

T1

101

T4

104

T5

20

auto[1]

26295

1

T1

99

T4

76

T7

30

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31923

1

T1

123

T4

100

T5

6

auto[1]

28021

1

T1

77

T4

80

T5

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39945	1			T1	101		T4	86		T5	10
values[1]	1101	1			T1	4		T4	5		T7	4
values[2]	1499	1			T1	8		T4	2		T12	4
values[3]	1389	1			T1	6		T4	5		T7	4
values[4]	1400	1			T1	3		T4	11		T5	2
values[5]	1440	1			T1	4		T4	14		T7	2
values[6]	1429	1			T1	7		T4	10		T12	1
values[7]	1534	1			T1	7		T4	6		T7	2
values[8]	10207	1			T1	60		T4	41		T5	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31412

1

T1

200

T4

180

T5

20

auto[1]

28532

1

T7

78

T47

1

T45

53

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56578

1

T1

194

T4

166

T5

14

write

3366

1

T1

6

T4

14

T5

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19589

1

T1

102

T4

100

T5

6

valids[0x1]

40355

1

T1

98

T4

80

T5

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1635	1			T1	6		T4	4		T5	2
internal_process_ops[0x5a]	1591	1			T1	7		T4	3		T7	2
internal_process_ops[0x05]	20906	1			T1	6		T4	5		T5	2
internal_process_ops[0x35]	1591	1			T1	8		T4	5		T7	5
internal_process_ops[0x15]	1592	1			T1	4		T4	7		T7	4
internal_process_ops[0x03]	1120	1			T1	11		T4	6		T5	2
internal_process_ops[0x0b]	1103	1			T1	9		T4	6		T5	2
internal_process_ops[0x3b]	1077	1			T1	9		T4	8		T5	2
internal_process_ops[0x6b]	1085	1			T1	5		T4	2		T7	1
internal_process_ops[0xbb]	1112	1			T1	7		T4	3		T7	1
internal_process_ops[0xeb]	1104	1			T1	7		T4	7		T5	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58291

1

T1

195

T4

174

T5

20

auto[1]

1653

1

T1

5

T4

6

T7

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57544

1

T1

192

T4

168

T5

20

auto[1]

2400

1

T1

8

T4

12

T7

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9657

1

T1

51

T4

46

T5

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7260

1

T1

22

T4

18

T12

28

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2062

1

T1

14

T4

18

T5

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1838

1

T1

15

T4

16

T8

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2541

1

T1

21

T4

19

T12

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2235

1

T1

31

T4

19

T8

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2233

1

T1

14

T4

15

T5

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1915

1

T1

26

T4

15

T8

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

104

1

T4

2

T5

2

T12

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T4

1

T12

1

T54

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

100

1

T1

1

T46

1

T54

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

106

1

T1

1

T4

3

T46

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

98

1

T53

1

T54

3

T163

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

91

1

T54

6

T55

1

T86

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

93

1

T4

1

T12

3

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

98

1

T1

1

T4

1

T52

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

131

1

T4

2

T5

4

T13

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T1

1

T4

1

T46

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

101

1

T34

1

T46

1

T51

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

117

1

T1

1

T12

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

135

1

T13

6

T51

4

T164

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

96

1

T12

3

T46

1

T56

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

110

1

T4

3

T12

2

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T1

1

T12

1

T46

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10676

1

T7

36

T45

10

T44

117

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6649

1

T7

9

T45

18

T44

40

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1485

1

T7

5

T47

1

T45

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1442

1

T7

10

T45

7

T44

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1868

1

T7

4

T45

3

T44

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1828

1

T7

6

T45

1

T44

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1442

1

T45

2

T44

14

T25

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1447

1

T7

3

T45

3

T44

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

78

1

T25

1

T39

1

T165

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T25

1

T39

1

T94

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

82

1

T7

1

T44

1

T25

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

111

1

T44

1

T25

3

T165

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

115

1

T44

2

T25

1

T26

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

107

1

T165

3

T85

3

T94

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

97

1

T45

1

T85

1

T166

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

104

1

T44

2

T25

2

T57

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

115

1

T7

1

T44

1

T25

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

103

1

T7

2

T44

1

T26

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

127

1

T45

1

T85

1

T94

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

109

1

T25

1

T57

2

T165

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

109

1

T25

1

T165

2

T167

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

111

1

T165

2

T85

1

T168

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

118

1

T45

1

T25

2

T39

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T7

1

T57

2

T39

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3980	1			T1	46		T4	40		T11	6
auto[0]	values[0]	valids[0x1]	16005	1			T1	55		T4	46		T5	10
auto[0]	values[1]	valids[0x1]	572	1			T1	4		T4	5		T12	4
auto[0]	values[2]	valids[0x0]	565	1			T1	5		T4	1		T12	2
auto[0]	values[2]	valids[0x1]	305	1			T1	3		T4	1		T12	2
auto[0]	values[3]	valids[0x0]	497	1			T1	4		T4	4		T12	6
auto[0]	values[3]	valids[0x1]	293	1			T1	2		T4	1		T12	2
auto[0]	values[4]	valids[0x0]	467	1			T1	1		T4	8		T10	4
auto[0]	values[4]	valids[0x1]	276	1			T1	2		T4	3		T5	2
auto[0]	values[5]	valids[0x0]	518	1			T4	8		T12	1		T34	5
auto[0]	values[5]	valids[0x1]	281	1			T1	4		T4	6		T46	2
auto[0]	values[6]	valids[0x0]	534	1			T1	3		T4	5		T12	1
auto[0]	values[6]	valids[0x1]	301	1			T1	4		T4	5		T95	2
auto[0]	values[7]	valids[0x0]	573	1			T1	4		T4	5		T12	2
auto[0]	values[7]	valids[0x1]	325	1			T1	3		T4	1		T8	2
auto[0]	values[8]	valids[0x0]	3714	1			T1	39		T4	29		T5	6
auto[0]	values[8]	valids[0x1]	2206	1			T1	21		T4	12		T5	2
auto[1]	values[0]	valids[0x0]	3952	1			T7	11		T45	11		T44	38
auto[1]	values[0]	valids[0x1]	16008	1			T7	39		T45	24		T44	123
auto[1]	values[1]	valids[0x1]	529	1			T7	4		T45	5		T44	2
auto[1]	values[2]	valids[0x0]	357	1			T45	1		T44	2		T57	1
auto[1]	values[2]	valids[0x1]	272	1			T44	1		T26	3		T57	1
auto[1]	values[3]	valids[0x0]	337	1			T45	2		T44	5		T25	11
auto[1]	values[3]	valids[0x1]	262	1			T7	4		T45	1		T44	9
auto[1]	values[4]	valids[0x0]	414	1			T7	2		T44	3		T25	1
auto[1]	values[4]	valids[0x1]	243	1			T7	1		T44	2		T25	2
auto[1]	values[5]	valids[0x0]	392	1			T44	7		T25	1		T165	6
auto[1]	values[5]	valids[0x1]	249	1			T7	2		T25	9		T165	1
auto[1]	values[6]	valids[0x0]	369	1			T45	3		T44	3		T25	6
auto[1]	values[6]	valids[0x1]	225	1			T44	4		T25	12		T26	2
auto[1]	values[7]	valids[0x0]	377	1			T7	2		T44	2		T25	3
auto[1]	values[7]	valids[0x1]	259	1			T44	8		T25	3		T57	4
auto[1]	values[8]	valids[0x0]	2543	1			T7	9		T47	1		T45	6
auto[1]	values[8]	valids[0x1]	1744	1			T7	4		T44	10		T25	18