Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3476745

1

T1

13562

T4

16836

T5

1

auto[1]

33312

1

T1

37

T4

419

T7

18

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

963577

1

T1

450

T4

412

T5

1

auto[1]

2546480

1

T1

13149

T4

16843

T7

2024

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	707928	1			T1	583		T4	3353		T5	1
auto[524288:1048575]	398139	1			T1	2995		T4	311		T7	1112
auto[1048576:1572863]	393694	1			T1	40		T4	2473		T7	14
auto[1572864:2097151]	460912	1			T1	3624		T4	4680		T7	6
auto[2097152:2621439]	395657	1			T1	3051		T4	25		T12	3244
auto[2621440:3145727]	440688	1			T1	35		T4	3147		T7	95
auto[3145728:3670015]	337042	1			T1	13		T4	3266		T7	515
auto[3670016:4194303]	375997	1			T1	3258		T7	176		T10	477

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2581155

1

T1

13592

T4

17250

T5

1

auto[1]

928902

1

T1

7

T4

5

T10

1463

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2985602

1

T1

13217

T4

13552

T5

1

auto[1]

524455

1

T1

382

T4

3703

T12

4

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	228302	1			T1	36		T4	65		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	399918	1			T1	517		T4	2494		T7	128
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	129361	1			T1	18		T4	36		T7	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	186302	1			T1	2974		T4	256		T7	1108
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	90643	1			T1	34		T4	17		T7	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	229385	1			T4	2449		T7	1		T12	2973
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	105143	1			T1	94		T4	44		T7	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	278788	1			T1	3504		T4	4424		T7	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	101892	1			T1	46		T4	9		T44	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	228514	1			T1	2997		T12	3244		T25	2124
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	96373	1			T1	22		T4	8		T12	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	277095	1			T4	256		T7	95		T12	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	92233	1			T1	2		T4	85		T7	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	183923	1			T4	3006		T7	512		T12	3780
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	104722	1			T1	46		T7	7		T10	477
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	226470	1			T1	2893		T7	165		T12	2754
auto[0]	auto[1]	auto[0:524287]	auto[0]	1837	1			T1	23		T4	12		T44	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	72318	1			T4	768		T44	929		T25	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1994	1			T1	3		T4	4		T25	69
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	77468	1			T25	1146		T34	4		T54	1400
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	700	1			T4	2		T45	1		T44	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	67649	1			T44	1		T25	128		T34	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1453	1			T1	21		T4	12		T25	8
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	71042	1			T1	3		T12	4		T25	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1645	1			T1	8		T4	1		T44	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59555	1			T25	640		T57	1		T54	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2024	1			T4	22		T25	13		T34	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	61911	1			T4	2859		T25	128		T46	7
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	602	1			T1	11		T4	7		T25	21
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	56615	1			T34	512		T46	810		T165	458
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	542	1			T1	49		T44	2		T25	16
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40326	1			T1	261		T44	1		T165	2527
auto[1]	auto[0]	auto[0:524287]	auto[0]	544	1			T1	7		T4	2		T25	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	4430	1			T26	1		T46	10		T164	22
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	416	1			T4	11		T44	1		T34	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1789	1			T44	7		T34	39		T46	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	396	1			T1	6		T4	5		T7	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3188	1			T7	10		T12	2		T45	12
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	416	1			T1	2		T4	3		T7	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3188	1			T4	197		T7	2		T44	56
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	432	1			T4	15		T25	6		T57	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2668	1			T57	2		T46	2		T54	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	432	1			T1	13		T4	2		T12	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2382	1			T12	2		T46	35		T54	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	351	1			T4	34		T12	4		T25	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2488	1			T4	134		T12	3		T54	11
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	351	1			T1	6		T7	2		T12	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3067	1			T7	2		T12	1		T46	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	117	1			T4	12		T57	1		T40	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	462	1			T40	4		T226	11		T230	26
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	108	1			T4	4		T25	5		T51	7
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	701	1			T56	2		T20	9		T129	11
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	99	1			T44	1		T54	2		T39	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1634	1			T44	8		T54	6		T39	14
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	109	1			T51	17		T54	1		T167	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	773	1			T51	4		T54	2		T86	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	105	1			T85	1		T94	4		T86	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	846	1			T86	8		T224	63		T35	60
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	83	1			T46	2		T165	2		T41	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	388	1			T46	1		T165	1		T41	52
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	70	1			T25	3		T165	3		T86	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	760	1			T165	2		T86	16		T231	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	82	1			T1	3		T44	1		T51	15
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	437	1			T44	5		T51	6		T166	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2036309	1			T1	13183		T4	13149		T5	1
auto[0]	auto[0]	auto[1]	922755	1			T10	1463		T11	123		T47	414
auto[0]	auto[1]	auto[0]	512217	1			T1	379		T4	3687		T12	4
auto[0]	auto[1]	auto[1]	5464	1			T44	2		T232	3		T165	1
auto[1]	auto[0]	auto[0]	25990	1			T1	28		T4	398		T7	18
auto[1]	auto[0]	auto[1]	548	1			T1	6		T4	5		T12	1
auto[1]	auto[1]	auto[0]	6639	1			T1	2		T4	16		T44	14
auto[1]	auto[1]	auto[1]	135	1			T1	1		T44	1		T25	1