Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2563874	1			T1	3604		T2	1		T3	1
all_pins[1]	2563874	1			T1	3604		T2	1		T3	1
all_pins[2]	2563874	1			T1	3604		T2	1		T3	1
all_pins[3]	2563874	1			T1	3604		T2	1		T3	1
all_pins[4]	2563874	1			T1	3604		T2	1		T3	1
all_pins[5]	2563874	1			T1	3604		T2	1		T3	1
all_pins[6]	2563874	1			T1	3604		T2	1		T3	1
all_pins[7]	2563874	1			T1	3604		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20394543	1			T1	28832		T2	8		T3	8
values[0x1]	116449	1			T15	57		T17	41		T18	109
transitions[0x0=>0x1]	115552	1			T15	44		T17	34		T18	108
transitions[0x1=>0x0]	115565	1			T15	44		T17	34		T18	108

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2563437	1			T1	3604		T2	1		T3	1
all_pins[0]	values[0x1]	437	1			T15	8		T17	7		T19	2
all_pins[0]	transitions[0x0=>0x1]	283	1			T15	8		T17	5		T19	2
all_pins[0]	transitions[0x1=>0x0]	143	1			T15	5		T17	2		T19	2
all_pins[1]	values[0x0]	2563577	1			T1	3604		T2	1		T3	1
all_pins[1]	values[0x1]	297	1			T15	5		T17	4		T19	2
all_pins[1]	transitions[0x0=>0x1]	201	1			T15	2		T17	4		T19	2
all_pins[1]	transitions[0x1=>0x0]	136	1			T15	4		T17	2		T18	8
all_pins[2]	values[0x0]	2563642	1			T1	3604		T2	1		T3	1
all_pins[2]	values[0x1]	232	1			T15	7		T17	2		T18	8
all_pins[2]	transitions[0x0=>0x1]	192	1			T15	6		T17	2		T18	7
all_pins[2]	transitions[0x1=>0x0]	153	1			T15	8		T17	3		T20	4
all_pins[3]	values[0x0]	2563681	1			T1	3604		T2	1		T3	1
all_pins[3]	values[0x1]	193	1			T15	9		T17	3		T18	1
all_pins[3]	transitions[0x0=>0x1]	143	1			T15	9		T17	3		T18	1
all_pins[3]	transitions[0x1=>0x0]	162	1			T15	10		T17	4		T19	2
all_pins[4]	values[0x0]	2563662	1			T1	3604		T2	1		T3	1
all_pins[4]	values[0x1]	212	1			T15	10		T17	4		T19	2
all_pins[4]	transitions[0x0=>0x1]	162	1			T15	6		T17	4		T20	1
all_pins[4]	transitions[0x1=>0x0]	597	1			T15	2		T17	4		T18	100
all_pins[5]	values[0x0]	2563227	1			T1	3604		T2	1		T3	1
all_pins[5]	values[0x1]	647	1			T15	6		T17	4		T18	100
all_pins[5]	transitions[0x0=>0x1]	243	1			T15	6		T17	2		T18	100
all_pins[5]	transitions[0x1=>0x0]	113842	1			T15	5		T17	9		T19	2
all_pins[6]	values[0x0]	2449628	1			T1	3604		T2	1		T3	1
all_pins[6]	values[0x1]	114246	1			T15	5		T17	11		T19	2
all_pins[6]	transitions[0x0=>0x1]	114202	1			T15	3		T17	10		T19	1
all_pins[6]	transitions[0x1=>0x0]	141	1			T15	5		T17	5		T19	3
all_pins[7]	values[0x0]	2563689	1			T1	3604		T2	1		T3	1
all_pins[7]	values[0x1]	185	1			T15	7		T17	6		T19	4
all_pins[7]	transitions[0x0=>0x1]	126	1			T15	4		T17	4		T19	3
all_pins[7]	transitions[0x1=>0x0]	391	1			T15	5		T17	5		T19	1