Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17348

1

T1

101

T4

104

T5

20

auto[1]

14064

1

T1

99

T4

76

T8

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3511	1			T10	4		T13	22		T46	65
values[1]	3885	1			T12	43		T34	20		T46	46
values[2]	4080	1			T5	20		T95	14		T34	24
values[3]	3986	1			T1	20		T4	40		T12	24
values[4]	3635	1			T1	40		T4	20		T34	23
values[5]	3842	1			T1	40		T4	40		T8	8
values[6]	4140	1			T1	20		T4	40		T11	6
values[7]	4333	1			T1	80		T4	40		T12	70

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3811	1			T1	20		T8	8		T12	50
values[1]	3832	1			T4	20		T34	60		T46	48
values[2]	3745	1			T4	40		T12	23		T14	10
values[3]	3971	1			T1	40		T4	20		T12	24
values[4]	3999	1			T1	60		T12	20		T34	24
values[5]	4086	1			T1	40		T4	40		T5	20
values[6]	3978	1			T1	20		T4	20		T11	6
values[7]	3990	1			T1	20		T4	40		T34	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	209	1			T46	16		T20	7		T41	9
auto[0]	values[0]	values[1]	231	1			T53	12		T18	16		T198	16
auto[0]	values[0]	values[2]	210	1			T54	10		T20	13		T183	12
auto[0]	values[0]	values[3]	134	1			T46	17		T54	23		T36	4
auto[0]	values[0]	values[4]	353	1			T51	26		T54	39		T210	14
auto[0]	values[0]	values[5]	272	1			T10	4		T233	20		T218	14
auto[0]	values[0]	values[6]	293	1			T13	22		T164	38		T54	9
auto[0]	values[0]	values[7]	315	1			T46	12		T20	11		T198	14
auto[0]	values[1]	values[0]	356	1			T12	15		T56	15		T86	43
auto[0]	values[1]	values[1]	147	1			T86	7		T87	11		T234	14
auto[0]	values[1]	values[2]	287	1			T51	17		T55	51		T86	17
auto[0]	values[1]	values[3]	254	1			T35	26		T184	10		T235	2
auto[0]	values[1]	values[4]	264	1			T86	9		T130	26		T189	5
auto[0]	values[1]	values[5]	352	1			T46	10		T53	7		T236	4
auto[0]	values[1]	values[6]	258	1			T12	7		T82	8		T40	5
auto[0]	values[1]	values[7]	231	1			T34	9		T46	7		T86	45
auto[0]	values[2]	values[0]	257	1			T95	14		T41	19		T226	24
auto[0]	values[2]	values[1]	261	1			T182	2		T55	12		T56	55
auto[0]	values[2]	values[2]	345	1			T237	2		T186	79		T226	92
auto[0]	values[2]	values[3]	384	1			T53	32		T54	32		T186	14
auto[0]	values[2]	values[4]	283	1			T34	8		T40	13		T192	12
auto[0]	values[2]	values[5]	329	1			T5	20		T238	4		T20	11
auto[0]	values[2]	values[6]	388	1			T55	5		T239	4		T20	12
auto[0]	values[2]	values[7]	146	1			T46	15		T54	16		T186	12
auto[0]	values[3]	values[0]	365	1			T51	14		T55	33		T215	11
auto[0]	values[3]	values[1]	161	1			T55	14		T56	14		T226	12
auto[0]	values[3]	values[2]	229	1			T54	23		T56	51		T86	12
auto[0]	values[3]	values[3]	211	1			T4	11		T12	7		T240	10
auto[0]	values[3]	values[4]	273	1			T1	13		T241	4		T20	12
auto[0]	values[3]	values[5]	253	1			T40	13		T185	26		T65	14
auto[0]	values[3]	values[6]	165	1			T19	20		T198	16		T215	17
auto[0]	values[3]	values[7]	323	1			T4	11		T92	2		T51	19
auto[0]	values[4]	values[0]	283	1			T40	20		T86	8		T240	10
auto[0]	values[4]	values[1]	127	1			T86	5		T221	6		T199	16
auto[0]	values[4]	values[2]	337	1			T86	10		T218	10		T87	11
auto[0]	values[4]	values[3]	205	1			T34	11		T96	16		T214	14
auto[0]	values[4]	values[4]	324	1			T51	7		T93	12		T242	2
auto[0]	values[4]	values[5]	147	1			T1	7		T243	12		T87	12
auto[0]	values[4]	values[6]	350	1			T46	13		T186	36		T86	19
auto[0]	values[4]	values[7]	398	1			T1	12		T4	17		T190	18
auto[0]	values[5]	values[0]	332	1			T51	12		T244	2		T40	10
auto[0]	values[5]	values[1]	353	1			T34	11		T46	18		T215	14
auto[0]	values[5]	values[2]	157	1			T4	9		T183	12		T198	12
auto[0]	values[5]	values[3]	268	1			T1	10		T55	10		T56	10
auto[0]	values[5]	values[4]	241	1			T1	9		T51	23		T56	52
auto[0]	values[5]	values[5]	311	1			T53	14		T217	16		T198	27
auto[0]	values[5]	values[6]	244	1			T4	9		T35	13		T245	8
auto[0]	values[5]	values[7]	204	1			T20	10		T36	9		T136	11
auto[0]	values[6]	values[0]	179	1			T56	16		T246	20		T87	35
auto[0]	values[6]	values[1]	376	1			T4	12		T51	11		T54	8
auto[0]	values[6]	values[2]	301	1			T220	8		T191	67		T20	9
auto[0]	values[6]	values[3]	304	1			T1	11		T46	55		T209	24
auto[0]	values[6]	values[4]	235	1			T51	9		T186	6		T177	69
auto[0]	values[6]	values[5]	342	1			T4	14		T86	16		T20	23
auto[0]	values[6]	values[6]	259	1			T11	6		T186	12		T247	4
auto[0]	values[6]	values[7]	309	1			T232	14		T41	11		T215	18
auto[0]	values[7]	values[0]	244	1			T1	10		T12	16		T51	12
auto[0]	values[7]	values[1]	330	1			T46	12		T53	28		T20	15
auto[0]	values[7]	values[2]	269	1			T4	12		T12	17		T54	27
auto[0]	values[7]	values[3]	377	1			T34	9		T51	9		T40	32
auto[0]	values[7]	values[4]	304	1			T1	10		T12	8		T36	10
auto[0]	values[7]	values[5]	266	1			T1	10		T4	9		T50	10
auto[0]	values[7]	values[6]	251	1			T1	9		T56	11		T183	17
auto[0]	values[7]	values[7]	182	1			T55	9		T183	13		T248	10
auto[1]	values[0]	values[0]	148	1			T46	4		T20	17		T41	11
auto[1]	values[0]	values[1]	188	1			T53	8		T18	12		T198	11
auto[1]	values[0]	values[2]	124	1			T54	10		T20	7		T183	8
auto[1]	values[0]	values[3]	88	1			T46	5		T54	3		T36	16
auto[1]	values[0]	values[4]	202	1			T51	14		T54	26		T210	6
auto[1]	values[0]	values[5]	317	1			T218	6		T185	3		T58	12
auto[1]	values[0]	values[6]	190	1			T54	11		T86	21		T41	17
auto[1]	values[0]	values[7]	237	1			T46	11		T20	9		T198	6
auto[1]	values[1]	values[0]	239	1			T12	8		T56	5		T86	7
auto[1]	values[1]	values[1]	112	1			T86	13		T87	9		T234	7
auto[1]	values[1]	values[2]	325	1			T51	3		T55	11		T86	31
auto[1]	values[1]	values[3]	258	1			T35	4		T208	18		T184	10
auto[1]	values[1]	values[4]	150	1			T86	17		T249	6		T189	15
auto[1]	values[1]	values[5]	226	1			T46	14		T53	40		T218	5
auto[1]	values[1]	values[6]	209	1			T12	13		T40	15		T234	9
auto[1]	values[1]	values[7]	217	1			T34	11		T46	15		T86	6
auto[1]	values[2]	values[0]	245	1			T41	6		T226	12		T200	111
auto[1]	values[2]	values[1]	128	1			T55	8		T56	4		T65	5
auto[1]	values[2]	values[2]	172	1			T186	6		T226	4		T187	19
auto[1]	values[2]	values[3]	258	1			T53	13		T54	19		T186	11
auto[1]	values[2]	values[4]	308	1			T34	16		T40	7		T87	21
auto[1]	values[2]	values[5]	117	1			T20	9		T185	7		T199	5
auto[1]	values[2]	values[6]	359	1			T55	55		T20	18		T41	69
auto[1]	values[2]	values[7]	100	1			T46	9		T54	8		T181	2
auto[1]	values[3]	values[0]	171	1			T51	6		T55	10		T215	34
auto[1]	values[3]	values[1]	345	1			T55	86		T56	9		T226	26
auto[1]	values[3]	values[2]	86	1			T54	4		T56	11		T86	12
auto[1]	values[3]	values[3]	318	1			T4	9		T12	17		T240	15
auto[1]	values[3]	values[4]	188	1			T1	7		T20	8		T41	10
auto[1]	values[3]	values[5]	288	1			T40	16		T185	14		T65	6
auto[1]	values[3]	values[6]	140	1			T19	11		T198	6		T215	3
auto[1]	values[3]	values[7]	470	1			T4	9		T51	21		T54	10
auto[1]	values[4]	values[0]	267	1			T40	14		T86	24		T240	10
auto[1]	values[4]	values[1]	110	1			T86	18		T199	7		T65	15
auto[1]	values[4]	values[2]	233	1			T86	10		T218	10		T87	11
auto[1]	values[4]	values[3]	156	1			T34	12		T184	11		T215	23
auto[1]	values[4]	values[4]	194	1			T51	13		T55	35		T41	8
auto[1]	values[4]	values[5]	158	1			T1	13		T250	2		T87	89
auto[1]	values[4]	values[6]	159	1			T46	7		T186	10		T86	3
auto[1]	values[4]	values[7]	187	1			T1	8		T4	3		T41	14
auto[1]	values[5]	values[0]	180	1			T8	8		T51	8		T40	15
auto[1]	values[5]	values[1]	211	1			T34	49		T46	6		T215	6
auto[1]	values[5]	values[2]	201	1			T4	11		T183	62		T198	15
auto[1]	values[5]	values[3]	283	1			T1	10		T55	10		T56	10
auto[1]	values[5]	values[4]	199	1			T1	11		T51	17		T56	8
auto[1]	values[5]	values[5]	224	1			T53	6		T198	41		T35	6
auto[1]	values[5]	values[6]	232	1			T4	11		T35	16		T184	14
auto[1]	values[5]	values[7]	202	1			T52	4		T20	10		T36	14
auto[1]	values[6]	values[0]	83	1			T56	4		T87	9		T187	8
auto[1]	values[6]	values[1]	291	1			T4	8		T51	9		T54	12
auto[1]	values[6]	values[2]	169	1			T20	11		T240	10		T87	40
auto[1]	values[6]	values[3]	263	1			T1	9		T46	8		T40	12
auto[1]	values[6]	values[4]	203	1			T51	11		T186	14		T184	26
auto[1]	values[6]	values[5]	246	1			T4	6		T86	7		T20	6
auto[1]	values[6]	values[6]	266	1			T186	8		T87	58		T200	10
auto[1]	values[6]	values[7]	314	1			T41	9		T215	10		T234	6
auto[1]	values[7]	values[0]	253	1			T1	10		T12	11		T51	8
auto[1]	values[7]	values[1]	461	1			T46	12		T53	8		T20	139
auto[1]	values[7]	values[2]	300	1			T4	8		T12	6		T14	10
auto[1]	values[7]	values[3]	210	1			T34	11		T51	11		T40	12
auto[1]	values[7]	values[4]	278	1			T1	10		T12	12		T36	10
auto[1]	values[7]	values[5]	238	1			T1	10		T4	11		T46	5
auto[1]	values[7]	values[6]	215	1			T1	11		T56	9		T183	10
auto[1]	values[7]	values[7]	155	1			T55	11		T183	13		T248	11