Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	436	1			T1	10		T4	1		T10	4
auto[ReadAddrCrossIntoMailbox]	304	1			T1	3		T4	1		T12	2
auto[ReadAddrCrossOutOfMailbox]	309	1			T1	6		T4	3		T12	2
auto[ReadAddrCrossAllMailbox]	250	1			T4	2		T12	1		T46	2
auto[ReadAddrOutsideMailbox]	3682	1			T1	29		T4	25		T5	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2501

1

T1

21

T4

19

T5

5

auto[1]

2480

1

T1

27

T4

13

T5

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	848	1			T1	11		T4	6		T5	2
read_ops[0x0b]	830	1			T1	9		T4	6		T5	2
read_ops[0x3b]	803	1			T1	9		T4	8		T5	2
read_ops[0x6b]	813	1			T1	5		T4	2		T8	2
read_ops[0xbb]	864	1			T1	7		T4	3		T12	5
read_ops[0xeb]	823	1			T1	7		T4	7		T5	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T1	1		T46	2		T54	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T1	1		T4	1		T12	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T82	1		T55	1		T186	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T1	1		T82	1		T19	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T4	1		T53	2		T55	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T1	2		T4	1		T183	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T46	1		T56	1		T20	3
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T54	2		T55	1		T228	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	340	1			T1	4		T4	1		T5	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T1	2		T4	2		T5	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T1	2		T46	1		T53	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T1	1		T207	1		T41	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T54	1		T86	1		T226	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T186	1		T86	1		T218	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T1	1		T56	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T20	1		T207	1		T218	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T4	1		T55	2		T186	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T53	1		T86	1		T228	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T1	2		T4	3		T5	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T1	3		T4	2		T5	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T1	1		T10	2		T51	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T1	2		T10	2		T54	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T4	1		T40	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T1	1		T53	1		T228	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T56	1		T41	1		T226	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T1	1		T12	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T12	1		T228	2		T226	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T4	1		T54	1		T20	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T1	1		T4	4		T5	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T1	3		T4	2		T5	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T1	2		T53	1		T55	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T34	1		T20	1		T41	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T12	1		T86	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T12	1		T86	2		T210	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T4	1		T12	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T54	1		T56	1		T251	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T55	2		T252	1		T207	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	30	1			T53	1		T54	2		T252	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T1	2		T8	1		T12	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T1	1		T4	1		T8	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T12	1		T19	1		T218	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T12	1		T56	1		T222	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T51	1		T55	1		T40	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T1	1		T40	2		T251	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T46	1		T53	1		T55	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T55	1		T207	2		T41	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T251	1		T86	1		T252	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T46	1		T53	1		T251	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T1	3		T4	3		T13	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T1	3		T12	3		T13	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T51	1		T186	1		T41	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T12	1		T46	1		T53	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T82	1		T55	1		T186	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T34	1		T82	1		T40	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T1	2		T46	1		T251	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T186	1		T251	1		T218	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T82	1		T226	1		T240	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T53	1		T54	1		T82	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T4	4		T5	2		T12	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T1	5		T4	3		T5	2