Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3856	1			T4	20		T5	20		T12	43
values[1]	4237	1			T1	40		T4	40		T12	43
values[2]	3798	1			T4	60		T34	23		T46	20
values[3]	4037	1			T1	40		T4	60		T8	8
values[4]	4279	1			T11	6		T12	27		T13	22
values[5]	3801	1			T1	60		T95	14		T34	20
values[6]	3291	1			T1	20		T51	60		T93	12
values[7]	4113	1			T1	40		T12	24		T46	67

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3954	1			T4	20		T8	8		T10	4
values[1]	4428	1			T1	40		T4	20		T12	24
values[2]	3846	1			T1	40		T4	20		T13	22
values[3]	3985	1			T1	60		T4	40		T34	23
values[4]	3505	1			T1	20		T4	20		T12	47
values[5]	4508	1			T1	20		T4	40		T5	20
values[6]	3694	1			T1	20		T12	20		T50	10
values[7]	3492	1			T4	20		T46	24		T51	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30613

1

T1

195

T4

174

T5

20

auto[1]

799

1

T1

5

T4

6

T12

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	347	1			T12	22		T34	24		T242	2
auto[0]	values[0]	values[1]	616	1			T52	2		T228	22		T210	19
auto[0]	values[0]	values[2]	337	1			T54	32		T86	20		T41	20
auto[0]	values[0]	values[3]	406	1			T51	20		T55	60		T204	18
auto[0]	values[0]	values[4]	470	1			T4	19		T12	20		T54	21
auto[0]	values[0]	values[5]	522	1			T5	20		T92	2		T54	24
auto[0]	values[0]	values[6]	490	1			T183	30		T184	20		T87	99
auto[0]	values[0]	values[7]	573	1			T46	23		T56	40		T86	20
auto[0]	values[1]	values[0]	620	1			T46	45		T240	18		T87	20
auto[0]	values[1]	values[1]	434	1			T14	10		T34	20		T40	23
auto[0]	values[1]	values[2]	594	1			T46	22		T232	14		T181	2
auto[0]	values[1]	values[3]	582	1			T1	19		T96	16		T53	44
auto[0]	values[1]	values[4]	470	1			T1	19		T54	22		T236	4
auto[0]	values[1]	values[5]	430	1			T4	18		T12	23		T51	20
auto[0]	values[1]	values[6]	430	1			T12	20		T226	77		T253	4
auto[0]	values[1]	values[7]	551	1			T4	20		T51	20		T41	20
auto[0]	values[2]	values[0]	478	1			T241	4		T192	12		T41	20
auto[0]	values[2]	values[1]	398	1			T46	20		T51	18		T86	26
auto[0]	values[2]	values[2]	523	1			T4	19		T20	20		T247	4
auto[0]	values[2]	values[3]	554	1			T4	20		T34	23		T54	20
auto[0]	values[2]	values[4]	464	1			T207	22		T240	20		T254	20
auto[0]	values[2]	values[5]	618	1			T4	20		T56	20		T41	45
auto[0]	values[2]	values[6]	356	1			T210	19		T65	35		T158	35
auto[0]	values[2]	values[7]	322	1			T217	16		T255	66		T256	22
auto[0]	values[3]	values[0]	621	1			T4	19		T8	8		T10	4
auto[0]	values[3]	values[1]	432	1			T4	19		T40	20		T185	20
auto[0]	values[3]	values[2]	598	1			T1	20		T19	31		T184	19
auto[0]	values[3]	values[3]	608	1			T1	20		T4	20		T46	22
auto[0]	values[3]	values[4]	312	1			T54	20		T234	20		T136	19
auto[0]	values[3]	values[5]	408	1			T54	20		T237	2		T131	10
auto[0]	values[3]	values[6]	491	1			T50	10		T97	2		T55	43
auto[0]	values[3]	values[7]	477	1			T86	31		T198	29		T221	6
auto[0]	values[4]	values[0]	529	1			T11	6		T34	60		T164	38
auto[0]	values[4]	values[1]	701	1			T46	62		T51	20		T82	8
auto[0]	values[4]	values[2]	495	1			T13	22		T53	20		T86	21
auto[0]	values[4]	values[3]	586	1			T51	20		T53	46		T54	27
auto[0]	values[4]	values[4]	375	1			T12	24		T51	19		T55	18
auto[0]	values[4]	values[5]	697	1			T54	20		T40	20		T86	31
auto[0]	values[4]	values[6]	436	1			T56	60		T86	23		T58	24
auto[0]	values[4]	values[7]	332	1			T53	36		T186	19		T198	61
auto[0]	values[5]	values[0]	537	1			T209	24		T41	20		T65	34
auto[0]	values[5]	values[1]	536	1			T1	39		T54	42		T186	20
auto[0]	values[5]	values[2]	369	1			T1	20		T20	19		T87	20
auto[0]	values[5]	values[3]	402	1			T41	21		T184	20		T235	2
auto[0]	values[5]	values[4]	588	1			T56	22		T186	24		T205	10
auto[0]	values[5]	values[5]	567	1			T95	14		T238	4		T226	70
auto[0]	values[5]	values[6]	456	1			T34	20		T46	22		T51	19
auto[0]	values[5]	values[7]	263	1			T86	20		T35	17		T215	42
auto[0]	values[6]	values[0]	355	1			T226	38		T257	8		T136	20
auto[0]	values[6]	values[1]	627	1			T54	23		T56	58		T87	22
auto[0]	values[6]	values[2]	332	1			T251	10		T35	29		T258	20
auto[0]	values[6]	values[3]	237	1			T239	4		T234	20		T193	14
auto[0]	values[6]	values[4]	310	1			T51	20		T55	39		T184	20
auto[0]	values[6]	values[5]	483	1			T1	20		T51	20		T220	8
auto[0]	values[6]	values[6]	319	1			T51	20		T93	12		T20	19
auto[0]	values[6]	values[7]	547	1			T40	42		T86	48		T198	33
auto[0]	values[7]	values[0]	382	1			T46	20		T184	20		T226	96
auto[0]	values[7]	values[1]	554	1			T12	22		T46	24		T182	2
auto[0]	values[7]	values[2]	487	1			T20	20		T198	61		T87	58
auto[0]	values[7]	values[3]	499	1			T1	20		T51	20		T259	20
auto[0]	values[7]	values[4]	413	1			T186	28		T86	35		T198	26
auto[0]	values[7]	values[5]	676	1			T46	21		T51	20		T20	29
auto[0]	values[7]	values[6]	646	1			T1	18		T86	48		T226	20
auto[0]	values[7]	values[7]	345	1			T18	20		T214	14		T130	26
auto[1]	values[0]	values[0]	8	1			T12	1		T87	1		T200	3
auto[1]	values[0]	values[1]	17	1			T52	2		T210	1		T260	1
auto[1]	values[0]	values[2]	15	1			T54	5		T199	4		T212	5
auto[1]	values[0]	values[3]	10	1			T260	1		T137	1		T261	1
auto[1]	values[0]	values[4]	13	1			T4	1		T41	2		T185	2
auto[1]	values[0]	values[5]	11	1			T20	1		T58	2		T262	1
auto[1]	values[0]	values[6]	7	1			T87	2		T263	2		T264	1
auto[1]	values[0]	values[7]	14	1			T46	1		T183	2		T215	1
auto[1]	values[1]	values[0]	15	1			T46	1		T240	2		T58	2
auto[1]	values[1]	values[1]	19	1			T40	2		T265	3		T266	2
auto[1]	values[1]	values[2]	24	1			T46	1		T210	1		T267	3
auto[1]	values[1]	values[3]	25	1			T1	1		T53	1		T54	1
auto[1]	values[1]	values[4]	17	1			T1	1		T54	4		T40	2
auto[1]	values[1]	values[5]	14	1			T4	2		T56	1		T40	2
auto[1]	values[1]	values[6]	6	1			T268	3		T212	1		T159	1
auto[1]	values[1]	values[7]	6	1			T262	2		T196	1		T261	2
auto[1]	values[2]	values[0]	10	1			T185	1		T199	3		T158	1
auto[1]	values[2]	values[1]	21	1			T51	2		T265	1		T212	1
auto[1]	values[2]	values[2]	7	1			T4	1		T87	2		T202	1
auto[1]	values[2]	values[3]	18	1			T55	1		T215	1		T240	2
auto[1]	values[2]	values[4]	4	1			T201	2		T269	1		T270	1
auto[1]	values[2]	values[5]	12	1			T265	1		T268	2		T271	1
auto[1]	values[2]	values[6]	4	1			T210	1		T271	1		T272	2
auto[1]	values[2]	values[7]	9	1			T273	1		T274	2		T275	1
auto[1]	values[3]	values[0]	18	1			T4	1		T186	1		T226	3
auto[1]	values[3]	values[1]	10	1			T4	1		T202	3		T276	1
auto[1]	values[3]	values[2]	14	1			T184	1		T277	1		T268	1
auto[1]	values[3]	values[3]	12	1			T46	2		T278	1		T266	5
auto[1]	values[3]	values[4]	7	1			T136	1		T279	1		T264	2
auto[1]	values[3]	values[5]	10	1			T227	4		T280	3		T281	3
auto[1]	values[3]	values[6]	8	1			T282	4		T262	2		T283	1
auto[1]	values[3]	values[7]	11	1			T86	1		T266	6		T284	1
auto[1]	values[4]	values[0]	12	1			T218	1		T184	1		T226	2
auto[1]	values[4]	values[1]	17	1			T46	1		T248	2		T65	1
auto[1]	values[4]	values[2]	20	1			T86	1		T41	1		T208	4
auto[1]	values[4]	values[3]	16	1			T53	1		T54	3		T65	2
auto[1]	values[4]	values[4]	21	1			T12	3		T51	1		T55	2
auto[1]	values[4]	values[5]	12	1			T87	2		T234	1		T200	2
auto[1]	values[4]	values[6]	15	1			T56	2		T58	3		T285	2
auto[1]	values[4]	values[7]	15	1			T186	1		T218	1		T184	1
auto[1]	values[5]	values[0]	6	1			T65	1		T281	1		T180	3
auto[1]	values[5]	values[1]	14	1			T1	1		T210	1		T248	1
auto[1]	values[5]	values[2]	12	1			T20	1		T136	1		T137	1
auto[1]	values[5]	values[3]	9	1			T41	1		T286	1		T255	2
auto[1]	values[5]	values[4]	12	1			T56	1		T186	1		T35	1
auto[1]	values[5]	values[5]	9	1			T226	3		T215	2		T187	1
auto[1]	values[5]	values[6]	11	1			T51	1		T56	1		T36	1
auto[1]	values[5]	values[7]	10	1			T35	3		T215	3		T136	2
auto[1]	values[6]	values[0]	9	1			T187	2		T287	1		T288	2
auto[1]	values[6]	values[1]	14	1			T54	1		T56	2		T136	2
auto[1]	values[6]	values[2]	9	1			T35	1		T200	1		T271	5
auto[1]	values[6]	values[3]	7	1			T201	3		T289	1		T290	3
auto[1]	values[6]	values[4]	14	1			T55	5		T291	2		T187	2
auto[1]	values[6]	values[5]	19	1			T20	4		T199	2		T265	3
auto[1]	values[6]	values[6]	5	1			T20	1		T70	4		-	-
auto[1]	values[6]	values[7]	4	1			T40	2		T263	1		T162	1
auto[1]	values[7]	values[0]	7	1			T292	2		T256	3		T60	1
auto[1]	values[7]	values[1]	18	1			T12	2		T54	2		T187	3
auto[1]	values[7]	values[2]	10	1			T198	4		T158	1		T293	1
auto[1]	values[7]	values[3]	14	1			T87	3		T199	3		T294	1
auto[1]	values[7]	values[4]	15	1			T186	1		T86	2		T198	1
auto[1]	values[7]	values[5]	20	1			T46	2		T183	1		T41	4
auto[1]	values[7]	values[6]	14	1			T1	2		T86	2		T58	3
auto[1]	values[7]	values[7]	13	1			T295	2		T296	1		T60	2