Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	866	1			T15	27		T17	21		T18	4
all_values[1]	866	1			T15	27		T17	21		T18	4
all_values[2]	866	1			T15	27		T17	21		T18	4
all_values[3]	866	1			T15	27		T17	21		T18	4
all_values[4]	866	1			T15	27		T17	21		T18	4
all_values[5]	866	1			T15	27		T17	21		T18	4
all_values[6]	866	1			T15	27		T17	21		T18	4
all_values[7]	866	1			T15	27		T17	21		T18	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3669

1

T15

90

T17

92

T18

14

auto[1]

3259

1

T15

126

T17

76

T18

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2728

1

T15

89

T17

61

T18

19

auto[1]

4200

1

T15

127

T17

107

T18

13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3947

1

T15

125

T17

94

T18

22

auto[1]

2981

1

T15

91

T17

74

T18

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	171	1			T15	3		T17	1		T19	3
all_values[0]	auto[0]	auto[0]	auto[1]	88	1			T15	1		T17	4		T18	1
all_values[0]	auto[0]	auto[1]	auto[0]	128	1			T15	6		T17	4		T18	1
all_values[0]	auto[0]	auto[1]	auto[1]	92	1			T15	2		T17	2		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	199	1			T15	7		T17	4		T18	2
all_values[0]	auto[1]	auto[1]	auto[1]	188	1			T15	8		T17	6		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	154	1			T15	1		T17	5		T21	5
all_values[1]	auto[0]	auto[0]	auto[1]	99	1			T15	3		T17	4		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	149	1			T15	8		T17	3		T18	1
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T15	1		T17	1		T19	2
all_values[1]	auto[1]	auto[0]	auto[1]	213	1			T15	5		T17	6		T18	2
all_values[1]	auto[1]	auto[1]	auto[1]	170	1			T15	9		T17	2		T19	2
all_values[2]	auto[0]	auto[0]	auto[0]	188	1			T15	5		T17	7		T19	1
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T15	3		T17	3		T19	2
all_values[2]	auto[0]	auto[1]	auto[0]	142	1			T15	7		T17	3		T20	4
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T15	2		T17	1		T18	1
all_values[2]	auto[1]	auto[0]	auto[1]	198	1			T15	2		T17	4		T19	4
all_values[2]	auto[1]	auto[1]	auto[1]	174	1			T15	8		T17	3		T18	3
all_values[3]	auto[0]	auto[0]	auto[0]	145	1			T15	1		T17	1		T18	1
all_values[3]	auto[0]	auto[0]	auto[1]	93	1			T15	2		T17	3		T19	2
all_values[3]	auto[0]	auto[1]	auto[0]	162	1			T15	9		T17	2		T18	2
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T15	4		T17	3		T20	3
all_values[3]	auto[1]	auto[0]	auto[1]	211	1			T15	7		T17	10		T19	2
all_values[3]	auto[1]	auto[1]	auto[1]	178	1			T15	4		T17	2		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	182	1			T15	5		T17	5		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T15	2		T19	1		T20	2
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T15	4		T17	4		T18	3
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T15	8		T17	4		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	184	1			T15	4		T17	6		T19	1
all_values[4]	auto[1]	auto[1]	auto[1]	177	1			T15	4		T17	2		T19	4
all_values[5]	auto[0]	auto[0]	auto[0]	264	1			T15	9		T17	3		T18	1
all_values[5]	auto[0]	auto[1]	auto[0]	240	1			T15	7		T17	8		T18	3
all_values[5]	auto[1]	auto[0]	auto[1]	200	1			T15	8		T17	8		T19	1
all_values[5]	auto[1]	auto[1]	auto[1]	162	1			T15	3		T17	2		T19	4
all_values[6]	auto[0]	auto[0]	auto[0]	172	1			T15	6		T17	4		T18	2
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T17	1		T19	1		T20	2
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T15	9		T17	3		T18	1
all_values[6]	auto[0]	auto[1]	auto[1]	101	1			T15	2		T17	2		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	206	1			T15	3		T17	2		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	166	1			T15	7		T17	9		T19	2
all_values[7]	auto[0]	auto[0]	auto[0]	169	1			T15	1		T17	3		T18	2
all_values[7]	auto[0]	auto[0]	auto[1]	88	1			T15	2		T17	3		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	172	1			T15	8		T17	5		T18	1
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T15	4		T17	2		T19	1
all_values[7]	auto[1]	auto[0]	auto[1]	198	1			T15	10		T17	5		T19	5
all_values[7]	auto[1]	auto[1]	auto[1]	157	1			T15	2		T17	3		T18	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal