Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1704

1

T2

2

T3

1

T7

6

auto[1]

1701

1

T2

1

T7

1

T12

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T7

7

T12

5

T29

4

auto[1]

1489

1

T2

3

T3

1

T12

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2694

1

T2

3

T3

1

T7

4

auto[1]

711

1

T7

3

T12

1

T29

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	677	1			T2	3		T12	3		T29	3
valid[1]	668	1			T7	2		T30	4		T33	1
valid[2]	664	1			T7	1		T12	1		T29	2
valid[3]	664	1			T3	1		T7	2		T12	1
valid[4]	732	1			T7	2		T12	2		T29	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	132	1			T12	1		T54	1		T308	1
auto[0]	auto[0]	valid[0]	auto[1]	151	1			T2	2		T29	2		T30	7
auto[0]	auto[0]	valid[1]	auto[0]	117	1			T7	1		T26	1		T57	1
auto[0]	auto[0]	valid[1]	auto[1]	151	1			T30	3		T33	1		T27	6
auto[0]	auto[0]	valid[2]	auto[0]	108	1			T26	1		T34	1		T54	1
auto[0]	auto[0]	valid[2]	auto[1]	140	1			T29	1		T30	2		T27	3
auto[0]	auto[0]	valid[3]	auto[0]	103	1			T7	1		T57	2		T54	1
auto[0]	auto[0]	valid[3]	auto[1]	145	1			T3	1		T30	1		T27	2
auto[0]	auto[0]	valid[4]	auto[0]	147	1			T7	1		T31	1		T26	1
auto[0]	auto[0]	valid[4]	auto[1]	147	1			T12	1		T30	3		T27	5
auto[0]	auto[1]	valid[0]	auto[0]	107	1			T12	1		T26	3		T57	2
auto[0]	auto[1]	valid[0]	auto[1]	155	1			T2	1		T12	1		T30	2
auto[0]	auto[1]	valid[1]	auto[0]	123	1			T31	1		T26	1		T54	2
auto[0]	auto[1]	valid[1]	auto[1]	143	1			T30	1		T27	3		T322	3
auto[0]	auto[1]	valid[2]	auto[0]	116	1			T12	1		T31	2		T26	1
auto[0]	auto[1]	valid[2]	auto[1]	157	1			T30	4		T57	1		T322	1
auto[0]	auto[1]	valid[3]	auto[0]	118	1			T7	1		T31	2		T26	1
auto[0]	auto[1]	valid[3]	auto[1]	150	1			T30	3		T27	1		T322	2
auto[0]	auto[1]	valid[4]	auto[0]	134	1			T12	1		T31	1		T54	1
auto[0]	auto[1]	valid[4]	auto[1]	150	1			T30	2		T27	2		T83	1
auto[1]	auto[0]	valid[0]	auto[0]	69	1			T26	1		T57	1		T308	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T7	1		T46	1		T40	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T7	1		T29	1		T317	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T12	1		T29	1		T57	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T7	1		T31	1		T26	1
auto[1]	auto[1]	valid[0]	auto[0]	63	1			T29	1		T46	2		T315	1
auto[1]	auto[1]	valid[1]	auto[0]	64	1			T57	1		T46	1		T83	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T38	1		T57	1		T46	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T308	1		T165	1		T85	1
auto[1]	auto[1]	valid[4]	auto[0]	73	1			T29	1		T26	1		T57	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal