Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49162

1

T6

14

T7

190

T12

160

auto[1]

15754

1

T2

3

T3

1

T7

30

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47020

1

T2

3

T3

1

T6

6

auto[1]

17896

1

T6

8

T7

71

T12

68

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33245	1			T2	3		T3	1		T6	5
others[1]	5517	1			T6	4		T7	24		T12	23
others[2]	5418	1			T6	1		T7	17		T12	13
others[3]	6395	1			T7	21		T12	21		T29	21
interest[1]	3476	1			T7	19		T12	9		T29	6
interest[4]	21758	1			T2	3		T3	1		T6	4
interest[64]	10865	1			T6	4		T7	31		T12	33

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15970	1			T6	2		T7	63		T12	42
auto[0]	auto[0]	others[1]	2644	1			T6	1		T7	13		T12	11
auto[0]	auto[0]	others[2]	2564	1			T7	4		T12	8		T29	7
auto[0]	auto[0]	others[3]	3072	1			T7	12		T12	8		T29	15
auto[0]	auto[0]	interest[1]	1716	1			T7	10		T12	7		T29	1
auto[0]	auto[0]	interest[4]	10344	1			T6	1		T7	38		T12	22
auto[0]	auto[0]	interest[64]	5300	1			T6	3		T7	17		T12	16
auto[0]	auto[1]	others[0]	8173	1			T2	3		T3	1		T7	12
auto[0]	auto[1]	others[1]	1315	1			T7	2		T12	3		T29	3
auto[0]	auto[1]	others[2]	1332	1			T7	4		T12	1		T29	11
auto[0]	auto[1]	others[3]	1502	1			T7	4		T12	4		T29	3
auto[0]	auto[1]	interest[1]	816	1			T7	2		T12	1		T29	2
auto[0]	auto[1]	interest[4]	5415	1			T2	3		T3	1		T7	8
auto[0]	auto[1]	interest[64]	2616	1			T7	6		T12	5		T29	7
auto[1]	auto[0]	others[0]	9102	1			T6	3		T7	33		T12	33
auto[1]	auto[0]	others[1]	1558	1			T6	3		T7	9		T12	9
auto[1]	auto[0]	others[2]	1522	1			T6	1		T7	9		T12	4
auto[1]	auto[0]	others[3]	1821	1			T7	5		T12	9		T29	3
auto[1]	auto[0]	interest[1]	944	1			T7	7		T12	1		T29	3
auto[1]	auto[0]	interest[4]	5999	1			T6	3		T7	18		T12	20
auto[1]	auto[0]	interest[64]	2949	1			T6	1		T7	8		T12	12

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal