Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T115 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.81477561 Jul 06 06:19:26 PM PDT 24 Jul 06 06:19:29 PM PDT 24 195735141 ps
T1038 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.915273896 Jul 06 06:20:08 PM PDT 24 Jul 06 06:20:09 PM PDT 24 29278795 ps
T102 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3279484870 Jul 06 06:19:45 PM PDT 24 Jul 06 06:20:04 PM PDT 24 4086781970 ps
T1039 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1287342073 Jul 06 06:18:57 PM PDT 24 Jul 06 06:18:59 PM PDT 24 75737584 ps
T1040 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1807756490 Jul 06 06:19:07 PM PDT 24 Jul 06 06:19:09 PM PDT 24 72631719 ps
T1041 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2915530714 Jul 06 06:19:48 PM PDT 24 Jul 06 06:19:49 PM PDT 24 35245658 ps
T103 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1181934922 Jul 06 06:18:33 PM PDT 24 Jul 06 06:18:37 PM PDT 24 230086774 ps
T1042 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2297063909 Jul 06 06:20:14 PM PDT 24 Jul 06 06:20:15 PM PDT 24 31408102 ps
T152 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1398413543 Jul 06 06:20:03 PM PDT 24 Jul 06 06:20:07 PM PDT 24 3742579791 ps
T105 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3488788569 Jul 06 06:19:11 PM PDT 24 Jul 06 06:19:15 PM PDT 24 340627761 ps
T1043 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2916186227 Jul 06 06:20:08 PM PDT 24 Jul 06 06:20:09 PM PDT 24 41254127 ps
T122 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1860506138 Jul 06 06:18:59 PM PDT 24 Jul 06 06:19:14 PM PDT 24 759825869 ps
T1044 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1109839296 Jul 06 06:19:12 PM PDT 24 Jul 06 06:19:14 PM PDT 24 25039835 ps
T1045 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3933032767 Jul 06 06:19:07 PM PDT 24 Jul 06 06:19:08 PM PDT 24 45992145 ps
T1046 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3057497490 Jul 06 06:20:08 PM PDT 24 Jul 06 06:20:09 PM PDT 24 35980545 ps
T104 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1240303149 Jul 06 06:18:42 PM PDT 24 Jul 06 06:19:02 PM PDT 24 295632898 ps
T106 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.173675891 Jul 06 06:19:06 PM PDT 24 Jul 06 06:19:10 PM PDT 24 689320639 ps
T1047 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1154518032 Jul 06 06:19:31 PM PDT 24 Jul 06 06:19:34 PM PDT 24 84043683 ps
T1048 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2540079240 Jul 06 06:20:06 PM PDT 24 Jul 06 06:20:07 PM PDT 24 59184319 ps
T1049 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3742841917 Jul 06 06:19:33 PM PDT 24 Jul 06 06:19:37 PM PDT 24 256744999 ps
T88 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2458803181 Jul 06 06:18:30 PM PDT 24 Jul 06 06:18:31 PM PDT 24 35773651 ps
T1050 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.354615083 Jul 06 06:19:44 PM PDT 24 Jul 06 06:19:45 PM PDT 24 51283136 ps
T1051 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2262838382 Jul 06 06:20:13 PM PDT 24 Jul 06 06:20:14 PM PDT 24 25313703 ps
T1052 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1524896892 Jul 06 06:19:44 PM PDT 24 Jul 06 06:19:45 PM PDT 24 18220407 ps
T1053 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4285146942 Jul 06 06:20:17 PM PDT 24 Jul 06 06:20:18 PM PDT 24 12866833 ps
T107 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1052542891 Jul 06 06:19:53 PM PDT 24 Jul 06 06:19:58 PM PDT 24 551816478 ps
T1054 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2271638952 Jul 06 06:19:48 PM PDT 24 Jul 06 06:19:51 PM PDT 24 161844950 ps
T1055 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3476827396 Jul 06 06:19:15 PM PDT 24 Jul 06 06:19:19 PM PDT 24 101622747 ps
T1056 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2795538824 Jul 06 06:20:03 PM PDT 24 Jul 06 06:20:04 PM PDT 24 31565999 ps
T108 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.625203779 Jul 06 06:19:48 PM PDT 24 Jul 06 06:19:52 PM PDT 24 196926292 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2562263550 Jul 06 06:18:50 PM PDT 24 Jul 06 06:18:51 PM PDT 24 45277562 ps
T123 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2790516366 Jul 06 06:18:40 PM PDT 24 Jul 06 06:18:41 PM PDT 24 110242483 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1203897446 Jul 06 06:18:57 PM PDT 24 Jul 06 06:18:58 PM PDT 24 32992086 ps
T1058 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3656039333 Jul 06 06:20:08 PM PDT 24 Jul 06 06:20:09 PM PDT 24 11793476 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4186557861 Jul 06 06:18:47 PM PDT 24 Jul 06 06:18:49 PM PDT 24 102661187 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1107921513 Jul 06 06:19:02 PM PDT 24 Jul 06 06:19:04 PM PDT 24 54616016 ps
T1060 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2207268058 Jul 06 06:20:13 PM PDT 24 Jul 06 06:20:15 PM PDT 24 13215456 ps
T125 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1822953342 Jul 06 06:18:57 PM PDT 24 Jul 06 06:19:28 PM PDT 24 4010289479 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1986471263 Jul 06 06:19:05 PM PDT 24 Jul 06 06:19:09 PM PDT 24 309543855 ps
T153 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3143708868 Jul 06 06:19:07 PM PDT 24 Jul 06 06:19:11 PM PDT 24 208105417 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3877725677 Jul 06 06:18:53 PM PDT 24 Jul 06 06:18:56 PM PDT 24 107441413 ps
T173 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1366707046 Jul 06 06:19:09 PM PDT 24 Jul 06 06:19:16 PM PDT 24 466192653 ps
T110 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1832212142 Jul 06 06:19:42 PM PDT 24 Jul 06 06:19:46 PM PDT 24 60569202 ps
T154 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4204823794 Jul 06 06:19:38 PM PDT 24 Jul 06 06:19:41 PM PDT 24 118526406 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.280210454 Jul 06 06:19:01 PM PDT 24 Jul 06 06:19:33 PM PDT 24 2086936722 ps
T1062 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.875512237 Jul 06 06:18:35 PM PDT 24 Jul 06 06:18:39 PM PDT 24 113256792 ps
T1063 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1252624433 Jul 06 06:19:28 PM PDT 24 Jul 06 06:19:31 PM PDT 24 152268202 ps
T155 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2339560378 Jul 06 06:19:02 PM PDT 24 Jul 06 06:19:18 PM PDT 24 919253000 ps
T172 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1630802695 Jul 06 06:19:24 PM PDT 24 Jul 06 06:19:43 PM PDT 24 591049033 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2182617932 Jul 06 06:18:43 PM PDT 24 Jul 06 06:18:45 PM PDT 24 85576243 ps
T1065 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4139339015 Jul 06 06:18:47 PM PDT 24 Jul 06 06:18:48 PM PDT 24 33623543 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.424954636 Jul 06 06:18:39 PM PDT 24 Jul 06 06:18:40 PM PDT 24 37175227 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1192017433 Jul 06 06:18:34 PM PDT 24 Jul 06 06:18:39 PM PDT 24 234686749 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3537300245 Jul 06 06:18:57 PM PDT 24 Jul 06 06:18:58 PM PDT 24 59691907 ps
T1069 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2020182002 Jul 06 06:20:03 PM PDT 24 Jul 06 06:20:05 PM PDT 24 14821368 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2789823632 Jul 06 06:18:44 PM PDT 24 Jul 06 06:18:56 PM PDT 24 1222753723 ps
T90 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2454033481 Jul 06 06:18:45 PM PDT 24 Jul 06 06:18:47 PM PDT 24 55464602 ps
T1071 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2232545389 Jul 06 06:19:28 PM PDT 24 Jul 06 06:19:31 PM PDT 24 286208390 ps
T109 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1319659314 Jul 06 06:18:26 PM PDT 24 Jul 06 06:18:28 PM PDT 24 58178231 ps
T174 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1762372274 Jul 06 06:19:53 PM PDT 24 Jul 06 06:20:13 PM PDT 24 4364867141 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2168953175 Jul 06 06:18:53 PM PDT 24 Jul 06 06:18:54 PM PDT 24 30558219 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2943331385 Jul 06 06:18:43 PM PDT 24 Jul 06 06:18:52 PM PDT 24 1358303142 ps
T128 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.584498553 Jul 06 06:19:16 PM PDT 24 Jul 06 06:19:18 PM PDT 24 69372605 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.44719776 Jul 06 06:19:43 PM PDT 24 Jul 06 06:19:44 PM PDT 24 12925230 ps
T1075 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2867712457 Jul 06 06:20:12 PM PDT 24 Jul 06 06:20:13 PM PDT 24 12210221 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.825430249 Jul 06 06:19:33 PM PDT 24 Jul 06 06:19:34 PM PDT 24 13091779 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.384619124 Jul 06 06:19:38 PM PDT 24 Jul 06 06:19:42 PM PDT 24 131722006 ps
T175 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3263040072 Jul 06 06:19:51 PM PDT 24 Jul 06 06:20:07 PM PDT 24 549593886 ps
T1078 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3872354102 Jul 06 06:18:32 PM PDT 24 Jul 06 06:18:45 PM PDT 24 669523958 ps
T1079 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.324550147 Jul 06 06:19:48 PM PDT 24 Jul 06 06:20:00 PM PDT 24 202688930 ps
T111 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.844489901 Jul 06 06:19:33 PM PDT 24 Jul 06 06:19:35 PM PDT 24 56236033 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3179704252 Jul 06 06:19:13 PM PDT 24 Jul 06 06:19:22 PM PDT 24 861971897 ps
T1081 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3453947306 Jul 06 06:19:13 PM PDT 24 Jul 06 06:19:14 PM PDT 24 114927262 ps
T1082 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.545448262 Jul 06 06:19:52 PM PDT 24 Jul 06 06:19:54 PM PDT 24 45249487 ps
T170 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1576948681 Jul 06 06:19:27 PM PDT 24 Jul 06 06:19:40 PM PDT 24 3341435829 ps
T1083 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.56166667 Jul 06 06:19:02 PM PDT 24 Jul 06 06:19:04 PM PDT 24 66655029 ps
T1084 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.295680670 Jul 06 06:19:28 PM PDT 24 Jul 06 06:19:50 PM PDT 24 1708204679 ps
T176 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1180408479 Jul 06 06:19:16 PM PDT 24 Jul 06 06:19:29 PM PDT 24 196945621 ps
T1085 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.249050122 Jul 06 06:18:30 PM PDT 24 Jul 06 06:18:32 PM PDT 24 242559336 ps
T1086 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1632726439 Jul 06 06:19:31 PM PDT 24 Jul 06 06:19:35 PM PDT 24 256306964 ps
T112 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1922989365 Jul 06 06:19:38 PM PDT 24 Jul 06 06:19:42 PM PDT 24 206644286 ps
T1087 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.170313218 Jul 06 06:20:03 PM PDT 24 Jul 06 06:20:04 PM PDT 24 52317033 ps
T1088 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.382336695 Jul 06 06:20:08 PM PDT 24 Jul 06 06:20:09 PM PDT 24 52059523 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3342331808 Jul 06 06:18:56 PM PDT 24 Jul 06 06:19:10 PM PDT 24 448333353 ps
T1090 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2658495393 Jul 06 06:20:14 PM PDT 24 Jul 06 06:20:15 PM PDT 24 40608046 ps
T1091 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4200039278 Jul 06 06:20:03 PM PDT 24 Jul 06 06:20:04 PM PDT 24 51671303 ps
T113 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2026897443 Jul 06 06:18:49 PM PDT 24 Jul 06 06:18:54 PM PDT 24 284968065 ps
T1092 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1258674816 Jul 06 06:19:33 PM PDT 24 Jul 06 06:19:36 PM PDT 24 297869790 ps
T1093 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2636324214 Jul 06 06:19:48 PM PDT 24 Jul 06 06:19:51 PM PDT 24 406695430 ps
T1094 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1176104566 Jul 06 06:20:14 PM PDT 24 Jul 06 06:20:15 PM PDT 24 15059659 ps
T1095 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3091094814 Jul 06 06:18:58 PM PDT 24 Jul 06 06:19:01 PM PDT 24 521607521 ps
T1096 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.59546754 Jul 06 06:19:12 PM PDT 24 Jul 06 06:19:14 PM PDT 24 36966122 ps
T114 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3045359880 Jul 06 06:19:23 PM PDT 24 Jul 06 06:19:27 PM PDT 24 254864055 ps
T1097 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.526686920 Jul 06 06:20:16 PM PDT 24 Jul 06 06:20:17 PM PDT 24 18652233 ps
T1098 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.531522590 Jul 06 06:19:34 PM PDT 24 Jul 06 06:19:36 PM PDT 24 356039437 ps
T1099 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.852392360 Jul 06 06:20:02 PM PDT 24 Jul 06 06:20:03 PM PDT 24 18667305 ps
T1100 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2698295013 Jul 06 06:19:47 PM PDT 24 Jul 06 06:19:52 PM PDT 24 345393221 ps
T1101 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1289785271 Jul 06 06:19:14 PM PDT 24 Jul 06 06:19:17 PM PDT 24 87270308 ps
T1102 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2197776599 Jul 06 06:20:18 PM PDT 24 Jul 06 06:20:19 PM PDT 24 238571053 ps
T1103 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4026578132 Jul 06 06:19:58 PM PDT 24 Jul 06 06:20:01 PM PDT 24 83156519 ps
T1104 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4213424456 Jul 06 06:19:16 PM PDT 24 Jul 06 06:19:20 PM PDT 24 404956736 ps
T1105 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.826237389 Jul 06 06:19:06 PM PDT 24 Jul 06 06:19:09 PM PDT 24 447850949 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2047900607 Jul 06 06:20:05 PM PDT 24 Jul 06 06:20:09 PM PDT 24 428454247 ps
T1107 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2127454763 Jul 06 06:20:07 PM PDT 24 Jul 06 06:20:08 PM PDT 24 11442088 ps
T1108 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2486078006 Jul 06 06:19:12 PM PDT 24 Jul 06 06:19:16 PM PDT 24 59922534 ps
T1109 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2525942171 Jul 06 06:19:14 PM PDT 24 Jul 06 06:19:26 PM PDT 24 1161724874 ps
T1110 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3505497076 Jul 06 06:19:57 PM PDT 24 Jul 06 06:20:04 PM PDT 24 208879483 ps
T1111 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3110403232 Jul 06 06:19:33 PM PDT 24 Jul 06 06:19:41 PM PDT 24 689239520 ps
T1112 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4187616311 Jul 06 06:19:32 PM PDT 24 Jul 06 06:19:37 PM PDT 24 167538714 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2066690266 Jul 06 06:18:31 PM PDT 24 Jul 06 06:18:33 PM PDT 24 71547307 ps
T1114 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2721527166 Jul 06 06:19:25 PM PDT 24 Jul 06 06:19:28 PM PDT 24 215649913 ps
T1115 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2794034677 Jul 06 06:20:12 PM PDT 24 Jul 06 06:20:13 PM PDT 24 85535814 ps
T1116 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2427401638 Jul 06 06:18:38 PM PDT 24 Jul 06 06:18:39 PM PDT 24 58213879 ps
T1117 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2996813228 Jul 06 06:18:51 PM PDT 24 Jul 06 06:19:03 PM PDT 24 742145802 ps
T1118 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3776939920 Jul 06 06:19:33 PM PDT 24 Jul 06 06:19:35 PM PDT 24 110691413 ps
T1119 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1735978643 Jul 06 06:19:24 PM PDT 24 Jul 06 06:19:27 PM PDT 24 144364576 ps
T1120 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3711197118 Jul 06 06:19:38 PM PDT 24 Jul 06 06:19:42 PM PDT 24 299682806 ps
T1121 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2504036860 Jul 06 06:19:24 PM PDT 24 Jul 06 06:19:25 PM PDT 24 45021458 ps
T1122 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1511326015 Jul 06 06:20:18 PM PDT 24 Jul 06 06:20:19 PM PDT 24 21387395 ps
T1123 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1830237878 Jul 06 06:20:13 PM PDT 24 Jul 06 06:20:14 PM PDT 24 72075411 ps
T169 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3073390950 Jul 06 06:19:59 PM PDT 24 Jul 06 06:20:02 PM PDT 24 48538609 ps
T1124 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1347491869 Jul 06 06:19:28 PM PDT 24 Jul 06 06:19:29 PM PDT 24 16826807 ps
T1125 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2315806139 Jul 06 06:19:42 PM PDT 24 Jul 06 06:19:46 PM PDT 24 202823350 ps
T1126 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3612587504 Jul 06 06:19:24 PM PDT 24 Jul 06 06:19:25 PM PDT 24 43245198 ps
T1127 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2423558756 Jul 06 06:19:30 PM PDT 24 Jul 06 06:19:33 PM PDT 24 39862102 ps
T1128 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1702358234 Jul 06 06:19:26 PM PDT 24 Jul 06 06:19:28 PM PDT 24 205569380 ps
T1129 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4059799003 Jul 06 06:19:03 PM PDT 24 Jul 06 06:19:04 PM PDT 24 13951830 ps
T1130 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1380935737 Jul 06 06:20:09 PM PDT 24 Jul 06 06:20:10 PM PDT 24 16989760 ps
T1131 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.994419054 Jul 06 06:19:45 PM PDT 24 Jul 06 06:19:48 PM PDT 24 484823379 ps
T1132 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2068316984 Jul 06 06:19:28 PM PDT 24 Jul 06 06:19:31 PM PDT 24 444076890 ps
T1133 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1924511690 Jul 06 06:19:37 PM PDT 24 Jul 06 06:19:59 PM PDT 24 1180750140 ps
T1134 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.640613609 Jul 06 06:19:48 PM PDT 24 Jul 06 06:19:51 PM PDT 24 85270140 ps
T1135 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1713760891 Jul 06 06:18:52 PM PDT 24 Jul 06 06:18:54 PM PDT 24 71023726 ps
T1136 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3391843468 Jul 06 06:19:42 PM PDT 24 Jul 06 06:19:46 PM PDT 24 221473097 ps
T1137 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2065722362 Jul 06 06:19:05 PM PDT 24 Jul 06 06:19:06 PM PDT 24 17756227 ps
T1138 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.480171224 Jul 06 06:18:29 PM PDT 24 Jul 06 06:18:46 PM PDT 24 2891057960 ps
T171 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.334016681 Jul 06 06:19:15 PM PDT 24 Jul 06 06:19:38 PM PDT 24 1634540865 ps
T1139 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1980396041 Jul 06 06:20:15 PM PDT 24 Jul 06 06:20:16 PM PDT 24 48366801 ps
T1140 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2753255296 Jul 06 06:19:53 PM PDT 24 Jul 06 06:19:54 PM PDT 24 35477843 ps
T1141 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3677966432 Jul 06 06:20:06 PM PDT 24 Jul 06 06:20:07 PM PDT 24 81198885 ps
T1142 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2885989267 Jul 06 06:18:49 PM PDT 24 Jul 06 06:19:13 PM PDT 24 7695148835 ps
T1143 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.328976751 Jul 06 06:19:02 PM PDT 24 Jul 06 06:19:06 PM PDT 24 168374118 ps
T1144 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2300549415 Jul 06 06:19:25 PM PDT 24 Jul 06 06:19:28 PM PDT 24 130395322 ps
T1145 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3349978809 Jul 06 06:19:15 PM PDT 24 Jul 06 06:19:18 PM PDT 24 42346021 ps
T1146 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.49942616 Jul 06 06:19:58 PM PDT 24 Jul 06 06:20:00 PM PDT 24 27642155 ps
T1147 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3295728387 Jul 06 06:19:02 PM PDT 24 Jul 06 06:19:05 PM PDT 24 143873104 ps
T1148 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.206584093 Jul 06 06:19:38 PM PDT 24 Jul 06 06:19:41 PM PDT 24 40422538 ps
T1149 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3599996238 Jul 06 06:19:52 PM PDT 24 Jul 06 06:19:54 PM PDT 24 16729608 ps
T1150 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2678254736 Jul 06 06:19:49 PM PDT 24 Jul 06 06:19:52 PM PDT 24 84616660 ps
T91 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.181226409 Jul 06 06:19:12 PM PDT 24 Jul 06 06:19:14 PM PDT 24 45514236 ps

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1137378687
Short name T1
Test name
Test status
Simulation time 108081697066 ps
CPU time 216.25 seconds
Started Jul 06 06:23:10 PM PDT 24
Finished Jul 06 06:26:46 PM PDT 24
Peak memory 250332 kb
Host smart-ecca2e15-9adb-436e-af0a-2e801161001f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137378687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1137378687
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1021997340
Short name T12
Test name
Test status
Simulation time 38855272999 ps
CPU time 209.13 seconds
Started Jul 06 06:24:06 PM PDT 24
Finished Jul 06 06:27:35 PM PDT 24
Peak memory 257920 kb
Host smart-73bfc654-5721-4abb-9270-fb57328f21ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021997340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1021997340
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2111870858
Short name T36
Test name
Test status
Simulation time 531984082949 ps
CPU time 342.33 seconds
Started Jul 06 06:23:50 PM PDT 24
Finished Jul 06 06:29:33 PM PDT 24
Peak memory 273984 kb
Host smart-160c4bea-af01-480d-9a65-d12e551741f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111870858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2111870858
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.177642509
Short name T20
Test name
Test status
Simulation time 39142157322 ps
CPU time 166.36 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:26:50 PM PDT 24
Peak memory 258344 kb
Host smart-79ece78b-16e3-400b-b02b-588a020f16d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177642509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.177642509
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3488788569
Short name T105
Test name
Test status
Simulation time 340627761 ps
CPU time 3.27 seconds
Started Jul 06 06:19:11 PM PDT 24
Finished Jul 06 06:19:15 PM PDT 24
Peak memory 218908 kb
Host smart-27e9d6a3-a8d8-4159-98b0-e36b81a6978b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488788569 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3488788569
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.396975696
Short name T54
Test name
Test status
Simulation time 124447843217 ps
CPU time 359.16 seconds
Started Jul 06 06:24:29 PM PDT 24
Finished Jul 06 06:30:29 PM PDT 24
Peak memory 267636 kb
Host smart-23846354-9d20-4c65-9be4-d0cc8aa98784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396975696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.396975696
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2288395067
Short name T75
Test name
Test status
Simulation time 45878518 ps
CPU time 0.72 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:21:29 PM PDT 24
Peak memory 217040 kb
Host smart-eb0a37ba-e53a-4caf-89e4-5ed57ee2c4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288395067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2288395067
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.450492975
Short name T35
Test name
Test status
Simulation time 31158980344 ps
CPU time 329.15 seconds
Started Jul 06 06:24:55 PM PDT 24
Finished Jul 06 06:30:24 PM PDT 24
Peak memory 268096 kb
Host smart-654970f2-daf2-4738-a8e8-59119a6c59f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450492975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.450492975
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2563608764
Short name T165
Test name
Test status
Simulation time 66907641016 ps
CPU time 201.36 seconds
Started Jul 06 06:24:23 PM PDT 24
Finished Jul 06 06:27:44 PM PDT 24
Peak memory 254032 kb
Host smart-2acfa9ce-110f-457f-9d42-c3cc1e459402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563608764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2563608764
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.721459413
Short name T16
Test name
Test status
Simulation time 109170255 ps
CPU time 1.25 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:21:53 PM PDT 24
Peak memory 236316 kb
Host smart-d671a7f9-226d-45ee-91b4-52161c15d0c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721459413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.721459413
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.838967759
Short name T40
Test name
Test status
Simulation time 4321807781 ps
CPU time 86.18 seconds
Started Jul 06 06:23:18 PM PDT 24
Finished Jul 06 06:24:44 PM PDT 24
Peak memory 266816 kb
Host smart-848d7639-d73c-47c3-abf6-1b78f1ef7e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838967759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.838967759
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.24644205
Short name T46
Test name
Test status
Simulation time 67358224698 ps
CPU time 213.29 seconds
Started Jul 06 06:24:59 PM PDT 24
Finished Jul 06 06:28:32 PM PDT 24
Peak memory 266636 kb
Host smart-cda6ae4a-2d6d-41ca-9aa4-21372ebd1fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24644205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.24644205
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2780373242
Short name T48
Test name
Test status
Simulation time 2847297826 ps
CPU time 11.66 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:51 PM PDT 24
Peak memory 220332 kb
Host smart-3e8dfb1b-7078-4b73-a993-5c6f2d160a5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2780373242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2780373242
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3694760389
Short name T136
Test name
Test status
Simulation time 41933651068 ps
CPU time 455.14 seconds
Started Jul 06 06:22:13 PM PDT 24
Finished Jul 06 06:29:49 PM PDT 24
Peak memory 283204 kb
Host smart-3e032426-73b2-4efc-9b57-a281c8c54f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694760389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3694760389
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2377156964
Short name T55
Test name
Test status
Simulation time 6535721741 ps
CPU time 86.11 seconds
Started Jul 06 06:23:55 PM PDT 24
Finished Jul 06 06:25:21 PM PDT 24
Peak memory 250224 kb
Host smart-4b66e8f5-cb90-4a95-84cf-68fc390d56fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377156964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2377156964
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3279484870
Short name T102
Test name
Test status
Simulation time 4086781970 ps
CPU time 18.36 seconds
Started Jul 06 06:19:45 PM PDT 24
Finished Jul 06 06:20:04 PM PDT 24
Peak memory 215580 kb
Host smart-2665815a-664d-459a-b5fb-040301d01042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279484870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3279484870
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2458803181
Short name T88
Test name
Test status
Simulation time 35773651 ps
CPU time 1.18 seconds
Started Jul 06 06:18:30 PM PDT 24
Finished Jul 06 06:18:31 PM PDT 24
Peak memory 207256 kb
Host smart-10d2f40a-89fb-49cb-be1f-c7d8c5b41fa7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458803181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2458803181
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3246045930
Short name T58
Test name
Test status
Simulation time 9559524316 ps
CPU time 153.63 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:27:10 PM PDT 24
Peak memory 258612 kb
Host smart-cd5db12a-0afe-412c-b3e1-b4eefe129db8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246045930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3246045930
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.261204080
Short name T262
Test name
Test status
Simulation time 26268340083 ps
CPU time 307.28 seconds
Started Jul 06 06:22:05 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 285424 kb
Host smart-d0d3c0aa-8fc4-4052-a3f9-6c1ed3c4a643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261204080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.261204080
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.72413951
Short name T9
Test name
Test status
Simulation time 85410256 ps
CPU time 1.15 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:02 PM PDT 24
Peak memory 217688 kb
Host smart-d3da981d-7e3f-462e-908c-93b8dd31e60b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72413951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.72413951
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3911560903
Short name T184
Test name
Test status
Simulation time 56183764161 ps
CPU time 225.86 seconds
Started Jul 06 06:25:08 PM PDT 24
Finished Jul 06 06:28:54 PM PDT 24
Peak memory 273400 kb
Host smart-216af902-cacc-4a5b-b72d-0f759d060485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911560903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3911560903
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3045359880
Short name T114
Test name
Test status
Simulation time 254864055 ps
CPU time 3.59 seconds
Started Jul 06 06:19:23 PM PDT 24
Finished Jul 06 06:19:27 PM PDT 24
Peak memory 215880 kb
Host smart-8d4aee83-4849-4400-b2c5-47d4c7bac8ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045359880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
045359880
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3778758946
Short name T57
Test name
Test status
Simulation time 72592708164 ps
CPU time 147.66 seconds
Started Jul 06 06:21:31 PM PDT 24
Finished Jul 06 06:24:00 PM PDT 24
Peak memory 250428 kb
Host smart-9abe300f-1e1c-4c4b-98fa-77b7c05f16dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778758946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3778758946
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.949691625
Short name T87
Test name
Test status
Simulation time 11700410243 ps
CPU time 160.5 seconds
Started Jul 06 06:23:14 PM PDT 24
Finished Jul 06 06:25:55 PM PDT 24
Peak memory 275000 kb
Host smart-6b68cc17-fe6f-46d9-a7ac-9cf2b7a8649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949691625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.949691625
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.688881091
Short name T86
Test name
Test status
Simulation time 327668602258 ps
CPU time 563.43 seconds
Started Jul 06 06:24:49 PM PDT 24
Finished Jul 06 06:34:13 PM PDT 24
Peak memory 251380 kb
Host smart-ec915765-39cc-42ee-a6e9-528c31a51e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688881091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.688881091
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.119031843
Short name T202
Test name
Test status
Simulation time 29289923145 ps
CPU time 73.37 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:23:50 PM PDT 24
Peak memory 258416 kb
Host smart-46a703e8-92e6-4ac9-bab5-9c7ce877713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119031843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.119031843
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2076782680
Short name T298
Test name
Test status
Simulation time 740470076 ps
CPU time 19.66 seconds
Started Jul 06 06:22:35 PM PDT 24
Finished Jul 06 06:22:55 PM PDT 24
Peak memory 225536 kb
Host smart-7de04731-f391-44ed-948d-7cfb858a02c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076782680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2076782680
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1897839295
Short name T18
Test name
Test status
Simulation time 56293340873 ps
CPU time 152.88 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:25:10 PM PDT 24
Peak memory 258416 kb
Host smart-9a294647-92de-4cb2-b958-8908da317e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897839295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1897839295
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.946708139
Short name T255
Test name
Test status
Simulation time 260446778238 ps
CPU time 475.59 seconds
Started Jul 06 06:24:42 PM PDT 24
Finished Jul 06 06:32:38 PM PDT 24
Peak memory 274112 kb
Host smart-edaf42ca-8381-4148-b3b5-14b00322cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946708139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.946708139
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.491750823
Short name T343
Test name
Test status
Simulation time 43395154 ps
CPU time 0.75 seconds
Started Jul 06 06:22:25 PM PDT 24
Finished Jul 06 06:22:26 PM PDT 24
Peak memory 205832 kb
Host smart-53745a55-9fb7-400b-9c86-84e35b572215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491750823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.491750823
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3789256067
Short name T290
Test name
Test status
Simulation time 342002408210 ps
CPU time 1095.13 seconds
Started Jul 06 06:22:39 PM PDT 24
Finished Jul 06 06:40:55 PM PDT 24
Peak memory 284144 kb
Host smart-5c120998-fc46-4523-8d14-7ff73bc1adb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789256067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3789256067
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1052542891
Short name T107
Test name
Test status
Simulation time 551816478 ps
CPU time 4.49 seconds
Started Jul 06 06:19:53 PM PDT 24
Finished Jul 06 06:19:58 PM PDT 24
Peak memory 215720 kb
Host smart-b3e60cda-d07b-4ab3-badd-9d0e57b4f849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052542891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1052542891
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.293770067
Short name T226
Test name
Test status
Simulation time 90524246917 ps
CPU time 308.56 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:28:46 PM PDT 24
Peak memory 250328 kb
Host smart-17da044e-b2e0-4902-94ae-5cb61fd7ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293770067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.293770067
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.295680670
Short name T1084
Test name
Test status
Simulation time 1708204679 ps
CPU time 21.36 seconds
Started Jul 06 06:19:28 PM PDT 24
Finished Jul 06 06:19:50 PM PDT 24
Peak memory 215580 kb
Host smart-14edbb66-21e6-496c-8261-0acc6fc1e3c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295680670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.295680670
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.624632226
Short name T25
Test name
Test status
Simulation time 67755503036 ps
CPU time 142.66 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:25:03 PM PDT 24
Peak memory 254448 kb
Host smart-ad763512-5c57-48b4-8a8d-b5bf2fab9c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624632226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.624632226
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.943034176
Short name T281
Test name
Test status
Simulation time 70793276357 ps
CPU time 262.14 seconds
Started Jul 06 06:23:16 PM PDT 24
Finished Jul 06 06:27:39 PM PDT 24
Peak memory 274892 kb
Host smart-7557d034-053c-4f11-84f2-7cc31729ae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943034176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.943034176
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.821405071
Short name T270
Test name
Test status
Simulation time 8762715756 ps
CPU time 124.21 seconds
Started Jul 06 06:24:02 PM PDT 24
Finished Jul 06 06:26:06 PM PDT 24
Peak memory 274012 kb
Host smart-be9c21ce-edb7-41b6-8ebb-2e7e0991109c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821405071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.821405071
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4102784176
Short name T3
Test name
Test status
Simulation time 92247226 ps
CPU time 0.74 seconds
Started Jul 06 06:25:33 PM PDT 24
Finished Jul 06 06:25:35 PM PDT 24
Peak memory 206936 kb
Host smart-971fd4a4-14d3-45f6-8a29-d68aeb251b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102784176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4102784176
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2310536630
Short name T263
Test name
Test status
Simulation time 43198837127 ps
CPU time 382.28 seconds
Started Jul 06 06:21:30 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 255700 kb
Host smart-900375f5-7898-4d2b-9479-ac2ea679b6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310536630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2310536630
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2027440380
Short name T300
Test name
Test status
Simulation time 2218308592 ps
CPU time 30.09 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:21:57 PM PDT 24
Peak memory 242148 kb
Host smart-c9f5fb25-f475-48c8-b943-e52a18f2d9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027440380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2027440380
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.65974046
Short name T314
Test name
Test status
Simulation time 29693780135 ps
CPU time 117.53 seconds
Started Jul 06 06:22:29 PM PDT 24
Finished Jul 06 06:24:27 PM PDT 24
Peak memory 265812 kb
Host smart-bf034418-1270-4912-b36d-bb23bd83e039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65974046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress
_all.65974046
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2008681683
Short name T261
Test name
Test status
Simulation time 80460622772 ps
CPU time 555.17 seconds
Started Jul 06 06:22:31 PM PDT 24
Finished Jul 06 06:31:47 PM PDT 24
Peak memory 258516 kb
Host smart-b741c98e-c861-4408-8316-a41f823a5ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008681683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2008681683
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3941166308
Short name T158
Test name
Test status
Simulation time 17169402018 ps
CPU time 91.27 seconds
Started Jul 06 06:23:18 PM PDT 24
Finished Jul 06 06:24:50 PM PDT 24
Peak memory 258588 kb
Host smart-71bc43fd-a0e0-4015-8bb7-c08957ac1ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941166308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3941166308
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1204704749
Short name T60
Test name
Test status
Simulation time 47245810144 ps
CPU time 420.21 seconds
Started Jul 06 06:25:03 PM PDT 24
Finished Jul 06 06:32:04 PM PDT 24
Peak memory 265048 kb
Host smart-26942638-6047-4221-9d3b-dc4235b44139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204704749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1204704749
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3609949818
Short name T92
Test name
Test status
Simulation time 3304374440 ps
CPU time 7.66 seconds
Started Jul 06 06:25:28 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 220020 kb
Host smart-5bc30ee8-181e-43cd-90dd-c2215310bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609949818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3609949818
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.173675891
Short name T106
Test name
Test status
Simulation time 689320639 ps
CPU time 4.38 seconds
Started Jul 06 06:19:06 PM PDT 24
Finished Jul 06 06:19:10 PM PDT 24
Peak memory 215844 kb
Host smart-a0d5b947-dd97-4a3c-9b32-b2f4ac2ef9df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173675891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.173675891
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1240303149
Short name T104
Test name
Test status
Simulation time 295632898 ps
CPU time 19.65 seconds
Started Jul 06 06:18:42 PM PDT 24
Finished Jul 06 06:19:02 PM PDT 24
Peak memory 215660 kb
Host smart-90a02b13-9e70-4b2c-82c0-08dc13c73adb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240303149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1240303149
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3071800535
Short name T178
Test name
Test status
Simulation time 47394943402 ps
CPU time 413.38 seconds
Started Jul 06 06:22:50 PM PDT 24
Finished Jul 06 06:29:44 PM PDT 24
Peak memory 257596 kb
Host smart-612a1dbe-6f31-4342-8f69-a20fbbc4cf2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071800535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3071800535
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.772422233
Short name T287
Test name
Test status
Simulation time 4070340092 ps
CPU time 36.54 seconds
Started Jul 06 06:22:59 PM PDT 24
Finished Jul 06 06:23:36 PM PDT 24
Peak memory 240176 kb
Host smart-9e91b404-25ef-4bcf-bb02-06c6a37c889d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772422233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.772422233
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1970276466
Short name T216
Test name
Test status
Simulation time 18174416310 ps
CPU time 50.91 seconds
Started Jul 06 06:21:45 PM PDT 24
Finished Jul 06 06:22:36 PM PDT 24
Peak memory 265576 kb
Host smart-79b316d1-1846-4afe-b2be-2cc529fbe97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970276466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1970276466
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2860808639
Short name T272
Test name
Test status
Simulation time 27377237571 ps
CPU time 177.27 seconds
Started Jul 06 06:24:16 PM PDT 24
Finished Jul 06 06:27:14 PM PDT 24
Peak memory 266384 kb
Host smart-3a88a11f-21fd-4236-b64e-2c7bb6d5eaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860808639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2860808639
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3729881306
Short name T324
Test name
Test status
Simulation time 19050841 ps
CPU time 0.78 seconds
Started Jul 06 06:22:43 PM PDT 24
Finished Jul 06 06:22:44 PM PDT 24
Peak memory 206444 kb
Host smart-685f7d1f-7536-4ec5-88b7-28295956e36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729881306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3729881306
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2454033481
Short name T90
Test name
Test status
Simulation time 55464602 ps
CPU time 1.39 seconds
Started Jul 06 06:18:45 PM PDT 24
Finished Jul 06 06:18:47 PM PDT 24
Peak memory 216548 kb
Host smart-d18b40a5-0840-42b6-aff8-02abefcd57de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454033481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2454033481
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.413637681
Short name T120
Test name
Test status
Simulation time 999208127 ps
CPU time 22.87 seconds
Started Jul 06 06:18:31 PM PDT 24
Finished Jul 06 06:18:54 PM PDT 24
Peak memory 207396 kb
Host smart-15b74457-8273-42fe-a9a3-cd957e237160
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413637681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.413637681
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3872354102
Short name T1078
Test name
Test status
Simulation time 669523958 ps
CPU time 12.2 seconds
Started Jul 06 06:18:32 PM PDT 24
Finished Jul 06 06:18:45 PM PDT 24
Peak memory 215528 kb
Host smart-3ebd00ad-9961-45a0-8ba7-2179df574d97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872354102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3872354102
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.875512237
Short name T1062
Test name
Test status
Simulation time 113256792 ps
CPU time 3.6 seconds
Started Jul 06 06:18:35 PM PDT 24
Finished Jul 06 06:18:39 PM PDT 24
Peak memory 218308 kb
Host smart-5d0436a0-a476-40be-acb5-411e7eb13900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875512237 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.875512237
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2066690266
Short name T1113
Test name
Test status
Simulation time 71547307 ps
CPU time 2.39 seconds
Started Jul 06 06:18:31 PM PDT 24
Finished Jul 06 06:18:33 PM PDT 24
Peak memory 215528 kb
Host smart-6554a75e-6e50-408b-88b1-81ad94a4531b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066690266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
066690266
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.375847050
Short name T1033
Test name
Test status
Simulation time 46922358 ps
CPU time 0.75 seconds
Started Jul 06 06:18:29 PM PDT 24
Finished Jul 06 06:18:30 PM PDT 24
Peak memory 204260 kb
Host smart-2770575a-6b33-49c1-94b0-8e3d0031569b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375847050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.375847050
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.249050122
Short name T1085
Test name
Test status
Simulation time 242559336 ps
CPU time 2.04 seconds
Started Jul 06 06:18:30 PM PDT 24
Finished Jul 06 06:18:32 PM PDT 24
Peak memory 215568 kb
Host smart-157a06f4-1495-4bd4-9048-540148b860cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249050122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.249050122
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2148214186
Short name T1028
Test name
Test status
Simulation time 19063674 ps
CPU time 0.69 seconds
Started Jul 06 06:18:31 PM PDT 24
Finished Jul 06 06:18:32 PM PDT 24
Peak memory 204276 kb
Host smart-e20e2665-5a32-4fca-81db-f6d8f527c454
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148214186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2148214186
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1192017433
Short name T1067
Test name
Test status
Simulation time 234686749 ps
CPU time 3.86 seconds
Started Jul 06 06:18:34 PM PDT 24
Finished Jul 06 06:18:39 PM PDT 24
Peak memory 215532 kb
Host smart-2140cf9a-856d-4e05-b5e9-ed85d99cc203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192017433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1192017433
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1319659314
Short name T109
Test name
Test status
Simulation time 58178231 ps
CPU time 1.95 seconds
Started Jul 06 06:18:26 PM PDT 24
Finished Jul 06 06:18:28 PM PDT 24
Peak memory 215748 kb
Host smart-e3ab06a9-0abd-44ba-bee0-6c1f21f3fe82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319659314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
319659314
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.480171224
Short name T1138
Test name
Test status
Simulation time 2891057960 ps
CPU time 16.47 seconds
Started Jul 06 06:18:29 PM PDT 24
Finished Jul 06 06:18:46 PM PDT 24
Peak memory 216160 kb
Host smart-9e095fb5-d685-4d40-bc3c-cd39c4d8dbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480171224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.480171224
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2943331385
Short name T1073
Test name
Test status
Simulation time 1358303142 ps
CPU time 8.95 seconds
Started Jul 06 06:18:43 PM PDT 24
Finished Jul 06 06:18:52 PM PDT 24
Peak memory 207520 kb
Host smart-ffa46889-7bc3-46ee-b415-34580b1dfa76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943331385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2943331385
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2789823632
Short name T1070
Test name
Test status
Simulation time 1222753723 ps
CPU time 11.71 seconds
Started Jul 06 06:18:44 PM PDT 24
Finished Jul 06 06:18:56 PM PDT 24
Peak memory 215516 kb
Host smart-e0f267da-8979-4b75-87f2-e16b7e7a3541
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789823632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2789823632
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3822606709
Short name T117
Test name
Test status
Simulation time 180458902 ps
CPU time 2.76 seconds
Started Jul 06 06:18:51 PM PDT 24
Finished Jul 06 06:18:54 PM PDT 24
Peak memory 218312 kb
Host smart-763d47e9-70b8-4594-a831-7a2b4564b70d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822606709 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3822606709
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4259522113
Short name T119
Test name
Test status
Simulation time 274858662 ps
CPU time 2.47 seconds
Started Jul 06 06:18:44 PM PDT 24
Finished Jul 06 06:18:47 PM PDT 24
Peak memory 215508 kb
Host smart-f59ea459-66bd-4834-9b72-e20a43bc3953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259522113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
259522113
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2427401638
Short name T1116
Test name
Test status
Simulation time 58213879 ps
CPU time 0.73 seconds
Started Jul 06 06:18:38 PM PDT 24
Finished Jul 06 06:18:39 PM PDT 24
Peak memory 204008 kb
Host smart-3b6faa38-ca90-4e5b-bb25-6136ff03333a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427401638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
427401638
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2790516366
Short name T123
Test name
Test status
Simulation time 110242483 ps
CPU time 1.34 seconds
Started Jul 06 06:18:40 PM PDT 24
Finished Jul 06 06:18:41 PM PDT 24
Peak memory 215528 kb
Host smart-b079d8b0-e56f-4952-a2a4-99947557267d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790516366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2790516366
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.424954636
Short name T1066
Test name
Test status
Simulation time 37175227 ps
CPU time 0.68 seconds
Started Jul 06 06:18:39 PM PDT 24
Finished Jul 06 06:18:40 PM PDT 24
Peak memory 203924 kb
Host smart-b5337383-19be-4332-bef0-5d38710fa28b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424954636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.424954636
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2182617932
Short name T1064
Test name
Test status
Simulation time 85576243 ps
CPU time 1.75 seconds
Started Jul 06 06:18:43 PM PDT 24
Finished Jul 06 06:18:45 PM PDT 24
Peak memory 215516 kb
Host smart-8356f460-4739-47e0-91dc-287c56329d59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182617932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2182617932
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1181934922
Short name T103
Test name
Test status
Simulation time 230086774 ps
CPU time 3.54 seconds
Started Jul 06 06:18:33 PM PDT 24
Finished Jul 06 06:18:37 PM PDT 24
Peak memory 215700 kb
Host smart-4aed0fad-b713-4b5b-9d15-55292f7e9de5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181934922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
181934922
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1632726439
Short name T1086
Test name
Test status
Simulation time 256306964 ps
CPU time 3.71 seconds
Started Jul 06 06:19:31 PM PDT 24
Finished Jul 06 06:19:35 PM PDT 24
Peak memory 218504 kb
Host smart-ee072714-0b5b-40aa-89ed-95c008b36068
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632726439 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1632726439
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2300549415
Short name T1144
Test name
Test status
Simulation time 130395322 ps
CPU time 2.03 seconds
Started Jul 06 06:19:25 PM PDT 24
Finished Jul 06 06:19:28 PM PDT 24
Peak memory 215516 kb
Host smart-914bc3ef-164e-4090-8479-aa0454c44da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300549415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2300549415
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2504036860
Short name T1121
Test name
Test status
Simulation time 45021458 ps
CPU time 0.82 seconds
Started Jul 06 06:19:24 PM PDT 24
Finished Jul 06 06:19:25 PM PDT 24
Peak memory 204272 kb
Host smart-b54a49f8-9ea1-40b1-a10f-c90de5eca6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504036860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2504036860
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2905882103
Short name T151
Test name
Test status
Simulation time 73874855 ps
CPU time 1.94 seconds
Started Jul 06 06:19:31 PM PDT 24
Finished Jul 06 06:19:33 PM PDT 24
Peak memory 215596 kb
Host smart-d444c229-9b52-4c59-b5d9-86922d82c0a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905882103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2905882103
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1702358234
Short name T1128
Test name
Test status
Simulation time 205569380 ps
CPU time 1.85 seconds
Started Jul 06 06:19:26 PM PDT 24
Finished Jul 06 06:19:28 PM PDT 24
Peak memory 215704 kb
Host smart-a2fdd478-a2c9-40e0-9f54-879379b713e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702358234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1702358234
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2954628684
Short name T101
Test name
Test status
Simulation time 951669639 ps
CPU time 6.3 seconds
Started Jul 06 06:19:28 PM PDT 24
Finished Jul 06 06:19:34 PM PDT 24
Peak memory 215540 kb
Host smart-11e9580c-ce10-4ebf-a7da-5eda79e1f6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954628684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2954628684
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1154518032
Short name T1047
Test name
Test status
Simulation time 84043683 ps
CPU time 3.06 seconds
Started Jul 06 06:19:31 PM PDT 24
Finished Jul 06 06:19:34 PM PDT 24
Peak memory 217692 kb
Host smart-7abe8af7-850f-4316-8648-e527a93ba4f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154518032 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1154518032
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2232545389
Short name T1071
Test name
Test status
Simulation time 286208390 ps
CPU time 2.07 seconds
Started Jul 06 06:19:28 PM PDT 24
Finished Jul 06 06:19:31 PM PDT 24
Peak memory 215604 kb
Host smart-f5f857f7-d8e8-4558-9f81-c061276df022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232545389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2232545389
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1347491869
Short name T1124
Test name
Test status
Simulation time 16826807 ps
CPU time 0.76 seconds
Started Jul 06 06:19:28 PM PDT 24
Finished Jul 06 06:19:29 PM PDT 24
Peak memory 204320 kb
Host smart-498ec452-6462-4667-8009-1a4341ed4a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347491869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1347491869
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3776939920
Short name T1118
Test name
Test status
Simulation time 110691413 ps
CPU time 1.95 seconds
Started Jul 06 06:19:33 PM PDT 24
Finished Jul 06 06:19:35 PM PDT 24
Peak memory 207364 kb
Host smart-533f264c-f93b-43ea-b1db-bf0f0400be03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776939920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3776939920
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2423558756
Short name T1127
Test name
Test status
Simulation time 39862102 ps
CPU time 2.51 seconds
Started Jul 06 06:19:30 PM PDT 24
Finished Jul 06 06:19:33 PM PDT 24
Peak memory 215824 kb
Host smart-1266b579-d2dc-4b43-ab48-df77a37df571
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423558756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2423558756
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3742841917
Short name T1049
Test name
Test status
Simulation time 256744999 ps
CPU time 3.69 seconds
Started Jul 06 06:19:33 PM PDT 24
Finished Jul 06 06:19:37 PM PDT 24
Peak memory 218780 kb
Host smart-3d323cf8-5125-46d7-85ae-1017a709161c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742841917 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3742841917
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1258674816
Short name T1092
Test name
Test status
Simulation time 297869790 ps
CPU time 2.26 seconds
Started Jul 06 06:19:33 PM PDT 24
Finished Jul 06 06:19:36 PM PDT 24
Peak memory 215512 kb
Host smart-1739ada2-5cfc-4cf9-a440-3fad31fd3809
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258674816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1258674816
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.825430249
Short name T1076
Test name
Test status
Simulation time 13091779 ps
CPU time 0.71 seconds
Started Jul 06 06:19:33 PM PDT 24
Finished Jul 06 06:19:34 PM PDT 24
Peak memory 204012 kb
Host smart-ed360412-c930-43a5-9efe-5da68adf9ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825430249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.825430249
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4187616311
Short name T1112
Test name
Test status
Simulation time 167538714 ps
CPU time 4.31 seconds
Started Jul 06 06:19:32 PM PDT 24
Finished Jul 06 06:19:37 PM PDT 24
Peak memory 215528 kb
Host smart-e80d83b2-8d59-4237-9fa3-3767c19b64b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187616311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4187616311
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2068316984
Short name T1132
Test name
Test status
Simulation time 444076890 ps
CPU time 2.49 seconds
Started Jul 06 06:19:28 PM PDT 24
Finished Jul 06 06:19:31 PM PDT 24
Peak memory 216664 kb
Host smart-6426fe32-8bb0-43c8-83b9-bc93e9466797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068316984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2068316984
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1576948681
Short name T170
Test name
Test status
Simulation time 3341435829 ps
CPU time 12.92 seconds
Started Jul 06 06:19:27 PM PDT 24
Finished Jul 06 06:19:40 PM PDT 24
Peak memory 215596 kb
Host smart-4ae0b3fa-c137-4e19-a2b1-41ee44e04f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576948681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1576948681
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4204823794
Short name T154
Test name
Test status
Simulation time 118526406 ps
CPU time 1.73 seconds
Started Jul 06 06:19:38 PM PDT 24
Finished Jul 06 06:19:41 PM PDT 24
Peak memory 215652 kb
Host smart-4b1647e8-c199-467a-8911-609aaa7c31d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204823794 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4204823794
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.206584093
Short name T1148
Test name
Test status
Simulation time 40422538 ps
CPU time 2.42 seconds
Started Jul 06 06:19:38 PM PDT 24
Finished Jul 06 06:19:41 PM PDT 24
Peak memory 207404 kb
Host smart-4e032ac3-058f-4f45-968c-540d30f16d5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206584093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.206584093
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1524896892
Short name T1052
Test name
Test status
Simulation time 18220407 ps
CPU time 0.7 seconds
Started Jul 06 06:19:44 PM PDT 24
Finished Jul 06 06:19:45 PM PDT 24
Peak memory 204308 kb
Host smart-9eab3b85-3d26-4e6e-b4d7-f517f725b067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524896892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1524896892
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.810393354
Short name T139
Test name
Test status
Simulation time 582444808 ps
CPU time 3.26 seconds
Started Jul 06 06:19:39 PM PDT 24
Finished Jul 06 06:19:43 PM PDT 24
Peak memory 215568 kb
Host smart-845962b2-0f8b-44a9-a55b-f7bf8ec68fba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810393354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.810393354
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.844489901
Short name T111
Test name
Test status
Simulation time 56236033 ps
CPU time 1.86 seconds
Started Jul 06 06:19:33 PM PDT 24
Finished Jul 06 06:19:35 PM PDT 24
Peak memory 215824 kb
Host smart-0f3a50cc-e564-4b38-ae96-dfdd59b49315
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844489901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.844489901
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3110403232
Short name T1111
Test name
Test status
Simulation time 689239520 ps
CPU time 8.21 seconds
Started Jul 06 06:19:33 PM PDT 24
Finished Jul 06 06:19:41 PM PDT 24
Peak memory 216132 kb
Host smart-eae6fc40-3205-41d6-b953-a1fe9c6ca6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110403232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3110403232
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2315806139
Short name T1125
Test name
Test status
Simulation time 202823350 ps
CPU time 3.24 seconds
Started Jul 06 06:19:42 PM PDT 24
Finished Jul 06 06:19:46 PM PDT 24
Peak memory 217380 kb
Host smart-9843885b-62a8-4e63-9b49-cd1b048e4485
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315806139 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2315806139
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3711197118
Short name T1120
Test name
Test status
Simulation time 299682806 ps
CPU time 2.78 seconds
Started Jul 06 06:19:38 PM PDT 24
Finished Jul 06 06:19:42 PM PDT 24
Peak memory 215520 kb
Host smart-82bed08f-a59a-4515-b248-7a79108f33a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711197118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3711197118
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.354615083
Short name T1050
Test name
Test status
Simulation time 51283136 ps
CPU time 0.77 seconds
Started Jul 06 06:19:44 PM PDT 24
Finished Jul 06 06:19:45 PM PDT 24
Peak memory 204068 kb
Host smart-1f5128bc-5b10-4c0f-9fe1-b6944e5e92f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354615083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.354615083
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.384619124
Short name T1077
Test name
Test status
Simulation time 131722006 ps
CPU time 2.88 seconds
Started Jul 06 06:19:38 PM PDT 24
Finished Jul 06 06:19:42 PM PDT 24
Peak memory 215572 kb
Host smart-54af52ba-9775-4492-84bc-424090002747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384619124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.384619124
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1922989365
Short name T112
Test name
Test status
Simulation time 206644286 ps
CPU time 3.45 seconds
Started Jul 06 06:19:38 PM PDT 24
Finished Jul 06 06:19:42 PM PDT 24
Peak memory 216704 kb
Host smart-3c29961c-f8fd-4db7-b332-21dc06d8d834
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922989365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1922989365
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1924511690
Short name T1133
Test name
Test status
Simulation time 1180750140 ps
CPU time 20.96 seconds
Started Jul 06 06:19:37 PM PDT 24
Finished Jul 06 06:19:59 PM PDT 24
Peak memory 216284 kb
Host smart-b5b486ac-1adc-4b88-ab50-a2695fdea81c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924511690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1924511690
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2636324214
Short name T1093
Test name
Test status
Simulation time 406695430 ps
CPU time 2.75 seconds
Started Jul 06 06:19:48 PM PDT 24
Finished Jul 06 06:19:51 PM PDT 24
Peak memory 216968 kb
Host smart-44b25d07-2225-4021-813e-3fc86e996e86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636324214 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2636324214
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.994419054
Short name T1131
Test name
Test status
Simulation time 484823379 ps
CPU time 2.52 seconds
Started Jul 06 06:19:45 PM PDT 24
Finished Jul 06 06:19:48 PM PDT 24
Peak memory 207356 kb
Host smart-1236635a-21d2-4e32-aa19-d734959bbe0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994419054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.994419054
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.44719776
Short name T1074
Test name
Test status
Simulation time 12925230 ps
CPU time 0.72 seconds
Started Jul 06 06:19:43 PM PDT 24
Finished Jul 06 06:19:44 PM PDT 24
Peak memory 203980 kb
Host smart-f396a4a4-8d9b-405d-a085-f97f54c25198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44719776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.44719776
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3391843468
Short name T1136
Test name
Test status
Simulation time 221473097 ps
CPU time 3.59 seconds
Started Jul 06 06:19:42 PM PDT 24
Finished Jul 06 06:19:46 PM PDT 24
Peak memory 215584 kb
Host smart-188b4baa-8739-4ba3-843a-15ea2a1394d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391843468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3391843468
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1832212142
Short name T110
Test name
Test status
Simulation time 60569202 ps
CPU time 3.72 seconds
Started Jul 06 06:19:42 PM PDT 24
Finished Jul 06 06:19:46 PM PDT 24
Peak memory 215764 kb
Host smart-fe7e99f9-df1c-49d6-81e2-160dc0518fee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832212142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1832212142
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.640613609
Short name T1134
Test name
Test status
Simulation time 85270140 ps
CPU time 2.75 seconds
Started Jul 06 06:19:48 PM PDT 24
Finished Jul 06 06:19:51 PM PDT 24
Peak memory 216984 kb
Host smart-d7ce4d8d-931d-4744-ba4c-4e41064efe13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640613609 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.640613609
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2678254736
Short name T1150
Test name
Test status
Simulation time 84616660 ps
CPU time 2.26 seconds
Started Jul 06 06:19:49 PM PDT 24
Finished Jul 06 06:19:52 PM PDT 24
Peak memory 215540 kb
Host smart-d0f7eb77-6ced-4095-a9ac-8d170846edec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678254736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2678254736
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2753255296
Short name T1140
Test name
Test status
Simulation time 35477843 ps
CPU time 0.71 seconds
Started Jul 06 06:19:53 PM PDT 24
Finished Jul 06 06:19:54 PM PDT 24
Peak memory 203920 kb
Host smart-e9cd87a3-438a-4033-b700-fbcd0183b102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753255296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2753255296
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2271638952
Short name T1054
Test name
Test status
Simulation time 161844950 ps
CPU time 2.78 seconds
Started Jul 06 06:19:48 PM PDT 24
Finished Jul 06 06:19:51 PM PDT 24
Peak memory 215560 kb
Host smart-add42eb1-2688-4d2a-b8df-05f3a3ee96ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271638952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2271638952
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2698295013
Short name T1100
Test name
Test status
Simulation time 345393221 ps
CPU time 4.65 seconds
Started Jul 06 06:19:47 PM PDT 24
Finished Jul 06 06:19:52 PM PDT 24
Peak memory 215688 kb
Host smart-52353039-1a46-4eb7-b91c-2afa81b20a81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698295013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2698295013
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3263040072
Short name T175
Test name
Test status
Simulation time 549593886 ps
CPU time 15.23 seconds
Started Jul 06 06:19:51 PM PDT 24
Finished Jul 06 06:20:07 PM PDT 24
Peak memory 215544 kb
Host smart-b06c71c6-0b7f-4c10-a0ef-1e56aca0337a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263040072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3263040072
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1227099041
Short name T99
Test name
Test status
Simulation time 504843140 ps
CPU time 3.68 seconds
Started Jul 06 06:19:52 PM PDT 24
Finished Jul 06 06:19:56 PM PDT 24
Peak memory 217420 kb
Host smart-be26bb9f-7ab4-413d-a50f-db4416cad401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227099041 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1227099041
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.49942616
Short name T1146
Test name
Test status
Simulation time 27642155 ps
CPU time 1.66 seconds
Started Jul 06 06:19:58 PM PDT 24
Finished Jul 06 06:20:00 PM PDT 24
Peak memory 215588 kb
Host smart-60f1e452-49b7-4b02-b75f-1773cfef43a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49942616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.49942616
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2915530714
Short name T1041
Test name
Test status
Simulation time 35245658 ps
CPU time 0.71 seconds
Started Jul 06 06:19:48 PM PDT 24
Finished Jul 06 06:19:49 PM PDT 24
Peak memory 203968 kb
Host smart-afd7f2b9-7098-4b05-86b0-9c693f9ca269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915530714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2915530714
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.884376822
Short name T140
Test name
Test status
Simulation time 86579522 ps
CPU time 2.75 seconds
Started Jul 06 06:19:54 PM PDT 24
Finished Jul 06 06:19:57 PM PDT 24
Peak memory 215440 kb
Host smart-08a591c8-8a7b-4deb-bfca-0573854d8ebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884376822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.884376822
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.625203779
Short name T108
Test name
Test status
Simulation time 196926292 ps
CPU time 3.46 seconds
Started Jul 06 06:19:48 PM PDT 24
Finished Jul 06 06:19:52 PM PDT 24
Peak memory 215684 kb
Host smart-ae163f97-079c-4f20-9771-f3a0a345cb76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625203779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.625203779
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.324550147
Short name T1079
Test name
Test status
Simulation time 202688930 ps
CPU time 12.03 seconds
Started Jul 06 06:19:48 PM PDT 24
Finished Jul 06 06:20:00 PM PDT 24
Peak memory 215468 kb
Host smart-c0a9c287-8c77-46db-a12e-803dcee2bbb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324550147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.324550147
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2253247454
Short name T116
Test name
Test status
Simulation time 209301487 ps
CPU time 2.89 seconds
Started Jul 06 06:19:53 PM PDT 24
Finished Jul 06 06:19:56 PM PDT 24
Peak memory 216940 kb
Host smart-47451fd1-da1f-4746-b811-34c925755d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253247454 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2253247454
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.545448262
Short name T1082
Test name
Test status
Simulation time 45249487 ps
CPU time 1.42 seconds
Started Jul 06 06:19:52 PM PDT 24
Finished Jul 06 06:19:54 PM PDT 24
Peak memory 215596 kb
Host smart-5594164e-c273-46ad-893c-f9cc8c9a13d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545448262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.545448262
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3599996238
Short name T1149
Test name
Test status
Simulation time 16729608 ps
CPU time 0.75 seconds
Started Jul 06 06:19:52 PM PDT 24
Finished Jul 06 06:19:54 PM PDT 24
Peak memory 204016 kb
Host smart-3fc76c70-72ec-481d-abbd-29d1e905ab0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599996238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3599996238
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4026578132
Short name T1103
Test name
Test status
Simulation time 83156519 ps
CPU time 2.02 seconds
Started Jul 06 06:19:58 PM PDT 24
Finished Jul 06 06:20:01 PM PDT 24
Peak memory 215604 kb
Host smart-1e95d6b4-3f86-4451-aa4e-2b3be5bede3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026578132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4026578132
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1762372274
Short name T174
Test name
Test status
Simulation time 4364867141 ps
CPU time 20.01 seconds
Started Jul 06 06:19:53 PM PDT 24
Finished Jul 06 06:20:13 PM PDT 24
Peak memory 216596 kb
Host smart-79ca7a28-c7bc-4111-a8df-9610e4430202
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762372274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1762372274
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2047900607
Short name T1106
Test name
Test status
Simulation time 428454247 ps
CPU time 2.9 seconds
Started Jul 06 06:20:05 PM PDT 24
Finished Jul 06 06:20:09 PM PDT 24
Peak memory 216632 kb
Host smart-fb4ddc45-4948-4eb5-8826-f320b8860d33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047900607 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2047900607
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.852392360
Short name T1099
Test name
Test status
Simulation time 18667305 ps
CPU time 1.19 seconds
Started Jul 06 06:20:02 PM PDT 24
Finished Jul 06 06:20:03 PM PDT 24
Peak memory 215496 kb
Host smart-67731c89-07c1-4c8d-9edf-f1fca4e8ed03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852392360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.852392360
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2107608097
Short name T1035
Test name
Test status
Simulation time 39875433 ps
CPU time 0.76 seconds
Started Jul 06 06:20:01 PM PDT 24
Finished Jul 06 06:20:02 PM PDT 24
Peak memory 204028 kb
Host smart-c0ca0aa1-19ab-47aa-b510-6621006526f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107608097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2107608097
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1398413543
Short name T152
Test name
Test status
Simulation time 3742579791 ps
CPU time 4.15 seconds
Started Jul 06 06:20:03 PM PDT 24
Finished Jul 06 06:20:07 PM PDT 24
Peak memory 215652 kb
Host smart-4cbbd0dc-f027-433e-acd2-df9a8da2f370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398413543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1398413543
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3073390950
Short name T169
Test name
Test status
Simulation time 48538609 ps
CPU time 3.03 seconds
Started Jul 06 06:19:59 PM PDT 24
Finished Jul 06 06:20:02 PM PDT 24
Peak memory 215756 kb
Host smart-55ac0c8a-9b17-4e58-a3f4-81a756e0907f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073390950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3073390950
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3505497076
Short name T1110
Test name
Test status
Simulation time 208879483 ps
CPU time 6.49 seconds
Started Jul 06 06:19:57 PM PDT 24
Finished Jul 06 06:20:04 PM PDT 24
Peak memory 215648 kb
Host smart-9536142f-d0e3-4904-bea0-1ef25b74b246
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505497076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3505497076
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1590359841
Short name T118
Test name
Test status
Simulation time 518205794 ps
CPU time 14.81 seconds
Started Jul 06 06:18:53 PM PDT 24
Finished Jul 06 06:19:08 PM PDT 24
Peak memory 215600 kb
Host smart-470d21d5-7f4c-43ed-bce4-d6899c83b2ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590359841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1590359841
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2996813228
Short name T1117
Test name
Test status
Simulation time 742145802 ps
CPU time 11.24 seconds
Started Jul 06 06:18:51 PM PDT 24
Finished Jul 06 06:19:03 PM PDT 24
Peak memory 207284 kb
Host smart-8cc35f88-793d-4248-bfca-957f27cf6a47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996813228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2996813228
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2168953175
Short name T1072
Test name
Test status
Simulation time 30558219 ps
CPU time 0.92 seconds
Started Jul 06 06:18:53 PM PDT 24
Finished Jul 06 06:18:54 PM PDT 24
Peak memory 206864 kb
Host smart-cac2f49b-5309-4793-a845-2d61f83d95b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168953175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2168953175
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1713760891
Short name T1135
Test name
Test status
Simulation time 71023726 ps
CPU time 2.03 seconds
Started Jul 06 06:18:52 PM PDT 24
Finished Jul 06 06:18:54 PM PDT 24
Peak memory 215568 kb
Host smart-0dbf4bb7-24ab-4920-bb8e-c5bd81d77509
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713760891 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1713760891
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3877725677
Short name T126
Test name
Test status
Simulation time 107441413 ps
CPU time 1.96 seconds
Started Jul 06 06:18:53 PM PDT 24
Finished Jul 06 06:18:56 PM PDT 24
Peak memory 207400 kb
Host smart-c3b491a5-76a8-45e4-a4b5-15ed1c511abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877725677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
877725677
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2562263550
Short name T1057
Test name
Test status
Simulation time 45277562 ps
CPU time 0.68 seconds
Started Jul 06 06:18:50 PM PDT 24
Finished Jul 06 06:18:51 PM PDT 24
Peak memory 203976 kb
Host smart-2c6be0fb-bfa8-441f-8efb-9ca680b1b974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562263550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
562263550
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4186557861
Short name T124
Test name
Test status
Simulation time 102661187 ps
CPU time 2.07 seconds
Started Jul 06 06:18:47 PM PDT 24
Finished Jul 06 06:18:49 PM PDT 24
Peak memory 215548 kb
Host smart-6200251d-abe5-4dd6-984c-cbb0c7f4f10b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186557861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4186557861
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4139339015
Short name T1065
Test name
Test status
Simulation time 33623543 ps
CPU time 0.67 seconds
Started Jul 06 06:18:47 PM PDT 24
Finished Jul 06 06:18:48 PM PDT 24
Peak memory 203880 kb
Host smart-aaffe41c-263f-42b2-a368-f0572db66ad8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139339015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4139339015
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1043051696
Short name T142
Test name
Test status
Simulation time 79699486 ps
CPU time 1.94 seconds
Started Jul 06 06:18:54 PM PDT 24
Finished Jul 06 06:18:56 PM PDT 24
Peak memory 215460 kb
Host smart-55891524-033b-469e-a002-8d6a6285502d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043051696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1043051696
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2026897443
Short name T113
Test name
Test status
Simulation time 284968065 ps
CPU time 3.93 seconds
Started Jul 06 06:18:49 PM PDT 24
Finished Jul 06 06:18:54 PM PDT 24
Peak memory 215668 kb
Host smart-82aa3120-ad1b-4d73-9dec-a3c83e7c1d51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026897443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
026897443
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2885989267
Short name T1142
Test name
Test status
Simulation time 7695148835 ps
CPU time 23.77 seconds
Started Jul 06 06:18:49 PM PDT 24
Finished Jul 06 06:19:13 PM PDT 24
Peak memory 217248 kb
Host smart-c8db6b22-6187-4549-81eb-fdc4b808a521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885989267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2885989267
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3057497490
Short name T1046
Test name
Test status
Simulation time 35980545 ps
CPU time 0.68 seconds
Started Jul 06 06:20:08 PM PDT 24
Finished Jul 06 06:20:09 PM PDT 24
Peak memory 203924 kb
Host smart-eb112407-d184-49d4-9a05-703f1fc7ddd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057497490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3057497490
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.170313218
Short name T1087
Test name
Test status
Simulation time 52317033 ps
CPU time 0.79 seconds
Started Jul 06 06:20:03 PM PDT 24
Finished Jul 06 06:20:04 PM PDT 24
Peak memory 203960 kb
Host smart-1932277a-8431-45c7-8ba5-886f34ade175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170313218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.170313218
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3656039333
Short name T1058
Test name
Test status
Simulation time 11793476 ps
CPU time 0.7 seconds
Started Jul 06 06:20:08 PM PDT 24
Finished Jul 06 06:20:09 PM PDT 24
Peak memory 204204 kb
Host smart-9cf94ff0-8bad-43f0-a976-8230216997f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656039333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3656039333
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4200039278
Short name T1091
Test name
Test status
Simulation time 51671303 ps
CPU time 0.75 seconds
Started Jul 06 06:20:03 PM PDT 24
Finished Jul 06 06:20:04 PM PDT 24
Peak memory 204232 kb
Host smart-4a859338-9180-488b-8c5e-dddca6dbdcf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200039278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4200039278
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2540079240
Short name T1048
Test name
Test status
Simulation time 59184319 ps
CPU time 0.79 seconds
Started Jul 06 06:20:06 PM PDT 24
Finished Jul 06 06:20:07 PM PDT 24
Peak memory 204260 kb
Host smart-cd2cd808-76a7-4a3c-96f8-e242a5f90f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540079240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2540079240
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2127454763
Short name T1107
Test name
Test status
Simulation time 11442088 ps
CPU time 0.68 seconds
Started Jul 06 06:20:07 PM PDT 24
Finished Jul 06 06:20:08 PM PDT 24
Peak memory 204324 kb
Host smart-4b0c5a7a-feb1-49d7-bc7b-369daf167406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127454763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2127454763
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2795538824
Short name T1056
Test name
Test status
Simulation time 31565999 ps
CPU time 0.66 seconds
Started Jul 06 06:20:03 PM PDT 24
Finished Jul 06 06:20:04 PM PDT 24
Peak memory 204304 kb
Host smart-b42d33e9-51bf-4d5c-b6b7-54d07626e6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795538824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2795538824
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3339962514
Short name T1029
Test name
Test status
Simulation time 17712661 ps
CPU time 0.82 seconds
Started Jul 06 06:20:05 PM PDT 24
Finished Jul 06 06:20:06 PM PDT 24
Peak memory 204280 kb
Host smart-67f15986-d452-44d5-99a5-a8af5172c2c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339962514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3339962514
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2020182002
Short name T1069
Test name
Test status
Simulation time 14821368 ps
CPU time 0.8 seconds
Started Jul 06 06:20:03 PM PDT 24
Finished Jul 06 06:20:05 PM PDT 24
Peak memory 204048 kb
Host smart-ba70211e-a2dc-4f03-8c2c-a6c5b5ab6a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020182002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2020182002
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3677966432
Short name T1141
Test name
Test status
Simulation time 81198885 ps
CPU time 0.73 seconds
Started Jul 06 06:20:06 PM PDT 24
Finished Jul 06 06:20:07 PM PDT 24
Peak memory 203984 kb
Host smart-da7ee8cb-f206-4cd6-8faf-a91e676e18f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677966432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3677966432
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1860506138
Short name T122
Test name
Test status
Simulation time 759825869 ps
CPU time 15.02 seconds
Started Jul 06 06:18:59 PM PDT 24
Finished Jul 06 06:19:14 PM PDT 24
Peak memory 215496 kb
Host smart-60104372-22f1-49d2-8441-cb9c8ec7d3b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860506138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1860506138
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1822953342
Short name T125
Test name
Test status
Simulation time 4010289479 ps
CPU time 31.29 seconds
Started Jul 06 06:18:57 PM PDT 24
Finished Jul 06 06:19:28 PM PDT 24
Peak memory 216652 kb
Host smart-941c8ec8-e394-45c7-92e6-2657119c38e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822953342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1822953342
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1203897446
Short name T89
Test name
Test status
Simulation time 32992086 ps
CPU time 0.89 seconds
Started Jul 06 06:18:57 PM PDT 24
Finished Jul 06 06:18:58 PM PDT 24
Peak memory 207084 kb
Host smart-e73f8c69-04dd-4b8d-91b0-42a3b54e899a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203897446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1203897446
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1107921513
Short name T1059
Test name
Test status
Simulation time 54616016 ps
CPU time 1.96 seconds
Started Jul 06 06:19:02 PM PDT 24
Finished Jul 06 06:19:04 PM PDT 24
Peak memory 216732 kb
Host smart-2084be79-6f03-4696-8ca3-9cc084a0e354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107921513 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1107921513
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3091094814
Short name T1095
Test name
Test status
Simulation time 521607521 ps
CPU time 2.37 seconds
Started Jul 06 06:18:58 PM PDT 24
Finished Jul 06 06:19:01 PM PDT 24
Peak memory 215580 kb
Host smart-4239bc08-1d26-409d-9669-18379f37504f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091094814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
091094814
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3537300245
Short name T1068
Test name
Test status
Simulation time 59691907 ps
CPU time 0.73 seconds
Started Jul 06 06:18:57 PM PDT 24
Finished Jul 06 06:18:58 PM PDT 24
Peak memory 204272 kb
Host smart-a1cdf406-2c31-4e53-ae70-9f8ceeaf8bfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537300245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
537300245
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1287342073
Short name T1039
Test name
Test status
Simulation time 75737584 ps
CPU time 1.58 seconds
Started Jul 06 06:18:57 PM PDT 24
Finished Jul 06 06:18:59 PM PDT 24
Peak memory 215592 kb
Host smart-7b06ac8f-a953-4fe3-8338-677f43fcb7d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287342073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1287342073
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1359243864
Short name T1032
Test name
Test status
Simulation time 10796915 ps
CPU time 0.67 seconds
Started Jul 06 06:18:57 PM PDT 24
Finished Jul 06 06:18:58 PM PDT 24
Peak memory 203848 kb
Host smart-7e5b6919-c4fc-402c-901f-59b3b649a065
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359243864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1359243864
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2486078006
Short name T1108
Test name
Test status
Simulation time 59922534 ps
CPU time 3.86 seconds
Started Jul 06 06:19:12 PM PDT 24
Finished Jul 06 06:19:16 PM PDT 24
Peak memory 215592 kb
Host smart-68dcb6d8-50dd-4aee-8ed1-27e3466ead46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486078006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2486078006
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.765557605
Short name T98
Test name
Test status
Simulation time 88301420 ps
CPU time 2.29 seconds
Started Jul 06 06:18:57 PM PDT 24
Finished Jul 06 06:18:59 PM PDT 24
Peak memory 215732 kb
Host smart-3f05a77e-b419-42f3-9e14-8cfd7eecf2e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765557605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.765557605
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3342331808
Short name T1089
Test name
Test status
Simulation time 448333353 ps
CPU time 13.54 seconds
Started Jul 06 06:18:56 PM PDT 24
Finished Jul 06 06:19:10 PM PDT 24
Peak memory 215396 kb
Host smart-c4ee1356-6c77-49da-bff0-22451dcd5b63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342331808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3342331808
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1830237878
Short name T1123
Test name
Test status
Simulation time 72075411 ps
CPU time 0.7 seconds
Started Jul 06 06:20:13 PM PDT 24
Finished Jul 06 06:20:14 PM PDT 24
Peak memory 203988 kb
Host smart-07b4b213-011c-433d-bc9e-aae6f5913edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830237878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1830237878
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2916186227
Short name T1043
Test name
Test status
Simulation time 41254127 ps
CPU time 0.71 seconds
Started Jul 06 06:20:08 PM PDT 24
Finished Jul 06 06:20:09 PM PDT 24
Peak memory 204036 kb
Host smart-3bb0757e-061e-47df-b7ea-e3dd68807b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916186227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2916186227
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.915273896
Short name T1038
Test name
Test status
Simulation time 29278795 ps
CPU time 0.73 seconds
Started Jul 06 06:20:08 PM PDT 24
Finished Jul 06 06:20:09 PM PDT 24
Peak memory 204048 kb
Host smart-9aebb18c-a5d0-4339-853a-bdfea2c7ad6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915273896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.915273896
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2839583000
Short name T1034
Test name
Test status
Simulation time 19247983 ps
CPU time 0.84 seconds
Started Jul 06 06:20:10 PM PDT 24
Finished Jul 06 06:20:11 PM PDT 24
Peak memory 204000 kb
Host smart-7c7d97e8-7f10-47d6-9c79-9e8058bc43fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839583000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2839583000
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4006748214
Short name T1031
Test name
Test status
Simulation time 25789977 ps
CPU time 0.72 seconds
Started Jul 06 06:20:07 PM PDT 24
Finished Jul 06 06:20:08 PM PDT 24
Peak memory 203992 kb
Host smart-9ab1cc6e-12d1-4ccc-a6a8-1575d27f3ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006748214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4006748214
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1380935737
Short name T1130
Test name
Test status
Simulation time 16989760 ps
CPU time 0.78 seconds
Started Jul 06 06:20:09 PM PDT 24
Finished Jul 06 06:20:10 PM PDT 24
Peak memory 204084 kb
Host smart-be2bc4de-44fd-4a0c-bdeb-a626210bb9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380935737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1380935737
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.927731875
Short name T1036
Test name
Test status
Simulation time 41209739 ps
CPU time 0.69 seconds
Started Jul 06 06:20:07 PM PDT 24
Finished Jul 06 06:20:08 PM PDT 24
Peak memory 204004 kb
Host smart-e68cb928-2f12-4112-b33f-d8fde5f58a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927731875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.927731875
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2207268058
Short name T1060
Test name
Test status
Simulation time 13215456 ps
CPU time 0.76 seconds
Started Jul 06 06:20:13 PM PDT 24
Finished Jul 06 06:20:15 PM PDT 24
Peak memory 204036 kb
Host smart-7492b3ed-6ec5-40a4-8b1b-500f2b9ce34b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207268058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2207268058
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.382336695
Short name T1088
Test name
Test status
Simulation time 52059523 ps
CPU time 0.74 seconds
Started Jul 06 06:20:08 PM PDT 24
Finished Jul 06 06:20:09 PM PDT 24
Peak memory 204004 kb
Host smart-a21c1104-5649-4548-8dbf-8a27a033f61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382336695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.382336695
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2658495393
Short name T1090
Test name
Test status
Simulation time 40608046 ps
CPU time 0.75 seconds
Started Jul 06 06:20:14 PM PDT 24
Finished Jul 06 06:20:15 PM PDT 24
Peak memory 204308 kb
Host smart-1a7c079f-6cb9-4770-90b9-6dae3e843fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658495393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2658495393
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3179704252
Short name T1080
Test name
Test status
Simulation time 861971897 ps
CPU time 8.78 seconds
Started Jul 06 06:19:13 PM PDT 24
Finished Jul 06 06:19:22 PM PDT 24
Peak memory 215408 kb
Host smart-cb843e9f-69a8-4081-9b24-85f851e6a0a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179704252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3179704252
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.280210454
Short name T127
Test name
Test status
Simulation time 2086936722 ps
CPU time 31.78 seconds
Started Jul 06 06:19:01 PM PDT 24
Finished Jul 06 06:19:33 PM PDT 24
Peak memory 207264 kb
Host smart-e4729866-ea96-43e1-8d6c-484164e1ae21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280210454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.280210454
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.181226409
Short name T91
Test name
Test status
Simulation time 45514236 ps
CPU time 1.36 seconds
Started Jul 06 06:19:12 PM PDT 24
Finished Jul 06 06:19:14 PM PDT 24
Peak memory 216552 kb
Host smart-09e72182-6380-4306-a21e-fb462e969f09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181226409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.181226409
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1986471263
Short name T1061
Test name
Test status
Simulation time 309543855 ps
CPU time 3.92 seconds
Started Jul 06 06:19:05 PM PDT 24
Finished Jul 06 06:19:09 PM PDT 24
Peak memory 217088 kb
Host smart-2b412d82-cd6b-49d9-ac52-4421f34430f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986471263 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1986471263
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3295728387
Short name T1147
Test name
Test status
Simulation time 143873104 ps
CPU time 2.55 seconds
Started Jul 06 06:19:02 PM PDT 24
Finished Jul 06 06:19:05 PM PDT 24
Peak memory 207276 kb
Host smart-c46b5f39-bf4a-477f-a305-01ffa102fd2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295728387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
295728387
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4059799003
Short name T1129
Test name
Test status
Simulation time 13951830 ps
CPU time 0.73 seconds
Started Jul 06 06:19:03 PM PDT 24
Finished Jul 06 06:19:04 PM PDT 24
Peak memory 204256 kb
Host smart-7a7960d2-8d97-4554-a8f5-e5ef053b29d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059799003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
059799003
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.56166667
Short name T1083
Test name
Test status
Simulation time 66655029 ps
CPU time 2.16 seconds
Started Jul 06 06:19:02 PM PDT 24
Finished Jul 06 06:19:04 PM PDT 24
Peak memory 215532 kb
Host smart-de74e921-9224-4b85-a1fe-c9dbc6f875ba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56166667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_d
evice_mem_partial_access.56166667
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.34303906
Short name T1037
Test name
Test status
Simulation time 11553624 ps
CPU time 0.7 seconds
Started Jul 06 06:19:02 PM PDT 24
Finished Jul 06 06:19:03 PM PDT 24
Peak memory 204292 kb
Host smart-7e37b776-bee7-4021-b0a9-dc0abe5c2eca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34303906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_
walk.34303906
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3143708868
Short name T153
Test name
Test status
Simulation time 208105417 ps
CPU time 4.22 seconds
Started Jul 06 06:19:07 PM PDT 24
Finished Jul 06 06:19:11 PM PDT 24
Peak memory 215828 kb
Host smart-af938bf5-7981-44cd-8467-3faddb4be72c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143708868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3143708868
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.328976751
Short name T1143
Test name
Test status
Simulation time 168374118 ps
CPU time 3.82 seconds
Started Jul 06 06:19:02 PM PDT 24
Finished Jul 06 06:19:06 PM PDT 24
Peak memory 215760 kb
Host smart-41d210d6-5baf-4696-9ba5-83d3a68305a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328976751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.328976751
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2339560378
Short name T155
Test name
Test status
Simulation time 919253000 ps
CPU time 16.02 seconds
Started Jul 06 06:19:02 PM PDT 24
Finished Jul 06 06:19:18 PM PDT 24
Peak memory 215936 kb
Host smart-703d461e-1693-41b4-bb55-32deed7fb840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339560378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2339560378
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.526686920
Short name T1097
Test name
Test status
Simulation time 18652233 ps
CPU time 0.72 seconds
Started Jul 06 06:20:16 PM PDT 24
Finished Jul 06 06:20:17 PM PDT 24
Peak memory 204324 kb
Host smart-8508da7f-b9c4-4c5a-87c9-ec103ccb6bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526686920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.526686920
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2867712457
Short name T1075
Test name
Test status
Simulation time 12210221 ps
CPU time 0.77 seconds
Started Jul 06 06:20:12 PM PDT 24
Finished Jul 06 06:20:13 PM PDT 24
Peak memory 203956 kb
Host smart-1bc52352-d271-44f5-9abb-7e4973ef97cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867712457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2867712457
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1176104566
Short name T1094
Test name
Test status
Simulation time 15059659 ps
CPU time 0.76 seconds
Started Jul 06 06:20:14 PM PDT 24
Finished Jul 06 06:20:15 PM PDT 24
Peak memory 204284 kb
Host smart-6577d465-c62b-454c-b34d-78c21967a641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176104566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1176104566
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1980396041
Short name T1139
Test name
Test status
Simulation time 48366801 ps
CPU time 0.72 seconds
Started Jul 06 06:20:15 PM PDT 24
Finished Jul 06 06:20:16 PM PDT 24
Peak memory 204300 kb
Host smart-10b5d33c-6ddc-4b16-abc0-f7ccc0f2bd60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980396041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1980396041
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2262838382
Short name T1051
Test name
Test status
Simulation time 25313703 ps
CPU time 0.77 seconds
Started Jul 06 06:20:13 PM PDT 24
Finished Jul 06 06:20:14 PM PDT 24
Peak memory 204296 kb
Host smart-0c1948f1-dc4a-46a3-afa7-de7bebabf856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262838382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2262838382
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2197776599
Short name T1102
Test name
Test status
Simulation time 238571053 ps
CPU time 0.73 seconds
Started Jul 06 06:20:18 PM PDT 24
Finished Jul 06 06:20:19 PM PDT 24
Peak memory 204048 kb
Host smart-689daae4-0b8b-43d3-b86b-a336a92d3db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197776599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2197776599
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2297063909
Short name T1042
Test name
Test status
Simulation time 31408102 ps
CPU time 0.69 seconds
Started Jul 06 06:20:14 PM PDT 24
Finished Jul 06 06:20:15 PM PDT 24
Peak memory 203952 kb
Host smart-3c3fa4ca-e0b6-4e55-b547-370f8f5615c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297063909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2297063909
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4285146942
Short name T1053
Test name
Test status
Simulation time 12866833 ps
CPU time 0.71 seconds
Started Jul 06 06:20:17 PM PDT 24
Finished Jul 06 06:20:18 PM PDT 24
Peak memory 204332 kb
Host smart-b336f39a-49ce-4082-ad61-e3ebc78b4ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285146942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4285146942
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2794034677
Short name T1115
Test name
Test status
Simulation time 85535814 ps
CPU time 0.68 seconds
Started Jul 06 06:20:12 PM PDT 24
Finished Jul 06 06:20:13 PM PDT 24
Peak memory 204292 kb
Host smart-d1ba07da-8c2d-49c0-8059-8b8ac4bf7ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794034677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2794034677
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1511326015
Short name T1122
Test name
Test status
Simulation time 21387395 ps
CPU time 0.79 seconds
Started Jul 06 06:20:18 PM PDT 24
Finished Jul 06 06:20:19 PM PDT 24
Peak memory 204036 kb
Host smart-89b36eb2-b5aa-4b92-b032-85220673874a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511326015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1511326015
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1807756490
Short name T1040
Test name
Test status
Simulation time 72631719 ps
CPU time 2.06 seconds
Started Jul 06 06:19:07 PM PDT 24
Finished Jul 06 06:19:09 PM PDT 24
Peak memory 215508 kb
Host smart-1d77bbec-4eed-478d-8596-675ebe6ee462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807756490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
807756490
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3933032767
Short name T1045
Test name
Test status
Simulation time 45992145 ps
CPU time 0.71 seconds
Started Jul 06 06:19:07 PM PDT 24
Finished Jul 06 06:19:08 PM PDT 24
Peak memory 204300 kb
Host smart-2d39198e-d6ed-416e-8aeb-9dfde33aa39c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933032767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
933032767
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.826237389
Short name T1105
Test name
Test status
Simulation time 447850949 ps
CPU time 3.38 seconds
Started Jul 06 06:19:06 PM PDT 24
Finished Jul 06 06:19:09 PM PDT 24
Peak memory 215548 kb
Host smart-c5939da9-c315-4225-b193-750a2f1e6de9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826237389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.826237389
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.676949712
Short name T100
Test name
Test status
Simulation time 81128744 ps
CPU time 2.35 seconds
Started Jul 06 06:19:06 PM PDT 24
Finished Jul 06 06:19:08 PM PDT 24
Peak memory 215644 kb
Host smart-4d1e1aac-349d-4246-9392-ca09486841e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676949712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.676949712
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1366707046
Short name T173
Test name
Test status
Simulation time 466192653 ps
CPU time 7.51 seconds
Started Jul 06 06:19:09 PM PDT 24
Finished Jul 06 06:19:16 PM PDT 24
Peak memory 215584 kb
Host smart-c97bd0be-2793-4ffa-b15a-353072ec6a69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366707046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1366707046
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3476827396
Short name T1055
Test name
Test status
Simulation time 101622747 ps
CPU time 3.56 seconds
Started Jul 06 06:19:15 PM PDT 24
Finished Jul 06 06:19:19 PM PDT 24
Peak memory 217896 kb
Host smart-cb2cbdab-55eb-42f0-8466-457281babc2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476827396 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3476827396
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2966143030
Short name T121
Test name
Test status
Simulation time 230529199 ps
CPU time 1.25 seconds
Started Jul 06 06:19:12 PM PDT 24
Finished Jul 06 06:19:13 PM PDT 24
Peak memory 207364 kb
Host smart-f6cc8272-e4de-4e8b-8caa-bef429f3728f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966143030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
966143030
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2065722362
Short name T1137
Test name
Test status
Simulation time 17756227 ps
CPU time 0.71 seconds
Started Jul 06 06:19:05 PM PDT 24
Finished Jul 06 06:19:06 PM PDT 24
Peak memory 204000 kb
Host smart-4ed4bdc4-7b6c-47c1-9957-d7027bb0b912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065722362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
065722362
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1109839296
Short name T1044
Test name
Test status
Simulation time 25039835 ps
CPU time 1.71 seconds
Started Jul 06 06:19:12 PM PDT 24
Finished Jul 06 06:19:14 PM PDT 24
Peak memory 215468 kb
Host smart-6642ebf5-4e5b-4cf8-87f3-63ca05707c3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109839296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1109839296
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2525942171
Short name T1109
Test name
Test status
Simulation time 1161724874 ps
CPU time 11.83 seconds
Started Jul 06 06:19:14 PM PDT 24
Finished Jul 06 06:19:26 PM PDT 24
Peak memory 215472 kb
Host smart-7322d663-232d-4840-9c9f-10ec5a8884d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525942171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2525942171
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3349978809
Short name T1145
Test name
Test status
Simulation time 42346021 ps
CPU time 2.91 seconds
Started Jul 06 06:19:15 PM PDT 24
Finished Jul 06 06:19:18 PM PDT 24
Peak memory 217328 kb
Host smart-8024d1ad-722e-457e-b259-88582e13c094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349978809 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3349978809
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.59546754
Short name T1096
Test name
Test status
Simulation time 36966122 ps
CPU time 1.3 seconds
Started Jul 06 06:19:12 PM PDT 24
Finished Jul 06 06:19:14 PM PDT 24
Peak memory 207336 kb
Host smart-ac8c4f86-5258-402e-80bb-efe043a15fb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59546754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.59546754
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3453947306
Short name T1081
Test name
Test status
Simulation time 114927262 ps
CPU time 0.71 seconds
Started Jul 06 06:19:13 PM PDT 24
Finished Jul 06 06:19:14 PM PDT 24
Peak memory 203880 kb
Host smart-02a42261-abe1-4119-9c5c-78c20b197814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453947306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
453947306
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4213424456
Short name T1104
Test name
Test status
Simulation time 404956736 ps
CPU time 4.32 seconds
Started Jul 06 06:19:16 PM PDT 24
Finished Jul 06 06:19:20 PM PDT 24
Peak memory 215576 kb
Host smart-b843ea2c-1080-4e99-8f80-090c2f82590d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213424456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4213424456
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1289785271
Short name T1101
Test name
Test status
Simulation time 87270308 ps
CPU time 2.42 seconds
Started Jul 06 06:19:14 PM PDT 24
Finished Jul 06 06:19:17 PM PDT 24
Peak memory 215824 kb
Host smart-dbfaf194-9a5d-4744-9456-733e93840a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289785271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
289785271
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.334016681
Short name T171
Test name
Test status
Simulation time 1634540865 ps
CPU time 22.42 seconds
Started Jul 06 06:19:15 PM PDT 24
Finished Jul 06 06:19:38 PM PDT 24
Peak memory 215572 kb
Host smart-e49802c8-4ac2-4427-92f3-9719d8074e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334016681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.334016681
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2721527166
Short name T1114
Test name
Test status
Simulation time 215649913 ps
CPU time 2.86 seconds
Started Jul 06 06:19:25 PM PDT 24
Finished Jul 06 06:19:28 PM PDT 24
Peak memory 217000 kb
Host smart-a5255189-5fac-4b23-a3d8-9f511dbd76dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721527166 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2721527166
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.584498553
Short name T128
Test name
Test status
Simulation time 69372605 ps
CPU time 1.97 seconds
Started Jul 06 06:19:16 PM PDT 24
Finished Jul 06 06:19:18 PM PDT 24
Peak memory 207328 kb
Host smart-59099b97-032f-4952-9665-0fd8372c0a4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584498553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.584498553
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2962380524
Short name T1030
Test name
Test status
Simulation time 15517050 ps
CPU time 0.74 seconds
Started Jul 06 06:19:15 PM PDT 24
Finished Jul 06 06:19:16 PM PDT 24
Peak memory 204316 kb
Host smart-b8fcbeca-048b-4138-9a3e-c7256db4c0aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962380524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
962380524
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3742258846
Short name T141
Test name
Test status
Simulation time 27427164 ps
CPU time 2.04 seconds
Started Jul 06 06:19:30 PM PDT 24
Finished Jul 06 06:19:33 PM PDT 24
Peak memory 206784 kb
Host smart-7cfd88e0-555e-48ff-9c52-587b68566fe8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742258846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3742258846
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.531522590
Short name T1098
Test name
Test status
Simulation time 356039437 ps
CPU time 2.38 seconds
Started Jul 06 06:19:34 PM PDT 24
Finished Jul 06 06:19:36 PM PDT 24
Peak memory 215784 kb
Host smart-f668797b-de12-4a6f-bd30-810869b5b0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531522590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.531522590
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1180408479
Short name T176
Test name
Test status
Simulation time 196945621 ps
CPU time 11.86 seconds
Started Jul 06 06:19:16 PM PDT 24
Finished Jul 06 06:19:29 PM PDT 24
Peak memory 216108 kb
Host smart-f721c995-b297-436a-9c18-c3ec0159e735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180408479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1180408479
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.81477561
Short name T115
Test name
Test status
Simulation time 195735141 ps
CPU time 2.76 seconds
Started Jul 06 06:19:26 PM PDT 24
Finished Jul 06 06:19:29 PM PDT 24
Peak memory 216648 kb
Host smart-ef90efd2-5d06-491b-88cd-06a5007f3984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81477561 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.81477561
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1735978643
Short name T1119
Test name
Test status
Simulation time 144364576 ps
CPU time 2.49 seconds
Started Jul 06 06:19:24 PM PDT 24
Finished Jul 06 06:19:27 PM PDT 24
Peak memory 215596 kb
Host smart-05837c8f-b6ce-4f24-80af-c0c1e70befdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735978643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
735978643
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3612587504
Short name T1126
Test name
Test status
Simulation time 43245198 ps
CPU time 0.74 seconds
Started Jul 06 06:19:24 PM PDT 24
Finished Jul 06 06:19:25 PM PDT 24
Peak memory 203864 kb
Host smart-f482b4c0-ae2e-4075-91af-edd9aa7d3d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612587504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
612587504
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1252624433
Short name T1063
Test name
Test status
Simulation time 152268202 ps
CPU time 2.66 seconds
Started Jul 06 06:19:28 PM PDT 24
Finished Jul 06 06:19:31 PM PDT 24
Peak memory 215604 kb
Host smart-576868d7-c123-4985-911e-d05a3eb92867
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252624433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1252624433
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1630802695
Short name T172
Test name
Test status
Simulation time 591049033 ps
CPU time 18.93 seconds
Started Jul 06 06:19:24 PM PDT 24
Finished Jul 06 06:19:43 PM PDT 24
Peak memory 215424 kb
Host smart-ac4d0a62-9cf7-46bc-b029-fb1da8e37717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630802695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1630802695
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1779878044
Short name T886
Test name
Test status
Simulation time 42212219 ps
CPU time 0.7 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:21:28 PM PDT 24
Peak memory 205808 kb
Host smart-1d31affd-df25-4b63-b7ce-1b31a36c5a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779878044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
779878044
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3742424513
Short name T697
Test name
Test status
Simulation time 15628631686 ps
CPU time 11.72 seconds
Started Jul 06 06:21:30 PM PDT 24
Finished Jul 06 06:21:42 PM PDT 24
Peak memory 225672 kb
Host smart-d4fcfc85-0971-4bb9-abcb-77b47791fac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742424513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3742424513
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2069531084
Short name T1015
Test name
Test status
Simulation time 15182564 ps
CPU time 0.74 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:21:29 PM PDT 24
Peak memory 206420 kb
Host smart-64b7ff98-e0af-4209-b124-a9083f71767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069531084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2069531084
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2391050409
Short name T790
Test name
Test status
Simulation time 340587652452 ps
CPU time 151.43 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:23:59 PM PDT 24
Peak memory 250316 kb
Host smart-d02f8af2-ae36-44ac-832d-214fcb4df56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391050409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2391050409
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2911975640
Short name T264
Test name
Test status
Simulation time 11467265518 ps
CPU time 117.59 seconds
Started Jul 06 06:21:28 PM PDT 24
Finished Jul 06 06:23:26 PM PDT 24
Peak memory 242220 kb
Host smart-498e6e86-dcb2-4202-842c-e866e2919a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911975640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2911975640
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2700491234
Short name T891
Test name
Test status
Simulation time 40168085742 ps
CPU time 267.83 seconds
Started Jul 06 06:21:30 PM PDT 24
Finished Jul 06 06:25:58 PM PDT 24
Peak memory 255736 kb
Host smart-54f37f01-0974-4826-930e-72b1b9327a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700491234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2700491234
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1411902979
Short name T626
Test name
Test status
Simulation time 4834751096 ps
CPU time 21.18 seconds
Started Jul 06 06:21:26 PM PDT 24
Finished Jul 06 06:21:48 PM PDT 24
Peak memory 233848 kb
Host smart-7facf825-996e-47a3-9445-4f5d7618b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411902979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1411902979
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3857785287
Short name T93
Test name
Test status
Simulation time 27632781319 ps
CPU time 54.83 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:22:23 PM PDT 24
Peak memory 250256 kb
Host smart-d794f278-d270-4338-8d68-d799c273b365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857785287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3857785287
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1214750554
Short name T43
Test name
Test status
Simulation time 26624320 ps
CPU time 1.08 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:21:29 PM PDT 24
Peak memory 217716 kb
Host smart-9aeb2315-af58-4f59-8504-4d1d0d16f24f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214750554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1214750554
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.120411304
Short name T759
Test name
Test status
Simulation time 3273519991 ps
CPU time 4.58 seconds
Started Jul 06 06:21:26 PM PDT 24
Finished Jul 06 06:21:31 PM PDT 24
Peak memory 233892 kb
Host smart-4f095b84-de2d-422d-9c4f-6c00bb2f1c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120411304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
120411304
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3653580215
Short name T720
Test name
Test status
Simulation time 456838098 ps
CPU time 2.4 seconds
Started Jul 06 06:21:26 PM PDT 24
Finished Jul 06 06:21:29 PM PDT 24
Peak memory 224932 kb
Host smart-cf825aa9-ac13-4f09-883a-839c7c01f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653580215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3653580215
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1613032535
Short name T454
Test name
Test status
Simulation time 279440302 ps
CPU time 5.2 seconds
Started Jul 06 06:21:26 PM PDT 24
Finished Jul 06 06:21:32 PM PDT 24
Peak memory 220456 kb
Host smart-b00c9dbf-3c62-47d4-95b9-5782561a6bac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1613032535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1613032535
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3804372510
Short name T77
Test name
Test status
Simulation time 239638684 ps
CPU time 1.09 seconds
Started Jul 06 06:21:29 PM PDT 24
Finished Jul 06 06:21:30 PM PDT 24
Peak memory 236784 kb
Host smart-890abdfb-9a4c-4edf-8e67-29ab9677f1f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804372510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3804372510
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3621591718
Short name T666
Test name
Test status
Simulation time 53587016 ps
CPU time 1.02 seconds
Started Jul 06 06:21:25 PM PDT 24
Finished Jul 06 06:21:26 PM PDT 24
Peak memory 207632 kb
Host smart-982843b6-9d42-4606-83e7-3b17906f5924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621591718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3621591718
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.92746724
Short name T530
Test name
Test status
Simulation time 6008808948 ps
CPU time 28.82 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:21:57 PM PDT 24
Peak memory 217580 kb
Host smart-e7f0dc3f-ef6b-4124-bcf5-327075ebf176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92746724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.92746724
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1414218161
Short name T679
Test name
Test status
Simulation time 8222753026 ps
CPU time 2.99 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:21:30 PM PDT 24
Peak memory 209116 kb
Host smart-7fd2a324-8ee3-4ba7-95dd-358376446598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414218161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1414218161
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3743259062
Short name T919
Test name
Test status
Simulation time 55087105 ps
CPU time 1.7 seconds
Started Jul 06 06:21:27 PM PDT 24
Finished Jul 06 06:21:29 PM PDT 24
Peak memory 217280 kb
Host smart-3fcda29a-47b1-4806-9870-b7c5d60e20d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743259062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3743259062
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2350754101
Short name T1010
Test name
Test status
Simulation time 116427984 ps
CPU time 0.99 seconds
Started Jul 06 06:21:25 PM PDT 24
Finished Jul 06 06:21:27 PM PDT 24
Peak memory 208020 kb
Host smart-80d0988b-887e-4833-9e4b-e18dfc86bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350754101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2350754101
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3043647268
Short name T525
Test name
Test status
Simulation time 48867180814 ps
CPU time 35.04 seconds
Started Jul 06 06:21:31 PM PDT 24
Finished Jul 06 06:22:06 PM PDT 24
Peak memory 237604 kb
Host smart-5c00f9e6-3b70-401a-ab0e-1139fb3d30d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043647268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3043647268
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2619603515
Short name T556
Test name
Test status
Simulation time 64277615 ps
CPU time 0.71 seconds
Started Jul 06 06:21:36 PM PDT 24
Finished Jul 06 06:21:37 PM PDT 24
Peak memory 206352 kb
Host smart-dcde1541-07b1-4fb9-af95-f1ac08845099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619603515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
619603515
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3611924342
Short name T567
Test name
Test status
Simulation time 111295896 ps
CPU time 2.6 seconds
Started Jul 06 06:21:31 PM PDT 24
Finished Jul 06 06:21:34 PM PDT 24
Peak memory 233756 kb
Host smart-bdf47490-2018-419d-a0bf-b9fd7dd0ab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611924342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3611924342
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.517261776
Short name T559
Test name
Test status
Simulation time 79826930 ps
CPU time 0.77 seconds
Started Jul 06 06:21:32 PM PDT 24
Finished Jul 06 06:21:33 PM PDT 24
Peak memory 206544 kb
Host smart-64c598cf-8bce-48df-b9fb-1de105480900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517261776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.517261776
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1426594363
Short name T230
Test name
Test status
Simulation time 18298364430 ps
CPU time 140 seconds
Started Jul 06 06:21:32 PM PDT 24
Finished Jul 06 06:23:52 PM PDT 24
Peak memory 256572 kb
Host smart-517a8c12-442f-413c-a485-7ab21b2014c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426594363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1426594363
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2474377698
Short name T490
Test name
Test status
Simulation time 48247517332 ps
CPU time 49.93 seconds
Started Jul 06 06:21:43 PM PDT 24
Finished Jul 06 06:22:33 PM PDT 24
Peak memory 251372 kb
Host smart-20d48a45-1e2a-4e36-b134-251aff379845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474377698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2474377698
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1202259560
Short name T964
Test name
Test status
Simulation time 6883040689 ps
CPU time 26.28 seconds
Started Jul 06 06:21:31 PM PDT 24
Finished Jul 06 06:21:58 PM PDT 24
Peak memory 237344 kb
Host smart-47362b08-9445-4791-b497-840c6335a055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202259560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1202259560
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2047042314
Short name T856
Test name
Test status
Simulation time 10202007226 ps
CPU time 44.29 seconds
Started Jul 06 06:21:33 PM PDT 24
Finished Jul 06 06:22:17 PM PDT 24
Peak memory 250228 kb
Host smart-cbc9b63f-9d8a-427d-9aa7-46f4133acf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047042314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2047042314
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2979512477
Short name T384
Test name
Test status
Simulation time 2599841689 ps
CPU time 11.85 seconds
Started Jul 06 06:21:34 PM PDT 24
Finished Jul 06 06:21:46 PM PDT 24
Peak memory 225668 kb
Host smart-6d469b28-7032-4490-a3ee-8e167d446957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979512477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2979512477
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1551774848
Short name T609
Test name
Test status
Simulation time 3647128619 ps
CPU time 40.77 seconds
Started Jul 06 06:21:32 PM PDT 24
Finished Jul 06 06:22:13 PM PDT 24
Peak memory 236524 kb
Host smart-8edf6ccf-9e7a-4263-9d47-8534dcd73cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551774848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1551774848
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.696786567
Short name T817
Test name
Test status
Simulation time 45312857 ps
CPU time 1.07 seconds
Started Jul 06 06:21:43 PM PDT 24
Finished Jul 06 06:21:44 PM PDT 24
Peak memory 217732 kb
Host smart-4405e54c-be14-493c-852e-8d1e88ce4c56
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696786567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.696786567
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2148934344
Short name T706
Test name
Test status
Simulation time 2826633908 ps
CPU time 14.29 seconds
Started Jul 06 06:21:31 PM PDT 24
Finished Jul 06 06:21:46 PM PDT 24
Peak memory 233912 kb
Host smart-a7f87eb3-da49-405a-b36c-c1bbb9cdb157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148934344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2148934344
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1007820222
Short name T244
Test name
Test status
Simulation time 940699624 ps
CPU time 4.27 seconds
Started Jul 06 06:21:35 PM PDT 24
Finished Jul 06 06:21:39 PM PDT 24
Peak memory 233824 kb
Host smart-265000ea-e947-4b21-be1f-c9482ad118e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007820222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1007820222
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3669172042
Short name T661
Test name
Test status
Simulation time 243440644 ps
CPU time 5.4 seconds
Started Jul 06 06:21:33 PM PDT 24
Finished Jul 06 06:21:39 PM PDT 24
Peak memory 223060 kb
Host smart-1e673820-f55f-4d7c-b2ed-1d80a7907f70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3669172042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3669172042
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1813852254
Short name T79
Test name
Test status
Simulation time 194026540 ps
CPU time 0.97 seconds
Started Jul 06 06:21:39 PM PDT 24
Finished Jul 06 06:21:41 PM PDT 24
Peak memory 236396 kb
Host smart-05296d69-eff0-4603-95df-21d5038dccce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813852254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1813852254
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.411701910
Short name T296
Test name
Test status
Simulation time 1683152709 ps
CPU time 42.89 seconds
Started Jul 06 06:21:40 PM PDT 24
Finished Jul 06 06:22:23 PM PDT 24
Peak memory 254080 kb
Host smart-d72a4ceb-bc04-492c-b9cb-aab96a6105e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411701910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.411701910
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2775011759
Short name T315
Test name
Test status
Simulation time 8972919188 ps
CPU time 24.36 seconds
Started Jul 06 06:21:31 PM PDT 24
Finished Jul 06 06:21:56 PM PDT 24
Peak memory 217508 kb
Host smart-7679c6ca-701c-40ae-821a-269a0c93c691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775011759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2775011759
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3500666668
Short name T652
Test name
Test status
Simulation time 2834999817 ps
CPU time 6.32 seconds
Started Jul 06 06:21:37 PM PDT 24
Finished Jul 06 06:21:44 PM PDT 24
Peak memory 217588 kb
Host smart-d5fc1622-bb66-4b9e-9308-2093beb4917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500666668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3500666668
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2765167930
Short name T483
Test name
Test status
Simulation time 145570641 ps
CPU time 4.52 seconds
Started Jul 06 06:21:32 PM PDT 24
Finished Jul 06 06:21:37 PM PDT 24
Peak memory 217388 kb
Host smart-6905120b-de2f-4f79-a6b3-1dcf0b1ade00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765167930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2765167930
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2591858000
Short name T394
Test name
Test status
Simulation time 67929162 ps
CPU time 0.69 seconds
Started Jul 06 06:21:34 PM PDT 24
Finished Jul 06 06:21:35 PM PDT 24
Peak memory 206600 kb
Host smart-1d93f23b-688a-41c9-93a2-5feba21dd1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591858000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2591858000
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1612574200
Short name T899
Test name
Test status
Simulation time 282324389 ps
CPU time 4.69 seconds
Started Jul 06 06:21:33 PM PDT 24
Finished Jul 06 06:21:38 PM PDT 24
Peak memory 233824 kb
Host smart-f4f5c177-9e0e-44a5-a5fe-96d1b7d5c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612574200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1612574200
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2774907824
Short name T778
Test name
Test status
Simulation time 69223327 ps
CPU time 2.61 seconds
Started Jul 06 06:22:19 PM PDT 24
Finished Jul 06 06:22:22 PM PDT 24
Peak memory 225492 kb
Host smart-0c1290f0-aac7-4630-8715-fea76c242573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774907824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2774907824
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3356890923
Short name T497
Test name
Test status
Simulation time 35053760 ps
CPU time 0.78 seconds
Started Jul 06 06:22:18 PM PDT 24
Finished Jul 06 06:22:19 PM PDT 24
Peak memory 207536 kb
Host smart-95c15d32-fff9-4aca-a86d-1b530b825797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356890923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3356890923
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3052496711
Short name T464
Test name
Test status
Simulation time 159382009697 ps
CPU time 130.74 seconds
Started Jul 06 06:22:23 PM PDT 24
Finished Jul 06 06:24:34 PM PDT 24
Peak memory 255588 kb
Host smart-ba695221-7501-49ab-b02d-23153d2c0e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052496711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3052496711
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2126221678
Short name T798
Test name
Test status
Simulation time 20331710270 ps
CPU time 188.58 seconds
Started Jul 06 06:22:22 PM PDT 24
Finished Jul 06 06:25:32 PM PDT 24
Peak memory 255632 kb
Host smart-b90a6799-dab3-4b18-a5cd-091bf91a7927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126221678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2126221678
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.946467645
Short name T39
Test name
Test status
Simulation time 3542506544 ps
CPU time 49.38 seconds
Started Jul 06 06:22:21 PM PDT 24
Finished Jul 06 06:23:10 PM PDT 24
Peak memory 250448 kb
Host smart-ab7828f4-3d07-4d6d-be0a-2d6e9b20d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946467645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.946467645
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3306239626
Short name T878
Test name
Test status
Simulation time 235985104 ps
CPU time 5.84 seconds
Started Jul 06 06:22:23 PM PDT 24
Finished Jul 06 06:22:29 PM PDT 24
Peak memory 225520 kb
Host smart-ef184bbe-35e2-4dfe-a8d7-22f0c7eed28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306239626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3306239626
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1087824435
Short name T599
Test name
Test status
Simulation time 1194337433 ps
CPU time 29.73 seconds
Started Jul 06 06:22:21 PM PDT 24
Finished Jul 06 06:22:51 PM PDT 24
Peak memory 250172 kb
Host smart-bb799b0a-c72b-40e5-bb3a-b8ab17733421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087824435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1087824435
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.501184371
Short name T1011
Test name
Test status
Simulation time 186440958 ps
CPU time 5.08 seconds
Started Jul 06 06:22:18 PM PDT 24
Finished Jul 06 06:22:23 PM PDT 24
Peak memory 233836 kb
Host smart-40654bf3-c127-43dd-bd5a-6592d30649ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501184371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.501184371
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2053954541
Short name T912
Test name
Test status
Simulation time 16336682559 ps
CPU time 146.21 seconds
Started Jul 06 06:22:19 PM PDT 24
Finished Jul 06 06:24:46 PM PDT 24
Peak memory 238024 kb
Host smart-606528a5-6be1-4892-b20a-1f93ccc72a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053954541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2053954541
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1125822352
Short name T400
Test name
Test status
Simulation time 14976060 ps
CPU time 1.04 seconds
Started Jul 06 06:22:20 PM PDT 24
Finished Jul 06 06:22:21 PM PDT 24
Peak memory 219028 kb
Host smart-a0aa1c2e-7464-41a3-b89d-f18cedab2b8f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125822352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1125822352
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1953723785
Short name T8
Test name
Test status
Simulation time 600572888 ps
CPU time 5.51 seconds
Started Jul 06 06:22:19 PM PDT 24
Finished Jul 06 06:22:25 PM PDT 24
Peak memory 225632 kb
Host smart-6e873c82-94ef-4e05-992e-a8c37c15618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953723785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1953723785
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1323305429
Short name T258
Test name
Test status
Simulation time 9084042276 ps
CPU time 26.38 seconds
Started Jul 06 06:22:18 PM PDT 24
Finished Jul 06 06:22:45 PM PDT 24
Peak memory 249716 kb
Host smart-91b5b337-fa71-4091-820d-39810ae62478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323305429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1323305429
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.866576493
Short name T148
Test name
Test status
Simulation time 2972989090 ps
CPU time 6.6 seconds
Started Jul 06 06:22:22 PM PDT 24
Finished Jul 06 06:22:29 PM PDT 24
Peak memory 223928 kb
Host smart-4730b64c-3257-4e1e-aae8-bbdf5b95ca03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866576493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.866576493
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1014964782
Short name T994
Test name
Test status
Simulation time 13043848946 ps
CPU time 47.59 seconds
Started Jul 06 06:22:23 PM PDT 24
Finished Jul 06 06:23:11 PM PDT 24
Peak memory 242184 kb
Host smart-bde60747-7791-4dc9-92e8-df235c109ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014964782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1014964782
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4219871721
Short name T812
Test name
Test status
Simulation time 4555173131 ps
CPU time 24.67 seconds
Started Jul 06 06:22:21 PM PDT 24
Finished Jul 06 06:22:46 PM PDT 24
Peak memory 217528 kb
Host smart-b78eba04-463b-4a19-abe5-40a5f531f15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219871721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4219871721
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3305301437
Short name T730
Test name
Test status
Simulation time 902225806 ps
CPU time 3.06 seconds
Started Jul 06 06:22:17 PM PDT 24
Finished Jul 06 06:22:20 PM PDT 24
Peak memory 217164 kb
Host smart-d32a4c84-3d1c-4dd5-aa15-3daa73cde8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305301437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3305301437
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.539608238
Short name T388
Test name
Test status
Simulation time 725199553 ps
CPU time 2.78 seconds
Started Jul 06 06:22:19 PM PDT 24
Finished Jul 06 06:22:22 PM PDT 24
Peak memory 217436 kb
Host smart-2412a043-6a96-4f6b-aa7a-5d06f3730615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539608238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.539608238
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3805152755
Short name T753
Test name
Test status
Simulation time 19983112 ps
CPU time 0.7 seconds
Started Jul 06 06:22:18 PM PDT 24
Finished Jul 06 06:22:19 PM PDT 24
Peak memory 206604 kb
Host smart-8090ec43-d8c9-43bd-927b-b6fa6784b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805152755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3805152755
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.626063380
Short name T981
Test name
Test status
Simulation time 522977002 ps
CPU time 4.29 seconds
Started Jul 06 06:22:18 PM PDT 24
Finished Jul 06 06:22:23 PM PDT 24
Peak memory 225572 kb
Host smart-9cb377c7-b2ab-456d-a067-d18923e9300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626063380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.626063380
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.722533418
Short name T752
Test name
Test status
Simulation time 37598921 ps
CPU time 0.71 seconds
Started Jul 06 06:22:27 PM PDT 24
Finished Jul 06 06:22:28 PM PDT 24
Peak memory 206420 kb
Host smart-48492386-31b8-4f5e-b1d2-939e14662c67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722533418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.722533418
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1970776976
Short name T11
Test name
Test status
Simulation time 548639125 ps
CPU time 3.21 seconds
Started Jul 06 06:22:28 PM PDT 24
Finished Jul 06 06:22:32 PM PDT 24
Peak memory 225572 kb
Host smart-ec8619cf-51a6-47f1-9542-4bafdd8bf214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970776976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1970776976
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4040557743
Short name T971
Test name
Test status
Simulation time 54514654 ps
CPU time 0.74 seconds
Started Jul 06 06:22:23 PM PDT 24
Finished Jul 06 06:22:24 PM PDT 24
Peak memory 206820 kb
Host smart-17b23dce-ced1-46c9-a2f9-1b328e2eda54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040557743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4040557743
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2270883794
Short name T185
Test name
Test status
Simulation time 4933821218 ps
CPU time 88.41 seconds
Started Jul 06 06:22:29 PM PDT 24
Finished Jul 06 06:23:58 PM PDT 24
Peak memory 267096 kb
Host smart-a7d8e98f-e394-4a7a-80e1-3f758bf363a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270883794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2270883794
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2617250659
Short name T762
Test name
Test status
Simulation time 3640470130 ps
CPU time 25.86 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:23:03 PM PDT 24
Peak memory 250436 kb
Host smart-00ce17d7-7319-499c-9797-d9c83d638908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617250659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2617250659
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1024766929
Short name T223
Test name
Test status
Simulation time 75146572082 ps
CPU time 320.72 seconds
Started Jul 06 06:22:28 PM PDT 24
Finished Jul 06 06:27:49 PM PDT 24
Peak memory 255048 kb
Host smart-9c4761c0-6178-4ff7-9887-a9096a370eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024766929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1024766929
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.673338718
Short name T976
Test name
Test status
Simulation time 4189248930 ps
CPU time 14.44 seconds
Started Jul 06 06:22:27 PM PDT 24
Finished Jul 06 06:22:42 PM PDT 24
Peak memory 240428 kb
Host smart-8532fb19-18bc-4832-b0af-818e36d413ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673338718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.673338718
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2954401969
Short name T284
Test name
Test status
Simulation time 124856644922 ps
CPU time 458.76 seconds
Started Jul 06 06:22:27 PM PDT 24
Finished Jul 06 06:30:06 PM PDT 24
Peak memory 256656 kb
Host smart-5e71e507-00d1-4edc-96cf-6ed7061c32ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954401969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2954401969
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1099880861
Short name T426
Test name
Test status
Simulation time 561921639 ps
CPU time 2.86 seconds
Started Jul 06 06:22:30 PM PDT 24
Finished Jul 06 06:22:33 PM PDT 24
Peak memory 225660 kb
Host smart-01dcd782-30a9-4fb3-b1fb-3e05977df7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099880861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1099880861
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.736641109
Short name T585
Test name
Test status
Simulation time 193282522 ps
CPU time 6.82 seconds
Started Jul 06 06:22:34 PM PDT 24
Finished Jul 06 06:22:41 PM PDT 24
Peak memory 240156 kb
Host smart-7f845e8c-4750-4e62-a541-7a4762e1a29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736641109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.736641109
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1329494141
Short name T568
Test name
Test status
Simulation time 59951247 ps
CPU time 1.02 seconds
Started Jul 06 06:22:22 PM PDT 24
Finished Jul 06 06:22:23 PM PDT 24
Peak memory 217612 kb
Host smart-7e4a9d0c-935a-4f0c-9d3a-2ee01ca2df56
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329494141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1329494141
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1967510923
Short name T227
Test name
Test status
Simulation time 7193393171 ps
CPU time 9.44 seconds
Started Jul 06 06:22:26 PM PDT 24
Finished Jul 06 06:22:36 PM PDT 24
Peak memory 249868 kb
Host smart-0de9acee-d5e0-46ca-a07f-bde5c92e7d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967510923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1967510923
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1913717950
Short name T205
Test name
Test status
Simulation time 4466750194 ps
CPU time 14.9 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:22:53 PM PDT 24
Peak memory 241828 kb
Host smart-15ec64e0-ea74-432d-9051-8823fed38751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913717950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1913717950
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1159582609
Short name T853
Test name
Test status
Simulation time 761038160 ps
CPU time 4.7 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:22:42 PM PDT 24
Peak memory 220316 kb
Host smart-fef30b23-8b7f-41d0-89e7-b95a3e1c4258
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1159582609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1159582609
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3208325727
Short name T310
Test name
Test status
Simulation time 1165477625 ps
CPU time 6.67 seconds
Started Jul 06 06:22:22 PM PDT 24
Finished Jul 06 06:22:30 PM PDT 24
Peak memory 217616 kb
Host smart-b643a2e8-834f-4979-a4e1-4f12080c1d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208325727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3208325727
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1197606616
Short name T377
Test name
Test status
Simulation time 136242434 ps
CPU time 1.53 seconds
Started Jul 06 06:22:24 PM PDT 24
Finished Jul 06 06:22:25 PM PDT 24
Peak memory 208916 kb
Host smart-f05a7125-0b94-48db-9f16-753eb176a290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197606616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1197606616
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.51974072
Short name T602
Test name
Test status
Simulation time 75736097 ps
CPU time 1.04 seconds
Started Jul 06 06:22:34 PM PDT 24
Finished Jul 06 06:22:35 PM PDT 24
Peak memory 207640 kb
Host smart-6fd59957-c6a0-4f96-9d51-5d58875a2f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51974072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.51974072
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3381606177
Short name T764
Test name
Test status
Simulation time 375403453 ps
CPU time 0.98 seconds
Started Jul 06 06:22:28 PM PDT 24
Finished Jul 06 06:22:29 PM PDT 24
Peak memory 206956 kb
Host smart-cb3c429b-0410-4653-b9a8-2a65c5cdb50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381606177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3381606177
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2495386771
Short name T442
Test name
Test status
Simulation time 304945707 ps
CPU time 3.76 seconds
Started Jul 06 06:22:30 PM PDT 24
Finished Jul 06 06:22:33 PM PDT 24
Peak memory 241924 kb
Host smart-a45f78bb-14fd-48ce-a881-efd62800f151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495386771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2495386771
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2659821192
Short name T732
Test name
Test status
Simulation time 18261543 ps
CPU time 0.7 seconds
Started Jul 06 06:22:30 PM PDT 24
Finished Jul 06 06:22:31 PM PDT 24
Peak memory 205828 kb
Host smart-7e7cbe36-e187-418e-9a50-d65c027bbd5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659821192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2659821192
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3185335856
Short name T578
Test name
Test status
Simulation time 124536045 ps
CPU time 2.55 seconds
Started Jul 06 06:22:31 PM PDT 24
Finished Jul 06 06:22:34 PM PDT 24
Peak memory 233544 kb
Host smart-34d2338f-3799-4b28-b96c-3e272e414296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185335856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3185335856
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2956946689
Short name T555
Test name
Test status
Simulation time 74366591 ps
CPU time 0.84 seconds
Started Jul 06 06:22:34 PM PDT 24
Finished Jul 06 06:22:35 PM PDT 24
Peak memory 207836 kb
Host smart-52500b63-a5c8-442e-ab62-1c445f98a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956946689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2956946689
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2412080077
Short name T218
Test name
Test status
Simulation time 12279840071 ps
CPU time 56.03 seconds
Started Jul 06 06:22:31 PM PDT 24
Finished Jul 06 06:23:28 PM PDT 24
Peak memory 250336 kb
Host smart-f155e1dc-56e3-4105-a39a-2a6eb97ad4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412080077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2412080077
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2361449389
Short name T550
Test name
Test status
Simulation time 10141400965 ps
CPU time 64.99 seconds
Started Jul 06 06:22:31 PM PDT 24
Finished Jul 06 06:23:37 PM PDT 24
Peak memory 258368 kb
Host smart-60859bf2-d289-4b66-b4b4-b11d4b87b29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361449389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2361449389
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2447144440
Short name T234
Test name
Test status
Simulation time 240587654494 ps
CPU time 257.66 seconds
Started Jul 06 06:22:32 PM PDT 24
Finished Jul 06 06:26:50 PM PDT 24
Peak memory 258064 kb
Host smart-568d612e-7f91-4648-8bb7-d6280de6a8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447144440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2447144440
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.878158627
Short name T948
Test name
Test status
Simulation time 244519395 ps
CPU time 6.41 seconds
Started Jul 06 06:22:38 PM PDT 24
Finished Jul 06 06:22:44 PM PDT 24
Peak memory 225568 kb
Host smart-55480d69-d282-4aad-9dc3-a6045d71abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878158627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.878158627
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3339459814
Short name T239
Test name
Test status
Simulation time 822127389 ps
CPU time 5.57 seconds
Started Jul 06 06:22:31 PM PDT 24
Finished Jul 06 06:22:37 PM PDT 24
Peak memory 233696 kb
Host smart-d61d0757-3a17-4af6-bb6d-60c20a64d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339459814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3339459814
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1508579138
Short name T431
Test name
Test status
Simulation time 321966820 ps
CPU time 5.5 seconds
Started Jul 06 06:22:43 PM PDT 24
Finished Jul 06 06:22:49 PM PDT 24
Peak memory 233764 kb
Host smart-1f8fb81f-beb9-47af-b53f-7464e1a3512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508579138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1508579138
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2340457939
Short name T389
Test name
Test status
Simulation time 228070185 ps
CPU time 1 seconds
Started Jul 06 06:22:29 PM PDT 24
Finished Jul 06 06:22:30 PM PDT 24
Peak memory 219012 kb
Host smart-fa276676-dc68-4796-9b70-7740cc2ddecd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340457939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2340457939
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4201402261
Short name T821
Test name
Test status
Simulation time 932788941 ps
CPU time 7.69 seconds
Started Jul 06 06:22:32 PM PDT 24
Finished Jul 06 06:22:40 PM PDT 24
Peak memory 225572 kb
Host smart-8832364e-dc8b-4f37-8b31-45df8258582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201402261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4201402261
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1691384916
Short name T946
Test name
Test status
Simulation time 3809885358 ps
CPU time 4.38 seconds
Started Jul 06 06:22:36 PM PDT 24
Finished Jul 06 06:22:41 PM PDT 24
Peak memory 225636 kb
Host smart-3546593e-3b1c-4bfe-a03e-a4f6760ed123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691384916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1691384916
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1347592633
Short name T144
Test name
Test status
Simulation time 1225831377 ps
CPU time 10.24 seconds
Started Jul 06 06:22:32 PM PDT 24
Finished Jul 06 06:22:43 PM PDT 24
Peak memory 220996 kb
Host smart-048861f3-1237-4b2f-8d22-10fd2592a8a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1347592633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1347592633
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.4232878968
Short name T659
Test name
Test status
Simulation time 219738843 ps
CPU time 1.15 seconds
Started Jul 06 06:22:36 PM PDT 24
Finished Jul 06 06:22:37 PM PDT 24
Peak memory 208140 kb
Host smart-7f84522d-3cda-47b0-8277-4bee7fe9bffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232878968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4232878968
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3580218319
Short name T693
Test name
Test status
Simulation time 205690539 ps
CPU time 2.76 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:22:41 PM PDT 24
Peak memory 217544 kb
Host smart-9a96fa57-f7f4-49f8-8b94-65020b6bd596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580218319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3580218319
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2960379627
Short name T576
Test name
Test status
Simulation time 9348013072 ps
CPU time 7.34 seconds
Started Jul 06 06:22:34 PM PDT 24
Finished Jul 06 06:22:42 PM PDT 24
Peak memory 217492 kb
Host smart-0f9968f4-fcdc-472e-aff4-3be677808c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960379627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2960379627
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.589108507
Short name T742
Test name
Test status
Simulation time 1107634572 ps
CPU time 3.17 seconds
Started Jul 06 06:22:32 PM PDT 24
Finished Jul 06 06:22:36 PM PDT 24
Peak memory 217396 kb
Host smart-0c5718fb-6440-4caa-a48d-1a3fb9a40183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589108507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.589108507
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2974808154
Short name T673
Test name
Test status
Simulation time 63230799 ps
CPU time 0.75 seconds
Started Jul 06 06:22:34 PM PDT 24
Finished Jul 06 06:22:35 PM PDT 24
Peak memory 207028 kb
Host smart-503fc8af-d665-46bc-b88a-0a35e773592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974808154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2974808154
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3408996598
Short name T188
Test name
Test status
Simulation time 1117853045 ps
CPU time 5.98 seconds
Started Jul 06 06:22:31 PM PDT 24
Finished Jul 06 06:22:37 PM PDT 24
Peak memory 225580 kb
Host smart-e2aaec85-7219-4c21-b944-9e884602e3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408996598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3408996598
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1450746166
Short name T717
Test name
Test status
Simulation time 12078335 ps
CPU time 0.72 seconds
Started Jul 06 06:22:36 PM PDT 24
Finished Jul 06 06:22:37 PM PDT 24
Peak memory 206720 kb
Host smart-6255d501-3211-425f-a51b-f52c3462545d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450746166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1450746166
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3169755249
Short name T67
Test name
Test status
Simulation time 404835479 ps
CPU time 2.17 seconds
Started Jul 06 06:22:43 PM PDT 24
Finished Jul 06 06:22:46 PM PDT 24
Peak memory 224828 kb
Host smart-bcbcd736-1c0d-4aba-9251-8920ef144514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169755249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3169755249
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.244517040
Short name T747
Test name
Test status
Simulation time 16967151 ps
CPU time 0.82 seconds
Started Jul 06 06:22:38 PM PDT 24
Finished Jul 06 06:22:39 PM PDT 24
Peak memory 207836 kb
Host smart-a2310b46-7d6a-4b02-97f6-93b923613d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244517040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.244517040
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.281558201
Short name T709
Test name
Test status
Simulation time 1603207748 ps
CPU time 29.81 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:23:10 PM PDT 24
Peak memory 252496 kb
Host smart-108465cb-a247-46b3-bb86-a4bda545c981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281558201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.281558201
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4272045674
Short name T269
Test name
Test status
Simulation time 38497846926 ps
CPU time 315.43 seconds
Started Jul 06 06:22:36 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 265932 kb
Host smart-ffbee8b4-1e00-435a-bea9-83583b87d6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272045674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4272045674
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3217115102
Short name T1002
Test name
Test status
Simulation time 50418451633 ps
CPU time 509.28 seconds
Started Jul 06 06:22:35 PM PDT 24
Finished Jul 06 06:31:04 PM PDT 24
Peak memory 270928 kb
Host smart-9be3cee8-be30-424c-aafd-c2a698a8f1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217115102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3217115102
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3956740905
Short name T879
Test name
Test status
Simulation time 2901646849 ps
CPU time 10.65 seconds
Started Jul 06 06:22:39 PM PDT 24
Finished Jul 06 06:22:50 PM PDT 24
Peak memory 233896 kb
Host smart-16c77e7f-b766-49a2-981a-362151387b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956740905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3956740905
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.949462840
Short name T247
Test name
Test status
Simulation time 120423734 ps
CPU time 3.34 seconds
Started Jul 06 06:22:39 PM PDT 24
Finished Jul 06 06:22:42 PM PDT 24
Peak memory 233876 kb
Host smart-a2c5cf3d-177f-4509-be47-381065c5b65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949462840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.949462840
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2710425361
Short name T42
Test name
Test status
Simulation time 16184342 ps
CPU time 1.03 seconds
Started Jul 06 06:22:35 PM PDT 24
Finished Jul 06 06:22:37 PM PDT 24
Peak memory 217672 kb
Host smart-9153372b-347c-4ab8-8134-a2416060fa74
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710425361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2710425361
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2381871043
Short name T282
Test name
Test status
Simulation time 4961346291 ps
CPU time 17.25 seconds
Started Jul 06 06:22:36 PM PDT 24
Finished Jul 06 06:22:54 PM PDT 24
Peak memory 233904 kb
Host smart-fffe8682-1a16-407f-a749-aa55117980b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381871043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2381871043
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.258895866
Short name T512
Test name
Test status
Simulation time 803320957 ps
CPU time 2.37 seconds
Started Jul 06 06:22:36 PM PDT 24
Finished Jul 06 06:22:39 PM PDT 24
Peak memory 225624 kb
Host smart-cfebfcb7-3a66-4076-b8b5-a546711a71df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258895866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.258895866
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2867625163
Short name T1020
Test name
Test status
Simulation time 29632519900 ps
CPU time 14.94 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:22:55 PM PDT 24
Peak memory 220096 kb
Host smart-d8026e12-0a57-43eb-a526-d5469291d9a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2867625163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2867625163
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1284744894
Short name T474
Test name
Test status
Simulation time 22135424199 ps
CPU time 34.66 seconds
Started Jul 06 06:22:33 PM PDT 24
Finished Jul 06 06:23:08 PM PDT 24
Peak memory 217516 kb
Host smart-6b43563b-365f-43a0-917b-2ec68b79ed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284744894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1284744894
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1063241210
Short name T869
Test name
Test status
Simulation time 15716199253 ps
CPU time 6.72 seconds
Started Jul 06 06:22:33 PM PDT 24
Finished Jul 06 06:22:41 PM PDT 24
Peak memory 217556 kb
Host smart-4e221e20-0fec-457d-b67a-dbcb3061c419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063241210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1063241210
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.630655670
Short name T381
Test name
Test status
Simulation time 111448499 ps
CPU time 3.26 seconds
Started Jul 06 06:22:31 PM PDT 24
Finished Jul 06 06:22:34 PM PDT 24
Peak memory 217372 kb
Host smart-5a727598-19d7-4d73-b9ca-bb289bcf7e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630655670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.630655670
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1617367659
Short name T329
Test name
Test status
Simulation time 28924250 ps
CPU time 0.66 seconds
Started Jul 06 06:22:30 PM PDT 24
Finished Jul 06 06:22:31 PM PDT 24
Peak memory 206552 kb
Host smart-8a7569dd-a2bc-40a5-b0de-a8b8f46d2d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617367659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1617367659
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4009724198
Short name T177
Test name
Test status
Simulation time 12213208861 ps
CPU time 15.98 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:22:57 PM PDT 24
Peak memory 233912 kb
Host smart-b3c19ac8-5cef-47be-a1ab-f8a26c613bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009724198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4009724198
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2557587271
Short name T581
Test name
Test status
Simulation time 38044824 ps
CPU time 0.73 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:22:41 PM PDT 24
Peak memory 206444 kb
Host smart-4a69d354-a2ec-4f07-ab9d-0afe8a6682cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557587271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2557587271
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3044711722
Short name T970
Test name
Test status
Simulation time 541267638 ps
CPU time 2.98 seconds
Started Jul 06 06:22:41 PM PDT 24
Finished Jul 06 06:22:44 PM PDT 24
Peak memory 225608 kb
Host smart-f9a56e0a-84a2-4029-a805-5857563dfaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044711722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3044711722
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3394373781
Short name T469
Test name
Test status
Simulation time 42502765 ps
CPU time 0.74 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:22:38 PM PDT 24
Peak memory 206504 kb
Host smart-ba5c076f-5bbf-452c-8d10-941f11bebfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394373781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3394373781
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.905976852
Short name T283
Test name
Test status
Simulation time 498982860 ps
CPU time 6.67 seconds
Started Jul 06 06:22:44 PM PDT 24
Finished Jul 06 06:22:51 PM PDT 24
Peak memory 235528 kb
Host smart-4297166d-4e8d-4942-9e8c-51c78601c516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905976852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.905976852
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1679574395
Short name T910
Test name
Test status
Simulation time 6951567210 ps
CPU time 37.78 seconds
Started Jul 06 06:22:44 PM PDT 24
Finished Jul 06 06:23:23 PM PDT 24
Peak memory 250236 kb
Host smart-742cacb1-1469-4657-a50b-69ced13d90b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679574395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1679574395
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2018451745
Short name T901
Test name
Test status
Simulation time 144315537877 ps
CPU time 307.29 seconds
Started Jul 06 06:22:45 PM PDT 24
Finished Jul 06 06:27:52 PM PDT 24
Peak memory 258056 kb
Host smart-3010c66e-2c5b-4174-a98c-de2e3b7da2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018451745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2018451745
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2344423642
Short name T658
Test name
Test status
Simulation time 2540674763 ps
CPU time 32.78 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:23:14 PM PDT 24
Peak memory 225764 kb
Host smart-c679cde8-42da-4471-8ba5-7f12f029e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344423642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2344423642
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2386208371
Short name T503
Test name
Test status
Simulation time 103163029 ps
CPU time 4.14 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:22:45 PM PDT 24
Peak memory 225620 kb
Host smart-00c9a71e-cf72-4ae9-b056-9a7392edd411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386208371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2386208371
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3402092251
Short name T132
Test name
Test status
Simulation time 399928605 ps
CPU time 7.47 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:22:48 PM PDT 24
Peak memory 241664 kb
Host smart-3c6e798b-9b3b-4016-83de-cbd83f63519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402092251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3402092251
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2930359580
Short name T365
Test name
Test status
Simulation time 104750030 ps
CPU time 1.05 seconds
Started Jul 06 06:22:38 PM PDT 24
Finished Jul 06 06:22:39 PM PDT 24
Peak memory 218996 kb
Host smart-a544b107-31d5-4280-abde-e9d2f8f9d21e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930359580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2930359580
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3867561444
Short name T70
Test name
Test status
Simulation time 18561913445 ps
CPU time 24.04 seconds
Started Jul 06 06:22:38 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 236084 kb
Host smart-b0bbbec0-dd74-4d28-ad6e-5af7f15b3c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867561444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3867561444
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.342536886
Short name T980
Test name
Test status
Simulation time 1308372094 ps
CPU time 7.15 seconds
Started Jul 06 06:22:36 PM PDT 24
Finished Jul 06 06:22:43 PM PDT 24
Peak memory 241904 kb
Host smart-3d79120a-531a-497f-b92f-bdb96041db78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342536886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.342536886
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2673101054
Short name T933
Test name
Test status
Simulation time 871568510 ps
CPU time 4.09 seconds
Started Jul 06 06:22:41 PM PDT 24
Finished Jul 06 06:22:45 PM PDT 24
Peak memory 222324 kb
Host smart-43b84053-bdc7-4bb5-af90-6ac118c62dbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2673101054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2673101054
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1901975163
Short name T625
Test name
Test status
Simulation time 2770321734 ps
CPU time 20.51 seconds
Started Jul 06 06:22:34 PM PDT 24
Finished Jul 06 06:22:55 PM PDT 24
Peak memory 217492 kb
Host smart-b62442c7-55da-4543-8e0f-4049dcd31ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901975163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1901975163
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3015253366
Short name T943
Test name
Test status
Simulation time 1171500951 ps
CPU time 7.59 seconds
Started Jul 06 06:22:36 PM PDT 24
Finished Jul 06 06:22:44 PM PDT 24
Peak memory 217364 kb
Host smart-e0f922d9-ccb0-44cf-8854-c844eb842d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015253366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3015253366
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1269761391
Short name T482
Test name
Test status
Simulation time 2455166776 ps
CPU time 2.91 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:22:40 PM PDT 24
Peak memory 217544 kb
Host smart-feb8c77c-f02f-47eb-a45a-5c23d3188d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269761391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1269761391
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2460357133
Short name T62
Test name
Test status
Simulation time 69788075 ps
CPU time 0.91 seconds
Started Jul 06 06:22:37 PM PDT 24
Finished Jul 06 06:22:38 PM PDT 24
Peak memory 206940 kb
Host smart-eba4a6de-1c20-43fb-8de9-af66723ba1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460357133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2460357133
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3894243345
Short name T473
Test name
Test status
Simulation time 6093190982 ps
CPU time 12.88 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:22:54 PM PDT 24
Peak memory 234832 kb
Host smart-2960e4ac-d624-4936-92f8-10aef94b11bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894243345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3894243345
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2106448588
Short name T644
Test name
Test status
Simulation time 25687610 ps
CPU time 0.74 seconds
Started Jul 06 06:22:44 PM PDT 24
Finished Jul 06 06:22:46 PM PDT 24
Peak memory 206328 kb
Host smart-31739872-1fb9-416f-8865-d02cd74f1cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106448588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2106448588
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3976470156
Short name T237
Test name
Test status
Simulation time 587438606 ps
CPU time 7.18 seconds
Started Jul 06 06:22:45 PM PDT 24
Finished Jul 06 06:22:52 PM PDT 24
Peak memory 225660 kb
Host smart-82cac4b5-8b33-42c8-83f4-20d521f4ce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976470156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3976470156
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1220414605
Short name T760
Test name
Test status
Simulation time 52104008 ps
CPU time 0.75 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:22:42 PM PDT 24
Peak memory 207552 kb
Host smart-fb415834-ad21-4e99-88bb-9b883315ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220414605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1220414605
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2040790523
Short name T276
Test name
Test status
Simulation time 34803460375 ps
CPU time 60.17 seconds
Started Jul 06 06:22:43 PM PDT 24
Finished Jul 06 06:23:43 PM PDT 24
Peak memory 236588 kb
Host smart-393d0239-498d-410f-be86-9b15b456d909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040790523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2040790523
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2499753584
Short name T26
Test name
Test status
Simulation time 12300391692 ps
CPU time 82.59 seconds
Started Jul 06 06:22:45 PM PDT 24
Finished Jul 06 06:24:08 PM PDT 24
Peak memory 234876 kb
Host smart-e753921b-a8da-4e69-9051-e6efd27f9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499753584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2499753584
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1676314676
Short name T293
Test name
Test status
Simulation time 20409481985 ps
CPU time 204.1 seconds
Started Jul 06 06:22:43 PM PDT 24
Finished Jul 06 06:26:08 PM PDT 24
Peak memory 251988 kb
Host smart-b8f577b7-d38e-41b1-b940-9c2f7cf5ce7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676314676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1676314676
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1728977481
Short name T880
Test name
Test status
Simulation time 468343572 ps
CPU time 2.96 seconds
Started Jul 06 06:22:44 PM PDT 24
Finished Jul 06 06:22:47 PM PDT 24
Peak memory 225500 kb
Host smart-9badf127-8825-4006-9264-aa292871c266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728977481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1728977481
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3302100198
Short name T279
Test name
Test status
Simulation time 7025172304 ps
CPU time 39.13 seconds
Started Jul 06 06:22:45 PM PDT 24
Finished Jul 06 06:23:24 PM PDT 24
Peak memory 250848 kb
Host smart-21a19d25-a3a1-4665-a851-a6920f7580b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302100198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3302100198
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.450061562
Short name T358
Test name
Test status
Simulation time 627641088 ps
CPU time 7.9 seconds
Started Jul 06 06:22:44 PM PDT 24
Finished Jul 06 06:22:52 PM PDT 24
Peak memory 225584 kb
Host smart-2c391f11-4573-4343-bbbc-af8ad6e4e3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450061562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.450061562
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2217367787
Short name T830
Test name
Test status
Simulation time 681269973 ps
CPU time 4.64 seconds
Started Jul 06 06:22:46 PM PDT 24
Finished Jul 06 06:22:51 PM PDT 24
Peak memory 225520 kb
Host smart-83b80b9c-ee4b-4d7e-b8c9-6e9f39d46728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217367787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2217367787
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3952093245
Short name T824
Test name
Test status
Simulation time 33324552 ps
CPU time 1.03 seconds
Started Jul 06 06:22:39 PM PDT 24
Finished Jul 06 06:22:41 PM PDT 24
Peak memory 217696 kb
Host smart-5bb39ecf-54e0-4a43-b4dd-f881f4e606ee
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952093245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3952093245
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4139028081
Short name T534
Test name
Test status
Simulation time 4018121020 ps
CPU time 10.05 seconds
Started Jul 06 06:22:44 PM PDT 24
Finished Jul 06 06:22:55 PM PDT 24
Peak memory 225732 kb
Host smart-70e1fa87-eb1a-463f-9f31-97889b81d1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139028081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4139028081
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2350424009
Short name T241
Test name
Test status
Simulation time 452692431 ps
CPU time 2.53 seconds
Started Jul 06 06:22:45 PM PDT 24
Finished Jul 06 06:22:48 PM PDT 24
Peak memory 219984 kb
Host smart-9c889e2d-5433-4ddb-8c6f-5ddd1e47bb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350424009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2350424009
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2796659218
Short name T411
Test name
Test status
Simulation time 5980002001 ps
CPU time 19.16 seconds
Started Jul 06 06:22:42 PM PDT 24
Finished Jul 06 06:23:01 PM PDT 24
Peak memory 219936 kb
Host smart-84a2d716-6ff1-44cb-833e-800684e2c03b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2796659218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2796659218
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1794161576
Short name T975
Test name
Test status
Simulation time 27773390202 ps
CPU time 316.3 seconds
Started Jul 06 06:22:44 PM PDT 24
Finished Jul 06 06:28:01 PM PDT 24
Peak memory 268060 kb
Host smart-7961432d-381f-4e31-af28-83304083fff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794161576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1794161576
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3801782665
Short name T750
Test name
Test status
Simulation time 7190098620 ps
CPU time 25.52 seconds
Started Jul 06 06:22:41 PM PDT 24
Finished Jul 06 06:23:07 PM PDT 24
Peak memory 217500 kb
Host smart-16ec2688-a33a-4d7f-a356-248756a9519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801782665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3801782665
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2332883817
Short name T27
Test name
Test status
Simulation time 1574486709 ps
CPU time 5.93 seconds
Started Jul 06 06:22:39 PM PDT 24
Finished Jul 06 06:22:46 PM PDT 24
Peak memory 217388 kb
Host smart-d5d27f6b-375d-4121-a98b-fb53e6fae195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332883817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2332883817
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1312504966
Short name T332
Test name
Test status
Simulation time 505298359 ps
CPU time 2.4 seconds
Started Jul 06 06:22:42 PM PDT 24
Finished Jul 06 06:22:45 PM PDT 24
Peak memory 217396 kb
Host smart-c3165ce1-aefa-4737-b13d-86c1ea84a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312504966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1312504966
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2576716885
Short name T348
Test name
Test status
Simulation time 80133001 ps
CPU time 0.9 seconds
Started Jul 06 06:22:40 PM PDT 24
Finished Jul 06 06:22:41 PM PDT 24
Peak memory 207000 kb
Host smart-e9ce6a9f-ead0-4782-a6d6-eaf439450e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576716885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2576716885
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2391145310
Short name T420
Test name
Test status
Simulation time 997835880 ps
CPU time 6.46 seconds
Started Jul 06 06:22:42 PM PDT 24
Finished Jul 06 06:22:49 PM PDT 24
Peak memory 233808 kb
Host smart-c65a33a7-4bb8-4316-8349-24e927ba464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391145310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2391145310
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3663081356
Short name T362
Test name
Test status
Simulation time 13091138 ps
CPU time 0.68 seconds
Started Jul 06 06:22:53 PM PDT 24
Finished Jul 06 06:22:54 PM PDT 24
Peak memory 206736 kb
Host smart-93c20f7a-83f2-4a03-b28c-a65358ef01ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663081356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3663081356
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1418630804
Short name T641
Test name
Test status
Simulation time 34083198 ps
CPU time 2.49 seconds
Started Jul 06 06:22:57 PM PDT 24
Finished Jul 06 06:23:00 PM PDT 24
Peak memory 233488 kb
Host smart-d16d73b1-d0fa-4617-bafb-ea7dcba29125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418630804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1418630804
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3639537569
Short name T1006
Test name
Test status
Simulation time 43625694633 ps
CPU time 27.67 seconds
Started Jul 06 06:22:59 PM PDT 24
Finished Jul 06 06:23:27 PM PDT 24
Peak memory 249424 kb
Host smart-1695be19-83ea-476a-9cbc-014ae01273aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639537569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3639537569
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3421056267
Short name T781
Test name
Test status
Simulation time 7005474774 ps
CPU time 58.02 seconds
Started Jul 06 06:22:55 PM PDT 24
Finished Jul 06 06:23:53 PM PDT 24
Peak memory 225800 kb
Host smart-346eef7a-88cf-4da5-aab0-ad23c1ef601c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421056267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3421056267
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2576243883
Short name T266
Test name
Test status
Simulation time 3648088317 ps
CPU time 83.14 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:24:19 PM PDT 24
Peak memory 266656 kb
Host smart-b42f4c3e-6b6f-4810-a243-aedffee74072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576243883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2576243883
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2975643613
Short name T305
Test name
Test status
Simulation time 5658519518 ps
CPU time 21.06 seconds
Started Jul 06 06:22:47 PM PDT 24
Finished Jul 06 06:23:09 PM PDT 24
Peak memory 225712 kb
Host smart-9515beb7-9a7f-47af-a32f-2e3e7b7bfad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975643613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2975643613
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3333064668
Short name T873
Test name
Test status
Simulation time 5467332157 ps
CPU time 38.25 seconds
Started Jul 06 06:22:49 PM PDT 24
Finished Jul 06 06:23:28 PM PDT 24
Peak memory 240780 kb
Host smart-8f664027-eb7a-435c-80e6-99da449386ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333064668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3333064668
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2701882090
Short name T703
Test name
Test status
Simulation time 2982949596 ps
CPU time 5.56 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:23:06 PM PDT 24
Peak memory 224932 kb
Host smart-82dda80e-46c7-476e-9f9f-3eee3b2e0500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701882090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2701882090
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.266750082
Short name T434
Test name
Test status
Simulation time 654337102 ps
CPU time 6.45 seconds
Started Jul 06 06:22:57 PM PDT 24
Finished Jul 06 06:23:03 PM PDT 24
Peak memory 233780 kb
Host smart-7337c83b-a6c4-4aca-85e0-57a571b91b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266750082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.266750082
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.4253399957
Short name T84
Test name
Test status
Simulation time 47433615 ps
CPU time 1 seconds
Started Jul 06 06:22:48 PM PDT 24
Finished Jul 06 06:22:49 PM PDT 24
Peak memory 217640 kb
Host smart-39fc6d79-c287-4166-8b58-befa21978ca0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253399957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.4253399957
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3958492045
Short name T97
Test name
Test status
Simulation time 339558561 ps
CPU time 2.41 seconds
Started Jul 06 06:22:55 PM PDT 24
Finished Jul 06 06:22:57 PM PDT 24
Peak memory 233808 kb
Host smart-6d6cd467-f2ac-42cb-a0aa-953d24801f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958492045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3958492045
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2475106490
Short name T836
Test name
Test status
Simulation time 9567055490 ps
CPU time 13.12 seconds
Started Jul 06 06:22:55 PM PDT 24
Finished Jul 06 06:23:08 PM PDT 24
Peak memory 233888 kb
Host smart-6085d592-6a83-43d8-8c39-f33c5f64b60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475106490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2475106490
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2059722713
Short name T995
Test name
Test status
Simulation time 131715684 ps
CPU time 3.83 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 221272 kb
Host smart-b31c7fa4-caa6-4dd8-90a9-20367d5ccc84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2059722713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2059722713
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2335217640
Short name T561
Test name
Test status
Simulation time 22176216284 ps
CPU time 25.83 seconds
Started Jul 06 06:22:48 PM PDT 24
Finished Jul 06 06:23:14 PM PDT 24
Peak memory 217496 kb
Host smart-eaa932a4-0855-4579-ae55-d820e5c10adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335217640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2335217640
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3740553309
Short name T539
Test name
Test status
Simulation time 1639424977 ps
CPU time 7.42 seconds
Started Jul 06 06:22:54 PM PDT 24
Finished Jul 06 06:23:01 PM PDT 24
Peak memory 217352 kb
Host smart-f37b3f3a-50bf-4626-8895-8e9f4a7d0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740553309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3740553309
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1796042670
Short name T571
Test name
Test status
Simulation time 92796865 ps
CPU time 0.87 seconds
Started Jul 06 06:22:59 PM PDT 24
Finished Jul 06 06:23:00 PM PDT 24
Peak memory 207780 kb
Host smart-6befa64a-f2e9-4fe7-a86f-f69ddc3b1552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796042670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1796042670
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2832917803
Short name T598
Test name
Test status
Simulation time 246216077 ps
CPU time 0.76 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:22:59 PM PDT 24
Peak memory 206904 kb
Host smart-ee0df496-f2ee-4089-931e-4cc3d384a3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832917803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2832917803
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1145503685
Short name T131
Test name
Test status
Simulation time 6014174655 ps
CPU time 6.46 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:23:03 PM PDT 24
Peak memory 225736 kb
Host smart-8e6af162-68c5-4459-9a1f-7ca7f7dd0733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145503685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1145503685
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2314568653
Short name T934
Test name
Test status
Simulation time 39567826 ps
CPU time 0.72 seconds
Started Jul 06 06:22:54 PM PDT 24
Finished Jul 06 06:22:54 PM PDT 24
Peak memory 205788 kb
Host smart-620dd345-c675-49c7-9b5c-99a924e674af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314568653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2314568653
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3509800644
Short name T566
Test name
Test status
Simulation time 612099770 ps
CPU time 3.96 seconds
Started Jul 06 06:22:54 PM PDT 24
Finished Jul 06 06:22:59 PM PDT 24
Peak memory 225608 kb
Host smart-f9e03676-ded6-4769-b692-c81e7abf6b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509800644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3509800644
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3758422747
Short name T71
Test name
Test status
Simulation time 13714337 ps
CPU time 0.79 seconds
Started Jul 06 06:22:54 PM PDT 24
Finished Jul 06 06:22:56 PM PDT 24
Peak memory 207556 kb
Host smart-cac86bc8-3b79-43c7-bd00-02e194c7e42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758422747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3758422747
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1499485014
Short name T577
Test name
Test status
Simulation time 1845394926 ps
CPU time 33.75 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:23:34 PM PDT 24
Peak memory 250080 kb
Host smart-684bd929-9920-436b-be64-4943a9231fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499485014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1499485014
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1887366123
Short name T277
Test name
Test status
Simulation time 10995140797 ps
CPU time 35.48 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:23:34 PM PDT 24
Peak memory 250380 kb
Host smart-a8a8b837-9b61-4799-b053-fbac0326420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887366123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1887366123
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.78157935
Short name T7
Test name
Test status
Simulation time 1274648124 ps
CPU time 27.69 seconds
Started Jul 06 06:22:54 PM PDT 24
Finished Jul 06 06:23:22 PM PDT 24
Peak memory 238204 kb
Host smart-6c8ebadd-de54-4374-9b64-8d0b0fd25c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78157935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.78157935
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.656106694
Short name T302
Test name
Test status
Simulation time 117234066 ps
CPU time 4.91 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:23:01 PM PDT 24
Peak memory 233808 kb
Host smart-5b3f88ac-a05c-479a-826e-d6914cfeb964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656106694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.656106694
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.575606548
Short name T656
Test name
Test status
Simulation time 14176559 ps
CPU time 0.77 seconds
Started Jul 06 06:22:57 PM PDT 24
Finished Jul 06 06:22:58 PM PDT 24
Peak memory 216956 kb
Host smart-124a6a9f-c6e3-4a0f-b56a-d7937ba6ebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575606548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.575606548
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.151598851
Short name T908
Test name
Test status
Simulation time 166895578 ps
CPU time 3.26 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:23:00 PM PDT 24
Peak memory 225564 kb
Host smart-88e7c8b5-0d43-4c61-a25b-81c2b666feff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151598851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.151598851
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1832621920
Short name T616
Test name
Test status
Simulation time 153236187 ps
CPU time 2.47 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:22:58 PM PDT 24
Peak memory 225544 kb
Host smart-f8f5fc3e-6f1e-4efa-993e-e2bb1a57f7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832621920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1832621920
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3141517180
Short name T698
Test name
Test status
Simulation time 94300730 ps
CPU time 1.02 seconds
Started Jul 06 06:22:52 PM PDT 24
Finished Jul 06 06:22:53 PM PDT 24
Peak memory 218936 kb
Host smart-d705ee9b-dbbb-459e-b7e5-8452de5d2ef0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141517180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3141517180
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.246214730
Short name T1009
Test name
Test status
Simulation time 3344481613 ps
CPU time 4.13 seconds
Started Jul 06 06:22:57 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 225676 kb
Host smart-dcb3d981-0ca1-4f63-a73f-effce14d62d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246214730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.246214730
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.554260122
Short name T349
Test name
Test status
Simulation time 75643482 ps
CPU time 2.84 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:22:59 PM PDT 24
Peak memory 233784 kb
Host smart-07226dfa-7b56-4fce-a8bc-61e7864c97e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554260122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.554260122
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1257002940
Short name T839
Test name
Test status
Simulation time 1414730792 ps
CPU time 3.86 seconds
Started Jul 06 06:22:55 PM PDT 24
Finished Jul 06 06:22:59 PM PDT 24
Peak memory 219744 kb
Host smart-6695449e-f793-4318-a2ee-c07fc3a60fcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1257002940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1257002940
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2654823872
Short name T671
Test name
Test status
Simulation time 52271221151 ps
CPU time 405.87 seconds
Started Jul 06 06:22:55 PM PDT 24
Finished Jul 06 06:29:41 PM PDT 24
Peak memory 283744 kb
Host smart-bcc671b9-5eb4-4fa3-8b82-8a73fb5c7e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654823872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2654823872
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.42785091
Short name T700
Test name
Test status
Simulation time 45094400370 ps
CPU time 45.11 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:23:43 PM PDT 24
Peak memory 217516 kb
Host smart-a68ca82f-a9d3-42ca-8433-161b9d8ace8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42785091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.42785091
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.303384667
Short name T927
Test name
Test status
Simulation time 2062472068 ps
CPU time 11.32 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:23:08 PM PDT 24
Peak memory 217340 kb
Host smart-2b53d54c-a8be-4b3d-8823-ef5ee564ed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303384667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.303384667
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.400811959
Short name T494
Test name
Test status
Simulation time 25091919 ps
CPU time 0.85 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:23:00 PM PDT 24
Peak memory 207716 kb
Host smart-e0b49987-c39a-4a1c-a28a-5f44cba9e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400811959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.400811959
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.457635422
Short name T410
Test name
Test status
Simulation time 130071744 ps
CPU time 0.92 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 207904 kb
Host smart-97f3691b-c020-4854-8e9b-b37c943114de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457635422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.457635422
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4284401809
Short name T501
Test name
Test status
Simulation time 4107780084 ps
CPU time 6.51 seconds
Started Jul 06 06:22:55 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 233972 kb
Host smart-1db99bae-fe39-4817-987e-dd19bd4832c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284401809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4284401809
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3687952737
Short name T398
Test name
Test status
Simulation time 16941978 ps
CPU time 0.75 seconds
Started Jul 06 06:23:02 PM PDT 24
Finished Jul 06 06:23:03 PM PDT 24
Peak memory 205812 kb
Host smart-0a28a4df-eab1-45da-b5d3-7f6b5892af53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687952737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3687952737
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.432972547
Short name T978
Test name
Test status
Simulation time 330054158 ps
CPU time 3.17 seconds
Started Jul 06 06:22:59 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 233764 kb
Host smart-f52bbe5c-d203-491e-92da-5abb54f1e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432972547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.432972547
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4136781803
Short name T851
Test name
Test status
Simulation time 26674064 ps
CPU time 0.76 seconds
Started Jul 06 06:22:54 PM PDT 24
Finished Jul 06 06:22:55 PM PDT 24
Peak memory 206520 kb
Host smart-0fb42a2d-b961-444f-be8a-612e23758ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136781803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4136781803
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2590383349
Short name T198
Test name
Test status
Simulation time 43073434511 ps
CPU time 311.85 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:28:12 PM PDT 24
Peak memory 256436 kb
Host smart-d76d9b06-971c-494f-a6d4-7e6d17ff9cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590383349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2590383349
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.174717825
Short name T65
Test name
Test status
Simulation time 12601919116 ps
CPU time 125.79 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:25:06 PM PDT 24
Peak memory 266668 kb
Host smart-3f440345-2309-4b64-99e4-92221e025061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174717825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.174717825
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4069345606
Short name T834
Test name
Test status
Simulation time 8895590500 ps
CPU time 31.24 seconds
Started Jul 06 06:22:59 PM PDT 24
Finished Jul 06 06:23:31 PM PDT 24
Peak memory 233956 kb
Host smart-1a46ee3d-79aa-44de-aa98-b7bc33c7b97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069345606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4069345606
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2675951851
Short name T724
Test name
Test status
Simulation time 21302480252 ps
CPU time 45.76 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:23:45 PM PDT 24
Peak memory 239248 kb
Host smart-896c5823-a451-4abd-bc6b-76897a38d375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675951851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2675951851
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3853183125
Short name T772
Test name
Test status
Simulation time 847666002 ps
CPU time 10.44 seconds
Started Jul 06 06:22:57 PM PDT 24
Finished Jul 06 06:23:08 PM PDT 24
Peak memory 225564 kb
Host smart-fe4ad5c7-c0a1-4b40-81b6-6686d0a571ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853183125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3853183125
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.216906998
Short name T771
Test name
Test status
Simulation time 22379838082 ps
CPU time 31.04 seconds
Started Jul 06 06:22:59 PM PDT 24
Finished Jul 06 06:23:30 PM PDT 24
Peak memory 225692 kb
Host smart-dca47cad-0d40-4e61-b1cf-772dc7f2226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216906998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.216906998
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1396708927
Short name T640
Test name
Test status
Simulation time 34254080 ps
CPU time 1.07 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:22:58 PM PDT 24
Peak memory 217688 kb
Host smart-91f10d22-1bb7-45ad-aa1b-f1c19b1446d6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396708927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1396708927
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3749489920
Short name T776
Test name
Test status
Simulation time 695367620 ps
CPU time 4.04 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:23:04 PM PDT 24
Peak memory 224884 kb
Host smart-712fa8aa-fc55-4f87-b007-776066bc0922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749489920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3749489920
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4294485953
Short name T217
Test name
Test status
Simulation time 24440080267 ps
CPU time 18.37 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:23:17 PM PDT 24
Peak memory 233916 kb
Host smart-82f5da2b-2bb2-4929-b102-27e6353f9c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294485953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4294485953
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.620298027
Short name T713
Test name
Test status
Simulation time 549676820 ps
CPU time 4.57 seconds
Started Jul 06 06:22:57 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 220372 kb
Host smart-9520be3d-1409-4f55-a676-bdfe878e80ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=620298027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.620298027
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1351343227
Short name T721
Test name
Test status
Simulation time 52617463772 ps
CPU time 344.88 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:28:45 PM PDT 24
Peak memory 257848 kb
Host smart-bf9bdae5-92c6-44bd-a27c-2f4127c99e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351343227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1351343227
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.603808084
Short name T788
Test name
Test status
Simulation time 6074512058 ps
CPU time 21.11 seconds
Started Jul 06 06:22:56 PM PDT 24
Finished Jul 06 06:23:17 PM PDT 24
Peak memory 217688 kb
Host smart-966c8810-9af5-4025-8928-05dd423f97d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603808084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.603808084
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4173309376
Short name T723
Test name
Test status
Simulation time 241263797 ps
CPU time 2.12 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:23:01 PM PDT 24
Peak memory 217232 kb
Host smart-52e30dab-8fbe-464c-8e1d-fc85d9383ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173309376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4173309376
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.580522500
Short name T364
Test name
Test status
Simulation time 157136534 ps
CPU time 1.23 seconds
Started Jul 06 06:22:58 PM PDT 24
Finished Jul 06 06:23:00 PM PDT 24
Peak memory 209032 kb
Host smart-00f754bb-c18d-47fa-8d14-6a7f07e4b5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580522500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.580522500
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.494710622
Short name T689
Test name
Test status
Simulation time 105057653 ps
CPU time 0.75 seconds
Started Jul 06 06:22:59 PM PDT 24
Finished Jul 06 06:23:00 PM PDT 24
Peak memory 206996 kb
Host smart-ed3bcf37-4371-4c80-9eb2-bab4068fa897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494710622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.494710622
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4020230448
Short name T726
Test name
Test status
Simulation time 16367521776 ps
CPU time 23.02 seconds
Started Jul 06 06:22:59 PM PDT 24
Finished Jul 06 06:23:22 PM PDT 24
Peak memory 233916 kb
Host smart-4325314c-7801-44d9-9c15-c834e1b45c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020230448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4020230448
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1714379903
Short name T866
Test name
Test status
Simulation time 21575796 ps
CPU time 0.73 seconds
Started Jul 06 06:23:10 PM PDT 24
Finished Jul 06 06:23:11 PM PDT 24
Peak memory 206360 kb
Host smart-a4e5477c-44d9-4e09-980a-ad473d5ad70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714379903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1714379903
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3942685137
Short name T749
Test name
Test status
Simulation time 112952425 ps
CPU time 2.27 seconds
Started Jul 06 06:23:07 PM PDT 24
Finished Jul 06 06:23:09 PM PDT 24
Peak memory 225600 kb
Host smart-70c18a29-d67e-41aa-b8ef-02367d32579b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942685137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3942685137
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3850370741
Short name T438
Test name
Test status
Simulation time 20941854 ps
CPU time 0.8 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:23:01 PM PDT 24
Peak memory 207552 kb
Host smart-35999d55-71e2-40c0-a441-095597c2d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850370741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3850370741
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1970680478
Short name T408
Test name
Test status
Simulation time 7843529066 ps
CPU time 54.82 seconds
Started Jul 06 06:23:04 PM PDT 24
Finished Jul 06 06:23:59 PM PDT 24
Peak memory 251280 kb
Host smart-7a1ce35e-8cfd-4473-97ae-10afd1d76911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970680478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1970680478
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4062701907
Short name T321
Test name
Test status
Simulation time 7886708555 ps
CPU time 94.05 seconds
Started Jul 06 06:23:10 PM PDT 24
Finished Jul 06 06:24:44 PM PDT 24
Peak memory 252276 kb
Host smart-0d1d015a-52de-401a-bf9f-e84a3a6180e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062701907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4062701907
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.199697340
Short name T796
Test name
Test status
Simulation time 10743892134 ps
CPU time 44.12 seconds
Started Jul 06 06:23:04 PM PDT 24
Finished Jul 06 06:23:48 PM PDT 24
Peak memory 254032 kb
Host smart-c3d544ae-3512-4256-92e6-49aefb411996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199697340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.199697340
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3345375279
Short name T150
Test name
Test status
Simulation time 635189164 ps
CPU time 4.05 seconds
Started Jul 06 06:23:05 PM PDT 24
Finished Jul 06 06:23:09 PM PDT 24
Peak memory 225600 kb
Host smart-3769e677-9336-48b0-adb9-8da1d59ea9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345375279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3345375279
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3420136428
Short name T765
Test name
Test status
Simulation time 9315355011 ps
CPU time 37.38 seconds
Started Jul 06 06:23:11 PM PDT 24
Finished Jul 06 06:23:49 PM PDT 24
Peak memory 225728 kb
Host smart-016ef8d0-b30e-48f3-a111-4d7296edfb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420136428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3420136428
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3523302833
Short name T513
Test name
Test status
Simulation time 2159796377 ps
CPU time 3.47 seconds
Started Jul 06 06:23:05 PM PDT 24
Finished Jul 06 06:23:08 PM PDT 24
Peak memory 233888 kb
Host smart-dc29f5dd-6058-4511-9ce0-f9b6c574dace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523302833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3523302833
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.361003743
Short name T973
Test name
Test status
Simulation time 4947151403 ps
CPU time 23.26 seconds
Started Jul 06 06:23:05 PM PDT 24
Finished Jul 06 06:23:28 PM PDT 24
Peak memory 225748 kb
Host smart-791eec65-f547-4ab4-a54e-80e2416464bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361003743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.361003743
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3268585269
Short name T333
Test name
Test status
Simulation time 69874508 ps
CPU time 1.02 seconds
Started Jul 06 06:23:00 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 217720 kb
Host smart-ebd45f64-5038-4ac4-9ae6-5b9b9fd039cd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268585269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3268585269
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3296593494
Short name T52
Test name
Test status
Simulation time 1961863163 ps
CPU time 3.87 seconds
Started Jul 06 06:23:04 PM PDT 24
Finished Jul 06 06:23:08 PM PDT 24
Peak memory 233780 kb
Host smart-49963a34-c0e7-4916-ada1-226c47251557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296593494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3296593494
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.515901032
Short name T432
Test name
Test status
Simulation time 59041998 ps
CPU time 2.42 seconds
Started Jul 06 06:23:04 PM PDT 24
Finished Jul 06 06:23:07 PM PDT 24
Peak memory 233548 kb
Host smart-864c6ed0-cedd-4950-ba97-e341f8a75de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515901032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.515901032
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1522116823
Short name T49
Test name
Test status
Simulation time 27093469150 ps
CPU time 16.33 seconds
Started Jul 06 06:23:05 PM PDT 24
Finished Jul 06 06:23:21 PM PDT 24
Peak memory 220188 kb
Host smart-8a7f46db-6e3d-4952-aa85-3b39bef2e697
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522116823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1522116823
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2970719910
Short name T996
Test name
Test status
Simulation time 161313919 ps
CPU time 1.01 seconds
Started Jul 06 06:23:09 PM PDT 24
Finished Jul 06 06:23:10 PM PDT 24
Peak memory 208024 kb
Host smart-c4d91d53-0510-4593-8eab-f1174c6cea4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970719910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2970719910
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2635635184
Short name T718
Test name
Test status
Simulation time 867180166 ps
CPU time 2.43 seconds
Started Jul 06 06:23:03 PM PDT 24
Finished Jul 06 06:23:05 PM PDT 24
Peak memory 220224 kb
Host smart-e3269c56-4dd9-4dfd-a667-2591ac74c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635635184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2635635184
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2345043693
Short name T986
Test name
Test status
Simulation time 171567465 ps
CPU time 1.86 seconds
Started Jul 06 06:23:02 PM PDT 24
Finished Jul 06 06:23:04 PM PDT 24
Peak memory 208916 kb
Host smart-91f0da1f-62f2-40de-a22b-dec929b519b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345043693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2345043693
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4056115001
Short name T319
Test name
Test status
Simulation time 52647533 ps
CPU time 1.01 seconds
Started Jul 06 06:23:01 PM PDT 24
Finished Jul 06 06:23:03 PM PDT 24
Peak memory 207620 kb
Host smart-c03e04ba-5feb-4fc2-94f0-16d5bcebce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056115001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4056115001
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4278237425
Short name T930
Test name
Test status
Simulation time 56789022 ps
CPU time 0.7 seconds
Started Jul 06 06:23:01 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 206584 kb
Host smart-4278774c-0852-4bf8-9987-7af9c99b00b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278237425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4278237425
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3134295019
Short name T660
Test name
Test status
Simulation time 926612130 ps
CPU time 3.95 seconds
Started Jul 06 06:23:03 PM PDT 24
Finished Jul 06 06:23:07 PM PDT 24
Peak memory 225568 kb
Host smart-ae809220-ec45-45e6-8354-8ba011395f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134295019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3134295019
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2220824951
Short name T418
Test name
Test status
Simulation time 18457382 ps
CPU time 0.72 seconds
Started Jul 06 06:21:45 PM PDT 24
Finished Jul 06 06:21:46 PM PDT 24
Peak memory 206388 kb
Host smart-33dda626-4390-4d76-9a23-a5483e93820a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220824951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
220824951
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3631709967
Short name T390
Test name
Test status
Simulation time 365553843 ps
CPU time 4.07 seconds
Started Jul 06 06:21:46 PM PDT 24
Finished Jul 06 06:21:50 PM PDT 24
Peak memory 233760 kb
Host smart-0f46119c-5d86-4b3f-a5d5-adbe2f851774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631709967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3631709967
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3746033814
Short name T855
Test name
Test status
Simulation time 122773120 ps
CPU time 0.78 seconds
Started Jul 06 06:21:36 PM PDT 24
Finished Jul 06 06:21:37 PM PDT 24
Peak memory 207504 kb
Host smart-435368bc-bc41-4c9a-9b09-5dccfde3de0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746033814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3746033814
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2010770115
Short name T286
Test name
Test status
Simulation time 17284507701 ps
CPU time 134.28 seconds
Started Jul 06 06:21:45 PM PDT 24
Finished Jul 06 06:23:59 PM PDT 24
Peak memory 254168 kb
Host smart-c82f22cf-d4c3-49c5-838d-f1d09ba34140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010770115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2010770115
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2121839352
Short name T318
Test name
Test status
Simulation time 2787957180 ps
CPU time 33.19 seconds
Started Jul 06 06:21:45 PM PDT 24
Finished Jul 06 06:22:18 PM PDT 24
Peak memory 234116 kb
Host smart-fe702545-f258-4d86-9d64-a9e488d72351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121839352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2121839352
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1670627458
Short name T248
Test name
Test status
Simulation time 130569778079 ps
CPU time 279.43 seconds
Started Jul 06 06:21:44 PM PDT 24
Finished Jul 06 06:26:24 PM PDT 24
Peak memory 251244 kb
Host smart-2a0e2bf2-5b51-43a2-8bd3-a43836a1c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670627458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1670627458
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3059083710
Short name T711
Test name
Test status
Simulation time 9293574549 ps
CPU time 27.18 seconds
Started Jul 06 06:21:43 PM PDT 24
Finished Jul 06 06:22:10 PM PDT 24
Peak memory 241780 kb
Host smart-2b469bd9-5b42-4923-9ab3-78e94ce688ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059083710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3059083710
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3816673132
Short name T235
Test name
Test status
Simulation time 163670847 ps
CPU time 3.45 seconds
Started Jul 06 06:21:41 PM PDT 24
Finished Jul 06 06:21:45 PM PDT 24
Peak memory 225580 kb
Host smart-e325ecb9-c3df-46f3-989e-20f3fcd71eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816673132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3816673132
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1856399831
Short name T499
Test name
Test status
Simulation time 16706495033 ps
CPU time 78.89 seconds
Started Jul 06 06:21:43 PM PDT 24
Finished Jul 06 06:23:02 PM PDT 24
Peak memory 233844 kb
Host smart-bbf7b12e-a2a3-4692-a2ce-a65a9bf5896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856399831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1856399831
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3995769224
Short name T498
Test name
Test status
Simulation time 104184625 ps
CPU time 1.18 seconds
Started Jul 06 06:21:37 PM PDT 24
Finished Jul 06 06:21:38 PM PDT 24
Peak memory 217692 kb
Host smart-a58090cb-1ad9-4134-aa9f-312e7017b759
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995769224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3995769224
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1803208311
Short name T291
Test name
Test status
Simulation time 82929363204 ps
CPU time 31.66 seconds
Started Jul 06 06:21:42 PM PDT 24
Finished Jul 06 06:22:13 PM PDT 24
Peak memory 249764 kb
Host smart-fb6aa653-765a-45a8-8b67-5ee060707fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803208311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1803208311
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.199979246
Short name T433
Test name
Test status
Simulation time 270967451 ps
CPU time 3.42 seconds
Started Jul 06 06:21:39 PM PDT 24
Finished Jul 06 06:21:42 PM PDT 24
Peak memory 233804 kb
Host smart-5f41cb44-bd5a-47f9-87cf-00d61777efff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199979246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.199979246
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.632413207
Short name T897
Test name
Test status
Simulation time 6454694320 ps
CPU time 14.81 seconds
Started Jul 06 06:21:40 PM PDT 24
Finished Jul 06 06:21:55 PM PDT 24
Peak memory 222888 kb
Host smart-35c31013-b33b-46eb-880a-2eeb123a982e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=632413207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.632413207
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.277955025
Short name T932
Test name
Test status
Simulation time 8320886903 ps
CPU time 76.59 seconds
Started Jul 06 06:21:44 PM PDT 24
Finished Jul 06 06:23:01 PM PDT 24
Peak memory 250444 kb
Host smart-cc9fbb8a-c6c6-49a0-8769-3187f12103d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277955025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.277955025
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1309156473
Short name T623
Test name
Test status
Simulation time 8676625883 ps
CPU time 11.57 seconds
Started Jul 06 06:21:36 PM PDT 24
Finished Jul 06 06:21:48 PM PDT 24
Peak memory 217512 kb
Host smart-5a95d2b3-be3b-4e4e-a396-68de28fabe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309156473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1309156473
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2397386255
Short name T391
Test name
Test status
Simulation time 1923598243 ps
CPU time 7.09 seconds
Started Jul 06 06:21:36 PM PDT 24
Finished Jul 06 06:21:44 PM PDT 24
Peak memory 217312 kb
Host smart-4e1e1a01-e601-449d-be59-d759f5866937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397386255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2397386255
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1768612897
Short name T648
Test name
Test status
Simulation time 537876397 ps
CPU time 5.67 seconds
Started Jul 06 06:21:41 PM PDT 24
Finished Jul 06 06:21:47 PM PDT 24
Peak memory 217348 kb
Host smart-5a605c77-1921-4b49-bf2a-6ba6f9701fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768612897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1768612897
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.621442838
Short name T974
Test name
Test status
Simulation time 28029099 ps
CPU time 0.85 seconds
Started Jul 06 06:21:36 PM PDT 24
Finished Jul 06 06:21:37 PM PDT 24
Peak memory 206988 kb
Host smart-397797ef-a0d9-4863-95d1-559a9e1a6b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621442838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.621442838
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.260175017
Short name T495
Test name
Test status
Simulation time 1356192241 ps
CPU time 8.54 seconds
Started Jul 06 06:21:43 PM PDT 24
Finished Jul 06 06:21:52 PM PDT 24
Peak memory 233820 kb
Host smart-e6a97bff-509c-4cdf-a7d9-159344f3bdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260175017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.260175017
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3491180298
Short name T380
Test name
Test status
Simulation time 17413319 ps
CPU time 0.76 seconds
Started Jul 06 06:23:14 PM PDT 24
Finished Jul 06 06:23:16 PM PDT 24
Peak memory 206396 kb
Host smart-d0550b78-137f-4300-a9c1-74fca3d353af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491180298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3491180298
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2028867294
Short name T246
Test name
Test status
Simulation time 633736852 ps
CPU time 4.3 seconds
Started Jul 06 06:23:09 PM PDT 24
Finished Jul 06 06:23:13 PM PDT 24
Peak memory 233840 kb
Host smart-fd89bfa0-8459-4eee-990e-b8bac135361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028867294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2028867294
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1754638040
Short name T935
Test name
Test status
Simulation time 62817361 ps
CPU time 0.78 seconds
Started Jul 06 06:23:12 PM PDT 24
Finished Jul 06 06:23:13 PM PDT 24
Peak memory 207484 kb
Host smart-d197c61e-5456-4eef-9baf-9c0ee0e78f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754638040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1754638040
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4252633632
Short name T516
Test name
Test status
Simulation time 13767055793 ps
CPU time 97.86 seconds
Started Jul 06 06:23:11 PM PDT 24
Finished Jul 06 06:24:49 PM PDT 24
Peak memory 239268 kb
Host smart-0d49100a-58fd-469b-b448-65d6c986a9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252633632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4252633632
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2406994410
Short name T774
Test name
Test status
Simulation time 29871589868 ps
CPU time 50.6 seconds
Started Jul 06 06:23:16 PM PDT 24
Finished Jul 06 06:24:07 PM PDT 24
Peak memory 250896 kb
Host smart-fc52c79a-7286-4662-965e-e9b59e0247bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406994410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2406994410
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3369450444
Short name T61
Test name
Test status
Simulation time 31455562257 ps
CPU time 241.13 seconds
Started Jul 06 06:23:16 PM PDT 24
Finished Jul 06 06:27:18 PM PDT 24
Peak memory 257464 kb
Host smart-946b6218-25d1-4766-944c-2b9334cfced8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369450444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3369450444
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2968480218
Short name T758
Test name
Test status
Simulation time 573483579 ps
CPU time 9.97 seconds
Started Jul 06 06:23:10 PM PDT 24
Finished Jul 06 06:23:20 PM PDT 24
Peak memory 225520 kb
Host smart-653a0cf2-289d-40e8-a3ff-4c6a7d50431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968480218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2968480218
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3094400429
Short name T870
Test name
Test status
Simulation time 6877525610 ps
CPU time 12.05 seconds
Started Jul 06 06:23:11 PM PDT 24
Finished Jul 06 06:23:24 PM PDT 24
Peak memory 234000 kb
Host smart-23ea6a2f-1eee-4fb3-b90c-36e13268cad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094400429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3094400429
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3280420572
Short name T756
Test name
Test status
Simulation time 2498609323 ps
CPU time 12.51 seconds
Started Jul 06 06:23:09 PM PDT 24
Finished Jul 06 06:23:22 PM PDT 24
Peak memory 225716 kb
Host smart-84762cf9-6b80-4145-8c4e-bbca906fe48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280420572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3280420572
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2206700884
Short name T945
Test name
Test status
Simulation time 38613982938 ps
CPU time 20.65 seconds
Started Jul 06 06:23:09 PM PDT 24
Finished Jul 06 06:23:29 PM PDT 24
Peak memory 228132 kb
Host smart-e75d088b-1f7c-486a-8015-268146826088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206700884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2206700884
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.506895946
Short name T488
Test name
Test status
Simulation time 525230663 ps
CPU time 4.05 seconds
Started Jul 06 06:23:09 PM PDT 24
Finished Jul 06 06:23:14 PM PDT 24
Peak memory 233752 kb
Host smart-748d924b-2cf2-43d0-b026-220f989543aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506895946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.506895946
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4244347238
Short name T453
Test name
Test status
Simulation time 718915802 ps
CPU time 4.49 seconds
Started Jul 06 06:23:09 PM PDT 24
Finished Jul 06 06:23:14 PM PDT 24
Peak memory 220272 kb
Host smart-aa4d4603-b2a7-414d-bc45-959590a7647b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4244347238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4244347238
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2935075031
Short name T734
Test name
Test status
Simulation time 9953703107 ps
CPU time 62.51 seconds
Started Jul 06 06:23:13 PM PDT 24
Finished Jul 06 06:24:16 PM PDT 24
Peak memory 242132 kb
Host smart-6c93d44e-2743-428d-bac6-c1c73eb73738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935075031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2935075031
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2090565165
Short name T959
Test name
Test status
Simulation time 49182321786 ps
CPU time 31.19 seconds
Started Jul 06 06:23:10 PM PDT 24
Finished Jul 06 06:23:42 PM PDT 24
Peak memory 217824 kb
Host smart-0625e515-bbfc-4400-9bcc-3da80dcb9654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090565165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2090565165
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1133358328
Short name T409
Test name
Test status
Simulation time 1006766380 ps
CPU time 3.04 seconds
Started Jul 06 06:23:16 PM PDT 24
Finished Jul 06 06:23:20 PM PDT 24
Peak memory 217356 kb
Host smart-10d7dbce-beaa-4dda-915d-44a223804bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133358328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1133358328
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4154559083
Short name T972
Test name
Test status
Simulation time 193105080 ps
CPU time 1.37 seconds
Started Jul 06 06:23:16 PM PDT 24
Finished Jul 06 06:23:18 PM PDT 24
Peak memory 217372 kb
Host smart-463f0e4d-7753-4965-a8ee-a55072c6a5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154559083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4154559083
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1251487780
Short name T363
Test name
Test status
Simulation time 19308767 ps
CPU time 0.72 seconds
Started Jul 06 06:23:12 PM PDT 24
Finished Jul 06 06:23:13 PM PDT 24
Peak memory 206516 kb
Host smart-85300912-39b7-4108-9483-27c94d388249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251487780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1251487780
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.623058630
Short name T618
Test name
Test status
Simulation time 258330178 ps
CPU time 3.43 seconds
Started Jul 06 06:23:13 PM PDT 24
Finished Jul 06 06:23:17 PM PDT 24
Peak memory 225600 kb
Host smart-af7a8499-cc93-4b4e-9b2a-6ce352de2f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623058630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.623058630
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.683464766
Short name T73
Test name
Test status
Simulation time 40061433 ps
CPU time 0.66 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:23:22 PM PDT 24
Peak memory 205780 kb
Host smart-e4124df6-b5dc-44b6-99a5-10bdb48f5db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683464766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.683464766
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2726401420
Short name T475
Test name
Test status
Simulation time 151362401 ps
CPU time 4.63 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:23:26 PM PDT 24
Peak memory 233780 kb
Host smart-ad408946-8ea5-4b0b-8b49-161c528b6988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726401420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2726401420
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2866202661
Short name T538
Test name
Test status
Simulation time 18943166 ps
CPU time 0.79 seconds
Started Jul 06 06:23:12 PM PDT 24
Finished Jul 06 06:23:13 PM PDT 24
Peak memory 207512 kb
Host smart-da206d53-4998-4f01-a327-95aa45ea661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866202661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2866202661
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.537672742
Short name T379
Test name
Test status
Simulation time 2943903961 ps
CPU time 25.06 seconds
Started Jul 06 06:23:19 PM PDT 24
Finished Jul 06 06:23:44 PM PDT 24
Peak memory 236796 kb
Host smart-b40e1791-ace3-4e4b-99df-5760431957d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537672742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.537672742
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3262641040
Short name T493
Test name
Test status
Simulation time 1391474942 ps
CPU time 28.43 seconds
Started Jul 06 06:23:12 PM PDT 24
Finished Jul 06 06:23:41 PM PDT 24
Peak memory 251316 kb
Host smart-834d5b8f-cc4f-4ec9-9b20-b21f2ff78126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262641040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3262641040
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3264168470
Short name T745
Test name
Test status
Simulation time 2168531584 ps
CPU time 6.19 seconds
Started Jul 06 06:23:14 PM PDT 24
Finished Jul 06 06:23:20 PM PDT 24
Peak memory 242056 kb
Host smart-207ca5bc-4787-44e5-95c8-b049feaffbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264168470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3264168470
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.16389158
Short name T1016
Test name
Test status
Simulation time 37804594740 ps
CPU time 252.44 seconds
Started Jul 06 06:23:14 PM PDT 24
Finished Jul 06 06:27:27 PM PDT 24
Peak memory 252320 kb
Host smart-3273413d-da86-4b71-b6ad-2ec546df8a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16389158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.16389158
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.118811550
Short name T998
Test name
Test status
Simulation time 46190128 ps
CPU time 2.5 seconds
Started Jul 06 06:23:14 PM PDT 24
Finished Jul 06 06:23:17 PM PDT 24
Peak memory 233812 kb
Host smart-15fafd1a-fc09-46b9-bf7b-7a5d56b69d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118811550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.118811550
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.197208550
Short name T795
Test name
Test status
Simulation time 18766142489 ps
CPU time 74.9 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:24:36 PM PDT 24
Peak memory 242124 kb
Host smart-d766ec67-6278-420d-8ae8-3963874c221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197208550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.197208550
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1958722988
Short name T213
Test name
Test status
Simulation time 2799613122 ps
CPU time 12.98 seconds
Started Jul 06 06:23:13 PM PDT 24
Finished Jul 06 06:23:27 PM PDT 24
Peak memory 233804 kb
Host smart-b1fbadf3-b736-4c06-9a1f-240c69d4ee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958722988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1958722988
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3759006439
Short name T238
Test name
Test status
Simulation time 231995343 ps
CPU time 3.46 seconds
Started Jul 06 06:23:16 PM PDT 24
Finished Jul 06 06:23:20 PM PDT 24
Peak memory 225572 kb
Host smart-c9d4be5a-7878-45d8-92da-de9f91e81d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759006439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3759006439
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.927723448
Short name T524
Test name
Test status
Simulation time 512095770 ps
CPU time 5.09 seconds
Started Jul 06 06:23:12 PM PDT 24
Finished Jul 06 06:23:18 PM PDT 24
Peak memory 223924 kb
Host smart-20f7ce2b-8ef9-400e-9324-705229d6d8cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=927723448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.927723448
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.884325705
Short name T909
Test name
Test status
Simulation time 208402684688 ps
CPU time 383.83 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:29:45 PM PDT 24
Peak memory 266876 kb
Host smart-ec3cebb8-90f8-48e1-9e55-bf301af5bad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884325705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.884325705
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3373592528
Short name T317
Test name
Test status
Simulation time 3246895888 ps
CPU time 12.75 seconds
Started Jul 06 06:23:21 PM PDT 24
Finished Jul 06 06:23:35 PM PDT 24
Peak memory 217676 kb
Host smart-282968bd-db09-42f3-934b-a410f995d9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373592528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3373592528
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3604882270
Short name T378
Test name
Test status
Simulation time 338028380 ps
CPU time 1.9 seconds
Started Jul 06 06:23:14 PM PDT 24
Finished Jul 06 06:23:16 PM PDT 24
Peak memory 217140 kb
Host smart-81be2241-05ca-4721-9549-9ff8c820398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604882270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3604882270
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3541644848
Short name T841
Test name
Test status
Simulation time 34968279 ps
CPU time 1.36 seconds
Started Jul 06 06:23:21 PM PDT 24
Finished Jul 06 06:23:23 PM PDT 24
Peak memory 217368 kb
Host smart-2b5eb389-d41d-40dc-9860-a6bcf8c07b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541644848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3541644848
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3449378840
Short name T484
Test name
Test status
Simulation time 109019170 ps
CPU time 0.99 seconds
Started Jul 06 06:23:12 PM PDT 24
Finished Jul 06 06:23:13 PM PDT 24
Peak memory 206988 kb
Host smart-8f519991-2751-4503-9eea-d0a74fe42e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449378840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3449378840
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.810252350
Short name T164
Test name
Test status
Simulation time 361015709 ps
CPU time 8.13 seconds
Started Jul 06 06:23:15 PM PDT 24
Finished Jul 06 06:23:24 PM PDT 24
Peak memory 250136 kb
Host smart-ffdf53f5-9d51-45e3-a500-274f0b2ba014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810252350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.810252350
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1885923316
Short name T383
Test name
Test status
Simulation time 64896697 ps
CPU time 0.73 seconds
Started Jul 06 06:23:19 PM PDT 24
Finished Jul 06 06:23:20 PM PDT 24
Peak memory 205832 kb
Host smart-600880cc-d9f0-410b-b728-524e509e710a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885923316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1885923316
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1243325926
Short name T245
Test name
Test status
Simulation time 188845551 ps
CPU time 3.83 seconds
Started Jul 06 06:23:18 PM PDT 24
Finished Jul 06 06:23:22 PM PDT 24
Peak memory 225572 kb
Host smart-bcfd0a8f-c979-4409-99a1-aa3649e937a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243325926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1243325926
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1736936382
Short name T990
Test name
Test status
Simulation time 37317947 ps
CPU time 0.79 seconds
Started Jul 06 06:23:15 PM PDT 24
Finished Jul 06 06:23:16 PM PDT 24
Peak memory 207532 kb
Host smart-42a3d67f-99d1-47e5-acb0-5e8fe9de834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736936382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1736936382
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2190608745
Short name T231
Test name
Test status
Simulation time 29211941786 ps
CPU time 98.86 seconds
Started Jul 06 06:23:17 PM PDT 24
Finished Jul 06 06:24:56 PM PDT 24
Peak memory 253348 kb
Host smart-62322dec-8645-4518-8458-2da694ea7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190608745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2190608745
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1660637412
Short name T307
Test name
Test status
Simulation time 583927949 ps
CPU time 6.92 seconds
Started Jul 06 06:23:18 PM PDT 24
Finished Jul 06 06:23:26 PM PDT 24
Peak memory 241964 kb
Host smart-6ed206eb-0f16-4d75-8b49-ecf5cf0d8f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660637412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1660637412
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.372060296
Short name T868
Test name
Test status
Simulation time 7913809114 ps
CPU time 64.38 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:24:25 PM PDT 24
Peak memory 250320 kb
Host smart-4f169340-6419-4e2f-a5d0-c0cf21683c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372060296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.372060296
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2391873203
Short name T193
Test name
Test status
Simulation time 3109069375 ps
CPU time 10.18 seconds
Started Jul 06 06:23:18 PM PDT 24
Finished Jul 06 06:23:29 PM PDT 24
Peak memory 225688 kb
Host smart-1a50449a-c782-4b36-9236-2dda123f9c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391873203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2391873203
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.750254714
Short name T228
Test name
Test status
Simulation time 29331377153 ps
CPU time 62.85 seconds
Started Jul 06 06:23:21 PM PDT 24
Finished Jul 06 06:24:25 PM PDT 24
Peak memory 225636 kb
Host smart-6c5164f6-cdab-4fcb-be75-5878b1374640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750254714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.750254714
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.422033981
Short name T195
Test name
Test status
Simulation time 66070839770 ps
CPU time 18.13 seconds
Started Jul 06 06:23:19 PM PDT 24
Finished Jul 06 06:23:37 PM PDT 24
Peak memory 239924 kb
Host smart-db374598-65c3-4d50-a817-450ad270b0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422033981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.422033981
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3629744933
Short name T634
Test name
Test status
Simulation time 5008538424 ps
CPU time 7.12 seconds
Started Jul 06 06:23:13 PM PDT 24
Finished Jul 06 06:23:20 PM PDT 24
Peak memory 233916 kb
Host smart-8d7b5594-b537-4a9b-9dd3-f3d3947e22e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629744933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3629744933
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.969179198
Short name T719
Test name
Test status
Simulation time 7243276025 ps
CPU time 10.14 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:23:31 PM PDT 24
Peak memory 221220 kb
Host smart-a7f27e6d-c001-4bf8-be96-a0f96a7c6860
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=969179198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.969179198
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1070350927
Short name T907
Test name
Test status
Simulation time 15859899709 ps
CPU time 27.04 seconds
Started Jul 06 06:23:15 PM PDT 24
Finished Jul 06 06:23:42 PM PDT 24
Peak memory 217620 kb
Host smart-6b5e58d0-1d4e-424e-a33b-267337a50c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070350927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1070350927
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4020772598
Short name T66
Test name
Test status
Simulation time 39934026 ps
CPU time 0.68 seconds
Started Jul 06 06:23:13 PM PDT 24
Finished Jul 06 06:23:14 PM PDT 24
Peak memory 206544 kb
Host smart-0d87ff62-189a-48f5-b2c5-46711d572fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020772598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4020772598
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1124755100
Short name T699
Test name
Test status
Simulation time 68413842 ps
CPU time 1.13 seconds
Started Jul 06 06:23:14 PM PDT 24
Finished Jul 06 06:23:15 PM PDT 24
Peak memory 208976 kb
Host smart-e87cb6f1-f32c-4130-9610-b7d1b68513dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124755100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1124755100
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.966034514
Short name T346
Test name
Test status
Simulation time 58557920 ps
CPU time 0.81 seconds
Started Jul 06 06:23:19 PM PDT 24
Finished Jul 06 06:23:20 PM PDT 24
Peak memory 206924 kb
Host smart-06811926-772b-48dc-a7d7-23ddd88a96d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966034514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.966034514
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.608035065
Short name T808
Test name
Test status
Simulation time 526065084 ps
CPU time 4.86 seconds
Started Jul 06 06:23:19 PM PDT 24
Finished Jul 06 06:23:24 PM PDT 24
Peak memory 225572 kb
Host smart-3abb14e8-1117-484a-ac18-a16b12a793f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608035065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.608035065
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3913585327
Short name T647
Test name
Test status
Simulation time 18227787 ps
CPU time 0.74 seconds
Started Jul 06 06:23:35 PM PDT 24
Finished Jul 06 06:23:36 PM PDT 24
Peak memory 206368 kb
Host smart-7c5a9a72-fe60-446d-9bee-61828fc829eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913585327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3913585327
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.875378120
Short name T695
Test name
Test status
Simulation time 1577640596 ps
CPU time 16.73 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:55 PM PDT 24
Peak memory 225572 kb
Host smart-8ebf02ac-753d-4aae-ae66-1903cb3d2886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875378120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.875378120
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1210784667
Short name T336
Test name
Test status
Simulation time 69900650 ps
CPU time 0.77 seconds
Started Jul 06 06:23:21 PM PDT 24
Finished Jul 06 06:23:23 PM PDT 24
Peak memory 207540 kb
Host smart-626c8e9f-e4ed-4009-aba0-3bb6bc51bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210784667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1210784667
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2426651223
Short name T545
Test name
Test status
Simulation time 160917547671 ps
CPU time 264.07 seconds
Started Jul 06 06:23:25 PM PDT 24
Finished Jul 06 06:27:49 PM PDT 24
Peak memory 254244 kb
Host smart-6d51f040-e097-4647-b949-93ae7964a623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426651223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2426651223
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3078178167
Short name T312
Test name
Test status
Simulation time 5329266004 ps
CPU time 39.47 seconds
Started Jul 06 06:23:34 PM PDT 24
Finished Jul 06 06:24:14 PM PDT 24
Peak memory 250364 kb
Host smart-0b289124-3619-42b1-a1b0-aba4056ab9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078178167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3078178167
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1828434437
Short name T1004
Test name
Test status
Simulation time 3324892497 ps
CPU time 92.43 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:25:13 PM PDT 24
Peak memory 270564 kb
Host smart-3668858f-08d2-43d9-8e7d-f87c95e4b1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828434437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1828434437
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.885150672
Short name T687
Test name
Test status
Simulation time 1056313437 ps
CPU time 5.35 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:45 PM PDT 24
Peak memory 237780 kb
Host smart-e6951e6a-ee3c-405f-82dd-fd8c81f25b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885150672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.885150672
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3731268401
Short name T4
Test name
Test status
Simulation time 11111270914 ps
CPU time 58.99 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:24:20 PM PDT 24
Peak memory 255176 kb
Host smart-9027d68b-710d-4e3a-b53c-767e65ed7f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731268401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3731268401
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1598576582
Short name T617
Test name
Test status
Simulation time 593208881 ps
CPU time 6.82 seconds
Started Jul 06 06:23:17 PM PDT 24
Finished Jul 06 06:23:24 PM PDT 24
Peak memory 225556 kb
Host smart-ff1ff02d-7b3a-4534-a978-812989286ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598576582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1598576582
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.230762637
Short name T547
Test name
Test status
Simulation time 1229614320 ps
CPU time 8.91 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:23:30 PM PDT 24
Peak memory 233872 kb
Host smart-ecb3386e-ed43-4e70-9c26-bb61e4916974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230762637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.230762637
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1038697632
Short name T580
Test name
Test status
Simulation time 13634506038 ps
CPU time 11.22 seconds
Started Jul 06 06:23:21 PM PDT 24
Finished Jul 06 06:23:33 PM PDT 24
Peak memory 241964 kb
Host smart-b9b0ed93-f77b-481b-ab43-cb2d5906dadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038697632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1038697632
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2649767585
Short name T903
Test name
Test status
Simulation time 3523261194 ps
CPU time 6.44 seconds
Started Jul 06 06:23:18 PM PDT 24
Finished Jul 06 06:23:24 PM PDT 24
Peak memory 241952 kb
Host smart-fea05028-aa7d-4499-aea1-bdd55d646f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649767585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2649767585
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3343736386
Short name T937
Test name
Test status
Simulation time 1170237788 ps
CPU time 10.2 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:23:32 PM PDT 24
Peak memory 219796 kb
Host smart-6b9b3131-a5ab-41ed-a809-7a6c3869e4f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3343736386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3343736386
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3001336611
Short name T160
Test name
Test status
Simulation time 9213467276 ps
CPU time 65.77 seconds
Started Jul 06 06:23:36 PM PDT 24
Finished Jul 06 06:24:42 PM PDT 24
Peak memory 254708 kb
Host smart-d42b3d9b-4344-4ffe-8319-78ea80b5a557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001336611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3001336611
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1296864585
Short name T1019
Test name
Test status
Simulation time 5260544981 ps
CPU time 18.57 seconds
Started Jul 06 06:23:18 PM PDT 24
Finished Jul 06 06:23:38 PM PDT 24
Peak memory 220668 kb
Host smart-b2b805c1-315c-4615-89a5-1c3f11a585b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296864585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1296864585
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1727025355
Short name T564
Test name
Test status
Simulation time 6196141776 ps
CPU time 2.42 seconds
Started Jul 06 06:23:18 PM PDT 24
Finished Jul 06 06:23:21 PM PDT 24
Peak memory 209108 kb
Host smart-60dcbbdd-14cb-445d-a8a9-8745a5906354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727025355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1727025355
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1144445717
Short name T960
Test name
Test status
Simulation time 54551294 ps
CPU time 1.01 seconds
Started Jul 06 06:23:17 PM PDT 24
Finished Jul 06 06:23:19 PM PDT 24
Peak memory 208000 kb
Host smart-46620da9-350d-4f8e-966a-6a96d2e34bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144445717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1144445717
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1723335776
Short name T950
Test name
Test status
Simulation time 239900631 ps
CPU time 0.84 seconds
Started Jul 06 06:23:20 PM PDT 24
Finished Jul 06 06:23:22 PM PDT 24
Peak memory 207004 kb
Host smart-e4b05e96-5ba8-47a3-b14b-90d8e0054da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723335776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1723335776
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2519961910
Short name T914
Test name
Test status
Simulation time 805781875 ps
CPU time 3.8 seconds
Started Jul 06 06:23:31 PM PDT 24
Finished Jul 06 06:23:35 PM PDT 24
Peak memory 233800 kb
Host smart-ecfa0556-3aba-4260-bd63-be0ceb2bd6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519961910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2519961910
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4279830206
Short name T997
Test name
Test status
Simulation time 21207102 ps
CPU time 0.72 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:23:43 PM PDT 24
Peak memory 206720 kb
Host smart-a86f1d76-c40a-47c0-aba3-cfb7579d3423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279830206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4279830206
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.55961430
Short name T675
Test name
Test status
Simulation time 242352666 ps
CPU time 4.12 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:23:46 PM PDT 24
Peak memory 225508 kb
Host smart-c32ddeb8-b49e-4210-b030-cabdd9ef7034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55961430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.55961430
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1654586545
Short name T761
Test name
Test status
Simulation time 213106486 ps
CPU time 0.76 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:23:43 PM PDT 24
Peak memory 207552 kb
Host smart-57c597d6-0d37-4229-ac19-b6310ac6bc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654586545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1654586545
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.538119580
Short name T701
Test name
Test status
Simulation time 92498365288 ps
CPU time 185.79 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:26:47 PM PDT 24
Peak memory 250312 kb
Host smart-d85ae7bd-127a-4be1-8bec-4598e4cdde77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538119580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.538119580
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3589773155
Short name T620
Test name
Test status
Simulation time 5643722298 ps
CPU time 75.99 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:24:56 PM PDT 24
Peak memory 257960 kb
Host smart-e7f1d36e-d394-400c-bf2f-4f75209fd1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589773155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3589773155
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1294804572
Short name T53
Test name
Test status
Simulation time 7400968545 ps
CPU time 49.95 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:24:28 PM PDT 24
Peak memory 242072 kb
Host smart-ab4f7ad4-a669-4824-a487-d3b1b54568a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294804572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1294804572
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2326037761
Short name T766
Test name
Test status
Simulation time 620974706 ps
CPU time 14.76 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:23:56 PM PDT 24
Peak memory 233816 kb
Host smart-f47ce3c0-f9bc-4ac7-a93c-fd03e6243596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326037761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2326037761
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.818093628
Short name T889
Test name
Test status
Simulation time 119030168 ps
CPU time 3.73 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:23:41 PM PDT 24
Peak memory 233780 kb
Host smart-891f2c75-cd22-4621-aa6a-989be386a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818093628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.818093628
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3655025039
Short name T884
Test name
Test status
Simulation time 991387888 ps
CPU time 13.02 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:23:55 PM PDT 24
Peak memory 225616 kb
Host smart-aa6e04cc-20a8-40a0-b51d-33d38c70e6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655025039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3655025039
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.495089405
Short name T676
Test name
Test status
Simulation time 1286795611 ps
CPU time 5.67 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:44 PM PDT 24
Peak memory 225624 kb
Host smart-9a7f432d-753f-4130-8065-9391a2708787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495089405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.495089405
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.362509965
Short name T684
Test name
Test status
Simulation time 212546016 ps
CPU time 4.77 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:23:42 PM PDT 24
Peak memory 238464 kb
Host smart-1c1bfce4-99b1-4d64-8fb9-de53034cf057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362509965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.362509965
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3906252911
Short name T289
Test name
Test status
Simulation time 167222570476 ps
CPU time 703.46 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:35:23 PM PDT 24
Peak memory 255424 kb
Host smart-ab79ea40-9368-4a74-8489-e8be26bb4aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906252911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3906252911
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2708181819
Short name T405
Test name
Test status
Simulation time 2203854653 ps
CPU time 21.19 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:24:00 PM PDT 24
Peak memory 221220 kb
Host smart-d3154087-ad3e-4e25-b86f-3bceda168aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708181819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2708181819
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2404000396
Short name T867
Test name
Test status
Simulation time 11367793175 ps
CPU time 7.66 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:47 PM PDT 24
Peak memory 217536 kb
Host smart-3ac61ddf-fa79-4493-acbb-3d466b1ba36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404000396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2404000396
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2927789474
Short name T736
Test name
Test status
Simulation time 100144107 ps
CPU time 1.52 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:23:39 PM PDT 24
Peak memory 217428 kb
Host smart-cd683b9d-4faa-465f-b910-1deb083ce764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927789474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2927789474
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1247635298
Short name T977
Test name
Test status
Simulation time 179181344 ps
CPU time 0.81 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:40 PM PDT 24
Peak memory 207020 kb
Host smart-9006d761-81b0-4c08-9711-193c8824fa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247635298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1247635298
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1376568657
Short name T446
Test name
Test status
Simulation time 17805565017 ps
CPU time 9.96 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:50 PM PDT 24
Peak memory 233904 kb
Host smart-73c28cd8-dc9b-4b54-878a-59095537d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376568657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1376568657
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4191618883
Short name T651
Test name
Test status
Simulation time 15093464 ps
CPU time 0.71 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:41 PM PDT 24
Peak memory 206344 kb
Host smart-885e71c6-8287-45c3-ab13-b4a09838682c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191618883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4191618883
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4074270818
Short name T672
Test name
Test status
Simulation time 1173072238 ps
CPU time 7.39 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:46 PM PDT 24
Peak memory 225616 kb
Host smart-0f9ae098-20c6-4ed2-b814-8b295d4c552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074270818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4074270818
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1206593726
Short name T371
Test name
Test status
Simulation time 13087412 ps
CPU time 0.78 seconds
Started Jul 06 06:23:36 PM PDT 24
Finished Jul 06 06:23:37 PM PDT 24
Peak memory 207548 kb
Host smart-848afffe-0890-4980-9fce-7433164f87f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206593726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1206593726
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4186594294
Short name T646
Test name
Test status
Simulation time 7929838090 ps
CPU time 30.06 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:24:12 PM PDT 24
Peak memory 225836 kb
Host smart-6a6ed5ba-cdd8-4e20-b2f3-d5627cc08e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186594294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4186594294
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2617666656
Short name T375
Test name
Test status
Simulation time 4877128565 ps
CPU time 61.37 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:24:40 PM PDT 24
Peak memory 254284 kb
Host smart-742eb141-adc3-48fd-9bac-b638a6fbb368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617666656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2617666656
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3879605123
Short name T297
Test name
Test status
Simulation time 936792455 ps
CPU time 8.66 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:47 PM PDT 24
Peak memory 225896 kb
Host smart-ae085063-84e1-4332-8631-79ab91d0af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879605123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3879605123
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1028387394
Short name T777
Test name
Test status
Simulation time 27700245 ps
CPU time 0.74 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:40 PM PDT 24
Peak memory 208708 kb
Host smart-83c4fc26-4f49-4478-8466-5584d923bd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028387394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1028387394
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3448049789
Short name T133
Test name
Test status
Simulation time 74873446 ps
CPU time 2.64 seconds
Started Jul 06 06:24:11 PM PDT 24
Finished Jul 06 06:24:14 PM PDT 24
Peak memory 219844 kb
Host smart-e3a157a4-d0ba-41e4-a589-ffcc41e4d00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448049789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3448049789
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2919373549
Short name T965
Test name
Test status
Simulation time 7831499572 ps
CPU time 71.1 seconds
Started Jul 06 06:23:43 PM PDT 24
Finished Jul 06 06:24:54 PM PDT 24
Peak memory 242092 kb
Host smart-f87a574e-838c-40c1-96ce-a3af9d933b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919373549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2919373549
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1534819081
Short name T913
Test name
Test status
Simulation time 2494032174 ps
CPU time 5.28 seconds
Started Jul 06 06:23:45 PM PDT 24
Finished Jul 06 06:23:50 PM PDT 24
Peak memory 233936 kb
Host smart-3b5715b5-4d5e-4c64-ad73-08944a66ceec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534819081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1534819081
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2008373592
Short name T645
Test name
Test status
Simulation time 643131009 ps
CPU time 3.66 seconds
Started Jul 06 06:23:42 PM PDT 24
Finished Jul 06 06:23:46 PM PDT 24
Peak memory 225552 kb
Host smart-eee11e33-d164-4ac8-8a4d-e83bdd3dc2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008373592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2008373592
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3058689694
Short name T629
Test name
Test status
Simulation time 410020310 ps
CPU time 4.6 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:23:47 PM PDT 24
Peak memory 220368 kb
Host smart-21aff79e-9c59-4efe-866d-e528cebfd07c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3058689694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3058689694
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3767698359
Short name T22
Test name
Test status
Simulation time 80482960460 ps
CPU time 199.67 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:26:59 PM PDT 24
Peak memory 258132 kb
Host smart-0d6772ef-290e-436b-9a57-9cb4a30bec37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767698359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3767698359
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3137715520
Short name T961
Test name
Test status
Simulation time 5889886742 ps
CPU time 29.56 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:24:07 PM PDT 24
Peak memory 217524 kb
Host smart-95c159f7-9170-4600-928b-6907cc4d8047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137715520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3137715520
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1562927911
Short name T835
Test name
Test status
Simulation time 12720444 ps
CPU time 0.72 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:41 PM PDT 24
Peak memory 206656 kb
Host smart-0aa769b7-f71d-41f0-9462-284f04910ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562927911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1562927911
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2596493496
Short name T422
Test name
Test status
Simulation time 106120036 ps
CPU time 1.15 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:23:42 PM PDT 24
Peak memory 208412 kb
Host smart-82ddc506-0edd-4f62-942f-79c9df4c419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596493496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2596493496
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3099055782
Short name T322
Test name
Test status
Simulation time 70617716 ps
CPU time 0.92 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:23:42 PM PDT 24
Peak memory 207972 kb
Host smart-7686fffd-ca5b-4946-90bc-6e77572cd12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099055782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3099055782
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1141305005
Short name T590
Test name
Test status
Simulation time 55146326 ps
CPU time 2.47 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:42 PM PDT 24
Peak memory 225316 kb
Host smart-5a1afd4c-f0c1-43a2-beec-a9570e532776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141305005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1141305005
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4067399703
Short name T967
Test name
Test status
Simulation time 41831744 ps
CPU time 0.73 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:23:41 PM PDT 24
Peak memory 206412 kb
Host smart-38a159f0-5088-44bf-b61f-e9a748446795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067399703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4067399703
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3244100411
Short name T714
Test name
Test status
Simulation time 67598044 ps
CPU time 2.78 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:43 PM PDT 24
Peak memory 233776 kb
Host smart-80c72f37-9bc9-42cc-959b-5148105edca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244100411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3244100411
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.343335661
Short name T744
Test name
Test status
Simulation time 35026200 ps
CPU time 0.73 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:40 PM PDT 24
Peak memory 207500 kb
Host smart-8c92607f-709f-4c9a-87dc-5135d20ad01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343335661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.343335661
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2453236520
Short name T44
Test name
Test status
Simulation time 20062461054 ps
CPU time 145.39 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:26:07 PM PDT 24
Peak memory 254976 kb
Host smart-863ade43-63b7-474c-abd3-d5d09070dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453236520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2453236520
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.602595038
Short name T735
Test name
Test status
Simulation time 11598236840 ps
CPU time 90.38 seconds
Started Jul 06 06:23:46 PM PDT 24
Finished Jul 06 06:25:17 PM PDT 24
Peak memory 250436 kb
Host smart-9f7e4ed6-e6e6-43e7-b721-8e91be839dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602595038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.602595038
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.579258093
Short name T793
Test name
Test status
Simulation time 4431216294 ps
CPU time 71.09 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:24:52 PM PDT 24
Peak memory 258312 kb
Host smart-f05959ed-b179-4551-a7f9-0a61337f2048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579258093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.579258093
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3336956443
Short name T504
Test name
Test status
Simulation time 1310909173 ps
CPU time 5.65 seconds
Started Jul 06 06:23:54 PM PDT 24
Finished Jul 06 06:24:00 PM PDT 24
Peak memory 238412 kb
Host smart-2fe023fc-098c-439c-aeed-533fabc0440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336956443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3336956443
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.921407472
Short name T859
Test name
Test status
Simulation time 62373119620 ps
CPU time 177.95 seconds
Started Jul 06 06:23:43 PM PDT 24
Finished Jul 06 06:26:41 PM PDT 24
Peak memory 255472 kb
Host smart-b95602ed-e5a2-467b-9148-1987f87a1144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921407472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.921407472
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1205019303
Short name T916
Test name
Test status
Simulation time 2896285769 ps
CPU time 15.85 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:55 PM PDT 24
Peak memory 225672 kb
Host smart-f5567fa4-5639-4342-b4f2-f5072896b6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205019303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1205019303
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.829556717
Short name T983
Test name
Test status
Simulation time 1538792529 ps
CPU time 11.2 seconds
Started Jul 06 06:23:36 PM PDT 24
Finished Jul 06 06:23:47 PM PDT 24
Peak memory 233816 kb
Host smart-452cbd59-96aa-4fce-adae-cff91718c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829556717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.829556717
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2907842346
Short name T208
Test name
Test status
Simulation time 2702629489 ps
CPU time 7.48 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:23:48 PM PDT 24
Peak memory 241824 kb
Host smart-343d059d-39a5-40fd-954d-4effa5e7eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907842346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2907842346
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3799968126
Short name T828
Test name
Test status
Simulation time 531236346 ps
CPU time 6.65 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:23:44 PM PDT 24
Peak memory 225536 kb
Host smart-d8fd09bc-9812-4b68-ac5e-7190e46f4473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799968126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3799968126
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1907132542
Short name T28
Test name
Test status
Simulation time 1141744765 ps
CPU time 5.01 seconds
Started Jul 06 06:23:50 PM PDT 24
Finished Jul 06 06:23:55 PM PDT 24
Peak memory 220516 kb
Host smart-aaef8c15-e190-41d4-a0f5-939cb516bc67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1907132542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1907132542
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1186208885
Short name T159
Test name
Test status
Simulation time 45375801464 ps
CPU time 463.17 seconds
Started Jul 06 06:23:40 PM PDT 24
Finished Jul 06 06:31:24 PM PDT 24
Peak memory 271884 kb
Host smart-cdf86e90-447e-4a5a-bbcc-5ab8ad504fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186208885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1186208885
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.120213967
Short name T29
Test name
Test status
Simulation time 1821248341 ps
CPU time 8.15 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:23:50 PM PDT 24
Peak memory 217376 kb
Host smart-0ba1f3fe-4658-4c8c-ae5e-6df5fd051045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120213967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.120213967
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.458544804
Short name T393
Test name
Test status
Simulation time 18792695955 ps
CPU time 15.77 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:23:53 PM PDT 24
Peak memory 217460 kb
Host smart-26c70fe7-2b3e-498b-a689-1d4ae87c04fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458544804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.458544804
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2650977289
Short name T331
Test name
Test status
Simulation time 24439432 ps
CPU time 0.75 seconds
Started Jul 06 06:23:37 PM PDT 24
Finished Jul 06 06:23:38 PM PDT 24
Peak memory 207032 kb
Host smart-e2d96a1b-b5dd-44c4-b1df-a30a2988b2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650977289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2650977289
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3974788423
Short name T399
Test name
Test status
Simulation time 37536028 ps
CPU time 0.69 seconds
Started Jul 06 06:23:38 PM PDT 24
Finished Jul 06 06:23:39 PM PDT 24
Peak memory 206600 kb
Host smart-bc64c085-d3f1-40d8-9d9a-a64055d50d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974788423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3974788423
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1241913055
Short name T708
Test name
Test status
Simulation time 47274424168 ps
CPU time 32.82 seconds
Started Jul 06 06:23:43 PM PDT 24
Finished Jul 06 06:24:16 PM PDT 24
Peak memory 250312 kb
Host smart-61d23d0d-554a-46a3-94b2-69c519bb7e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241913055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1241913055
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2166100333
Short name T716
Test name
Test status
Simulation time 49255436 ps
CPU time 0.75 seconds
Started Jul 06 06:23:50 PM PDT 24
Finished Jul 06 06:23:51 PM PDT 24
Peak memory 206388 kb
Host smart-d42135d9-73d4-4bbf-89e9-3d229e3497e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166100333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2166100333
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3202900688
Short name T376
Test name
Test status
Simulation time 707048612 ps
CPU time 9.67 seconds
Started Jul 06 06:23:50 PM PDT 24
Finished Jul 06 06:24:00 PM PDT 24
Peak memory 225596 kb
Host smart-84155591-c38d-4103-8efa-7df035601dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202900688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3202900688
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3245296871
Short name T423
Test name
Test status
Simulation time 119382489 ps
CPU time 0.77 seconds
Started Jul 06 06:23:47 PM PDT 24
Finished Jul 06 06:23:48 PM PDT 24
Peak memory 206848 kb
Host smart-4b858cce-20da-4835-980c-94917021e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245296871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3245296871
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.26284779
Short name T947
Test name
Test status
Simulation time 6525804895 ps
CPU time 36.24 seconds
Started Jul 06 06:23:50 PM PDT 24
Finished Jul 06 06:24:27 PM PDT 24
Peak memory 250340 kb
Host smart-fa28fda2-ef8b-4985-8a7c-4c4887d95229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26284779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.26284779
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3833013166
Short name T591
Test name
Test status
Simulation time 5477915201 ps
CPU time 39.16 seconds
Started Jul 06 06:23:51 PM PDT 24
Finished Jul 06 06:24:30 PM PDT 24
Peak memory 250456 kb
Host smart-09117b15-3b5b-418e-b19f-2144a365541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833013166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3833013166
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.968930553
Short name T791
Test name
Test status
Simulation time 5012040433 ps
CPU time 69.49 seconds
Started Jul 06 06:23:52 PM PDT 24
Finished Jul 06 06:25:01 PM PDT 24
Peak memory 258604 kb
Host smart-036c71b5-7aca-4803-8dbd-a3837f067d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968930553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.968930553
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2375471604
Short name T401
Test name
Test status
Simulation time 65282120 ps
CPU time 2.88 seconds
Started Jul 06 06:23:51 PM PDT 24
Finished Jul 06 06:23:54 PM PDT 24
Peak memory 233768 kb
Host smart-3721a344-1a08-484a-8782-0a72af7a7217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375471604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2375471604
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.814112607
Short name T273
Test name
Test status
Simulation time 79962421729 ps
CPU time 200.38 seconds
Started Jul 06 06:23:54 PM PDT 24
Finished Jul 06 06:27:14 PM PDT 24
Peak memory 258524 kb
Host smart-9fb70ed7-07df-4f90-baa3-3cd71ff77c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814112607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.814112607
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2274526331
Short name T682
Test name
Test status
Simulation time 5241782366 ps
CPU time 12.56 seconds
Started Jul 06 06:23:46 PM PDT 24
Finished Jul 06 06:23:59 PM PDT 24
Peak memory 233912 kb
Host smart-c312b960-3a65-42fa-85cb-895f32631e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274526331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2274526331
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3268311879
Short name T251
Test name
Test status
Simulation time 40895948855 ps
CPU time 57.62 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:24:40 PM PDT 24
Peak memory 233844 kb
Host smart-4033fdc8-1801-45ca-a339-9fe2be8881cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268311879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3268311879
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.31074867
Short name T993
Test name
Test status
Simulation time 281481639 ps
CPU time 3.36 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:23:45 PM PDT 24
Peak memory 225548 kb
Host smart-1547a1d1-d665-47cb-9eec-2f41a9dec2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31074867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.31074867
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2491800393
Short name T449
Test name
Test status
Simulation time 176050235 ps
CPU time 2.67 seconds
Started Jul 06 06:23:45 PM PDT 24
Finished Jul 06 06:23:48 PM PDT 24
Peak memory 233748 kb
Host smart-539339ff-eff6-4c0f-b21a-c034e9fe5467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491800393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2491800393
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1515647282
Short name T357
Test name
Test status
Simulation time 419379737 ps
CPU time 5.63 seconds
Started Jul 06 06:23:55 PM PDT 24
Finished Jul 06 06:24:01 PM PDT 24
Peak memory 224008 kb
Host smart-769e8a88-9bf7-4db3-95cc-e21ba4dd7586
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1515647282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1515647282
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3391357783
Short name T833
Test name
Test status
Simulation time 598304556973 ps
CPU time 852.82 seconds
Started Jul 06 06:23:53 PM PDT 24
Finished Jul 06 06:38:06 PM PDT 24
Peak memory 283192 kb
Host smart-3f5809df-a545-44b1-a247-fb2883b38955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391357783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3391357783
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1495152416
Short name T311
Test name
Test status
Simulation time 440498935 ps
CPU time 5.93 seconds
Started Jul 06 06:23:41 PM PDT 24
Finished Jul 06 06:23:48 PM PDT 24
Peak memory 217364 kb
Host smart-b5e8d05a-9111-4a0b-96d8-90272f913656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495152416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1495152416
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1302734866
Short name T551
Test name
Test status
Simulation time 947432352 ps
CPU time 3.65 seconds
Started Jul 06 06:23:44 PM PDT 24
Finished Jul 06 06:23:48 PM PDT 24
Peak memory 217356 kb
Host smart-ed1bb4e9-a245-44b3-92dd-1c0eea731930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302734866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1302734866
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2935864961
Short name T323
Test name
Test status
Simulation time 75809630 ps
CPU time 0.68 seconds
Started Jul 06 06:23:43 PM PDT 24
Finished Jul 06 06:23:44 PM PDT 24
Peak memory 206600 kb
Host smart-6613398b-6cd6-47bf-b272-31dd9e6333cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935864961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2935864961
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3990733814
Short name T356
Test name
Test status
Simulation time 19082313 ps
CPU time 0.77 seconds
Started Jul 06 06:23:39 PM PDT 24
Finished Jul 06 06:23:41 PM PDT 24
Peak memory 206584 kb
Host smart-593a0136-f59b-4416-a9cd-4c630f910e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990733814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3990733814
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2924153517
Short name T792
Test name
Test status
Simulation time 954893853 ps
CPU time 6.48 seconds
Started Jul 06 06:23:48 PM PDT 24
Finished Jul 06 06:23:55 PM PDT 24
Peak memory 233812 kb
Host smart-8b32bfc1-97e0-4b28-9e41-fd8b6f4f8dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924153517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2924153517
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.188675830
Short name T492
Test name
Test status
Simulation time 26053283 ps
CPU time 0.68 seconds
Started Jul 06 06:23:54 PM PDT 24
Finished Jul 06 06:23:55 PM PDT 24
Peak memory 206696 kb
Host smart-3e2df589-0f6f-405d-9fc1-f36f96dba137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188675830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.188675830
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2913937277
Short name T710
Test name
Test status
Simulation time 999492077 ps
CPU time 9.07 seconds
Started Jul 06 06:23:54 PM PDT 24
Finished Jul 06 06:24:03 PM PDT 24
Peak memory 225512 kb
Host smart-e946836a-f6b3-4f01-80b0-3dfeaa23b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913937277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2913937277
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4030778338
Short name T852
Test name
Test status
Simulation time 18127405 ps
CPU time 0.75 seconds
Started Jul 06 06:23:49 PM PDT 24
Finished Jul 06 06:23:50 PM PDT 24
Peak memory 206788 kb
Host smart-83a8ee4f-d299-439a-bfdf-867b304279ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030778338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4030778338
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3943886218
Short name T278
Test name
Test status
Simulation time 286889260132 ps
CPU time 317.57 seconds
Started Jul 06 06:23:58 PM PDT 24
Finished Jul 06 06:29:16 PM PDT 24
Peak memory 255180 kb
Host smart-af8178d7-94a2-4a3d-b41f-14dfda35a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943886218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3943886218
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.523759919
Short name T1005
Test name
Test status
Simulation time 1401493791 ps
CPU time 22.39 seconds
Started Jul 06 06:23:58 PM PDT 24
Finished Jul 06 06:24:21 PM PDT 24
Peak memory 218568 kb
Host smart-ea8e8b04-3864-446d-b347-b10a5d0210ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523759919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.523759919
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3375942688
Short name T306
Test name
Test status
Simulation time 3365771211 ps
CPU time 25.22 seconds
Started Jul 06 06:23:58 PM PDT 24
Finished Jul 06 06:24:23 PM PDT 24
Peak memory 225724 kb
Host smart-5965601b-1284-450e-a1e1-0c970e8a3574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375942688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3375942688
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1262621702
Short name T911
Test name
Test status
Simulation time 67874272149 ps
CPU time 192.87 seconds
Started Jul 06 06:23:53 PM PDT 24
Finished Jul 06 06:27:06 PM PDT 24
Peak memory 261188 kb
Host smart-7eba874d-e47b-443a-bd1b-c9311d6151a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262621702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1262621702
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.455375689
Short name T606
Test name
Test status
Simulation time 928725142 ps
CPU time 11.17 seconds
Started Jul 06 06:23:58 PM PDT 24
Finished Jul 06 06:24:09 PM PDT 24
Peak memory 225536 kb
Host smart-21b0a66e-22d1-447f-9f1c-a7c649cb4fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455375689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.455375689
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2091935889
Short name T955
Test name
Test status
Simulation time 3472588753 ps
CPU time 23.87 seconds
Started Jul 06 06:23:52 PM PDT 24
Finished Jul 06 06:24:16 PM PDT 24
Peak memory 241800 kb
Host smart-1c22044f-21f5-4eda-89e4-7721fce7cef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091935889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2091935889
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3752477223
Short name T953
Test name
Test status
Simulation time 1403416410 ps
CPU time 7.2 seconds
Started Jul 06 06:23:55 PM PDT 24
Finished Jul 06 06:24:02 PM PDT 24
Peak memory 233776 kb
Host smart-e52f7eb8-ecfb-4ae1-939f-139464a2482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752477223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3752477223
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2835903069
Short name T924
Test name
Test status
Simulation time 449266404 ps
CPU time 7.7 seconds
Started Jul 06 06:23:53 PM PDT 24
Finished Jul 06 06:24:01 PM PDT 24
Peak memory 233752 kb
Host smart-900b1d00-6dab-48a9-8eff-fdfc3099ef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835903069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2835903069
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1613704768
Short name T429
Test name
Test status
Simulation time 1051920970 ps
CPU time 12.42 seconds
Started Jul 06 06:23:51 PM PDT 24
Finished Jul 06 06:24:04 PM PDT 24
Peak memory 224104 kb
Host smart-06dcda03-d31e-4ca5-883c-e0c1d67211f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1613704768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1613704768
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2968618869
Short name T743
Test name
Test status
Simulation time 7992421624 ps
CPU time 6.24 seconds
Started Jul 06 06:23:56 PM PDT 24
Finished Jul 06 06:24:02 PM PDT 24
Peak memory 221252 kb
Host smart-d70464d3-e18c-4cb9-a291-acec09cda5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968618869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2968618869
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.220774942
Short name T900
Test name
Test status
Simulation time 1667561517 ps
CPU time 3.09 seconds
Started Jul 06 06:23:48 PM PDT 24
Finished Jul 06 06:23:52 PM PDT 24
Peak memory 217396 kb
Host smart-6838e557-cae6-4f96-bc32-c953c593a1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220774942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.220774942
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1376765076
Short name T883
Test name
Test status
Simulation time 125218485 ps
CPU time 1.64 seconds
Started Jul 06 06:23:53 PM PDT 24
Finished Jul 06 06:23:55 PM PDT 24
Peak memory 217312 kb
Host smart-65b68786-ec93-43f8-ba9f-d5cabdd9075f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376765076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1376765076
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2390231988
Short name T447
Test name
Test status
Simulation time 1225317206 ps
CPU time 1.08 seconds
Started Jul 06 06:23:55 PM PDT 24
Finished Jul 06 06:23:56 PM PDT 24
Peak memory 208024 kb
Host smart-d470f2ea-5ee3-4420-bd95-2d4c84ba85ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390231988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2390231988
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2806355802
Short name T650
Test name
Test status
Simulation time 258378059 ps
CPU time 2.03 seconds
Started Jul 06 06:23:57 PM PDT 24
Finished Jul 06 06:24:00 PM PDT 24
Peak memory 218172 kb
Host smart-2e7054e8-d9fe-4392-99de-d672a0783378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806355802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2806355802
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.555366933
Short name T368
Test name
Test status
Simulation time 38148554 ps
CPU time 0.75 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:24:04 PM PDT 24
Peak memory 206348 kb
Host smart-ed81964b-3d95-4cbb-b19c-2a109f5acb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555366933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.555366933
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3468570686
Short name T372
Test name
Test status
Simulation time 219704676 ps
CPU time 5.5 seconds
Started Jul 06 06:24:04 PM PDT 24
Finished Jul 06 06:24:10 PM PDT 24
Peak memory 225584 kb
Host smart-795dfa4b-7793-4cf4-abf9-8567f9647081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468570686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3468570686
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3211199296
Short name T341
Test name
Test status
Simulation time 29121167 ps
CPU time 0.76 seconds
Started Jul 06 06:23:50 PM PDT 24
Finished Jul 06 06:23:51 PM PDT 24
Peak memory 207868 kb
Host smart-b6f6af42-f83f-4fb6-8e59-a8dc81f6c750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211199296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3211199296
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1335346271
Short name T444
Test name
Test status
Simulation time 111852586505 ps
CPU time 191.56 seconds
Started Jul 06 06:23:59 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 256984 kb
Host smart-31736db2-db77-4548-8530-65ce2332cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335346271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1335346271
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2088864751
Short name T685
Test name
Test status
Simulation time 50546209727 ps
CPU time 136.67 seconds
Started Jul 06 06:23:58 PM PDT 24
Finished Jul 06 06:26:15 PM PDT 24
Peak memory 250428 kb
Host smart-d5e0b873-c4f5-400e-bc94-a25b0bf92353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088864751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2088864751
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3589516772
Short name T481
Test name
Test status
Simulation time 23946809239 ps
CPU time 111.93 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 250520 kb
Host smart-d78f9390-7067-48f5-809e-15c1e324ac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589516772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3589516772
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4258758902
Short name T794
Test name
Test status
Simulation time 4997796950 ps
CPU time 24.49 seconds
Started Jul 06 06:23:59 PM PDT 24
Finished Jul 06 06:24:23 PM PDT 24
Peak memory 242144 kb
Host smart-b271a8da-4daa-4f72-bea3-2deb89de2040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258758902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4258758902
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.842560881
Short name T421
Test name
Test status
Simulation time 31817175 ps
CPU time 0.73 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:24:04 PM PDT 24
Peak memory 216932 kb
Host smart-06dabcf5-8352-49be-ab3d-0454ae646ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842560881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.842560881
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.816981955
Short name T731
Test name
Test status
Simulation time 957752156 ps
CPU time 9.11 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:10 PM PDT 24
Peak memory 233820 kb
Host smart-17be6a5b-19e3-4064-8f1c-f5219fbdd643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816981955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.816981955
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3044017129
Short name T69
Test name
Test status
Simulation time 31783711 ps
CPU time 2.02 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:24:02 PM PDT 24
Peak memory 224628 kb
Host smart-a5a91874-f8cc-4c74-b7f0-63e7d1ad8266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044017129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3044017129
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1018190764
Short name T203
Test name
Test status
Simulation time 32543478904 ps
CPU time 14.96 seconds
Started Jul 06 06:23:59 PM PDT 24
Finished Jul 06 06:24:14 PM PDT 24
Peak memory 233868 kb
Host smart-cb5732ba-58be-45c2-98a4-996ef96a2431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018190764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1018190764
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3635672163
Short name T775
Test name
Test status
Simulation time 17036290630 ps
CPU time 14.73 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:24:15 PM PDT 24
Peak memory 233896 kb
Host smart-694c2cf2-9778-47e5-a5a1-0eeb522eee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635672163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3635672163
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2429093888
Short name T921
Test name
Test status
Simulation time 2404640833 ps
CPU time 9.33 seconds
Started Jul 06 06:23:59 PM PDT 24
Finished Jul 06 06:24:09 PM PDT 24
Peak memory 224224 kb
Host smart-6c1628cf-94a2-4cfd-8914-1ac32b0d1209
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2429093888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2429093888
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3574098940
Short name T15
Test name
Test status
Simulation time 79729048 ps
CPU time 1.18 seconds
Started Jul 06 06:24:02 PM PDT 24
Finished Jul 06 06:24:04 PM PDT 24
Peak memory 208716 kb
Host smart-97ac2b26-a255-4d1e-9ec8-37460a87d443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574098940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3574098940
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4177161927
Short name T1007
Test name
Test status
Simulation time 2177450634 ps
CPU time 12.27 seconds
Started Jul 06 06:24:04 PM PDT 24
Finished Jul 06 06:24:17 PM PDT 24
Peak memory 217512 kb
Host smart-0fa51f3e-d8f3-4fa5-a421-724cb4b1f7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177161927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4177161927
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2322368713
Short name T862
Test name
Test status
Simulation time 22144037454 ps
CPU time 17.72 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:19 PM PDT 24
Peak memory 217476 kb
Host smart-c5124ffb-7242-4e14-ad9f-d1483ed32b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322368713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2322368713
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1329345338
Short name T80
Test name
Test status
Simulation time 116689378 ps
CPU time 1.84 seconds
Started Jul 06 06:24:06 PM PDT 24
Finished Jul 06 06:24:08 PM PDT 24
Peak memory 217440 kb
Host smart-723ce5c7-baee-417b-b54b-ffa05e329430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329345338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1329345338
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1082481177
Short name T366
Test name
Test status
Simulation time 147255925 ps
CPU time 0.8 seconds
Started Jul 06 06:23:59 PM PDT 24
Finished Jul 06 06:24:00 PM PDT 24
Peak memory 206924 kb
Host smart-da6501b1-631b-4146-8fb6-2ec36add8d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082481177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1082481177
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3957626085
Short name T441
Test name
Test status
Simulation time 6251719656 ps
CPU time 7.54 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:09 PM PDT 24
Peak memory 225796 kb
Host smart-a2c44565-a834-4604-930b-44ccbff37200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957626085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3957626085
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2632017418
Short name T769
Test name
Test status
Simulation time 12246050 ps
CPU time 0.72 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:01 PM PDT 24
Peak memory 206768 kb
Host smart-68e32689-ca91-490a-82a7-95dbe7dd9f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632017418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
632017418
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2802530115
Short name T558
Test name
Test status
Simulation time 449343203 ps
CPU time 3.87 seconds
Started Jul 06 06:21:46 PM PDT 24
Finished Jul 06 06:21:51 PM PDT 24
Peak memory 233776 kb
Host smart-f6c6c43f-4f13-4a26-bf37-fd30844bd8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802530115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2802530115
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2242860919
Short name T885
Test name
Test status
Simulation time 55214297 ps
CPU time 0.82 seconds
Started Jul 06 06:21:46 PM PDT 24
Finished Jul 06 06:21:47 PM PDT 24
Peak memory 207548 kb
Host smart-71d235b2-3a71-45a6-8b96-6bb95dc6ca89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242860919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2242860919
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3780581369
Short name T135
Test name
Test status
Simulation time 21422361 ps
CPU time 0.85 seconds
Started Jul 06 06:21:53 PM PDT 24
Finished Jul 06 06:21:54 PM PDT 24
Peak memory 216944 kb
Host smart-a6a80d49-5e13-420b-b284-e389a84fe322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780581369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3780581369
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3236979425
Short name T956
Test name
Test status
Simulation time 43016823518 ps
CPU time 43.89 seconds
Started Jul 06 06:21:54 PM PDT 24
Finished Jul 06 06:22:38 PM PDT 24
Peak memory 242156 kb
Host smart-cd1ca77d-24e0-4bfc-a0f3-47430a96ad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236979425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3236979425
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3001903888
Short name T59
Test name
Test status
Simulation time 6064382519 ps
CPU time 91.08 seconds
Started Jul 06 06:21:48 PM PDT 24
Finished Jul 06 06:23:20 PM PDT 24
Peak memory 267440 kb
Host smart-ee584809-a3ed-4f06-aed1-f2426b7ac006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001903888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3001903888
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.292065222
Short name T871
Test name
Test status
Simulation time 69505884 ps
CPU time 3.17 seconds
Started Jul 06 06:21:45 PM PDT 24
Finished Jul 06 06:21:48 PM PDT 24
Peak memory 233760 kb
Host smart-42878287-f458-4dca-8db2-2141fb522a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292065222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.292065222
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3013211648
Short name T463
Test name
Test status
Simulation time 5486058745 ps
CPU time 71.39 seconds
Started Jul 06 06:21:54 PM PDT 24
Finished Jul 06 06:23:06 PM PDT 24
Peak memory 250628 kb
Host smart-b0695ece-236f-4b4e-9656-e4d8b08fad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013211648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3013211648
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3096679773
Short name T327
Test name
Test status
Simulation time 49128232 ps
CPU time 2.3 seconds
Started Jul 06 06:21:48 PM PDT 24
Finished Jul 06 06:21:51 PM PDT 24
Peak memory 233516 kb
Host smart-9d6efd3f-b07a-499b-a7ff-9c66f4911432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096679773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3096679773
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2351612310
Short name T809
Test name
Test status
Simulation time 1002354646 ps
CPU time 14.08 seconds
Started Jul 06 06:21:47 PM PDT 24
Finished Jul 06 06:22:02 PM PDT 24
Peak memory 233740 kb
Host smart-a21829af-5f5a-4fc7-a710-6a5998b8fe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351612310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2351612310
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2581268105
Short name T806
Test name
Test status
Simulation time 65142736 ps
CPU time 1.09 seconds
Started Jul 06 06:21:48 PM PDT 24
Finished Jul 06 06:21:50 PM PDT 24
Peak memory 217712 kb
Host smart-1d4296a1-0510-4015-8ffb-9c90b593a86e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581268105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2581268105
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1489951111
Short name T219
Test name
Test status
Simulation time 226107880 ps
CPU time 4.99 seconds
Started Jul 06 06:21:48 PM PDT 24
Finished Jul 06 06:21:54 PM PDT 24
Peak memory 233760 kb
Host smart-ef97082e-b3df-4413-a155-2743f6a8fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489951111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1489951111
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.705414993
Short name T243
Test name
Test status
Simulation time 23360369586 ps
CPU time 19.24 seconds
Started Jul 06 06:21:54 PM PDT 24
Finished Jul 06 06:22:13 PM PDT 24
Peak memory 238396 kb
Host smart-8d907acc-c5c2-4185-8715-ff93cb9d10e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705414993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.705414993
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3558781075
Short name T149
Test name
Test status
Simulation time 4892713962 ps
CPU time 14.75 seconds
Started Jul 06 06:21:51 PM PDT 24
Finished Jul 06 06:22:06 PM PDT 24
Peak memory 223396 kb
Host smart-f6bb652b-45c7-44ce-b0f2-140a9353f2ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3558781075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3558781075
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.551333303
Short name T76
Test name
Test status
Simulation time 30467602 ps
CPU time 0.94 seconds
Started Jul 06 06:21:52 PM PDT 24
Finished Jul 06 06:21:54 PM PDT 24
Peak memory 236396 kb
Host smart-57880e4a-5540-4ad1-8336-29c0e2f7f2ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551333303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.551333303
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3459355820
Short name T162
Test name
Test status
Simulation time 100938885737 ps
CPU time 994.34 seconds
Started Jul 06 06:21:52 PM PDT 24
Finished Jul 06 06:38:27 PM PDT 24
Peak memory 266012 kb
Host smart-c6e137ea-7a59-4eae-a8d7-33a833ce7b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459355820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3459355820
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2695708772
Short name T320
Test name
Test status
Simulation time 2282575704 ps
CPU time 22.66 seconds
Started Jul 06 06:21:51 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 217540 kb
Host smart-b9de0858-c4e4-4c20-b2ff-ae3304f03422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695708772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2695708772
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2348575270
Short name T595
Test name
Test status
Simulation time 631933182 ps
CPU time 5.27 seconds
Started Jul 06 06:21:48 PM PDT 24
Finished Jul 06 06:21:54 PM PDT 24
Peak memory 217308 kb
Host smart-0952a4d3-416f-4c3f-847b-8f69f2c5dbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348575270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2348575270
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1265609206
Short name T898
Test name
Test status
Simulation time 19457738 ps
CPU time 0.74 seconds
Started Jul 06 06:21:45 PM PDT 24
Finished Jul 06 06:21:46 PM PDT 24
Peak memory 207012 kb
Host smart-446c12d8-00e5-4e8e-a6bc-434f015ccd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265609206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1265609206
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.121445906
Short name T509
Test name
Test status
Simulation time 74178531 ps
CPU time 0.79 seconds
Started Jul 06 06:21:45 PM PDT 24
Finished Jul 06 06:21:46 PM PDT 24
Peak memory 206916 kb
Host smart-82f5059c-9f80-4232-a40b-db6bb51d9593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121445906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.121445906
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2542859745
Short name T191
Test name
Test status
Simulation time 14064278352 ps
CPU time 21.36 seconds
Started Jul 06 06:21:54 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 233932 kb
Host smart-74d5984e-06e0-4c91-b53c-b533c23bafd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542859745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2542859745
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3092897589
Short name T737
Test name
Test status
Simulation time 52444256 ps
CPU time 0.75 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:02 PM PDT 24
Peak memory 205664 kb
Host smart-131fee75-dfcc-4a73-9340-c24da0b8385c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092897589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3092897589
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.108622870
Short name T677
Test name
Test status
Simulation time 209195246 ps
CPU time 3.29 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:24:04 PM PDT 24
Peak memory 225584 kb
Host smart-7fe73a4b-16b5-4317-b7f6-d5783f2554aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108622870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.108622870
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1094766049
Short name T754
Test name
Test status
Simulation time 17888865 ps
CPU time 0.82 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:02 PM PDT 24
Peak memory 207880 kb
Host smart-7323087c-e5e0-4feb-8439-8e41c5e07520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094766049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1094766049
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1496574645
Short name T168
Test name
Test status
Simulation time 6933389190 ps
CPU time 48.09 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:49 PM PDT 24
Peak memory 258544 kb
Host smart-43c0c373-7df1-4b52-932c-6bf8ff1344eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496574645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1496574645
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1825539563
Short name T542
Test name
Test status
Simulation time 19898381942 ps
CPU time 97.25 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:25:38 PM PDT 24
Peak memory 239716 kb
Host smart-43e5d629-f434-431b-9c9e-7b65af5d3520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825539563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1825539563
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.330353490
Short name T951
Test name
Test status
Simulation time 156769413 ps
CPU time 4.96 seconds
Started Jul 06 06:23:58 PM PDT 24
Finished Jul 06 06:24:03 PM PDT 24
Peak memory 225568 kb
Host smart-504b09b2-bd73-4ff3-9a3e-8c16a48902b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330353490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.330353490
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3766096969
Short name T632
Test name
Test status
Simulation time 1204372815 ps
CPU time 13.72 seconds
Started Jul 06 06:24:06 PM PDT 24
Finished Jul 06 06:24:19 PM PDT 24
Peak memory 250180 kb
Host smart-5c459f1b-434d-42a7-8d4f-827f791a8ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766096969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3766096969
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2505455358
Short name T755
Test name
Test status
Simulation time 1329878444 ps
CPU time 13.96 seconds
Started Jul 06 06:23:59 PM PDT 24
Finished Jul 06 06:24:13 PM PDT 24
Peak memory 233820 kb
Host smart-a1a1f066-cc29-496f-98f6-0905be3f6387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505455358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2505455358
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3473348356
Short name T68
Test name
Test status
Simulation time 6676446360 ps
CPU time 9.36 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:24:09 PM PDT 24
Peak memory 225704 kb
Host smart-4815161d-c96e-44f3-9f2d-d8d876e6f60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473348356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3473348356
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3323419711
Short name T653
Test name
Test status
Simulation time 6865914744 ps
CPU time 13.6 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:24:14 PM PDT 24
Peak memory 241984 kb
Host smart-214026fa-515f-4133-b4ca-22847380a59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323419711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3323419711
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3199347438
Short name T386
Test name
Test status
Simulation time 9537458152 ps
CPU time 24.25 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:26 PM PDT 24
Peak memory 233960 kb
Host smart-c40b09c5-4cd6-4411-9287-e17a3f434734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199347438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3199347438
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.676369766
Short name T881
Test name
Test status
Simulation time 1018715715 ps
CPU time 9.38 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:24:10 PM PDT 24
Peak memory 220372 kb
Host smart-f72eaa58-e9be-400b-902e-c733e71ba839
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=676369766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.676369766
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.792047560
Short name T479
Test name
Test status
Simulation time 33126560064 ps
CPU time 17.08 seconds
Started Jul 06 06:23:58 PM PDT 24
Finished Jul 06 06:24:15 PM PDT 24
Peak memory 217492 kb
Host smart-04145d0f-1143-45a1-88fd-45c22a2d06ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792047560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.792047560
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1786388615
Short name T819
Test name
Test status
Simulation time 22573739853 ps
CPU time 7.35 seconds
Started Jul 06 06:24:06 PM PDT 24
Finished Jul 06 06:24:14 PM PDT 24
Peak memory 217572 kb
Host smart-a344804e-029e-4e97-88ec-f733baac1331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786388615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1786388615
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1362714619
Short name T570
Test name
Test status
Simulation time 30656206 ps
CPU time 0.7 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:02 PM PDT 24
Peak memory 206416 kb
Host smart-dd3cc427-7b76-43fd-8cf9-8c1ea922fcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362714619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1362714619
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.398034939
Short name T1012
Test name
Test status
Simulation time 30564065 ps
CPU time 0.79 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:24:01 PM PDT 24
Peak memory 207000 kb
Host smart-90118f3a-a5ed-4fb3-97fc-5db4d385f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398034939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.398034939
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.377404336
Short name T874
Test name
Test status
Simulation time 34737050 ps
CPU time 2.31 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:04 PM PDT 24
Peak memory 233852 kb
Host smart-3174520c-ed8b-4acd-a04b-bb14fec6f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377404336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.377404336
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.662901953
Short name T619
Test name
Test status
Simulation time 43119091 ps
CPU time 0.74 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:24:04 PM PDT 24
Peak memory 205816 kb
Host smart-7feb4732-2dec-4001-be93-9e286b6d65b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662901953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.662901953
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3587928297
Short name T783
Test name
Test status
Simulation time 68211895 ps
CPU time 2.65 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:24:06 PM PDT 24
Peak memory 233724 kb
Host smart-ee3a9c60-0653-4e0e-baad-a31c647822cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587928297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3587928297
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.777857480
Short name T694
Test name
Test status
Simulation time 44277426 ps
CPU time 0.78 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:02 PM PDT 24
Peak memory 207576 kb
Host smart-dc36a2ef-d25e-4bd5-b3a0-d1e5cc8df26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777857480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.777857480
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2730928276
Short name T280
Test name
Test status
Simulation time 4237116895 ps
CPU time 76.75 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:25:21 PM PDT 24
Peak memory 265780 kb
Host smart-6b6928c8-6d50-4be6-b615-7cb0291843fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730928276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2730928276
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2094748867
Short name T285
Test name
Test status
Simulation time 165738791314 ps
CPU time 269.54 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:28:33 PM PDT 24
Peak memory 255564 kb
Host smart-cdcf5b29-d39b-4cec-99bc-fd320a7ff428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094748867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2094748867
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.205873645
Short name T751
Test name
Test status
Simulation time 14618435281 ps
CPU time 122.62 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:26:06 PM PDT 24
Peak memory 241520 kb
Host smart-a109f5f3-e240-4090-a3f2-7a1490774d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205873645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.205873645
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.743059630
Short name T593
Test name
Test status
Simulation time 2120799387 ps
CPU time 9.43 seconds
Started Jul 06 06:24:04 PM PDT 24
Finished Jul 06 06:24:14 PM PDT 24
Peak memory 225600 kb
Host smart-b724b028-4d85-4dc8-abb1-22ea032ee196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743059630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.743059630
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1719298901
Short name T275
Test name
Test status
Simulation time 6907217559 ps
CPU time 36.09 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:24:40 PM PDT 24
Peak memory 251764 kb
Host smart-34e73a8f-2ee7-421f-b8f3-bf664e498610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719298901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1719298901
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.662488624
Short name T476
Test name
Test status
Simulation time 6764046877 ps
CPU time 26.25 seconds
Started Jul 06 06:24:02 PM PDT 24
Finished Jul 06 06:24:29 PM PDT 24
Peak memory 233884 kb
Host smart-fa482b91-7e5b-47f0-8559-f37ceea40dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662488624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.662488624
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1685047828
Short name T603
Test name
Test status
Simulation time 672901397 ps
CPU time 6.02 seconds
Started Jul 06 06:24:02 PM PDT 24
Finished Jul 06 06:24:09 PM PDT 24
Peak memory 241184 kb
Host smart-abdeb4b6-a27b-42ba-93e4-21b942ed29c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685047828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1685047828
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2227192520
Short name T818
Test name
Test status
Simulation time 451837137 ps
CPU time 3.01 seconds
Started Jul 06 06:24:02 PM PDT 24
Finished Jul 06 06:24:05 PM PDT 24
Peak memory 233756 kb
Host smart-304d0e10-8440-4409-9264-0114908d353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227192520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2227192520
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2220724134
Short name T514
Test name
Test status
Simulation time 484598634 ps
CPU time 3.02 seconds
Started Jul 06 06:23:59 PM PDT 24
Finished Jul 06 06:24:02 PM PDT 24
Peak memory 225604 kb
Host smart-6484a277-ebdc-4d33-a307-904486c1517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220724134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2220724134
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3324862548
Short name T143
Test name
Test status
Simulation time 1564150303 ps
CPU time 7.03 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:24:10 PM PDT 24
Peak memory 222864 kb
Host smart-8fb2da3d-a8fc-4081-8b46-9822630581c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3324862548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3324862548
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3025096916
Short name T308
Test name
Test status
Simulation time 1423873482 ps
CPU time 10.82 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:12 PM PDT 24
Peak memory 217464 kb
Host smart-08bb07b0-4275-4a15-9f24-c8e15b5ab86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025096916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3025096916
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2338230877
Short name T522
Test name
Test status
Simulation time 911701849 ps
CPU time 4.01 seconds
Started Jul 06 06:24:00 PM PDT 24
Finished Jul 06 06:24:04 PM PDT 24
Peak memory 217308 kb
Host smart-c49c9be5-91d6-41e0-b9b0-fe345dd4a754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338230877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2338230877
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2560249320
Short name T316
Test name
Test status
Simulation time 48149260 ps
CPU time 1.3 seconds
Started Jul 06 06:23:59 PM PDT 24
Finished Jul 06 06:24:00 PM PDT 24
Peak memory 209192 kb
Host smart-5b656c97-4b94-4841-8ed0-9f6486e6201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560249320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2560249320
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1786230224
Short name T134
Test name
Test status
Simulation time 62054033 ps
CPU time 0.89 seconds
Started Jul 06 06:24:04 PM PDT 24
Finished Jul 06 06:24:05 PM PDT 24
Peak memory 207004 kb
Host smart-fcb0167c-a2f4-475e-b76d-f2dc7cb3d1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786230224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1786230224
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.29225605
Short name T748
Test name
Test status
Simulation time 455133637 ps
CPU time 3.72 seconds
Started Jul 06 06:24:02 PM PDT 24
Finished Jul 06 06:24:06 PM PDT 24
Peak memory 225564 kb
Host smart-b426853b-10e8-418b-a2b2-59cff1802d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29225605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.29225605
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2203143275
Short name T478
Test name
Test status
Simulation time 80737021 ps
CPU time 0.7 seconds
Started Jul 06 06:24:14 PM PDT 24
Finished Jul 06 06:24:15 PM PDT 24
Peak memory 206404 kb
Host smart-24a8246a-a19f-4700-a90d-5f4c30c4a1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203143275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2203143275
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.529633372
Short name T763
Test name
Test status
Simulation time 158901752 ps
CPU time 2.97 seconds
Started Jul 06 06:24:10 PM PDT 24
Finished Jul 06 06:24:14 PM PDT 24
Peak memory 233720 kb
Host smart-c4bee50f-6b37-4bc0-8067-2f10269c10da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529633372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.529633372
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3973115047
Short name T822
Test name
Test status
Simulation time 35980167 ps
CPU time 0.77 seconds
Started Jul 06 06:24:05 PM PDT 24
Finished Jul 06 06:24:06 PM PDT 24
Peak memory 206844 kb
Host smart-a4225d1e-bdac-4dfd-8e60-99234d2d4134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973115047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3973115047
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3839969364
Short name T876
Test name
Test status
Simulation time 4849213530 ps
CPU time 53.52 seconds
Started Jul 06 06:24:17 PM PDT 24
Finished Jul 06 06:25:11 PM PDT 24
Peak memory 251884 kb
Host smart-eb00689d-a375-4efc-ab7d-6689e2caab69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839969364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3839969364
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4129359170
Short name T138
Test name
Test status
Simulation time 159080044698 ps
CPU time 177.99 seconds
Started Jul 06 06:24:15 PM PDT 24
Finished Jul 06 06:27:13 PM PDT 24
Peak memory 253828 kb
Host smart-3ed839dc-8687-4294-bfc0-674246a3332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129359170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4129359170
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1808972133
Short name T583
Test name
Test status
Simulation time 421156008 ps
CPU time 9.69 seconds
Started Jul 06 06:24:09 PM PDT 24
Finished Jul 06 06:24:19 PM PDT 24
Peak memory 233832 kb
Host smart-e101d915-65ac-4f1d-99ac-fbf3764c8e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808972133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1808972133
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1491131791
Short name T229
Test name
Test status
Simulation time 8451995883 ps
CPU time 59.92 seconds
Started Jul 06 06:24:16 PM PDT 24
Finished Jul 06 06:25:16 PM PDT 24
Peak memory 266704 kb
Host smart-6a9bbb75-b883-418e-b1eb-9596460a85f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491131791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1491131791
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3752330019
Short name T458
Test name
Test status
Simulation time 1155450397 ps
CPU time 13.11 seconds
Started Jul 06 06:24:08 PM PDT 24
Finished Jul 06 06:24:21 PM PDT 24
Peak memory 225632 kb
Host smart-679a4186-4b36-4da0-ab7a-2bc7beab6c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752330019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3752330019
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3802961769
Short name T920
Test name
Test status
Simulation time 9367898638 ps
CPU time 85.86 seconds
Started Jul 06 06:24:09 PM PDT 24
Finished Jul 06 06:25:35 PM PDT 24
Peak memory 242088 kb
Host smart-4f34cbae-e21e-4a0b-9003-195e798354a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802961769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3802961769
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.874828147
Short name T944
Test name
Test status
Simulation time 609389041 ps
CPU time 7.69 seconds
Started Jul 06 06:24:08 PM PDT 24
Finished Jul 06 06:24:16 PM PDT 24
Peak memory 233704 kb
Host smart-a9af83c1-6896-4245-8ace-79253af4672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874828147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.874828147
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1677964657
Short name T573
Test name
Test status
Simulation time 563762855 ps
CPU time 5.93 seconds
Started Jul 06 06:24:10 PM PDT 24
Finished Jul 06 06:24:16 PM PDT 24
Peak memory 233804 kb
Host smart-268f42b6-7bb6-4aa7-8859-5bd0facb7503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677964657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1677964657
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1639598189
Short name T1008
Test name
Test status
Simulation time 5834039411 ps
CPU time 7.56 seconds
Started Jul 06 06:24:13 PM PDT 24
Finished Jul 06 06:24:21 PM PDT 24
Peak memory 223084 kb
Host smart-38fa33b4-d645-4e1e-bc40-60b91ce74ce2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1639598189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1639598189
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1743147705
Short name T523
Test name
Test status
Simulation time 310828937 ps
CPU time 1.01 seconds
Started Jul 06 06:24:15 PM PDT 24
Finished Jul 06 06:24:17 PM PDT 24
Peak memory 208732 kb
Host smart-841cea3b-7300-436a-b936-59ee4a6736ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743147705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1743147705
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1761972581
Short name T627
Test name
Test status
Simulation time 1303825449 ps
CPU time 9.06 seconds
Started Jul 06 06:24:04 PM PDT 24
Finished Jul 06 06:24:13 PM PDT 24
Peak memory 217400 kb
Host smart-eca80400-0fec-49e6-aabd-651503b029b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761972581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1761972581
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1826004918
Short name T533
Test name
Test status
Simulation time 2335440587 ps
CPU time 3.79 seconds
Started Jul 06 06:24:01 PM PDT 24
Finished Jul 06 06:24:05 PM PDT 24
Peak memory 217500 kb
Host smart-1180454a-5c7b-4c3d-a384-934a05102c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826004918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1826004918
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3053206513
Short name T638
Test name
Test status
Simulation time 369474057 ps
CPU time 2.17 seconds
Started Jul 06 06:24:07 PM PDT 24
Finished Jul 06 06:24:09 PM PDT 24
Peak memory 217352 kb
Host smart-f00fc910-3d03-4ac4-9b9d-40a28e11e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053206513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3053206513
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1408142886
Short name T637
Test name
Test status
Simulation time 108031725 ps
CPU time 0.98 seconds
Started Jul 06 06:24:03 PM PDT 24
Finished Jul 06 06:24:05 PM PDT 24
Peak memory 206996 kb
Host smart-5c79b8a1-656b-46f6-9597-3729d4e0831b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408142886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1408142886
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3958945632
Short name T802
Test name
Test status
Simulation time 2508805099 ps
CPU time 10.28 seconds
Started Jul 06 06:24:10 PM PDT 24
Finished Jul 06 06:24:20 PM PDT 24
Peak memory 241840 kb
Host smart-0c1bd101-0bcd-46b7-8aed-7831fe82f555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958945632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3958945632
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.657884149
Short name T589
Test name
Test status
Simulation time 30975057 ps
CPU time 0.77 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:37 PM PDT 24
Peak memory 206340 kb
Host smart-d9122c11-0fad-41b7-bbb0-636e7482eba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657884149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.657884149
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.291111671
Short name T865
Test name
Test status
Simulation time 524773975 ps
CPU time 5.3 seconds
Started Jul 06 06:24:15 PM PDT 24
Finished Jul 06 06:24:21 PM PDT 24
Peak memory 233656 kb
Host smart-11da82a7-5d9f-4db8-8cab-3c6610df067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291111671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.291111671
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.249756850
Short name T622
Test name
Test status
Simulation time 32613412 ps
CPU time 0.78 seconds
Started Jul 06 06:24:13 PM PDT 24
Finished Jul 06 06:24:14 PM PDT 24
Peak memory 207856 kb
Host smart-c64ed9d8-da77-4a31-a96a-967e07894f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249756850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.249756850
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2001271307
Short name T958
Test name
Test status
Simulation time 26194819790 ps
CPU time 133.44 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:26:50 PM PDT 24
Peak memory 255436 kb
Host smart-73601573-971c-4cfb-a143-db66ac1120f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001271307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2001271307
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3071786634
Short name T892
Test name
Test status
Simulation time 33904522625 ps
CPU time 343.22 seconds
Started Jul 06 06:24:17 PM PDT 24
Finished Jul 06 06:30:00 PM PDT 24
Peak memory 266832 kb
Host smart-a008d83f-5d68-44aa-bf02-8ad0949c0477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071786634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3071786634
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.977141293
Short name T837
Test name
Test status
Simulation time 10843733188 ps
CPU time 44.46 seconds
Started Jul 06 06:24:17 PM PDT 24
Finished Jul 06 06:25:02 PM PDT 24
Peak memory 250404 kb
Host smart-e74f7572-ea82-4c98-8465-07b3b680400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977141293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.977141293
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3114894644
Short name T864
Test name
Test status
Simulation time 4910023520 ps
CPU time 37.93 seconds
Started Jul 06 06:24:14 PM PDT 24
Finished Jul 06 06:24:52 PM PDT 24
Peak memory 225736 kb
Host smart-0a98bb82-6fa4-4552-8326-680392de0c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114894644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3114894644
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.927008005
Short name T928
Test name
Test status
Simulation time 7639926475 ps
CPU time 72.82 seconds
Started Jul 06 06:24:19 PM PDT 24
Finished Jul 06 06:25:32 PM PDT 24
Peak memory 250272 kb
Host smart-a00fda73-606f-41dd-9772-f42125a59cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927008005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.927008005
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.265431525
Short name T451
Test name
Test status
Simulation time 8244761624 ps
CPU time 27.18 seconds
Started Jul 06 06:24:16 PM PDT 24
Finished Jul 06 06:24:44 PM PDT 24
Peak memory 225724 kb
Host smart-83500c5c-25ea-44fa-92de-d8ee6c1e1345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265431525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.265431525
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2984300941
Short name T82
Test name
Test status
Simulation time 2455020603 ps
CPU time 32.77 seconds
Started Jul 06 06:24:16 PM PDT 24
Finished Jul 06 06:24:49 PM PDT 24
Peak memory 233924 kb
Host smart-c74d55a5-d1ba-413a-b5b3-040dd7b55c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984300941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2984300941
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.628789695
Short name T412
Test name
Test status
Simulation time 1843383184 ps
CPU time 3.16 seconds
Started Jul 06 06:24:14 PM PDT 24
Finished Jul 06 06:24:18 PM PDT 24
Peak memory 225520 kb
Host smart-33c66ab9-08b2-4512-b595-de99e4a50dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628789695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.628789695
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.253653461
Short name T579
Test name
Test status
Simulation time 2143476603 ps
CPU time 10.54 seconds
Started Jul 06 06:24:13 PM PDT 24
Finished Jul 06 06:24:24 PM PDT 24
Peak memory 225636 kb
Host smart-0560d864-7d8c-4283-b613-49f2e8cb0a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253653461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.253653461
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1264600544
Short name T511
Test name
Test status
Simulation time 121505539 ps
CPU time 4.11 seconds
Started Jul 06 06:24:16 PM PDT 24
Finished Jul 06 06:24:21 PM PDT 24
Peak memory 224076 kb
Host smart-30f05d83-ec2b-42b1-a27f-1e9ca6b5a47f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1264600544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1264600544
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3753720887
Short name T161
Test name
Test status
Simulation time 382330303 ps
CPU time 1.02 seconds
Started Jul 06 06:24:20 PM PDT 24
Finished Jul 06 06:24:21 PM PDT 24
Peak memory 207808 kb
Host smart-17967e69-b810-4b31-92fd-c29cf310316f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753720887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3753720887
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1613393474
Short name T780
Test name
Test status
Simulation time 1537037173 ps
CPU time 3.36 seconds
Started Jul 06 06:24:14 PM PDT 24
Finished Jul 06 06:24:17 PM PDT 24
Peak memory 217420 kb
Host smart-b769c653-500c-400a-8525-6c32ed5f3255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613393474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1613393474
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3589305998
Short name T815
Test name
Test status
Simulation time 2086742828 ps
CPU time 7.55 seconds
Started Jul 06 06:24:15 PM PDT 24
Finished Jul 06 06:24:22 PM PDT 24
Peak memory 217364 kb
Host smart-81f23720-45f4-4108-bcc7-80236121d0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589305998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3589305998
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.209815588
Short name T404
Test name
Test status
Simulation time 818387155 ps
CPU time 1.78 seconds
Started Jul 06 06:24:14 PM PDT 24
Finished Jul 06 06:24:16 PM PDT 24
Peak memory 217280 kb
Host smart-f2862ce5-6f81-4695-9d8c-cf089fc2eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209815588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.209815588
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2613964024
Short name T1027
Test name
Test status
Simulation time 56251067 ps
CPU time 0.82 seconds
Started Jul 06 06:24:13 PM PDT 24
Finished Jul 06 06:24:15 PM PDT 24
Peak memory 206996 kb
Host smart-cc6ab4c7-7c76-4e3a-9de1-ddba1d3da621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613964024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2613964024
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3402537385
Short name T50
Test name
Test status
Simulation time 571850111 ps
CPU time 3.29 seconds
Started Jul 06 06:24:15 PM PDT 24
Finished Jul 06 06:24:18 PM PDT 24
Peak memory 225552 kb
Host smart-8ffc60e5-9d81-4dfa-b035-cb919f7865c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402537385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3402537385
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3195245052
Short name T445
Test name
Test status
Simulation time 15358238 ps
CPU time 0.76 seconds
Started Jul 06 06:24:18 PM PDT 24
Finished Jul 06 06:24:19 PM PDT 24
Peak memory 206356 kb
Host smart-fdb2df04-e2c2-4c90-b7f3-f1f7d9d5afdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195245052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3195245052
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3812621040
Short name T893
Test name
Test status
Simulation time 1378195760 ps
CPU time 8.75 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:45 PM PDT 24
Peak memory 233756 kb
Host smart-7548a2cc-0322-473f-8414-db4a2b1e5216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812621040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3812621040
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1428015951
Short name T407
Test name
Test status
Simulation time 21366175 ps
CPU time 0.74 seconds
Started Jul 06 06:24:18 PM PDT 24
Finished Jul 06 06:24:19 PM PDT 24
Peak memory 207832 kb
Host smart-0b20f6fd-114a-47c1-aaf9-d682d6a999f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428015951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1428015951
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1375952454
Short name T848
Test name
Test status
Simulation time 16042523646 ps
CPU time 105.46 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:26:21 PM PDT 24
Peak memory 252336 kb
Host smart-76005ff7-254b-40dd-8c12-61be49d02e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375952454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1375952454
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1196793862
Short name T166
Test name
Test status
Simulation time 17441919728 ps
CPU time 74.24 seconds
Started Jul 06 06:24:19 PM PDT 24
Finished Jul 06 06:25:33 PM PDT 24
Peak memory 257364 kb
Host smart-edfd1c9e-221e-44b0-b65e-dda61465d493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196793862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1196793862
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3249979935
Short name T572
Test name
Test status
Simulation time 56764318950 ps
CPU time 112.72 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:26:29 PM PDT 24
Peak memory 250392 kb
Host smart-a23a27fd-8243-4684-9832-4361ef306f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249979935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3249979935
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2669027221
Short name T882
Test name
Test status
Simulation time 5962137930 ps
CPU time 13.51 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:50 PM PDT 24
Peak memory 242060 kb
Host smart-470536df-916c-4848-a132-62109c434d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669027221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2669027221
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2077301270
Short name T915
Test name
Test status
Simulation time 3996753064 ps
CPU time 35.52 seconds
Started Jul 06 06:24:16 PM PDT 24
Finished Jul 06 06:24:52 PM PDT 24
Peak memory 239296 kb
Host smart-e48d458a-1ebb-455b-ad0b-8be2272fdd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077301270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2077301270
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3778194055
Short name T521
Test name
Test status
Simulation time 605960219 ps
CPU time 3.58 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:40 PM PDT 24
Peak memory 233604 kb
Host smart-3db157f7-4bea-4f66-a99c-6c81d642cee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778194055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3778194055
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.539563146
Short name T630
Test name
Test status
Simulation time 27045390736 ps
CPU time 42.9 seconds
Started Jul 06 06:24:18 PM PDT 24
Finished Jul 06 06:25:01 PM PDT 24
Peak memory 235692 kb
Host smart-4890fcec-e1d1-4d71-8b46-226e783dd053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539563146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.539563146
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4197494113
Short name T554
Test name
Test status
Simulation time 16430257800 ps
CPU time 11.9 seconds
Started Jul 06 06:24:18 PM PDT 24
Finished Jul 06 06:24:30 PM PDT 24
Peak memory 225568 kb
Host smart-3b844692-5c76-47cd-85b4-6164a2bcf1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197494113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4197494113
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3201303994
Short name T64
Test name
Test status
Simulation time 51486187673 ps
CPU time 14.12 seconds
Started Jul 06 06:24:17 PM PDT 24
Finished Jul 06 06:24:31 PM PDT 24
Peak memory 233900 kb
Host smart-e4f24bf6-89e1-4dad-b5a8-5663c9db0a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201303994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3201303994
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.231101964
Short name T663
Test name
Test status
Simulation time 1328861438 ps
CPU time 14.56 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:51 PM PDT 24
Peak memory 220204 kb
Host smart-24e3a42e-7429-43fd-8e2f-958b802fee3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=231101964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.231101964
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.609949285
Short name T194
Test name
Test status
Simulation time 19909460080 ps
CPU time 228.25 seconds
Started Jul 06 06:24:18 PM PDT 24
Finished Jul 06 06:28:07 PM PDT 24
Peak memory 266764 kb
Host smart-7dcaa11d-abc9-43d9-9f70-5870bf500b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609949285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.609949285
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.424017001
Short name T540
Test name
Test status
Simulation time 3569858516 ps
CPU time 23.94 seconds
Started Jul 06 06:24:20 PM PDT 24
Finished Jul 06 06:24:44 PM PDT 24
Peak memory 217504 kb
Host smart-33c47906-ae21-41ef-a5d2-c4836d10068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424017001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.424017001
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.927774125
Short name T459
Test name
Test status
Simulation time 10766756 ps
CPU time 0.68 seconds
Started Jul 06 06:24:17 PM PDT 24
Finished Jul 06 06:24:17 PM PDT 24
Peak memory 206660 kb
Host smart-ed7fb063-e48f-46f8-9109-709d1e9a62d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927774125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.927774125
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4234298867
Short name T587
Test name
Test status
Simulation time 25392146 ps
CPU time 1.07 seconds
Started Jul 06 06:24:19 PM PDT 24
Finished Jul 06 06:24:20 PM PDT 24
Peak memory 208984 kb
Host smart-cf01850a-344f-4936-ae81-876995ac29cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234298867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4234298867
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2374397456
Short name T847
Test name
Test status
Simulation time 34146586 ps
CPU time 0.75 seconds
Started Jul 06 06:24:18 PM PDT 24
Finished Jul 06 06:24:19 PM PDT 24
Peak memory 206952 kb
Host smart-94fde733-f806-4c17-8ac7-88210942b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374397456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2374397456
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3575329726
Short name T192
Test name
Test status
Simulation time 22094157259 ps
CPU time 19.86 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:56 PM PDT 24
Peak memory 238112 kb
Host smart-320e53df-a5e4-41ce-841b-2988f9f22478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575329726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3575329726
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1235983585
Short name T797
Test name
Test status
Simulation time 11592331 ps
CPU time 0.73 seconds
Started Jul 06 06:24:27 PM PDT 24
Finished Jul 06 06:24:29 PM PDT 24
Peak memory 206744 kb
Host smart-5585a92d-4ad4-45c9-9a12-a1bb982a38d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235983585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1235983585
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2636256025
Short name T1014
Test name
Test status
Simulation time 901305830 ps
CPU time 2.54 seconds
Started Jul 06 06:24:22 PM PDT 24
Finished Jul 06 06:24:25 PM PDT 24
Peak memory 225632 kb
Host smart-821f80a6-ad45-46f0-839c-548056373218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636256025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2636256025
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.458249023
Short name T604
Test name
Test status
Simulation time 19951962 ps
CPU time 0.82 seconds
Started Jul 06 06:24:22 PM PDT 24
Finished Jul 06 06:24:23 PM PDT 24
Peak memory 207440 kb
Host smart-a1564bdc-7c80-4248-8681-32efc2dbd240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458249023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.458249023
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1315911012
Short name T56
Test name
Test status
Simulation time 96060288708 ps
CPU time 351.69 seconds
Started Jul 06 06:24:21 PM PDT 24
Finished Jul 06 06:30:13 PM PDT 24
Peak memory 257652 kb
Host smart-62901275-65a4-4823-8f98-f1c0489b60f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315911012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1315911012
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.145676348
Short name T201
Test name
Test status
Simulation time 8178293200 ps
CPU time 48.69 seconds
Started Jul 06 06:24:23 PM PDT 24
Finished Jul 06 06:25:12 PM PDT 24
Peak memory 258664 kb
Host smart-d3cfc832-70bb-4288-a388-8acdec92f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145676348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.145676348
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1089257380
Short name T301
Test name
Test status
Simulation time 241018335 ps
CPU time 3.77 seconds
Started Jul 06 06:24:23 PM PDT 24
Finished Jul 06 06:24:27 PM PDT 24
Peak memory 225548 kb
Host smart-ef2ce484-3e15-4c0f-8978-3cdc2465edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089257380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1089257380
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3124326904
Short name T917
Test name
Test status
Simulation time 144724108935 ps
CPU time 273.73 seconds
Started Jul 06 06:24:22 PM PDT 24
Finished Jul 06 06:28:56 PM PDT 24
Peak memory 264708 kb
Host smart-56985647-5897-4441-a1ea-0afdb6bafb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124326904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3124326904
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1948675034
Short name T182
Test name
Test status
Simulation time 1547736007 ps
CPU time 4.14 seconds
Started Jul 06 06:24:21 PM PDT 24
Finished Jul 06 06:24:25 PM PDT 24
Peak memory 228964 kb
Host smart-94f9b8eb-eaf7-4d05-ac7b-b0684294c6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948675034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1948675034
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4262642363
Short name T236
Test name
Test status
Simulation time 12702643640 ps
CPU time 6.81 seconds
Started Jul 06 06:24:21 PM PDT 24
Finished Jul 06 06:24:28 PM PDT 24
Peak memory 225756 kb
Host smart-e6521e86-d125-4a91-afb1-43ab9c2d1b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262642363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4262642363
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1107971598
Short name T466
Test name
Test status
Simulation time 9379172101 ps
CPU time 10.01 seconds
Started Jul 06 06:24:22 PM PDT 24
Finished Jul 06 06:24:32 PM PDT 24
Peak memory 233916 kb
Host smart-f1d27b1b-a4d4-47e6-b09e-c5686a8cfb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107971598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1107971598
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1464366017
Short name T417
Test name
Test status
Simulation time 1188494938 ps
CPU time 6.38 seconds
Started Jul 06 06:24:21 PM PDT 24
Finished Jul 06 06:24:28 PM PDT 24
Peak memory 241960 kb
Host smart-c36fffa2-34cb-4c9f-b986-2f3d71151bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464366017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1464366017
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1624903250
Short name T147
Test name
Test status
Simulation time 101091207 ps
CPU time 3.66 seconds
Started Jul 06 06:24:24 PM PDT 24
Finished Jul 06 06:24:28 PM PDT 24
Peak memory 223776 kb
Host smart-042ca62c-dac0-439e-be55-1972eace1ca1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1624903250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1624903250
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2555078975
Short name T969
Test name
Test status
Simulation time 63586648137 ps
CPU time 122.13 seconds
Started Jul 06 06:24:25 PM PDT 24
Finished Jul 06 06:26:28 PM PDT 24
Peak memory 234048 kb
Host smart-80d7f2bf-7a63-4435-acca-bf6371020b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555078975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2555078975
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2360180290
Short name T966
Test name
Test status
Simulation time 2731778369 ps
CPU time 14.73 seconds
Started Jul 06 06:24:22 PM PDT 24
Finished Jul 06 06:24:37 PM PDT 24
Peak memory 217584 kb
Host smart-1f5356e2-e8ba-4e4d-87d1-4dede02bc06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360180290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2360180290
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1856653922
Short name T844
Test name
Test status
Simulation time 10263282548 ps
CPU time 17.22 seconds
Started Jul 06 06:24:21 PM PDT 24
Finished Jul 06 06:24:38 PM PDT 24
Peak memory 217496 kb
Host smart-0a175f43-20ea-434a-b011-13939e3ca038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856653922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1856653922
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.869199633
Short name T535
Test name
Test status
Simulation time 200777205 ps
CPU time 2.23 seconds
Started Jul 06 06:24:22 PM PDT 24
Finished Jul 06 06:24:24 PM PDT 24
Peak memory 217360 kb
Host smart-55a5f370-0b73-41ce-87b0-4d3aa4fd531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869199633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.869199633
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2891468906
Short name T2
Test name
Test status
Simulation time 109499781 ps
CPU time 0.81 seconds
Started Jul 06 06:24:23 PM PDT 24
Finished Jul 06 06:24:24 PM PDT 24
Peak memory 206972 kb
Host smart-220e8f01-8233-4e98-bca5-ce496c566a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891468906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2891468906
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3634826943
Short name T860
Test name
Test status
Simulation time 5510447414 ps
CPU time 9.72 seconds
Started Jul 06 06:24:22 PM PDT 24
Finished Jul 06 06:24:32 PM PDT 24
Peak memory 233892 kb
Host smart-ef210a4a-af72-431f-8b23-c30d898ddf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634826943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3634826943
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.820979895
Short name T74
Test name
Test status
Simulation time 33792492 ps
CPU time 0.7 seconds
Started Jul 06 06:24:32 PM PDT 24
Finished Jul 06 06:24:33 PM PDT 24
Peak memory 205820 kb
Host smart-b6d7c616-edf0-47ba-a2c9-f75fd36aa999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820979895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.820979895
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3797254459
Short name T450
Test name
Test status
Simulation time 37219081 ps
CPU time 2.29 seconds
Started Jul 06 06:24:30 PM PDT 24
Finished Jul 06 06:24:32 PM PDT 24
Peak memory 225596 kb
Host smart-29024414-ab49-4b8d-8b4a-f284d3efa787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797254459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3797254459
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3452557622
Short name T705
Test name
Test status
Simulation time 41351935 ps
CPU time 0.8 seconds
Started Jul 06 06:24:25 PM PDT 24
Finished Jul 06 06:24:26 PM PDT 24
Peak memory 207868 kb
Host smart-d1d6695d-d078-471a-9e74-5b841393c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452557622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3452557622
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3252450496
Short name T224
Test name
Test status
Simulation time 26699693290 ps
CPU time 43.63 seconds
Started Jul 06 06:24:30 PM PDT 24
Finished Jul 06 06:25:14 PM PDT 24
Peak memory 252716 kb
Host smart-bf3c239d-93c3-4f94-8536-4bbe4402f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252450496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3252450496
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2657624581
Short name T968
Test name
Test status
Simulation time 2000682886 ps
CPU time 33.09 seconds
Started Jul 06 06:24:30 PM PDT 24
Finished Jul 06 06:25:04 PM PDT 24
Peak memory 250628 kb
Host smart-1f408351-4abf-4a5c-83ff-603596add5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657624581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2657624581
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.4216001732
Short name T496
Test name
Test status
Simulation time 7459167459 ps
CPU time 54.27 seconds
Started Jul 06 06:24:31 PM PDT 24
Finished Jul 06 06:25:25 PM PDT 24
Peak memory 242072 kb
Host smart-3d6740dc-54d6-47f5-9229-a1ed299babd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216001732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4216001732
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2160591640
Short name T565
Test name
Test status
Simulation time 2681873960 ps
CPU time 36.57 seconds
Started Jul 06 06:24:29 PM PDT 24
Finished Jul 06 06:25:06 PM PDT 24
Peak memory 250324 kb
Host smart-172301b7-02b4-4c45-b4d6-d60d0ddcd4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160591640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2160591640
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2352703544
Short name T197
Test name
Test status
Simulation time 156085676 ps
CPU time 4.48 seconds
Started Jul 06 06:24:26 PM PDT 24
Finished Jul 06 06:24:30 PM PDT 24
Peak memory 225532 kb
Host smart-49c0f41e-e2be-41a6-b50c-5ad843906e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352703544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2352703544
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2937540086
Short name T704
Test name
Test status
Simulation time 31267729396 ps
CPU time 109.83 seconds
Started Jul 06 06:24:27 PM PDT 24
Finished Jul 06 06:26:17 PM PDT 24
Peak memory 241688 kb
Host smart-e8092f03-3f21-48cc-acc7-8b24ece456d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937540086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2937540086
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2399485510
Short name T584
Test name
Test status
Simulation time 11584542831 ps
CPU time 14.5 seconds
Started Jul 06 06:24:26 PM PDT 24
Finished Jul 06 06:24:41 PM PDT 24
Peak memory 242028 kb
Host smart-8d996fe7-049d-442e-ba74-e3021dba51ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399485510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2399485510
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3335169628
Short name T787
Test name
Test status
Simulation time 37683239563 ps
CPU time 28.83 seconds
Started Jul 06 06:24:26 PM PDT 24
Finished Jul 06 06:24:55 PM PDT 24
Peak memory 241924 kb
Host smart-1a72085b-116f-46d1-bb6d-db233e863055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335169628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3335169628
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1140342044
Short name T611
Test name
Test status
Simulation time 2992609436 ps
CPU time 9.43 seconds
Started Jul 06 06:24:30 PM PDT 24
Finished Jul 06 06:24:40 PM PDT 24
Peak memory 223172 kb
Host smart-aa7d28a5-fa3c-4ec2-8cd9-3401db069efc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1140342044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1140342044
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.760781097
Short name T782
Test name
Test status
Simulation time 65125145087 ps
CPU time 189.76 seconds
Started Jul 06 06:24:30 PM PDT 24
Finished Jul 06 06:27:40 PM PDT 24
Peak memory 270420 kb
Host smart-7e9883bf-b503-4afd-9bd4-2b3d1148d345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760781097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.760781097
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3003949628
Short name T468
Test name
Test status
Simulation time 1122523847 ps
CPU time 10.63 seconds
Started Jul 06 06:24:26 PM PDT 24
Finished Jul 06 06:24:37 PM PDT 24
Peak memory 217436 kb
Host smart-78c3179b-a2cf-4d46-803f-4e4ba92e291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003949628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3003949628
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2850828486
Short name T727
Test name
Test status
Simulation time 345918980 ps
CPU time 2.01 seconds
Started Jul 06 06:24:25 PM PDT 24
Finished Jul 06 06:24:27 PM PDT 24
Peak memory 217160 kb
Host smart-caff4092-c049-44f5-a05b-6f81d59e758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850828486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2850828486
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3031544591
Short name T691
Test name
Test status
Simulation time 84664393 ps
CPU time 1.04 seconds
Started Jul 06 06:24:26 PM PDT 24
Finished Jul 06 06:24:27 PM PDT 24
Peak memory 208980 kb
Host smart-3ea5a5cc-04de-4e6f-9461-e7a7c4ecbdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031544591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3031544591
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2875274415
Short name T543
Test name
Test status
Simulation time 100934438 ps
CPU time 0.96 seconds
Started Jul 06 06:24:24 PM PDT 24
Finished Jul 06 06:24:25 PM PDT 24
Peak memory 207004 kb
Host smart-b9bd0e8f-10cb-4ede-9683-903039e3c14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875274415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2875274415
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2046135515
Short name T991
Test name
Test status
Simulation time 1407573473 ps
CPU time 3.76 seconds
Started Jul 06 06:24:26 PM PDT 24
Finished Jul 06 06:24:30 PM PDT 24
Peak memory 241908 kb
Host smart-bba974b1-58e5-461b-920c-c753f17744d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046135515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2046135515
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1002415687
Short name T359
Test name
Test status
Simulation time 16026682 ps
CPU time 0.73 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:37 PM PDT 24
Peak memory 205804 kb
Host smart-b26532c4-4cb3-44d0-adf0-258782243bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002415687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1002415687
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3476117194
Short name T896
Test name
Test status
Simulation time 9793249221 ps
CPU time 12.54 seconds
Started Jul 06 06:24:34 PM PDT 24
Finished Jul 06 06:24:47 PM PDT 24
Peak memory 225756 kb
Host smart-a9c079ad-d0b6-48be-8481-1a3be9d05407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476117194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3476117194
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2399768390
Short name T440
Test name
Test status
Simulation time 15504395 ps
CPU time 0.77 seconds
Started Jul 06 06:24:30 PM PDT 24
Finished Jul 06 06:24:31 PM PDT 24
Peak memory 206480 kb
Host smart-46196755-2ba9-4944-9ee4-9504292b9be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399768390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2399768390
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2405156753
Short name T183
Test name
Test status
Simulation time 43046152220 ps
CPU time 95.19 seconds
Started Jul 06 06:24:36 PM PDT 24
Finished Jul 06 06:26:12 PM PDT 24
Peak memory 250356 kb
Host smart-1664a8aa-b7e8-4c44-ad8f-93ebcb25270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405156753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2405156753
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2142760797
Short name T949
Test name
Test status
Simulation time 190361339782 ps
CPU time 387.74 seconds
Started Jul 06 06:24:34 PM PDT 24
Finished Jul 06 06:31:02 PM PDT 24
Peak memory 250352 kb
Host smart-32068a44-45bb-48eb-81df-9f57fee1a439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142760797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2142760797
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.791801406
Short name T129
Test name
Test status
Simulation time 10534926804 ps
CPU time 102.65 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:26:19 PM PDT 24
Peak memory 250472 kb
Host smart-b5e29723-c7da-4f5e-971f-59da64b6fc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791801406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.791801406
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2978329467
Short name T810
Test name
Test status
Simulation time 812870930 ps
CPU time 20.67 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:56 PM PDT 24
Peak memory 250200 kb
Host smart-cf8bcd7a-0df1-408a-92b2-2fed43c3bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978329467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2978329467
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1434173270
Short name T265
Test name
Test status
Simulation time 15183314592 ps
CPU time 84.16 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:25:59 PM PDT 24
Peak memory 256708 kb
Host smart-61b3c915-a888-4710-bb89-14e8a1725a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434173270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1434173270
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3542982420
Short name T257
Test name
Test status
Simulation time 801794106 ps
CPU time 4.91 seconds
Started Jul 06 06:24:37 PM PDT 24
Finished Jul 06 06:24:42 PM PDT 24
Peak memory 225852 kb
Host smart-ae0e7f40-a156-4519-840e-0b24bf3b7de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542982420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3542982420
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1597853953
Short name T480
Test name
Test status
Simulation time 158271885 ps
CPU time 3.76 seconds
Started Jul 06 06:24:38 PM PDT 24
Finished Jul 06 06:24:42 PM PDT 24
Peak memory 225864 kb
Host smart-e7a44c04-f79b-42ec-ba09-daa059b1b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597853953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1597853953
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3702243307
Short name T610
Test name
Test status
Simulation time 1276044662 ps
CPU time 4.78 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:41 PM PDT 24
Peak memory 225572 kb
Host smart-1cce3300-f7db-4576-b575-254823986b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702243307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3702243307
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2383803091
Short name T253
Test name
Test status
Simulation time 1397857547 ps
CPU time 6.26 seconds
Started Jul 06 06:24:37 PM PDT 24
Finished Jul 06 06:24:43 PM PDT 24
Peak memory 233796 kb
Host smart-3fb65daf-bbab-4062-82e8-5f207c66c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383803091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2383803091
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1712915119
Short name T858
Test name
Test status
Simulation time 1092993029 ps
CPU time 5.5 seconds
Started Jul 06 06:24:34 PM PDT 24
Finished Jul 06 06:24:40 PM PDT 24
Peak memory 222852 kb
Host smart-ab3e8042-7f3e-48fe-bed9-837292115cd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1712915119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1712915119
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1942601992
Short name T962
Test name
Test status
Simulation time 1200876283 ps
CPU time 7.1 seconds
Started Jul 06 06:24:38 PM PDT 24
Finished Jul 06 06:24:45 PM PDT 24
Peak memory 217412 kb
Host smart-ec03f2a7-8272-4495-a419-9c8443383d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942601992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1942601992
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4942430
Short name T963
Test name
Test status
Simulation time 251189100 ps
CPU time 1.66 seconds
Started Jul 06 06:24:30 PM PDT 24
Finished Jul 06 06:24:32 PM PDT 24
Peak memory 208104 kb
Host smart-9ce866c7-289e-4a29-80ab-a324d42df981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4942430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4942430
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3747184683
Short name T460
Test name
Test status
Simulation time 107108261 ps
CPU time 0.98 seconds
Started Jul 06 06:24:34 PM PDT 24
Finished Jul 06 06:24:36 PM PDT 24
Peak memory 208928 kb
Host smart-6b89cfdd-7220-4572-b5cf-9b63cd172793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747184683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3747184683
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1542336681
Short name T374
Test name
Test status
Simulation time 230869588 ps
CPU time 1 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:36 PM PDT 24
Peak memory 207972 kb
Host smart-b140d75a-ee42-4616-be0a-2ada840a210d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542336681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1542336681
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.762083230
Short name T214
Test name
Test status
Simulation time 1327110719 ps
CPU time 10.3 seconds
Started Jul 06 06:24:34 PM PDT 24
Finished Jul 06 06:24:45 PM PDT 24
Peak memory 233748 kb
Host smart-828184c6-8f3c-4177-8edf-b4cdfb214aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762083230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.762083230
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3960705840
Short name T23
Test name
Test status
Simulation time 35871342 ps
CPU time 0.74 seconds
Started Jul 06 06:24:43 PM PDT 24
Finished Jul 06 06:24:44 PM PDT 24
Peak memory 206412 kb
Host smart-6fa2a433-43be-4585-b0c1-b5c40d07c4ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960705840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3960705840
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2970788717
Short name T502
Test name
Test status
Simulation time 187057982 ps
CPU time 2.15 seconds
Started Jul 06 06:24:42 PM PDT 24
Finished Jul 06 06:24:45 PM PDT 24
Peak memory 225544 kb
Host smart-dd3e25da-85a2-458d-b416-d216d31e2a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970788717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2970788717
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1616334625
Short name T786
Test name
Test status
Simulation time 16257187 ps
CPU time 0.76 seconds
Started Jul 06 06:24:35 PM PDT 24
Finished Jul 06 06:24:36 PM PDT 24
Peak memory 206516 kb
Host smart-d020933c-2c6b-4b22-8e82-fbcc2d94b08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616334625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1616334625
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1492495913
Short name T256
Test name
Test status
Simulation time 29186957906 ps
CPU time 332.43 seconds
Started Jul 06 06:24:39 PM PDT 24
Finished Jul 06 06:30:12 PM PDT 24
Peak memory 282696 kb
Host smart-416db8fc-59b5-4f16-8777-5630718145eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492495913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1492495913
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1841439366
Short name T500
Test name
Test status
Simulation time 819875916 ps
CPU time 13.09 seconds
Started Jul 06 06:24:39 PM PDT 24
Finished Jul 06 06:24:52 PM PDT 24
Peak memory 221020 kb
Host smart-36e85a65-2b77-4b69-b49d-e7016f425ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841439366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1841439366
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3285455742
Short name T1022
Test name
Test status
Simulation time 13475599419 ps
CPU time 39.08 seconds
Started Jul 06 06:24:42 PM PDT 24
Finished Jul 06 06:25:22 PM PDT 24
Peak memory 250224 kb
Host smart-95a93c2b-d696-463a-9b4f-5b2cdbf6f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285455742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3285455742
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1908223410
Short name T1023
Test name
Test status
Simulation time 24292422413 ps
CPU time 35.18 seconds
Started Jul 06 06:24:41 PM PDT 24
Finished Jul 06 06:25:17 PM PDT 24
Peak memory 251776 kb
Host smart-8e50e42a-231b-442d-9c96-2b3bd5b5f0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908223410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1908223410
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1273728912
Short name T527
Test name
Test status
Simulation time 260560818 ps
CPU time 4.43 seconds
Started Jul 06 06:24:45 PM PDT 24
Finished Jul 06 06:24:49 PM PDT 24
Peak memory 220812 kb
Host smart-e06e3c74-bcf9-4e2d-a1a1-53e6f203a7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273728912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1273728912
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.124022219
Short name T350
Test name
Test status
Simulation time 1281539099 ps
CPU time 18.4 seconds
Started Jul 06 06:24:41 PM PDT 24
Finished Jul 06 06:24:59 PM PDT 24
Peak memory 250188 kb
Host smart-8b08ea02-5c23-49f9-a1a9-a9fc1c687145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124022219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.124022219
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3458055319
Short name T801
Test name
Test status
Simulation time 3489158395 ps
CPU time 11.97 seconds
Started Jul 06 06:24:40 PM PDT 24
Finished Jul 06 06:24:52 PM PDT 24
Peak memory 225664 kb
Host smart-36948c70-8d85-4f08-972d-513262b20dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458055319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3458055319
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2322082327
Short name T465
Test name
Test status
Simulation time 34815013 ps
CPU time 2.31 seconds
Started Jul 06 06:24:39 PM PDT 24
Finished Jul 06 06:24:42 PM PDT 24
Peak memory 233508 kb
Host smart-b40a2092-6f6d-437f-8538-2008881295ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322082327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2322082327
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3832581675
Short name T537
Test name
Test status
Simulation time 2552303897 ps
CPU time 15.93 seconds
Started Jul 06 06:24:39 PM PDT 24
Finished Jul 06 06:24:56 PM PDT 24
Peak memory 223468 kb
Host smart-c1359d34-e554-436d-bfb2-40e26fe97a5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3832581675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3832581675
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4254540614
Short name T471
Test name
Test status
Simulation time 20094269725 ps
CPU time 88.09 seconds
Started Jul 06 06:24:39 PM PDT 24
Finished Jul 06 06:26:08 PM PDT 24
Peak memory 266144 kb
Host smart-d94d28e7-db72-4b1d-84bc-6d03021d3a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254540614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4254540614
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1468039187
Short name T309
Test name
Test status
Simulation time 9357150586 ps
CPU time 10.5 seconds
Started Jul 06 06:24:38 PM PDT 24
Finished Jul 06 06:24:49 PM PDT 24
Peak memory 217788 kb
Host smart-c9e29645-3ef0-4e01-892f-739b76a2b260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468039187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1468039187
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2322456466
Short name T938
Test name
Test status
Simulation time 5358591635 ps
CPU time 6.64 seconds
Started Jul 06 06:24:38 PM PDT 24
Finished Jul 06 06:24:45 PM PDT 24
Peak memory 217796 kb
Host smart-f7863556-7847-4051-bfcf-2ed7a011ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322456466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2322456466
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4099250979
Short name T596
Test name
Test status
Simulation time 54790579 ps
CPU time 0.84 seconds
Started Jul 06 06:24:40 PM PDT 24
Finished Jul 06 06:24:41 PM PDT 24
Peak memory 207724 kb
Host smart-63a7430a-fa94-42af-b3b2-366e992d8e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099250979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4099250979
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3284335920
Short name T940
Test name
Test status
Simulation time 42623974 ps
CPU time 0.77 seconds
Started Jul 06 06:24:41 PM PDT 24
Finished Jul 06 06:24:42 PM PDT 24
Peak memory 206984 kb
Host smart-94c346a6-6f4f-466e-be74-597affea34ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284335920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3284335920
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4126596726
Short name T204
Test name
Test status
Simulation time 414530324 ps
CPU time 7.08 seconds
Started Jul 06 06:24:40 PM PDT 24
Finished Jul 06 06:24:47 PM PDT 24
Peak memory 233804 kb
Host smart-4beefaf3-5a4f-4457-800b-18a07dc1db6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126596726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4126596726
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4044199514
Short name T342
Test name
Test status
Simulation time 42131350 ps
CPU time 0.75 seconds
Started Jul 06 06:24:46 PM PDT 24
Finished Jul 06 06:24:47 PM PDT 24
Peak memory 206360 kb
Host smart-27a5477f-e91f-4fea-9fcb-9984a234a934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044199514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4044199514
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2065151688
Short name T690
Test name
Test status
Simulation time 242764245 ps
CPU time 4.07 seconds
Started Jul 06 06:24:47 PM PDT 24
Finished Jul 06 06:24:51 PM PDT 24
Peak memory 233748 kb
Host smart-ea1cd614-f435-43da-ba0e-2c9eaddd0922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065151688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2065151688
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1090718509
Short name T657
Test name
Test status
Simulation time 51142804 ps
CPU time 0.77 seconds
Started Jul 06 06:24:40 PM PDT 24
Finished Jul 06 06:24:41 PM PDT 24
Peak memory 207852 kb
Host smart-6a3a3fee-bcb9-4c85-967d-b28233bf988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090718509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1090718509
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.968220358
Short name T813
Test name
Test status
Simulation time 5598750671 ps
CPU time 17.67 seconds
Started Jul 06 06:24:46 PM PDT 24
Finished Jul 06 06:25:04 PM PDT 24
Peak memory 225724 kb
Host smart-4e94fc84-c899-471c-b4ec-aea9a9e1e317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968220358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.968220358
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4104113105
Short name T225
Test name
Test status
Simulation time 91539482682 ps
CPU time 146.32 seconds
Started Jul 06 06:24:47 PM PDT 24
Finished Jul 06 06:27:14 PM PDT 24
Peak memory 242076 kb
Host smart-7e0e5756-a8da-47e3-9d60-ccff8d6c8fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104113105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4104113105
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.90015598
Short name T137
Test name
Test status
Simulation time 23796816120 ps
CPU time 132.1 seconds
Started Jul 06 06:24:45 PM PDT 24
Finished Jul 06 06:26:57 PM PDT 24
Peak memory 269228 kb
Host smart-22d49c82-1bf5-43c5-bfc4-1b2071ca1991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90015598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.90015598
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.592349473
Short name T854
Test name
Test status
Simulation time 596874720 ps
CPU time 4.72 seconds
Started Jul 06 06:24:47 PM PDT 24
Finished Jul 06 06:24:52 PM PDT 24
Peak memory 233848 kb
Host smart-6cc9a6ff-6cd5-4c2c-92f9-6f8a4b1c9841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592349473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.592349473
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.203588219
Short name T773
Test name
Test status
Simulation time 152803500380 ps
CPU time 133.39 seconds
Started Jul 06 06:24:44 PM PDT 24
Finished Jul 06 06:26:58 PM PDT 24
Peak memory 253344 kb
Host smart-b70875d0-4636-4135-be88-85041e336199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203588219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.203588219
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2285946776
Short name T222
Test name
Test status
Simulation time 427240253 ps
CPU time 6.31 seconds
Started Jul 06 06:24:46 PM PDT 24
Finished Jul 06 06:24:53 PM PDT 24
Peak memory 225608 kb
Host smart-f1b4f24c-da4a-44c9-b408-0e13ee280250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285946776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2285946776
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3125556261
Short name T846
Test name
Test status
Simulation time 21938395880 ps
CPU time 56.64 seconds
Started Jul 06 06:24:47 PM PDT 24
Finished Jul 06 06:25:44 PM PDT 24
Peak memory 225660 kb
Host smart-a627f405-6eec-49fc-8d19-d86c175f24bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125556261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3125556261
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.771641784
Short name T456
Test name
Test status
Simulation time 848993264 ps
CPU time 2.72 seconds
Started Jul 06 06:24:48 PM PDT 24
Finished Jul 06 06:24:51 PM PDT 24
Peak memory 233816 kb
Host smart-2c642d10-8952-4ce3-8165-68fe1e1bf27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771641784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.771641784
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3657093428
Short name T373
Test name
Test status
Simulation time 371492441 ps
CPU time 6.28 seconds
Started Jul 06 06:24:44 PM PDT 24
Finished Jul 06 06:24:51 PM PDT 24
Peak memory 233792 kb
Host smart-ed747410-1591-4de3-bf31-59dc35ecc38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657093428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3657093428
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.793307181
Short name T850
Test name
Test status
Simulation time 902298592 ps
CPU time 4.1 seconds
Started Jul 06 06:24:45 PM PDT 24
Finished Jul 06 06:24:50 PM PDT 24
Peak memory 219780 kb
Host smart-332bb937-1be1-47d3-95c1-a0066be86076
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793307181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.793307181
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1255382221
Short name T574
Test name
Test status
Simulation time 7943445473 ps
CPU time 38.75 seconds
Started Jul 06 06:24:43 PM PDT 24
Finished Jul 06 06:25:22 PM PDT 24
Peak memory 250760 kb
Host smart-c1da25fd-09e4-432d-86a6-7b17890e13ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255382221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1255382221
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3195812587
Short name T615
Test name
Test status
Simulation time 1641200938 ps
CPU time 22.13 seconds
Started Jul 06 06:24:40 PM PDT 24
Finished Jul 06 06:25:02 PM PDT 24
Peak memory 217388 kb
Host smart-a9332384-e71d-4656-ae0d-fa5bcef22fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195812587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3195812587
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4148037107
Short name T686
Test name
Test status
Simulation time 16491446534 ps
CPU time 24.51 seconds
Started Jul 06 06:24:40 PM PDT 24
Finished Jul 06 06:25:05 PM PDT 24
Peak memory 217448 kb
Host smart-e05eed10-ad84-4184-bec7-e4ebea7faf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148037107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4148037107
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.779952621
Short name T823
Test name
Test status
Simulation time 13464701 ps
CPU time 0.88 seconds
Started Jul 06 06:24:40 PM PDT 24
Finished Jul 06 06:24:42 PM PDT 24
Peak memory 208096 kb
Host smart-dbe46b0a-c556-4994-9dd2-5fc5ce49bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779952621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.779952621
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3588170332
Short name T557
Test name
Test status
Simulation time 45909503 ps
CPU time 0.73 seconds
Started Jul 06 06:24:39 PM PDT 24
Finished Jul 06 06:24:40 PM PDT 24
Peak memory 207008 kb
Host smart-5e6bab11-0db7-4bce-a928-57db3ae1da23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588170332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3588170332
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.203289971
Short name T875
Test name
Test status
Simulation time 660032175 ps
CPU time 9.03 seconds
Started Jul 06 06:24:45 PM PDT 24
Finished Jul 06 06:24:54 PM PDT 24
Peak memory 240044 kb
Host smart-8810f3ea-7ffd-4c17-872b-813ad5844d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203289971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.203289971
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3060322717
Short name T683
Test name
Test status
Simulation time 23011392 ps
CPU time 0.78 seconds
Started Jul 06 06:21:53 PM PDT 24
Finished Jul 06 06:21:54 PM PDT 24
Peak memory 205840 kb
Host smart-73d04865-2169-428d-a556-fefbe727075c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060322717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
060322717
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.191407119
Short name T608
Test name
Test status
Simulation time 5510315067 ps
CPU time 12.54 seconds
Started Jul 06 06:21:52 PM PDT 24
Finished Jul 06 06:22:05 PM PDT 24
Peak memory 233936 kb
Host smart-b8203ad2-3789-4d02-814d-5d6eb1983483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191407119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.191407119
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.153889631
Short name T340
Test name
Test status
Simulation time 14044753 ps
CPU time 0.81 seconds
Started Jul 06 06:21:52 PM PDT 24
Finished Jul 06 06:21:53 PM PDT 24
Peak memory 207528 kb
Host smart-586c0c9c-a21b-417e-9e9a-28434bb1fb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153889631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.153889631
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.237426529
Short name T601
Test name
Test status
Simulation time 13442552241 ps
CPU time 48.28 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:22:40 PM PDT 24
Peak memory 242132 kb
Host smart-b6d44a25-4de1-45eb-ace4-86e26ba386ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237426529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.237426529
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1062066667
Short name T894
Test name
Test status
Simulation time 22154838295 ps
CPU time 112.37 seconds
Started Jul 06 06:21:52 PM PDT 24
Finished Jul 06 06:23:45 PM PDT 24
Peak memory 250260 kb
Host smart-ba299896-9e5c-402a-962d-2ad201067b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062066667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1062066667
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1047351043
Short name T462
Test name
Test status
Simulation time 37554943515 ps
CPU time 220.8 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:25:32 PM PDT 24
Peak memory 274904 kb
Host smart-fa240f2d-812c-4b6a-923c-9a257671e3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047351043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1047351043
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1494261959
Short name T303
Test name
Test status
Simulation time 4229340635 ps
CPU time 29.46 seconds
Started Jul 06 06:21:51 PM PDT 24
Finished Jul 06 06:22:21 PM PDT 24
Peak memory 241724 kb
Host smart-3e02ed87-9a24-4a4b-9c87-ca7d6dc27529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494261959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1494261959
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4069342946
Short name T560
Test name
Test status
Simulation time 42515852 ps
CPU time 0.74 seconds
Started Jul 06 06:21:49 PM PDT 24
Finished Jul 06 06:21:51 PM PDT 24
Peak memory 216952 kb
Host smart-d1670895-c35f-4305-b987-87531984af83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069342946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4069342946
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3625725152
Short name T740
Test name
Test status
Simulation time 345164590 ps
CPU time 3.03 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:21:54 PM PDT 24
Peak memory 233808 kb
Host smart-09e0232f-d36d-43cc-a792-cbf483669c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625725152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3625725152
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1178743074
Short name T929
Test name
Test status
Simulation time 104186330 ps
CPU time 2.57 seconds
Started Jul 06 06:25:03 PM PDT 24
Finished Jul 06 06:25:06 PM PDT 24
Peak memory 233448 kb
Host smart-e3b803ab-8442-4d62-87cb-9fb948566f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178743074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1178743074
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3101966901
Short name T328
Test name
Test status
Simulation time 32179248 ps
CPU time 1.06 seconds
Started Jul 06 06:21:53 PM PDT 24
Finished Jul 06 06:21:54 PM PDT 24
Peak memory 217672 kb
Host smart-b56748df-3964-47da-af10-f13086c5fdf8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101966901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3101966901
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3085823898
Short name T635
Test name
Test status
Simulation time 13476503629 ps
CPU time 12.37 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:22:04 PM PDT 24
Peak memory 233820 kb
Host smart-05d73663-da51-4c8c-b726-aaccf1762dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085823898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3085823898
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2035525173
Short name T477
Test name
Test status
Simulation time 30025733 ps
CPU time 2.15 seconds
Started Jul 06 06:21:51 PM PDT 24
Finished Jul 06 06:21:54 PM PDT 24
Peak memory 225092 kb
Host smart-71db7d65-e81e-445b-921c-72ad271ba0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035525173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2035525173
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3648979242
Short name T360
Test name
Test status
Simulation time 109739447 ps
CPU time 3.29 seconds
Started Jul 06 06:21:52 PM PDT 24
Finished Jul 06 06:21:55 PM PDT 24
Peak memory 220444 kb
Host smart-92ab134a-be05-4a72-9859-74716784db4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3648979242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3648979242
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1200809422
Short name T78
Test name
Test status
Simulation time 102308512 ps
CPU time 1.17 seconds
Started Jul 06 06:21:51 PM PDT 24
Finished Jul 06 06:21:53 PM PDT 24
Peak memory 237360 kb
Host smart-65926504-80d9-4682-8287-7dff589beff6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200809422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1200809422
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3985623431
Short name T829
Test name
Test status
Simulation time 11228622328 ps
CPU time 61.32 seconds
Started Jul 06 06:21:49 PM PDT 24
Finished Jul 06 06:22:51 PM PDT 24
Peak memory 253232 kb
Host smart-b8b58b10-3d40-4723-b13d-3102741f9504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985623431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3985623431
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3818600935
Short name T487
Test name
Test status
Simulation time 1405002503 ps
CPU time 18.01 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:22:08 PM PDT 24
Peak memory 217352 kb
Host smart-5e34a6dd-b827-47b3-b27b-6a99b9ee831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818600935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3818600935
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3371996730
Short name T334
Test name
Test status
Simulation time 611453228 ps
CPU time 5.25 seconds
Started Jul 06 06:21:54 PM PDT 24
Finished Jul 06 06:21:59 PM PDT 24
Peak memory 217268 kb
Host smart-bbaf2445-41a1-49ee-abe6-8c9d06eecd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371996730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3371996730
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3602051811
Short name T954
Test name
Test status
Simulation time 95454946 ps
CPU time 1.3 seconds
Started Jul 06 06:21:53 PM PDT 24
Finished Jul 06 06:21:55 PM PDT 24
Peak memory 217356 kb
Host smart-9a6119b9-73da-4cc2-87a2-b7a73ba44a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602051811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3602051811
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.570608097
Short name T662
Test name
Test status
Simulation time 50561218 ps
CPU time 0.85 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:21:51 PM PDT 24
Peak memory 207008 kb
Host smart-adb7a28c-a86f-4d85-85a8-e26950eb9def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570608097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.570608097
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.848660380
Short name T669
Test name
Test status
Simulation time 173664748 ps
CPU time 4.55 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:04 PM PDT 24
Peak memory 233844 kb
Host smart-a33ab7a7-9ead-4b55-89da-1b77e49b16c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848660380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.848660380
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4024961039
Short name T887
Test name
Test status
Simulation time 52910411 ps
CPU time 0.78 seconds
Started Jul 06 06:24:52 PM PDT 24
Finished Jul 06 06:24:53 PM PDT 24
Peak memory 206364 kb
Host smart-ed098cc3-a742-44eb-892b-adb72014c843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024961039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4024961039
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1972861128
Short name T428
Test name
Test status
Simulation time 181497958 ps
CPU time 2.32 seconds
Started Jul 06 06:24:49 PM PDT 24
Finished Jul 06 06:24:52 PM PDT 24
Peak memory 225652 kb
Host smart-80f6d42d-75d5-4c4a-badb-6af81cff822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972861128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1972861128
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2286097410
Short name T81
Test name
Test status
Simulation time 20537676 ps
CPU time 0.81 seconds
Started Jul 06 06:24:45 PM PDT 24
Finished Jul 06 06:24:46 PM PDT 24
Peak memory 207904 kb
Host smart-0241a8bc-c78c-41e2-a09d-4aa1c2e630e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286097410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2286097410
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.421620458
Short name T200
Test name
Test status
Simulation time 2117870183 ps
CPU time 49.64 seconds
Started Jul 06 06:24:51 PM PDT 24
Finished Jul 06 06:25:41 PM PDT 24
Peak memory 250156 kb
Host smart-a3fa6e18-ade8-4d5e-a13e-feec77660db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421620458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.421620458
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1673752094
Short name T339
Test name
Test status
Simulation time 211663734 ps
CPU time 5.36 seconds
Started Jul 06 06:24:52 PM PDT 24
Finished Jul 06 06:24:58 PM PDT 24
Peak memory 233784 kb
Host smart-083b1977-2bd6-4c81-aab4-01c8db029dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673752094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1673752094
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2229757262
Short name T439
Test name
Test status
Simulation time 2840183660 ps
CPU time 20.78 seconds
Started Jul 06 06:24:50 PM PDT 24
Finished Jul 06 06:25:11 PM PDT 24
Peak memory 236120 kb
Host smart-26054414-328d-4171-8ef0-c5f4b2125dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229757262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2229757262
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2303579006
Short name T221
Test name
Test status
Simulation time 313751755 ps
CPU time 3.64 seconds
Started Jul 06 06:24:49 PM PDT 24
Finished Jul 06 06:24:53 PM PDT 24
Peak memory 225580 kb
Host smart-4f75f9da-3f55-444a-b5c2-279729b6760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303579006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2303579006
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4149917692
Short name T207
Test name
Test status
Simulation time 6922309494 ps
CPU time 16.56 seconds
Started Jul 06 06:24:50 PM PDT 24
Finished Jul 06 06:25:07 PM PDT 24
Peak memory 233976 kb
Host smart-cf45fe0c-64bd-44e5-bb2a-c5257af8a25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149917692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4149917692
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3721334289
Short name T181
Test name
Test status
Simulation time 393932260 ps
CPU time 2.45 seconds
Started Jul 06 06:24:50 PM PDT 24
Finished Jul 06 06:24:53 PM PDT 24
Peak memory 225608 kb
Host smart-7278a88e-51a7-400f-83ed-cc03cfaea013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721334289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3721334289
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2622495548
Short name T549
Test name
Test status
Simulation time 2754022977 ps
CPU time 6.46 seconds
Started Jul 06 06:24:46 PM PDT 24
Finished Jul 06 06:24:53 PM PDT 24
Peak memory 233848 kb
Host smart-d3aba700-29f2-48b4-9223-6b25350b651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622495548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2622495548
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4173561826
Short name T385
Test name
Test status
Simulation time 354903369 ps
CPU time 6.6 seconds
Started Jul 06 06:24:49 PM PDT 24
Finished Jul 06 06:24:57 PM PDT 24
Peak memory 223604 kb
Host smart-94779736-e976-449a-819c-20491656987b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4173561826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4173561826
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2369145283
Short name T17
Test name
Test status
Simulation time 75389263 ps
CPU time 0.93 seconds
Started Jul 06 06:24:49 PM PDT 24
Finished Jul 06 06:24:51 PM PDT 24
Peak memory 208388 kb
Host smart-da68e140-0bd2-4f1a-bd3a-954e0a84350f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369145283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2369145283
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1863906212
Short name T825
Test name
Test status
Simulation time 13162549989 ps
CPU time 31.9 seconds
Started Jul 06 06:24:46 PM PDT 24
Finished Jul 06 06:25:18 PM PDT 24
Peak memory 217452 kb
Host smart-48fdb1c3-5ee2-4cb6-a979-713ded619d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863906212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1863906212
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2685441274
Short name T631
Test name
Test status
Simulation time 457914619 ps
CPU time 2.58 seconds
Started Jul 06 06:24:47 PM PDT 24
Finished Jul 06 06:24:50 PM PDT 24
Peak memory 217324 kb
Host smart-c73d231d-a767-4c15-89ef-1db6d1701089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685441274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2685441274
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1219793105
Short name T6
Test name
Test status
Simulation time 223073608 ps
CPU time 2.31 seconds
Started Jul 06 06:24:46 PM PDT 24
Finished Jul 06 06:24:48 PM PDT 24
Peak memory 217364 kb
Host smart-25c569a9-1211-4d77-a999-863b9c544eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219793105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1219793105
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1091380641
Short name T692
Test name
Test status
Simulation time 158813715 ps
CPU time 0.84 seconds
Started Jul 06 06:24:46 PM PDT 24
Finished Jul 06 06:24:47 PM PDT 24
Peak memory 207016 kb
Host smart-1c93c958-691f-40d4-9527-3b6fd2802304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091380641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1091380641
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3263407655
Short name T784
Test name
Test status
Simulation time 3323364848 ps
CPU time 9.92 seconds
Started Jul 06 06:24:50 PM PDT 24
Finished Jul 06 06:25:00 PM PDT 24
Peak memory 240544 kb
Host smart-4d5f7985-485f-4102-aee8-27efd38e9ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263407655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3263407655
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1760189680
Short name T361
Test name
Test status
Simulation time 23774458 ps
CPU time 0.71 seconds
Started Jul 06 06:24:53 PM PDT 24
Finished Jul 06 06:24:54 PM PDT 24
Peak memory 205836 kb
Host smart-c3ba4e8d-d935-4b4d-9858-40fb5c59ec3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760189680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1760189680
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3013735771
Short name T448
Test name
Test status
Simulation time 4323819623 ps
CPU time 9.31 seconds
Started Jul 06 06:24:54 PM PDT 24
Finished Jul 06 06:25:04 PM PDT 24
Peak memory 233988 kb
Host smart-16bf9013-6635-48b1-8074-87eb4b799e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013735771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3013735771
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.149502340
Short name T939
Test name
Test status
Simulation time 33758355 ps
CPU time 0.77 seconds
Started Jul 06 06:24:49 PM PDT 24
Finished Jul 06 06:24:51 PM PDT 24
Peak memory 207552 kb
Host smart-250728c1-2832-47ae-a576-6fd3cbeaf757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149502340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.149502340
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2623460399
Short name T180
Test name
Test status
Simulation time 38581770634 ps
CPU time 136.17 seconds
Started Jul 06 06:24:54 PM PDT 24
Finished Jul 06 06:27:11 PM PDT 24
Peak memory 263008 kb
Host smart-11060ec4-efb9-40c6-b92e-5dfa8b1bb08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623460399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2623460399
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.19774551
Short name T491
Test name
Test status
Simulation time 21765998029 ps
CPU time 25.94 seconds
Started Jul 06 06:24:55 PM PDT 24
Finished Jul 06 06:25:22 PM PDT 24
Peak memory 240888 kb
Host smart-773b3a41-bd9c-416f-9214-3c5d0ac9bdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19774551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.19774551
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2970953020
Short name T733
Test name
Test status
Simulation time 3291547173 ps
CPU time 46.72 seconds
Started Jul 06 06:24:53 PM PDT 24
Finished Jul 06 06:25:40 PM PDT 24
Peak memory 242252 kb
Host smart-2347136f-1350-47db-987e-2d5c3c702c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970953020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2970953020
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3236387638
Short name T728
Test name
Test status
Simulation time 283874927 ps
CPU time 2.73 seconds
Started Jul 06 06:24:53 PM PDT 24
Finished Jul 06 06:24:56 PM PDT 24
Peak memory 225564 kb
Host smart-cfac708e-d5b4-40a4-80b5-cc72c6c31c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236387638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3236387638
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2621748016
Short name T267
Test name
Test status
Simulation time 30930471369 ps
CPU time 199.72 seconds
Started Jul 06 06:24:56 PM PDT 24
Finished Jul 06 06:28:16 PM PDT 24
Peak memory 250344 kb
Host smart-92b663dc-2664-4d8c-861f-7fb178cbbf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621748016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2621748016
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.80975748
Short name T582
Test name
Test status
Simulation time 369963146 ps
CPU time 4.25 seconds
Started Jul 06 06:24:48 PM PDT 24
Finished Jul 06 06:24:52 PM PDT 24
Peak memory 225600 kb
Host smart-e3093a1c-dd0a-4f59-be38-687193e5ce54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80975748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.80975748
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.925551044
Short name T586
Test name
Test status
Simulation time 22844607997 ps
CPU time 52.49 seconds
Started Jul 06 06:24:51 PM PDT 24
Finished Jul 06 06:25:44 PM PDT 24
Peak memory 220188 kb
Host smart-ba824219-8741-4c1f-ac7e-1bd62e45acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925551044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.925551044
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1263426749
Short name T999
Test name
Test status
Simulation time 702222669 ps
CPU time 8.99 seconds
Started Jul 06 06:24:51 PM PDT 24
Finished Jul 06 06:25:00 PM PDT 24
Peak memory 233828 kb
Host smart-7dc70105-09a5-47e9-a0e5-e3cddc7f6a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263426749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1263426749
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1779439540
Short name T984
Test name
Test status
Simulation time 6991433732 ps
CPU time 14.17 seconds
Started Jul 06 06:24:49 PM PDT 24
Finished Jul 06 06:25:05 PM PDT 24
Peak memory 233908 kb
Host smart-9b2290e6-4caa-462d-b5ad-0592eba43a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779439540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1779439540
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.186096395
Short name T467
Test name
Test status
Simulation time 209775328 ps
CPU time 5.16 seconds
Started Jul 06 06:24:54 PM PDT 24
Finished Jul 06 06:24:59 PM PDT 24
Peak memory 224100 kb
Host smart-1f0d46bc-e049-488b-8c4e-88a79145a9a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=186096395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.186096395
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3906695332
Short name T654
Test name
Test status
Simulation time 2422925457 ps
CPU time 7.1 seconds
Started Jul 06 06:24:50 PM PDT 24
Finished Jul 06 06:24:57 PM PDT 24
Peak memory 217500 kb
Host smart-c41a07a4-4d15-4e4c-84de-e2143984e85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906695332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3906695332
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2491496493
Short name T526
Test name
Test status
Simulation time 834567966 ps
CPU time 2.32 seconds
Started Jul 06 06:24:47 PM PDT 24
Finished Jul 06 06:24:50 PM PDT 24
Peak memory 217396 kb
Host smart-2dd2f238-595a-475a-b34b-849f32fb51ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491496493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2491496493
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.923034475
Short name T712
Test name
Test status
Simulation time 119879125 ps
CPU time 2.29 seconds
Started Jul 06 06:24:48 PM PDT 24
Finished Jul 06 06:24:50 PM PDT 24
Peak memory 217392 kb
Host smart-b2a172ae-1735-43c1-bc25-71df9a80169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923034475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.923034475
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.851635511
Short name T403
Test name
Test status
Simulation time 89559512 ps
CPU time 0.78 seconds
Started Jul 06 06:24:50 PM PDT 24
Finished Jul 06 06:24:51 PM PDT 24
Peak memory 207008 kb
Host smart-85a3ae50-a834-46bf-9813-d2727a7a881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851635511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.851635511
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2562820782
Short name T789
Test name
Test status
Simulation time 4816520488 ps
CPU time 15.29 seconds
Started Jul 06 06:24:54 PM PDT 24
Finished Jul 06 06:25:09 PM PDT 24
Peak memory 225680 kb
Host smart-8b8ad072-f802-49f4-9833-370522464b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562820782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2562820782
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1715648754
Short name T37
Test name
Test status
Simulation time 19311302 ps
CPU time 0.69 seconds
Started Jul 06 06:25:00 PM PDT 24
Finished Jul 06 06:25:01 PM PDT 24
Peak memory 205716 kb
Host smart-18d8532f-966d-4937-b2c7-d86a77b03675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715648754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1715648754
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2292164580
Short name T179
Test name
Test status
Simulation time 2408363134 ps
CPU time 6.23 seconds
Started Jul 06 06:24:53 PM PDT 24
Finished Jul 06 06:24:59 PM PDT 24
Peak memory 233832 kb
Host smart-0613f864-e7f2-4b4f-86df-25339c4a7a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292164580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2292164580
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3584824380
Short name T330
Test name
Test status
Simulation time 17692500 ps
CPU time 0.82 seconds
Started Jul 06 06:24:52 PM PDT 24
Finished Jul 06 06:24:53 PM PDT 24
Peak memory 207548 kb
Host smart-c0d04cd9-99c0-4762-8fef-d203356bfa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584824380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3584824380
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1817550272
Short name T840
Test name
Test status
Simulation time 56004052540 ps
CPU time 252.9 seconds
Started Jul 06 06:24:59 PM PDT 24
Finished Jul 06 06:29:12 PM PDT 24
Peak memory 257724 kb
Host smart-e318558d-57e2-4e81-8e0d-aacbcf32ce01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817550272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1817550272
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3194715746
Short name T288
Test name
Test status
Simulation time 13497536974 ps
CPU time 71.58 seconds
Started Jul 06 06:24:59 PM PDT 24
Finished Jul 06 06:26:11 PM PDT 24
Peak memory 241932 kb
Host smart-b213c9d7-f79f-4b40-9326-d0abf8fb2049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194715746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3194715746
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2753772784
Short name T562
Test name
Test status
Simulation time 2256812219 ps
CPU time 11.68 seconds
Started Jul 06 06:25:01 PM PDT 24
Finished Jul 06 06:25:13 PM PDT 24
Peak memory 225732 kb
Host smart-ca160c31-85f8-4e17-bb16-b0d03f739736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753772784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2753772784
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3122942674
Short name T260
Test name
Test status
Simulation time 131829491590 ps
CPU time 247.4 seconds
Started Jul 06 06:24:58 PM PDT 24
Finished Jul 06 06:29:06 PM PDT 24
Peak memory 263800 kb
Host smart-e2253ceb-6dba-4b1b-9314-8ef221ca7826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122942674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3122942674
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2921282632
Short name T220
Test name
Test status
Simulation time 1258438057 ps
CPU time 6.11 seconds
Started Jul 06 06:24:53 PM PDT 24
Finished Jul 06 06:25:00 PM PDT 24
Peak memory 233764 kb
Host smart-962ad418-977e-4bb8-b62d-c68a4a6ce76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921282632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2921282632
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3126531515
Short name T190
Test name
Test status
Simulation time 6908339849 ps
CPU time 65.16 seconds
Started Jul 06 06:24:52 PM PDT 24
Finished Jul 06 06:25:57 PM PDT 24
Peak memory 252880 kb
Host smart-70921edf-96da-491c-8786-d9a9f3cfd10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126531515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3126531515
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3575691839
Short name T250
Test name
Test status
Simulation time 2129176263 ps
CPU time 2.85 seconds
Started Jul 06 06:24:54 PM PDT 24
Finished Jul 06 06:24:57 PM PDT 24
Peak memory 233772 kb
Host smart-97c04284-ebd7-4070-9e43-b9a064fc6aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575691839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3575691839
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4192087193
Short name T13
Test name
Test status
Simulation time 11521659688 ps
CPU time 9 seconds
Started Jul 06 06:24:53 PM PDT 24
Finished Jul 06 06:25:03 PM PDT 24
Peak memory 225680 kb
Host smart-75922c8a-2941-4b79-ba8d-cd4dd983ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192087193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4192087193
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.804037511
Short name T838
Test name
Test status
Simulation time 186767842 ps
CPU time 4.33 seconds
Started Jul 06 06:25:00 PM PDT 24
Finished Jul 06 06:25:05 PM PDT 24
Peak memory 223376 kb
Host smart-4fda3df0-0f25-4b6d-9f91-1925c05f0b9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=804037511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.804037511
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2287359984
Short name T157
Test name
Test status
Simulation time 10074255965 ps
CPU time 126.25 seconds
Started Jul 06 06:25:01 PM PDT 24
Finished Jul 06 06:27:07 PM PDT 24
Peak memory 275028 kb
Host smart-647eaa9f-e7f4-4545-8f5a-4db5609d07a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287359984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2287359984
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3413046683
Short name T1025
Test name
Test status
Simulation time 167587731 ps
CPU time 2.77 seconds
Started Jul 06 06:24:55 PM PDT 24
Finished Jul 06 06:24:58 PM PDT 24
Peak memory 217372 kb
Host smart-36a60b3d-ae81-45cb-9d59-6a4415fb87b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413046683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3413046683
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.584833
Short name T515
Test name
Test status
Simulation time 4483756892 ps
CPU time 13.2 seconds
Started Jul 06 06:24:53 PM PDT 24
Finished Jul 06 06:25:07 PM PDT 24
Peak memory 217444 kb
Host smart-ea308c29-84f9-48ba-8b1c-0fce600a7285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.584833
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2657593415
Short name T507
Test name
Test status
Simulation time 209943257 ps
CPU time 3.7 seconds
Started Jul 06 06:24:56 PM PDT 24
Finished Jul 06 06:25:00 PM PDT 24
Peak memory 217020 kb
Host smart-d8477228-e558-42e3-9767-92309e67adb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657593415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2657593415
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3155644512
Short name T529
Test name
Test status
Simulation time 51730408 ps
CPU time 0.77 seconds
Started Jul 06 06:24:55 PM PDT 24
Finished Jul 06 06:24:56 PM PDT 24
Peak memory 206992 kb
Host smart-539dd5b7-0589-48e5-92eb-7e437f28c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155644512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3155644512
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2990281763
Short name T430
Test name
Test status
Simulation time 16245821548 ps
CPU time 26.49 seconds
Started Jul 06 06:24:56 PM PDT 24
Finished Jul 06 06:25:23 PM PDT 24
Peak memory 238220 kb
Host smart-8d0bff65-e273-4068-ae54-322ff7b642e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990281763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2990281763
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2651772944
Short name T926
Test name
Test status
Simulation time 151554749 ps
CPU time 0.74 seconds
Started Jul 06 06:25:07 PM PDT 24
Finished Jul 06 06:25:08 PM PDT 24
Peak memory 206360 kb
Host smart-3cec9c97-6d89-4198-8d39-d92ce64f23de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651772944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2651772944
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.861945744
Short name T942
Test name
Test status
Simulation time 3931192209 ps
CPU time 10.66 seconds
Started Jul 06 06:25:04 PM PDT 24
Finished Jul 06 06:25:15 PM PDT 24
Peak memory 225708 kb
Host smart-c6f535e8-6153-44f2-b406-90e3790e8e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861945744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.861945744
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4184185465
Short name T32
Test name
Test status
Simulation time 18588160 ps
CPU time 0.76 seconds
Started Jul 06 06:25:00 PM PDT 24
Finished Jul 06 06:25:01 PM PDT 24
Peak memory 206536 kb
Host smart-750b81ea-a392-4b6d-b0f4-b11b4178674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184185465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4184185465
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.367816410
Short name T678
Test name
Test status
Simulation time 20214403758 ps
CPU time 135.43 seconds
Started Jul 06 06:25:05 PM PDT 24
Finished Jul 06 06:27:21 PM PDT 24
Peak memory 250248 kb
Host smart-91e58cf5-0e2e-4bd1-8aef-6248b9d9605a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367816410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.367816410
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2675346842
Short name T396
Test name
Test status
Simulation time 26007574208 ps
CPU time 147.97 seconds
Started Jul 06 06:25:03 PM PDT 24
Finished Jul 06 06:27:31 PM PDT 24
Peak memory 251392 kb
Host smart-1dcb47e5-d1d3-436d-8914-ba56d310c867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675346842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2675346842
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2969568017
Short name T212
Test name
Test status
Simulation time 56575992658 ps
CPU time 540.71 seconds
Started Jul 06 06:25:03 PM PDT 24
Finished Jul 06 06:34:04 PM PDT 24
Peak memory 266660 kb
Host smart-9aa8c041-6aa2-44d5-8beb-b0fa1d9bfd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969568017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2969568017
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.810229926
Short name T146
Test name
Test status
Simulation time 1089513912 ps
CPU time 12.38 seconds
Started Jul 06 06:25:02 PM PDT 24
Finished Jul 06 06:25:15 PM PDT 24
Peak memory 233812 kb
Host smart-4de6cffb-43c3-450f-8e6d-face16d9256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810229926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.810229926
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3001143425
Short name T800
Test name
Test status
Simulation time 1018624050 ps
CPU time 20.74 seconds
Started Jul 06 06:25:02 PM PDT 24
Finished Jul 06 06:25:23 PM PDT 24
Peak memory 225604 kb
Host smart-11f6b180-290c-4549-b484-8c726fa95526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001143425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3001143425
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.159922371
Short name T890
Test name
Test status
Simulation time 954204581 ps
CPU time 7.79 seconds
Started Jul 06 06:24:59 PM PDT 24
Finished Jul 06 06:25:07 PM PDT 24
Peak memory 233824 kb
Host smart-f7ac3ef2-88bf-4e0c-b236-f9a2618fe876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159922371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.159922371
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1113452002
Short name T729
Test name
Test status
Simulation time 15557452818 ps
CPU time 30.36 seconds
Started Jul 06 06:25:00 PM PDT 24
Finished Jul 06 06:25:31 PM PDT 24
Peak memory 233804 kb
Host smart-05018e87-6e76-48be-8eac-dc88c1c22753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113452002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1113452002
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3751866340
Short name T674
Test name
Test status
Simulation time 1393013719 ps
CPU time 5.2 seconds
Started Jul 06 06:24:59 PM PDT 24
Finished Jul 06 06:25:04 PM PDT 24
Peak memory 233812 kb
Host smart-31d319a7-40f9-47b1-b320-ed3447bb83f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751866340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3751866340
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1015656669
Short name T96
Test name
Test status
Simulation time 32951874595 ps
CPU time 24.13 seconds
Started Jul 06 06:24:58 PM PDT 24
Finished Jul 06 06:25:23 PM PDT 24
Peak memory 233920 kb
Host smart-3fcb003e-1e79-43af-8d1d-c618e76b6525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015656669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1015656669
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.972312375
Short name T536
Test name
Test status
Simulation time 709140529 ps
CPU time 10.41 seconds
Started Jul 06 06:25:02 PM PDT 24
Finished Jul 06 06:25:13 PM PDT 24
Peak memory 223548 kb
Host smart-4b7a67ea-a374-40d9-b1a8-9d7e715e5d7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972312375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.972312375
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2016976113
Short name T156
Test name
Test status
Simulation time 68689732958 ps
CPU time 164.3 seconds
Started Jul 06 06:25:04 PM PDT 24
Finished Jul 06 06:27:49 PM PDT 24
Peak memory 242220 kb
Host smart-78ca616a-1e3b-4c31-88e1-3dd872e1a812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016976113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2016976113
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.870041178
Short name T1017
Test name
Test status
Simulation time 25370147408 ps
CPU time 34.22 seconds
Started Jul 06 06:24:57 PM PDT 24
Finished Jul 06 06:25:32 PM PDT 24
Peak memory 217496 kb
Host smart-2a275231-ca84-4add-802a-afaf316cd3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870041178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.870041178
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.294604290
Short name T402
Test name
Test status
Simulation time 1932914377 ps
CPU time 4.13 seconds
Started Jul 06 06:25:00 PM PDT 24
Finished Jul 06 06:25:05 PM PDT 24
Peak memory 217404 kb
Host smart-9ea1f84f-3162-4784-8272-f5c28e38269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294604290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.294604290
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2754085833
Short name T472
Test name
Test status
Simulation time 804610785 ps
CPU time 3.44 seconds
Started Jul 06 06:25:01 PM PDT 24
Finished Jul 06 06:25:05 PM PDT 24
Peak memory 217432 kb
Host smart-d67e8261-a588-486c-b6c3-c8f6c06d4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754085833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2754085833
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1939394430
Short name T33
Test name
Test status
Simulation time 66072229 ps
CPU time 0.77 seconds
Started Jul 06 06:25:00 PM PDT 24
Finished Jul 06 06:25:01 PM PDT 24
Peak memory 206972 kb
Host smart-63f12d19-6cda-42bc-8b6d-5c1315878b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939394430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1939394430
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3066982676
Short name T461
Test name
Test status
Simulation time 463196887 ps
CPU time 3.6 seconds
Started Jul 06 06:25:02 PM PDT 24
Finished Jul 06 06:25:06 PM PDT 24
Peak memory 233864 kb
Host smart-193b4ada-72cd-43dd-a18e-1a9c093a0326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066982676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3066982676
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1497612726
Short name T826
Test name
Test status
Simulation time 51482931 ps
CPU time 0.78 seconds
Started Jul 06 06:25:08 PM PDT 24
Finished Jul 06 06:25:09 PM PDT 24
Peak memory 206420 kb
Host smart-b766b503-38f1-4c04-ba4f-457f26b14d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497612726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1497612726
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1632508531
Short name T918
Test name
Test status
Simulation time 102043587 ps
CPU time 2.47 seconds
Started Jul 06 06:25:07 PM PDT 24
Finished Jul 06 06:25:10 PM PDT 24
Peak memory 225580 kb
Host smart-77a269e1-eb31-447d-9c0f-08977c5a1c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632508531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1632508531
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2176846268
Short name T344
Test name
Test status
Simulation time 32565277 ps
CPU time 0.82 seconds
Started Jul 06 06:25:05 PM PDT 24
Finished Jul 06 06:25:07 PM PDT 24
Peak memory 207540 kb
Host smart-d130ffae-55d8-4501-b576-bab9a110de88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176846268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2176846268
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.665940214
Short name T382
Test name
Test status
Simulation time 10592434419 ps
CPU time 17.14 seconds
Started Jul 06 06:25:08 PM PDT 24
Finished Jul 06 06:25:26 PM PDT 24
Peak memory 225712 kb
Host smart-615adfa1-d9db-404d-a3fe-6ae49834fc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665940214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.665940214
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3890904378
Short name T457
Test name
Test status
Simulation time 87822245756 ps
CPU time 177.8 seconds
Started Jul 06 06:25:10 PM PDT 24
Finished Jul 06 06:28:08 PM PDT 24
Peak memory 256252 kb
Host smart-6a186ae9-1eef-4e03-a002-0aee5d4fdebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890904378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3890904378
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2324405985
Short name T41
Test name
Test status
Simulation time 9248241372 ps
CPU time 116.25 seconds
Started Jul 06 06:25:08 PM PDT 24
Finished Jul 06 06:27:05 PM PDT 24
Peak memory 266816 kb
Host smart-1fa65317-a71b-4bb2-b3eb-b9012ac69637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324405985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2324405985
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1461907263
Short name T681
Test name
Test status
Simulation time 651939648 ps
CPU time 8.67 seconds
Started Jul 06 06:25:09 PM PDT 24
Finished Jul 06 06:25:18 PM PDT 24
Peak memory 242028 kb
Host smart-531547ab-586f-48ce-a0f6-0d1c870fc5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461907263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1461907263
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1537635074
Short name T553
Test name
Test status
Simulation time 242648603 ps
CPU time 3.47 seconds
Started Jul 06 06:25:04 PM PDT 24
Finished Jul 06 06:25:07 PM PDT 24
Peak memory 225544 kb
Host smart-7653acc0-975a-49cd-becf-a146b7f1d34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537635074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1537635074
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.815696759
Short name T370
Test name
Test status
Simulation time 35169144581 ps
CPU time 105.29 seconds
Started Jul 06 06:25:06 PM PDT 24
Finished Jul 06 06:26:51 PM PDT 24
Peak memory 234860 kb
Host smart-e2946cd6-3d50-4fe7-b98a-6cea7911ff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815696759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.815696759
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3646511997
Short name T249
Test name
Test status
Simulation time 1378139704 ps
CPU time 2.66 seconds
Started Jul 06 06:25:03 PM PDT 24
Finished Jul 06 06:25:06 PM PDT 24
Peak memory 225636 kb
Host smart-85b01486-28de-497d-bb2a-0a6971db1022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646511997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3646511997
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.114093315
Short name T957
Test name
Test status
Simulation time 46496879368 ps
CPU time 30.34 seconds
Started Jul 06 06:25:04 PM PDT 24
Finished Jul 06 06:25:34 PM PDT 24
Peak memory 233856 kb
Host smart-0bf7d3c1-6c5d-4fa6-bfaf-d9ce874ef86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114093315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.114093315
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2248337114
Short name T145
Test name
Test status
Simulation time 4141286816 ps
CPU time 12.36 seconds
Started Jul 06 06:25:12 PM PDT 24
Finished Jul 06 06:25:24 PM PDT 24
Peak memory 221356 kb
Host smart-79f65cee-aae0-4d57-9267-cd348242e1a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2248337114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2248337114
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.976132226
Short name T877
Test name
Test status
Simulation time 289914210177 ps
CPU time 598.53 seconds
Started Jul 06 06:25:08 PM PDT 24
Finished Jul 06 06:35:07 PM PDT 24
Peak memory 250816 kb
Host smart-6b7df532-2888-4dcb-afbf-6516a7efe6f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976132226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.976132226
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1465770509
Short name T83
Test name
Test status
Simulation time 10091152539 ps
CPU time 25.35 seconds
Started Jul 06 06:25:05 PM PDT 24
Finished Jul 06 06:25:31 PM PDT 24
Peak memory 220888 kb
Host smart-b3206963-b5c6-40f4-8092-b0e74bb7cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465770509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1465770509
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1260494063
Short name T987
Test name
Test status
Simulation time 14372525742 ps
CPU time 10.1 seconds
Started Jul 06 06:25:02 PM PDT 24
Finished Jul 06 06:25:13 PM PDT 24
Peak memory 218768 kb
Host smart-f45c275f-b6c2-4629-a629-665296a8ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260494063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1260494063
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3180923511
Short name T668
Test name
Test status
Simulation time 96812817 ps
CPU time 2.66 seconds
Started Jul 06 06:25:07 PM PDT 24
Finished Jul 06 06:25:10 PM PDT 24
Peak memory 217332 kb
Host smart-b72bbe3c-ffa1-414d-af38-dcb25344988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180923511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3180923511
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2738403542
Short name T338
Test name
Test status
Simulation time 61376140 ps
CPU time 0.71 seconds
Started Jul 06 06:25:03 PM PDT 24
Finished Jul 06 06:25:04 PM PDT 24
Peak memory 207004 kb
Host smart-c3c4b31e-396a-401f-8e8b-9fdffde3be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738403542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2738403542
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3395027681
Short name T397
Test name
Test status
Simulation time 61733459 ps
CPU time 2.42 seconds
Started Jul 06 06:25:08 PM PDT 24
Finished Jul 06 06:25:11 PM PDT 24
Peak memory 225332 kb
Host smart-dacfe1fe-4504-46e1-bf65-ffdd2043c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395027681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3395027681
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1682418954
Short name T1003
Test name
Test status
Simulation time 19242524 ps
CPU time 0.7 seconds
Started Jul 06 06:25:18 PM PDT 24
Finished Jul 06 06:25:19 PM PDT 24
Peak memory 206396 kb
Host smart-0968d263-999e-4cdf-9103-5587436300be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682418954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1682418954
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.820440892
Short name T345
Test name
Test status
Simulation time 644427413 ps
CPU time 8.54 seconds
Started Jul 06 06:25:12 PM PDT 24
Finished Jul 06 06:25:21 PM PDT 24
Peak memory 233736 kb
Host smart-05ff98f6-5231-4c6c-a267-53b64931f749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820440892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.820440892
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.778345846
Short name T415
Test name
Test status
Simulation time 48727776 ps
CPU time 0.77 seconds
Started Jul 06 06:25:07 PM PDT 24
Finished Jul 06 06:25:08 PM PDT 24
Peak memory 207532 kb
Host smart-ef2b550f-d3b9-485b-b8eb-4f3b9a3e4bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778345846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.778345846
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3430680712
Short name T294
Test name
Test status
Simulation time 17394332366 ps
CPU time 169.07 seconds
Started Jul 06 06:25:16 PM PDT 24
Finished Jul 06 06:28:05 PM PDT 24
Peak memory 258480 kb
Host smart-c07d9b2a-8bef-48f5-96eb-6cd07d640558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430680712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3430680712
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4021939021
Short name T167
Test name
Test status
Simulation time 1752281741 ps
CPU time 36.75 seconds
Started Jul 06 06:25:17 PM PDT 24
Finished Jul 06 06:25:54 PM PDT 24
Peak memory 241708 kb
Host smart-1a690ce3-d993-4b4e-a77d-1443eae2aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021939021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4021939021
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3188480154
Short name T992
Test name
Test status
Simulation time 4661663222 ps
CPU time 13.99 seconds
Started Jul 06 06:25:17 PM PDT 24
Finished Jul 06 06:25:32 PM PDT 24
Peak memory 218640 kb
Host smart-1583ebb5-4c7b-49b9-befd-89570f71c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188480154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3188480154
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1427498939
Short name T304
Test name
Test status
Simulation time 465295030 ps
CPU time 4.16 seconds
Started Jul 06 06:25:13 PM PDT 24
Finished Jul 06 06:25:17 PM PDT 24
Peak memory 225632 kb
Host smart-f4f223fd-81d2-4eb4-b219-d6eeae725e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427498939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1427498939
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.913868884
Short name T271
Test name
Test status
Simulation time 7680499151 ps
CPU time 86.17 seconds
Started Jul 06 06:25:13 PM PDT 24
Finished Jul 06 06:26:39 PM PDT 24
Peak memory 253312 kb
Host smart-7cbabf2c-15b2-4f80-8f2c-fddc0e3ce721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913868884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.913868884
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2532890712
Short name T923
Test name
Test status
Simulation time 1218413613 ps
CPU time 13.85 seconds
Started Jul 06 06:25:14 PM PDT 24
Finished Jul 06 06:25:29 PM PDT 24
Peak memory 233800 kb
Host smart-b5f2c3db-8793-40ac-8d41-1c497bb3d223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532890712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2532890712
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.272401473
Short name T252
Test name
Test status
Simulation time 5313193298 ps
CPU time 15.56 seconds
Started Jul 06 06:25:15 PM PDT 24
Finished Jul 06 06:25:30 PM PDT 24
Peak memory 225716 kb
Host smart-a92dec89-7b82-4b28-b8c5-882a7ac9e93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272401473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.272401473
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2404918686
Short name T624
Test name
Test status
Simulation time 114166180 ps
CPU time 2.32 seconds
Started Jul 06 06:25:14 PM PDT 24
Finished Jul 06 06:25:17 PM PDT 24
Peak memory 233476 kb
Host smart-63de6f81-f9a5-4c19-aee8-0d29a92baa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404918686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2404918686
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2004789202
Short name T95
Test name
Test status
Simulation time 1253403202 ps
CPU time 5.59 seconds
Started Jul 06 06:25:14 PM PDT 24
Finished Jul 06 06:25:20 PM PDT 24
Peak memory 225572 kb
Host smart-37dba1cf-9220-4cc2-bcb1-f75ffb1f1556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004789202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2004789202
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.266099323
Short name T416
Test name
Test status
Simulation time 2349756245 ps
CPU time 5.22 seconds
Started Jul 06 06:25:12 PM PDT 24
Finished Jul 06 06:25:18 PM PDT 24
Peak memory 224208 kb
Host smart-4d12470d-a9e2-42ef-ab26-7dcc5cb2db5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=266099323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.266099323
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4218896171
Short name T21
Test name
Test status
Simulation time 163989701 ps
CPU time 1.02 seconds
Started Jul 06 06:25:18 PM PDT 24
Finished Jul 06 06:25:19 PM PDT 24
Peak memory 208056 kb
Host smart-03b9c778-ff78-4317-bf86-a9041dc36d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218896171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4218896171
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3351829612
Short name T811
Test name
Test status
Simulation time 48750906266 ps
CPU time 33.56 seconds
Started Jul 06 06:25:14 PM PDT 24
Finished Jul 06 06:25:48 PM PDT 24
Peak memory 217524 kb
Host smart-9ab1b919-021a-439b-9bcd-78bd0f8d8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351829612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3351829612
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.738403724
Short name T952
Test name
Test status
Simulation time 23619986 ps
CPU time 0.72 seconds
Started Jul 06 06:25:15 PM PDT 24
Finished Jul 06 06:25:16 PM PDT 24
Peak memory 206648 kb
Host smart-99bebf50-bad8-46d6-a6ff-3bd241f054e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738403724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.738403724
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3265685782
Short name T680
Test name
Test status
Simulation time 49130082 ps
CPU time 1.03 seconds
Started Jul 06 06:25:11 PM PDT 24
Finished Jul 06 06:25:13 PM PDT 24
Peak memory 208424 kb
Host smart-3e42d8b0-fb84-41c5-a31f-b3247a566ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265685782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3265685782
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1496690204
Short name T489
Test name
Test status
Simulation time 161312715 ps
CPU time 0.91 seconds
Started Jul 06 06:25:12 PM PDT 24
Finished Jul 06 06:25:13 PM PDT 24
Peak memory 206964 kb
Host smart-47805a83-26ed-4d9d-8598-c3b442232cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496690204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1496690204
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.978865911
Short name T925
Test name
Test status
Simulation time 3111035698 ps
CPU time 15.17 seconds
Started Jul 06 06:27:02 PM PDT 24
Finished Jul 06 06:27:18 PM PDT 24
Peak memory 233896 kb
Host smart-3d689d31-4e1a-4491-85e8-211ff7f5ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978865911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.978865911
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1726193674
Short name T352
Test name
Test status
Simulation time 10621764 ps
CPU time 0.7 seconds
Started Jul 06 06:25:20 PM PDT 24
Finished Jul 06 06:25:21 PM PDT 24
Peak memory 206660 kb
Host smart-cc250a76-3448-4764-ae35-5c781f124811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726193674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1726193674
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.349883415
Short name T232
Test name
Test status
Simulation time 297758847 ps
CPU time 2.85 seconds
Started Jul 06 06:25:16 PM PDT 24
Finished Jul 06 06:25:19 PM PDT 24
Peak memory 233832 kb
Host smart-9f5c8b9b-329e-43e8-83d1-82bd6397ec90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349883415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.349883415
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.918560221
Short name T425
Test name
Test status
Simulation time 27316273 ps
CPU time 0.74 seconds
Started Jul 06 06:25:18 PM PDT 24
Finished Jul 06 06:25:19 PM PDT 24
Peak memory 206792 kb
Host smart-8439c655-8c8d-45a3-8142-3bb32b7049c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918560221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.918560221
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1933646677
Short name T804
Test name
Test status
Simulation time 55034631 ps
CPU time 0.93 seconds
Started Jul 06 06:25:18 PM PDT 24
Finished Jul 06 06:25:19 PM PDT 24
Peak memory 217200 kb
Host smart-a35cac17-8192-4203-8564-b7a21e344926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933646677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1933646677
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3856711253
Short name T607
Test name
Test status
Simulation time 3489484533 ps
CPU time 81.87 seconds
Started Jul 06 06:25:20 PM PDT 24
Finished Jul 06 06:26:42 PM PDT 24
Peak memory 257152 kb
Host smart-4a8cee44-8942-4289-ab76-e07361e8f6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856711253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3856711253
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1314628345
Short name T722
Test name
Test status
Simulation time 6196296248 ps
CPU time 82.17 seconds
Started Jul 06 06:25:21 PM PDT 24
Finished Jul 06 06:26:44 PM PDT 24
Peak memory 270504 kb
Host smart-328c3a6e-a258-4b8a-a87e-452ae60957f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314628345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1314628345
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3573685846
Short name T861
Test name
Test status
Simulation time 753321561 ps
CPU time 9.29 seconds
Started Jul 06 06:25:16 PM PDT 24
Finished Jul 06 06:25:26 PM PDT 24
Peak memory 225596 kb
Host smart-f70b30c1-5eb1-4adc-8ce8-d4fcddc95349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573685846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3573685846
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.581827157
Short name T187
Test name
Test status
Simulation time 4491179323 ps
CPU time 98.65 seconds
Started Jul 06 06:25:16 PM PDT 24
Finished Jul 06 06:26:55 PM PDT 24
Peak memory 266320 kb
Host smart-5ecab051-42e1-4e55-a09f-3e3f7920f69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581827157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.581827157
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3068436265
Short name T655
Test name
Test status
Simulation time 115249158 ps
CPU time 4.11 seconds
Started Jul 06 06:25:17 PM PDT 24
Finished Jul 06 06:25:22 PM PDT 24
Peak memory 233704 kb
Host smart-4386f46e-8db3-4afe-8182-8b452d010235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068436265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3068436265
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1632722401
Short name T820
Test name
Test status
Simulation time 1983774033 ps
CPU time 28.46 seconds
Started Jul 06 06:25:18 PM PDT 24
Finished Jul 06 06:25:47 PM PDT 24
Peak memory 234804 kb
Host smart-b553d91d-0172-4efd-9b41-df7a3e34c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632722401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1632722401
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2760019008
Short name T292
Test name
Test status
Simulation time 7090331159 ps
CPU time 8.33 seconds
Started Jul 06 06:25:16 PM PDT 24
Finished Jul 06 06:25:25 PM PDT 24
Peak memory 233896 kb
Host smart-af30d824-0bc5-48d3-8d90-e1d6304a4424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760019008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2760019008
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3147012967
Short name T353
Test name
Test status
Simulation time 170497817 ps
CPU time 2.88 seconds
Started Jul 06 06:25:17 PM PDT 24
Finished Jul 06 06:25:20 PM PDT 24
Peak memory 225564 kb
Host smart-e36e3214-e918-406e-8a22-10dabac76183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147012967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3147012967
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.930862482
Short name T667
Test name
Test status
Simulation time 345557403 ps
CPU time 4.91 seconds
Started Jul 06 06:25:17 PM PDT 24
Finished Jul 06 06:25:22 PM PDT 24
Peak memory 221392 kb
Host smart-234343a2-723f-4d2e-b81c-7a50cb983923
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=930862482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.930862482
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2013646150
Short name T240
Test name
Test status
Simulation time 36691079161 ps
CPU time 204.9 seconds
Started Jul 06 06:25:21 PM PDT 24
Finished Jul 06 06:28:47 PM PDT 24
Peak memory 255668 kb
Host smart-f98a910e-0401-4e5c-bd5f-31d8c14b1379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013646150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2013646150
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3210152051
Short name T552
Test name
Test status
Simulation time 5964146895 ps
CPU time 8.12 seconds
Started Jul 06 06:25:16 PM PDT 24
Finished Jul 06 06:25:25 PM PDT 24
Peak memory 217532 kb
Host smart-6fef4fe0-a55b-41ff-ae60-93d1a0530af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210152051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3210152051
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2338394021
Short name T337
Test name
Test status
Simulation time 1454031695 ps
CPU time 3.8 seconds
Started Jul 06 06:25:16 PM PDT 24
Finished Jul 06 06:25:20 PM PDT 24
Peak memory 217456 kb
Host smart-79725524-7472-419b-a735-b7f6d673566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338394021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2338394021
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.519352256
Short name T347
Test name
Test status
Simulation time 107647682 ps
CPU time 3.1 seconds
Started Jul 06 06:25:18 PM PDT 24
Finished Jul 06 06:25:21 PM PDT 24
Peak memory 217336 kb
Host smart-b1f240b3-dcc4-4b83-9fb0-2ff512575337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519352256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.519352256
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1063233626
Short name T979
Test name
Test status
Simulation time 30897794 ps
CPU time 0.81 seconds
Started Jul 06 06:25:17 PM PDT 24
Finished Jul 06 06:25:19 PM PDT 24
Peak memory 207964 kb
Host smart-0cb8781b-7fe5-4e94-b77c-9076159c4ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063233626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1063233626
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3047117665
Short name T242
Test name
Test status
Simulation time 66711896 ps
CPU time 2.2 seconds
Started Jul 06 06:25:16 PM PDT 24
Finished Jul 06 06:25:19 PM PDT 24
Peak memory 233764 kb
Host smart-2bb663b1-db85-452c-8ec6-35af3aede742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047117665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3047117665
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2947381404
Short name T354
Test name
Test status
Simulation time 16898845 ps
CPU time 0.72 seconds
Started Jul 06 06:25:28 PM PDT 24
Finished Jul 06 06:25:28 PM PDT 24
Peak memory 206348 kb
Host smart-b983666f-0b04-4712-a935-f84d8566dd9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947381404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2947381404
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3969831387
Short name T982
Test name
Test status
Simulation time 205606583 ps
CPU time 4.59 seconds
Started Jul 06 06:25:24 PM PDT 24
Finished Jul 06 06:25:29 PM PDT 24
Peak memory 233820 kb
Host smart-de20c03f-c3ad-47b7-9339-2e856c095eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969831387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3969831387
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.289613563
Short name T863
Test name
Test status
Simulation time 18229666 ps
CPU time 0.76 seconds
Started Jul 06 06:25:20 PM PDT 24
Finished Jul 06 06:25:22 PM PDT 24
Peak memory 206860 kb
Host smart-f7a6fbf4-13cd-4ecc-a0e7-86151332626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289613563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.289613563
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.441319212
Short name T211
Test name
Test status
Simulation time 178332165287 ps
CPU time 173.72 seconds
Started Jul 06 06:25:22 PM PDT 24
Finished Jul 06 06:28:17 PM PDT 24
Peak memory 256156 kb
Host smart-7837a055-974d-4ca7-af39-077bf84a1dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441319212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.441319212
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2825538960
Short name T895
Test name
Test status
Simulation time 20832454271 ps
CPU time 81.21 seconds
Started Jul 06 06:25:21 PM PDT 24
Finished Jul 06 06:26:42 PM PDT 24
Peak memory 264560 kb
Host smart-434175ca-b804-4e65-a91f-1c5e78282d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825538960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2825538960
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3508278918
Short name T505
Test name
Test status
Simulation time 105448777188 ps
CPU time 296.52 seconds
Started Jul 06 06:25:26 PM PDT 24
Finished Jul 06 06:30:23 PM PDT 24
Peak memory 253472 kb
Host smart-7801ab34-aa80-4f48-9dab-9ff13f9aba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508278918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3508278918
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2783696246
Short name T47
Test name
Test status
Simulation time 294777153 ps
CPU time 3.8 seconds
Started Jul 06 06:25:22 PM PDT 24
Finished Jul 06 06:25:27 PM PDT 24
Peak memory 225604 kb
Host smart-b1b38370-5be9-4ea9-80cd-b9a4a4f3a234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783696246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2783696246
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.991279293
Short name T189
Test name
Test status
Simulation time 7369909940 ps
CPU time 59.26 seconds
Started Jul 06 06:25:21 PM PDT 24
Finished Jul 06 06:26:21 PM PDT 24
Peak memory 250340 kb
Host smart-2a0e9dca-6d00-4473-9b49-1fba73c78778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991279293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.991279293
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4143468200
Short name T642
Test name
Test status
Simulation time 97354065 ps
CPU time 2.15 seconds
Started Jul 06 06:25:22 PM PDT 24
Finished Jul 06 06:25:24 PM PDT 24
Peak memory 224944 kb
Host smart-538914f5-7a3d-42ea-8aca-1db548e7451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143468200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4143468200
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.403424068
Short name T486
Test name
Test status
Simulation time 509279394 ps
CPU time 6.53 seconds
Started Jul 06 06:25:21 PM PDT 24
Finished Jul 06 06:25:28 PM PDT 24
Peak memory 225588 kb
Host smart-79637554-58c2-4e43-a0aa-2a1f9b8fceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403424068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.403424068
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2133598824
Short name T508
Test name
Test status
Simulation time 9689886855 ps
CPU time 29.33 seconds
Started Jul 06 06:25:23 PM PDT 24
Finished Jul 06 06:25:53 PM PDT 24
Peak memory 252856 kb
Host smart-81d41f10-d983-4ff1-9bf6-4735ea311ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133598824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2133598824
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.444101928
Short name T419
Test name
Test status
Simulation time 388492036 ps
CPU time 3.14 seconds
Started Jul 06 06:25:22 PM PDT 24
Finished Jul 06 06:25:25 PM PDT 24
Peak memory 233740 kb
Host smart-76a1b63f-fd13-4723-af64-54a823957415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444101928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.444101928
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.404244534
Short name T414
Test name
Test status
Simulation time 745776139 ps
CPU time 4.75 seconds
Started Jul 06 06:25:20 PM PDT 24
Finished Jul 06 06:25:25 PM PDT 24
Peak memory 220248 kb
Host smart-eea305bf-82a6-4b3b-b461-2c978a434b39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=404244534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.404244534
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3826151868
Short name T827
Test name
Test status
Simulation time 21488650002 ps
CPU time 260.61 seconds
Started Jul 06 06:25:25 PM PDT 24
Finished Jul 06 06:29:46 PM PDT 24
Peak memory 266816 kb
Host smart-5c5da667-7b5b-4076-a8d5-f85365fb11da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826151868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3826151868
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1801053043
Short name T31
Test name
Test status
Simulation time 1978773108 ps
CPU time 11.99 seconds
Started Jul 06 06:25:22 PM PDT 24
Finished Jul 06 06:25:34 PM PDT 24
Peak memory 217416 kb
Host smart-c344f6cd-916e-4af0-a2b6-da22db3e28e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801053043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1801053043
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.113665736
Short name T621
Test name
Test status
Simulation time 4073717190 ps
CPU time 15.27 seconds
Started Jul 06 06:25:21 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 217500 kb
Host smart-a939c49d-827b-485b-accb-767899d1b7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113665736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.113665736
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2499658906
Short name T437
Test name
Test status
Simulation time 139296689 ps
CPU time 0.9 seconds
Started Jul 06 06:25:22 PM PDT 24
Finished Jul 06 06:25:24 PM PDT 24
Peak memory 208040 kb
Host smart-f45d3893-bae7-4826-af4a-d3301b559b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499658906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2499658906
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1024813060
Short name T592
Test name
Test status
Simulation time 223728199 ps
CPU time 0.88 seconds
Started Jul 06 06:25:22 PM PDT 24
Finished Jul 06 06:25:24 PM PDT 24
Peak memory 207004 kb
Host smart-034b123f-3aca-4e40-a93b-632aafe1ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024813060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1024813060
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2349243829
Short name T427
Test name
Test status
Simulation time 1656409938 ps
CPU time 3.05 seconds
Started Jul 06 06:25:23 PM PDT 24
Finished Jul 06 06:25:26 PM PDT 24
Peak memory 233844 kb
Host smart-746506bf-0585-40b2-bdbc-b222f0cbd5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349243829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2349243829
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3158086763
Short name T785
Test name
Test status
Simulation time 14955171 ps
CPU time 0.72 seconds
Started Jul 06 06:25:33 PM PDT 24
Finished Jul 06 06:25:34 PM PDT 24
Peak memory 206680 kb
Host smart-19a3bd03-3a2b-4ef9-83e4-65b6396bbce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158086763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3158086763
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1317085148
Short name T24
Test name
Test status
Simulation time 82025928 ps
CPU time 2.64 seconds
Started Jul 06 06:25:31 PM PDT 24
Finished Jul 06 06:25:35 PM PDT 24
Peak memory 233676 kb
Host smart-071e925e-ba22-4eed-a203-b0b75e76b7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317085148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1317085148
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3576470886
Short name T922
Test name
Test status
Simulation time 16108400 ps
CPU time 0.79 seconds
Started Jul 06 06:25:25 PM PDT 24
Finished Jul 06 06:25:27 PM PDT 24
Peak memory 207544 kb
Host smart-7618f7af-f295-4b82-ba66-a8bdbc008f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576470886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3576470886
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.410017469
Short name T845
Test name
Test status
Simulation time 13908245338 ps
CPU time 43.15 seconds
Started Jul 06 06:25:25 PM PDT 24
Finished Jul 06 06:26:08 PM PDT 24
Peak memory 250344 kb
Host smart-b97cfd54-409c-4dc4-96ae-6ae4486d74f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410017469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.410017469
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1040949705
Short name T295
Test name
Test status
Simulation time 2240910795 ps
CPU time 15.86 seconds
Started Jul 06 06:25:28 PM PDT 24
Finished Jul 06 06:25:45 PM PDT 24
Peak memory 234068 kb
Host smart-264fefa9-2318-43c2-b521-40fb88b9ee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040949705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1040949705
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.4009980226
Short name T254
Test name
Test status
Simulation time 21796909447 ps
CPU time 81.8 seconds
Started Jul 06 06:25:24 PM PDT 24
Finished Jul 06 06:26:46 PM PDT 24
Peak memory 239752 kb
Host smart-f85eb97b-e1d2-453c-8d41-80f774bef607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009980226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.4009980226
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.381318807
Short name T519
Test name
Test status
Simulation time 282501902 ps
CPU time 3.25 seconds
Started Jul 06 06:25:31 PM PDT 24
Finished Jul 06 06:25:35 PM PDT 24
Peak memory 233712 kb
Host smart-e833a795-a1bd-4cfc-b2c7-e67eedcda81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381318807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.381318807
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1220288600
Short name T715
Test name
Test status
Simulation time 62543084086 ps
CPU time 141.54 seconds
Started Jul 06 06:25:24 PM PDT 24
Finished Jul 06 06:27:46 PM PDT 24
Peak memory 250340 kb
Host smart-5f9e23b5-2fa3-4bb7-90fe-374a5dd2d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220288600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1220288600
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2363335998
Short name T10
Test name
Test status
Simulation time 393076302 ps
CPU time 5.96 seconds
Started Jul 06 06:25:34 PM PDT 24
Finished Jul 06 06:25:40 PM PDT 24
Peak memory 225548 kb
Host smart-452cce6e-fb8e-4584-8cd8-d94d096f93d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363335998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2363335998
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2352363727
Short name T63
Test name
Test status
Simulation time 968677470 ps
CPU time 5.14 seconds
Started Jul 06 06:25:25 PM PDT 24
Finished Jul 06 06:25:30 PM PDT 24
Peak memory 233840 kb
Host smart-d715d3c4-9b8f-4be9-9384-3b3eee6d6622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352363727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2352363727
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3620492896
Short name T14
Test name
Test status
Simulation time 3726159073 ps
CPU time 7.69 seconds
Started Jul 06 06:25:25 PM PDT 24
Finished Jul 06 06:25:33 PM PDT 24
Peak memory 233968 kb
Host smart-7309620b-9976-4370-8163-0b5deacf3cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620492896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3620492896
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3911401894
Short name T413
Test name
Test status
Simulation time 30997401 ps
CPU time 2.31 seconds
Started Jul 06 06:25:28 PM PDT 24
Finished Jul 06 06:25:30 PM PDT 24
Peak memory 233600 kb
Host smart-8a2fb84f-8d34-40fa-9cf4-2b6e46bee05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911401894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3911401894
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2148458578
Short name T767
Test name
Test status
Simulation time 371676385 ps
CPU time 5.03 seconds
Started Jul 06 06:25:27 PM PDT 24
Finished Jul 06 06:25:33 PM PDT 24
Peak memory 223836 kb
Host smart-644a0828-2056-4c2b-92dd-91fef6e909b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2148458578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2148458578
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2043417708
Short name T857
Test name
Test status
Simulation time 14445840809 ps
CPU time 37.38 seconds
Started Jul 06 06:25:34 PM PDT 24
Finished Jul 06 06:26:12 PM PDT 24
Peak memory 225728 kb
Host smart-b63b304e-824c-4f68-b9a9-bb9c2cd12ba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043417708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2043417708
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2053811624
Short name T613
Test name
Test status
Simulation time 1634948541 ps
CPU time 7.9 seconds
Started Jul 06 06:25:34 PM PDT 24
Finished Jul 06 06:25:42 PM PDT 24
Peak memory 217360 kb
Host smart-68f7ce00-5715-4ce9-b306-e23b71179e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053811624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2053811624
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3887773114
Short name T1021
Test name
Test status
Simulation time 10448035984 ps
CPU time 7.44 seconds
Started Jul 06 06:25:28 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 219060 kb
Host smart-342211f9-38c7-4be4-8cd7-c6d000407422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887773114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3887773114
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1936133869
Short name T803
Test name
Test status
Simulation time 136983168 ps
CPU time 1.64 seconds
Started Jul 06 06:25:24 PM PDT 24
Finished Jul 06 06:25:26 PM PDT 24
Peak memory 209164 kb
Host smart-60a391da-56ab-409c-a01a-433026a5af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936133869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1936133869
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_upload.2713185505
Short name T209
Test name
Test status
Simulation time 9953878008 ps
CPU time 19.64 seconds
Started Jul 06 06:25:34 PM PDT 24
Finished Jul 06 06:25:54 PM PDT 24
Peak memory 242036 kb
Host smart-aca40b3f-27e1-489c-9b8a-d547eda90d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713185505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2713185505
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1281317928
Short name T1000
Test name
Test status
Simulation time 13067059 ps
CPU time 0.69 seconds
Started Jul 06 06:25:30 PM PDT 24
Finished Jul 06 06:25:32 PM PDT 24
Peak memory 205816 kb
Host smart-49204155-c8c0-4266-a615-14fa892ae004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281317928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1281317928
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1907885903
Short name T351
Test name
Test status
Simulation time 684723403 ps
CPU time 3.77 seconds
Started Jul 06 06:25:31 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 233776 kb
Host smart-ec494081-0d24-4b95-b3f6-03149541b4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907885903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1907885903
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.71830247
Short name T643
Test name
Test status
Simulation time 49065256 ps
CPU time 0.77 seconds
Started Jul 06 06:25:31 PM PDT 24
Finished Jul 06 06:25:33 PM PDT 24
Peak memory 207444 kb
Host smart-fac8c05e-b3f5-4f72-816f-4bc59f2d3d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71830247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.71830247
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1250790660
Short name T268
Test name
Test status
Simulation time 20541459240 ps
CPU time 53.16 seconds
Started Jul 06 06:25:32 PM PDT 24
Finished Jul 06 06:26:26 PM PDT 24
Peak memory 254620 kb
Host smart-105b78cb-4d85-40dd-9a33-0f11a0d87580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250790660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1250790660
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1008768328
Short name T842
Test name
Test status
Simulation time 11289051437 ps
CPU time 59.42 seconds
Started Jul 06 06:25:32 PM PDT 24
Finished Jul 06 06:26:32 PM PDT 24
Peak memory 240392 kb
Host smart-c1a74a93-a8f2-4111-b746-6022d623cf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008768328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1008768328
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2361568678
Short name T1013
Test name
Test status
Simulation time 15517975265 ps
CPU time 130.37 seconds
Started Jul 06 06:25:29 PM PDT 24
Finished Jul 06 06:27:40 PM PDT 24
Peak memory 250456 kb
Host smart-45f925d8-b7ca-411a-9dfe-7e0c60de1dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361568678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2361568678
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1107287216
Short name T299
Test name
Test status
Simulation time 796321106 ps
CPU time 14.91 seconds
Started Jul 06 06:25:31 PM PDT 24
Finished Jul 06 06:25:46 PM PDT 24
Peak memory 233796 kb
Host smart-5b22f8bc-ae86-4acd-9f0a-435fcc9badbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107287216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1107287216
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.578550616
Short name T335
Test name
Test status
Simulation time 30795680073 ps
CPU time 43.99 seconds
Started Jul 06 06:25:29 PM PDT 24
Finished Jul 06 06:26:13 PM PDT 24
Peak memory 236196 kb
Host smart-a6e97b95-fe18-447d-aa46-5c4202e6afbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578550616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.578550616
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1067635680
Short name T941
Test name
Test status
Simulation time 13741122360 ps
CPU time 23.36 seconds
Started Jul 06 06:25:28 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 236928 kb
Host smart-3f63447d-ba78-4437-9d20-44cfa408beac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067635680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1067635680
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1676646063
Short name T816
Test name
Test status
Simulation time 4927166376 ps
CPU time 7.1 seconds
Started Jul 06 06:25:28 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 233884 kb
Host smart-6dd15f58-6da1-4026-b9b2-1e769f87b56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676646063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1676646063
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.903415123
Short name T936
Test name
Test status
Simulation time 1493677259 ps
CPU time 6.02 seconds
Started Jul 06 06:25:24 PM PDT 24
Finished Jul 06 06:25:31 PM PDT 24
Peak memory 225600 kb
Host smart-5de13d09-ffdf-4781-8325-0a5b821bdc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903415123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.903415123
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1574691710
Short name T470
Test name
Test status
Simulation time 1684182946 ps
CPU time 19.69 seconds
Started Jul 06 06:25:32 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 224172 kb
Host smart-b693c8ef-34c3-4086-a491-63447f054368
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1574691710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1574691710
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1581919057
Short name T274
Test name
Test status
Simulation time 40714384580 ps
CPU time 178.12 seconds
Started Jul 06 06:25:29 PM PDT 24
Finished Jul 06 06:28:28 PM PDT 24
Peak memory 267536 kb
Host smart-ac0d763f-b2a8-4ab4-9c80-d844c58ff2fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581919057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1581919057
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.639626537
Short name T605
Test name
Test status
Simulation time 18518851744 ps
CPU time 26.44 seconds
Started Jul 06 06:25:25 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 217532 kb
Host smart-22dafd12-3b00-444a-9703-fcb46d6b42b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639626537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.639626537
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.514345344
Short name T696
Test name
Test status
Simulation time 183539189 ps
CPU time 2.02 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:37 PM PDT 24
Peak memory 217132 kb
Host smart-02b2a883-bc61-4dea-ad3a-1990bb436518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514345344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.514345344
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3752429995
Short name T988
Test name
Test status
Simulation time 18881021 ps
CPU time 0.88 seconds
Started Jul 06 06:25:25 PM PDT 24
Finished Jul 06 06:25:26 PM PDT 24
Peak memory 208028 kb
Host smart-dfe6066e-3cec-4ea3-9c58-841bb3404945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752429995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3752429995
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1954622127
Short name T435
Test name
Test status
Simulation time 474508975 ps
CPU time 1.03 seconds
Started Jul 06 06:25:27 PM PDT 24
Finished Jul 06 06:25:29 PM PDT 24
Peak memory 208036 kb
Host smart-e5b51125-95a0-465f-8522-ced8368852fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954622127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1954622127
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1981150721
Short name T130
Test name
Test status
Simulation time 3913275804 ps
CPU time 6.39 seconds
Started Jul 06 06:25:30 PM PDT 24
Finished Jul 06 06:25:37 PM PDT 24
Peak memory 233844 kb
Host smart-94028762-3a73-499d-8b14-2342c0603d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981150721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1981150721
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1205463903
Short name T518
Test name
Test status
Simulation time 30729516 ps
CPU time 0.68 seconds
Started Jul 06 06:21:56 PM PDT 24
Finished Jul 06 06:21:57 PM PDT 24
Peak memory 206312 kb
Host smart-2dc80a71-15ff-4805-9eb0-9c6c520cfb19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205463903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
205463903
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2916481109
Short name T259
Test name
Test status
Simulation time 867948270 ps
CPU time 5 seconds
Started Jul 06 06:21:57 PM PDT 24
Finished Jul 06 06:22:02 PM PDT 24
Peak memory 233668 kb
Host smart-8e5c17a7-04e1-4321-8184-9525219a000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916481109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2916481109
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.822127459
Short name T614
Test name
Test status
Simulation time 16353591 ps
CPU time 0.78 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:01 PM PDT 24
Peak memory 207560 kb
Host smart-54e6204f-dc16-4870-9f89-e0aabdbbaee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822127459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.822127459
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.260725751
Short name T45
Test name
Test status
Simulation time 5266285527 ps
CPU time 37.8 seconds
Started Jul 06 06:21:56 PM PDT 24
Finished Jul 06 06:22:34 PM PDT 24
Peak memory 242128 kb
Host smart-59e3fb3b-42d0-4ca8-81c0-1bf6176ebf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260725751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.260725751
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2608829161
Short name T905
Test name
Test status
Simulation time 1896918698 ps
CPU time 18.47 seconds
Started Jul 06 06:21:56 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 218764 kb
Host smart-d9e3ca0d-a277-4704-b0a8-aa1133b5e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608829161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2608829161
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3808589593
Short name T199
Test name
Test status
Simulation time 57729497908 ps
CPU time 586.17 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 266072 kb
Host smart-0e97498f-4d35-416c-85bf-b4595fa0e325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808589593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3808589593
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2242979213
Short name T325
Test name
Test status
Simulation time 669166126 ps
CPU time 4.49 seconds
Started Jul 06 06:21:55 PM PDT 24
Finished Jul 06 06:22:00 PM PDT 24
Peak memory 236212 kb
Host smart-71f17310-52cf-48f8-a65d-a34c54a8d1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242979213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2242979213
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2842307142
Short name T931
Test name
Test status
Simulation time 4030119512 ps
CPU time 46.26 seconds
Started Jul 06 06:21:55 PM PDT 24
Finished Jul 06 06:22:41 PM PDT 24
Peak memory 255780 kb
Host smart-08f4283a-2000-40ed-a4e7-f1a954d61435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842307142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2842307142
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2715418973
Short name T1018
Test name
Test status
Simulation time 2808868512 ps
CPU time 6.92 seconds
Started Jul 06 06:21:52 PM PDT 24
Finished Jul 06 06:22:00 PM PDT 24
Peak memory 225692 kb
Host smart-dc0184e4-b9e6-40a9-a136-1eab3d5da0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715418973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2715418973
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.77640486
Short name T670
Test name
Test status
Simulation time 14663825605 ps
CPU time 69.73 seconds
Started Jul 06 06:21:58 PM PDT 24
Finished Jul 06 06:23:08 PM PDT 24
Peak memory 237820 kb
Host smart-f27c2795-fcbd-4863-9663-17b5afec102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77640486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.77640486
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1743149013
Short name T326
Test name
Test status
Simulation time 25482549 ps
CPU time 1.06 seconds
Started Jul 06 06:21:49 PM PDT 24
Finished Jul 06 06:21:51 PM PDT 24
Peak memory 217680 kb
Host smart-ef875502-9244-4722-a9d1-d716ea9903d4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743149013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1743149013
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2738323180
Short name T779
Test name
Test status
Simulation time 513324761 ps
CPU time 5.59 seconds
Started Jul 06 06:21:51 PM PDT 24
Finished Jul 06 06:21:58 PM PDT 24
Peak memory 233824 kb
Host smart-ada0c6dc-91f5-4216-a4fa-7d9131562bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738323180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2738323180
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.288457136
Short name T664
Test name
Test status
Simulation time 6719146931 ps
CPU time 22.13 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:22:12 PM PDT 24
Peak memory 233924 kb
Host smart-51af3949-2338-46f9-9028-a8ddb36c2668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288457136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.288457136
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2706711019
Short name T597
Test name
Test status
Simulation time 493789823 ps
CPU time 3.48 seconds
Started Jul 06 06:21:55 PM PDT 24
Finished Jul 06 06:21:59 PM PDT 24
Peak memory 220896 kb
Host smart-89f5fb59-bc27-4729-bf1a-91e942ba8253
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2706711019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2706711019
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2251611493
Short name T196
Test name
Test status
Simulation time 25281474667 ps
CPU time 159.05 seconds
Started Jul 06 06:21:59 PM PDT 24
Finished Jul 06 06:24:39 PM PDT 24
Peak memory 274004 kb
Host smart-3e37ff9a-be2c-4192-8bf4-43ca2b37f3dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251611493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2251611493
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2879512814
Short name T989
Test name
Test status
Simulation time 6842855565 ps
CPU time 6.46 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:21:57 PM PDT 24
Peak memory 219840 kb
Host smart-671cd1b9-65a8-456a-a0e0-51c6adea53bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879512814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2879512814
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2433844961
Short name T628
Test name
Test status
Simulation time 2441418392 ps
CPU time 5.79 seconds
Started Jul 06 06:21:50 PM PDT 24
Finished Jul 06 06:21:57 PM PDT 24
Peak memory 217444 kb
Host smart-1eb363af-db7c-43dc-8cdf-ef16ffc76396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433844961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2433844961
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2033775548
Short name T575
Test name
Test status
Simulation time 30967663 ps
CPU time 0.78 seconds
Started Jul 06 06:21:55 PM PDT 24
Finished Jul 06 06:21:56 PM PDT 24
Peak memory 206932 kb
Host smart-4e0a5ff2-c36b-468a-ba7e-9c1d5bdc2910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033775548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2033775548
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3636515510
Short name T563
Test name
Test status
Simulation time 24286174 ps
CPU time 0.77 seconds
Started Jul 06 06:21:51 PM PDT 24
Finished Jul 06 06:21:52 PM PDT 24
Peak memory 207004 kb
Host smart-babd4a73-ea27-4f01-b75f-3f7d246bd78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636515510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3636515510
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3156187901
Short name T757
Test name
Test status
Simulation time 7650060081 ps
CPU time 19.54 seconds
Started Jul 06 06:21:55 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 242036 kb
Host smart-e192132f-8ae1-47c8-a986-b42a56e631ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156187901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3156187901
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.420879078
Short name T770
Test name
Test status
Simulation time 47021397 ps
CPU time 0.71 seconds
Started Jul 06 06:22:13 PM PDT 24
Finished Jul 06 06:22:14 PM PDT 24
Peak memory 206368 kb
Host smart-b61a97a6-7328-43f3-9674-d00f27a91406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420879078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.420879078
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3728688250
Short name T600
Test name
Test status
Simulation time 201890504 ps
CPU time 3.92 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:14 PM PDT 24
Peak memory 233784 kb
Host smart-6d3a64f5-db10-4068-b0e3-fc5161b420f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728688250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3728688250
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.4290804795
Short name T355
Test name
Test status
Simulation time 30601208 ps
CPU time 0.77 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:11 PM PDT 24
Peak memory 206728 kb
Host smart-c66f621a-3239-49f0-b26b-338f8a2872d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290804795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.4290804795
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2469900068
Short name T1001
Test name
Test status
Simulation time 18494170644 ps
CPU time 32.78 seconds
Started Jul 06 06:21:59 PM PDT 24
Finished Jul 06 06:22:32 PM PDT 24
Peak memory 242104 kb
Host smart-a64c4618-ed34-4ad6-920d-e03b2ec87c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469900068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2469900068
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1018777125
Short name T34
Test name
Test status
Simulation time 2793516281 ps
CPU time 52.65 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:53 PM PDT 24
Peak memory 237736 kb
Host smart-7fa59e3e-24dc-4bf2-b7c3-6fdc0b3cc318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018777125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1018777125
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4288533061
Short name T85
Test name
Test status
Simulation time 302084812743 ps
CPU time 343.07 seconds
Started Jul 06 06:22:02 PM PDT 24
Finished Jul 06 06:27:46 PM PDT 24
Peak memory 263716 kb
Host smart-b3624fc5-ebdc-4fd4-bf21-0bc2107584ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288533061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4288533061
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3583101058
Short name T649
Test name
Test status
Simulation time 1285512941 ps
CPU time 7.58 seconds
Started Jul 06 06:21:56 PM PDT 24
Finished Jul 06 06:22:03 PM PDT 24
Peak memory 233880 kb
Host smart-407b198f-06ef-4bda-a504-072cd194f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583101058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3583101058
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4174345642
Short name T210
Test name
Test status
Simulation time 19758699673 ps
CPU time 194.53 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:25:25 PM PDT 24
Peak memory 253332 kb
Host smart-e0f05b5f-87b4-4435-8fff-b08701e4bfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174345642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4174345642
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1298994497
Short name T517
Test name
Test status
Simulation time 1168922180 ps
CPU time 5.53 seconds
Started Jul 06 06:21:54 PM PDT 24
Finished Jul 06 06:22:00 PM PDT 24
Peak memory 225584 kb
Host smart-51cd01f6-7646-453f-9330-11422560b16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298994497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1298994497
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2514685340
Short name T395
Test name
Test status
Simulation time 3605664933 ps
CPU time 11.11 seconds
Started Jul 06 06:21:55 PM PDT 24
Finished Jul 06 06:22:06 PM PDT 24
Peak memory 233844 kb
Host smart-821260cd-9aff-4afb-8814-82107e0e8743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514685340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2514685340
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3659083018
Short name T665
Test name
Test status
Simulation time 87918259 ps
CPU time 1.01 seconds
Started Jul 06 06:21:55 PM PDT 24
Finished Jul 06 06:21:56 PM PDT 24
Peak memory 219000 kb
Host smart-64a519a7-1f5d-4add-837f-583bb5e613bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659083018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3659083018
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1172149457
Short name T569
Test name
Test status
Simulation time 7255911541 ps
CPU time 19.84 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:30 PM PDT 24
Peak memory 241868 kb
Host smart-6ac7979e-f27f-498e-8c88-9a35fd8bf97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172149457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1172149457
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.893985425
Short name T707
Test name
Test status
Simulation time 2513527269 ps
CPU time 7.32 seconds
Started Jul 06 06:21:57 PM PDT 24
Finished Jul 06 06:22:04 PM PDT 24
Peak memory 233816 kb
Host smart-0b869528-2135-4ae2-bef6-ffa25baaa4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893985425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.893985425
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2265701182
Short name T367
Test name
Test status
Simulation time 1555870699 ps
CPU time 4.79 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 224120 kb
Host smart-96691874-c711-4a0c-8fde-e333a0365754
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2265701182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2265701182
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1203771108
Short name T520
Test name
Test status
Simulation time 1493024745 ps
CPU time 18.97 seconds
Started Jul 06 06:21:56 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 217464 kb
Host smart-43caedc6-dc38-41b4-a030-e68e826c6d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203771108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1203771108
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1195588576
Short name T406
Test name
Test status
Simulation time 4315516034 ps
CPU time 11.35 seconds
Started Jul 06 06:21:54 PM PDT 24
Finished Jul 06 06:22:06 PM PDT 24
Peak memory 217536 kb
Host smart-16a7e60e-11e3-47ca-a9b7-b231528247d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195588576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1195588576
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.101815996
Short name T831
Test name
Test status
Simulation time 126780921 ps
CPU time 1.48 seconds
Started Jul 06 06:21:56 PM PDT 24
Finished Jul 06 06:21:58 PM PDT 24
Peak memory 217448 kb
Host smart-1395cc2e-7fee-4989-bb70-92a2f9540b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101815996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.101815996
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1618442452
Short name T424
Test name
Test status
Simulation time 219284414 ps
CPU time 0.9 seconds
Started Jul 06 06:21:56 PM PDT 24
Finished Jul 06 06:21:57 PM PDT 24
Peak memory 207024 kb
Host smart-b3ab16ea-8c63-4681-8e1d-7e599dad99aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618442452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1618442452
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1472937318
Short name T588
Test name
Test status
Simulation time 30883092811 ps
CPU time 10.15 seconds
Started Jul 06 06:21:56 PM PDT 24
Finished Jul 06 06:22:07 PM PDT 24
Peak memory 225732 kb
Host smart-8b17bdf0-484f-46b0-bec0-7c2bccec0af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472937318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1472937318
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1817216878
Short name T72
Test name
Test status
Simulation time 31678994 ps
CPU time 0.71 seconds
Started Jul 06 06:22:01 PM PDT 24
Finished Jul 06 06:22:02 PM PDT 24
Peak memory 206644 kb
Host smart-be953d7b-9b7f-4de8-ad7e-121ab05d658e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817216878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
817216878
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1564373429
Short name T455
Test name
Test status
Simulation time 169331117 ps
CPU time 2.58 seconds
Started Jul 06 06:22:01 PM PDT 24
Finished Jul 06 06:22:04 PM PDT 24
Peak memory 233704 kb
Host smart-8bd1ff25-dcbb-41f5-8b2f-5570fd8aeaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564373429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1564373429
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2901513951
Short name T612
Test name
Test status
Simulation time 27263813 ps
CPU time 0.79 seconds
Started Jul 06 06:22:13 PM PDT 24
Finished Jul 06 06:22:14 PM PDT 24
Peak memory 207536 kb
Host smart-d310afbe-ebd4-4ba7-97c4-5787a5ad5ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901513951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2901513951
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3188578148
Short name T541
Test name
Test status
Simulation time 53429144 ps
CPU time 0.97 seconds
Started Jul 06 06:21:59 PM PDT 24
Finished Jul 06 06:22:00 PM PDT 24
Peak memory 217168 kb
Host smart-d6c8e13a-c72e-475d-b783-eb4abec22649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188578148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3188578148
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.105414829
Short name T902
Test name
Test status
Simulation time 1824813347 ps
CPU time 27.75 seconds
Started Jul 06 06:22:03 PM PDT 24
Finished Jul 06 06:22:31 PM PDT 24
Peak memory 250560 kb
Host smart-b687b316-65b3-4566-9884-b5f4337925e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105414829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.105414829
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.498609896
Short name T215
Test name
Test status
Simulation time 10445816621 ps
CPU time 166.61 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:24:47 PM PDT 24
Peak memory 266092 kb
Host smart-7a07b703-1a8c-4c78-95d4-e185b294d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498609896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
498609896
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4172148570
Short name T807
Test name
Test status
Simulation time 43910981447 ps
CPU time 31.65 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:32 PM PDT 24
Peak memory 233848 kb
Host smart-b19b72a3-8201-4aa5-b929-d29458dc217b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172148570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4172148570
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.226722616
Short name T94
Test name
Test status
Simulation time 103900891987 ps
CPU time 182.86 seconds
Started Jul 06 06:21:58 PM PDT 24
Finished Jul 06 06:25:01 PM PDT 24
Peak memory 252384 kb
Host smart-316f4b15-b072-46f3-b924-f2a5031e9199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226722616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
226722616
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3503499377
Short name T392
Test name
Test status
Simulation time 748270964 ps
CPU time 3.69 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:04 PM PDT 24
Peak memory 225612 kb
Host smart-643de5e5-a113-4114-af98-16117d00b7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503499377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3503499377
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1253202224
Short name T532
Test name
Test status
Simulation time 31856113703 ps
CPU time 40.12 seconds
Started Jul 06 06:22:09 PM PDT 24
Finished Jul 06 06:22:50 PM PDT 24
Peak memory 240476 kb
Host smart-ff4cd4c3-3466-4fe0-a202-6c89ae608566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253202224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1253202224
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1230902475
Short name T739
Test name
Test status
Simulation time 29908641 ps
CPU time 1 seconds
Started Jul 06 06:22:03 PM PDT 24
Finished Jul 06 06:22:04 PM PDT 24
Peak memory 219232 kb
Host smart-6b5ca405-4597-431e-8e30-31066ceba5f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230902475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1230902475
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2194913463
Short name T849
Test name
Test status
Simulation time 943779988 ps
CPU time 4.61 seconds
Started Jul 06 06:22:13 PM PDT 24
Finished Jul 06 06:22:18 PM PDT 24
Peak memory 225576 kb
Host smart-6151e395-3275-434c-8137-b65889c4f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194913463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2194913463
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3191869701
Short name T233
Test name
Test status
Simulation time 17281637957 ps
CPU time 20.83 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:31 PM PDT 24
Peak memory 241912 kb
Host smart-84a7e624-11df-4779-bb9c-20e98177f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191869701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3191869701
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1237463659
Short name T702
Test name
Test status
Simulation time 782020511 ps
CPU time 10.05 seconds
Started Jul 06 06:21:59 PM PDT 24
Finished Jul 06 06:22:10 PM PDT 24
Peak memory 223292 kb
Host smart-460bb47f-df79-4b2f-b4b4-c537ff85fc1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1237463659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1237463659
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2161229732
Short name T906
Test name
Test status
Simulation time 359068646 ps
CPU time 1.05 seconds
Started Jul 06 06:22:01 PM PDT 24
Finished Jul 06 06:22:03 PM PDT 24
Peak memory 208092 kb
Host smart-36fe22a7-6ef7-4473-bf12-55bb27ac8720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161229732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2161229732
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1112925590
Short name T38
Test name
Test status
Simulation time 1044506828 ps
CPU time 8.21 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:08 PM PDT 24
Peak memory 217500 kb
Host smart-a451d1cc-83f9-4811-91fa-6ff0d2414535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112925590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1112925590
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3933533511
Short name T688
Test name
Test status
Simulation time 2095152502 ps
CPU time 4.97 seconds
Started Jul 06 06:22:03 PM PDT 24
Finished Jul 06 06:22:08 PM PDT 24
Peak memory 217572 kb
Host smart-e2fc8196-6ad8-4319-ad42-c8d58c49331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933533511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3933533511
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2474281832
Short name T843
Test name
Test status
Simulation time 131970838 ps
CPU time 1.06 seconds
Started Jul 06 06:22:01 PM PDT 24
Finished Jul 06 06:22:03 PM PDT 24
Peak memory 208996 kb
Host smart-9dbdeb74-c6eb-414f-8cb1-aa7326d93edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474281832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2474281832
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.969054986
Short name T485
Test name
Test status
Simulation time 226172191 ps
CPU time 0.88 seconds
Started Jul 06 06:22:02 PM PDT 24
Finished Jul 06 06:22:03 PM PDT 24
Peak memory 208016 kb
Host smart-48195b17-8c8e-4ca1-abcf-21f5c378d018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969054986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.969054986
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2054511091
Short name T506
Test name
Test status
Simulation time 518065620 ps
CPU time 8.04 seconds
Started Jul 06 06:22:03 PM PDT 24
Finished Jul 06 06:22:11 PM PDT 24
Peak memory 234060 kb
Host smart-297803de-0cc6-4210-977d-4a29843ca174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054511091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2054511091
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3848977939
Short name T872
Test name
Test status
Simulation time 65195888 ps
CPU time 0.73 seconds
Started Jul 06 06:22:06 PM PDT 24
Finished Jul 06 06:22:07 PM PDT 24
Peak memory 205736 kb
Host smart-429b446c-5412-4e64-9304-8f9115d2bcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848977939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
848977939
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.243296306
Short name T369
Test name
Test status
Simulation time 710428816 ps
CPU time 2.35 seconds
Started Jul 06 06:22:04 PM PDT 24
Finished Jul 06 06:22:07 PM PDT 24
Peak memory 225156 kb
Host smart-c95a51de-0957-4775-994d-2fb1df1ab9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243296306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.243296306
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3142732639
Short name T544
Test name
Test status
Simulation time 14764122 ps
CPU time 0.76 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:11 PM PDT 24
Peak memory 207448 kb
Host smart-a1106c1c-96ff-4022-84fa-71e1859aa8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142732639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3142732639
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1441024370
Short name T814
Test name
Test status
Simulation time 23489910781 ps
CPU time 164.71 seconds
Started Jul 06 06:22:04 PM PDT 24
Finished Jul 06 06:24:49 PM PDT 24
Peak memory 250368 kb
Host smart-674b6f45-d506-427d-87c9-9dac88110cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441024370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1441024370
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2599656768
Short name T1026
Test name
Test status
Simulation time 61710078365 ps
CPU time 238.86 seconds
Started Jul 06 06:22:05 PM PDT 24
Finished Jul 06 06:26:05 PM PDT 24
Peak memory 258636 kb
Host smart-86fb76e5-02d3-433c-a1b2-d2d960d62de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599656768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2599656768
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.582448552
Short name T799
Test name
Test status
Simulation time 70336512 ps
CPU time 3.09 seconds
Started Jul 06 06:22:07 PM PDT 24
Finished Jul 06 06:22:11 PM PDT 24
Peak memory 233788 kb
Host smart-b42fa337-be30-4b7f-9e61-3faddb62e3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582448552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.582448552
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.350830990
Short name T832
Test name
Test status
Simulation time 3922390495 ps
CPU time 52.38 seconds
Started Jul 06 06:22:05 PM PDT 24
Finished Jul 06 06:22:58 PM PDT 24
Peak memory 241060 kb
Host smart-3acb2f10-86b9-4454-b1a9-353b5288e32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350830990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
350830990
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2956615571
Short name T904
Test name
Test status
Simulation time 259481361 ps
CPU time 2.46 seconds
Started Jul 06 06:22:04 PM PDT 24
Finished Jul 06 06:22:07 PM PDT 24
Peak memory 225528 kb
Host smart-59920f47-174c-4af1-8124-28b93d2e1660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956615571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2956615571
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2183921393
Short name T738
Test name
Test status
Simulation time 2956802297 ps
CPU time 12.08 seconds
Started Jul 06 06:22:05 PM PDT 24
Finished Jul 06 06:22:18 PM PDT 24
Peak memory 225712 kb
Host smart-18fdddc6-7105-40ea-a17f-0b9f4ad0faea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183921393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2183921393
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1039524574
Short name T636
Test name
Test status
Simulation time 1559204679 ps
CPU time 6.59 seconds
Started Jul 06 06:22:01 PM PDT 24
Finished Jul 06 06:22:08 PM PDT 24
Peak memory 241912 kb
Host smart-fa906ac0-c05f-4907-a6a3-51550d6ad85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039524574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1039524574
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3267990753
Short name T725
Test name
Test status
Simulation time 6962012901 ps
CPU time 14.3 seconds
Started Jul 06 06:21:58 PM PDT 24
Finished Jul 06 06:22:13 PM PDT 24
Peak memory 233892 kb
Host smart-5e883327-d721-481f-be08-172f6845dc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267990753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3267990753
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1667562003
Short name T452
Test name
Test status
Simulation time 93904177 ps
CPU time 3.61 seconds
Started Jul 06 06:22:08 PM PDT 24
Finished Jul 06 06:22:12 PM PDT 24
Peak memory 219712 kb
Host smart-1b5fea97-5301-4471-b2de-8ee24707cfcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1667562003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1667562003
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1412029351
Short name T19
Test name
Test status
Simulation time 1379837207 ps
CPU time 6.39 seconds
Started Jul 06 06:22:08 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 225584 kb
Host smart-38202f9d-6825-4c65-8ba3-a9b0788862b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412029351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1412029351
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2073121890
Short name T510
Test name
Test status
Simulation time 47338463026 ps
CPU time 15.55 seconds
Started Jul 06 06:22:01 PM PDT 24
Finished Jul 06 06:22:17 PM PDT 24
Peak memory 217572 kb
Host smart-a56cd25a-846c-4117-b26f-670b65aa0984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073121890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2073121890
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.843680659
Short name T30
Test name
Test status
Simulation time 1302508022 ps
CPU time 5.19 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:16 PM PDT 24
Peak memory 217372 kb
Host smart-b999688e-7895-4cf7-afd3-16889500854e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843680659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.843680659
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1539592484
Short name T594
Test name
Test status
Simulation time 134450711 ps
CPU time 1.6 seconds
Started Jul 06 06:22:00 PM PDT 24
Finished Jul 06 06:22:02 PM PDT 24
Peak memory 217452 kb
Host smart-188616ee-b587-422a-acd5-14dc0fcf5cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539592484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1539592484
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.315400603
Short name T387
Test name
Test status
Simulation time 19471224 ps
CPU time 0.75 seconds
Started Jul 06 06:22:01 PM PDT 24
Finished Jul 06 06:22:02 PM PDT 24
Peak memory 207004 kb
Host smart-78307b1c-e588-4044-a994-e4d16da94947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315400603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.315400603
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3013223064
Short name T163
Test name
Test status
Simulation time 5868968597 ps
CPU time 21.25 seconds
Started Jul 06 06:22:12 PM PDT 24
Finished Jul 06 06:22:34 PM PDT 24
Peak memory 250152 kb
Host smart-bd94ed11-d255-4c6d-919c-22c04ca714f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013223064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3013223064
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2637376292
Short name T531
Test name
Test status
Simulation time 12923739 ps
CPU time 0.73 seconds
Started Jul 06 06:22:14 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 205812 kb
Host smart-f320f2cc-9072-4d22-ae87-028739d456d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637376292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
637376292
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.83985059
Short name T639
Test name
Test status
Simulation time 130534436 ps
CPU time 2.28 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:13 PM PDT 24
Peak memory 225600 kb
Host smart-be0ea38d-8493-4451-8f07-831ac5ed133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83985059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.83985059
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1554691690
Short name T443
Test name
Test status
Simulation time 16444003 ps
CPU time 0.75 seconds
Started Jul 06 06:22:06 PM PDT 24
Finished Jul 06 06:22:07 PM PDT 24
Peak memory 207848 kb
Host smart-c770fff9-55c7-4f46-acca-d8a97c1b5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554691690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1554691690
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.797415563
Short name T186
Test name
Test status
Simulation time 43250160981 ps
CPU time 197.8 seconds
Started Jul 06 06:22:14 PM PDT 24
Finished Jul 06 06:25:33 PM PDT 24
Peak memory 255012 kb
Host smart-614f3dd5-1f08-46fe-a417-a2782e00fbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797415563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.797415563
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3893441777
Short name T1024
Test name
Test status
Simulation time 7961552590 ps
CPU time 34.86 seconds
Started Jul 06 06:22:15 PM PDT 24
Finished Jul 06 06:22:50 PM PDT 24
Peak memory 242220 kb
Host smart-5a290cc9-8dc7-4433-87ac-76a4dd758e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893441777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3893441777
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.26692820
Short name T206
Test name
Test status
Simulation time 13180342050 ps
CPU time 29.17 seconds
Started Jul 06 06:22:16 PM PDT 24
Finished Jul 06 06:22:46 PM PDT 24
Peak memory 255276 kb
Host smart-fc419e5f-efc2-4560-92ea-c53bf10796de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26692820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.26692820
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1756829346
Short name T768
Test name
Test status
Simulation time 535173765 ps
CPU time 10.16 seconds
Started Jul 06 06:22:12 PM PDT 24
Finished Jul 06 06:22:23 PM PDT 24
Peak memory 234800 kb
Host smart-86c14a47-084b-4c88-9a55-3ed6324a8499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756829346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1756829346
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2047609357
Short name T51
Test name
Test status
Simulation time 10064116134 ps
CPU time 133.24 seconds
Started Jul 06 06:22:14 PM PDT 24
Finished Jul 06 06:24:27 PM PDT 24
Peak memory 273996 kb
Host smart-aac50451-43da-41ce-bb63-ee1802469051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047609357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2047609357
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2830110789
Short name T985
Test name
Test status
Simulation time 30974755 ps
CPU time 2.53 seconds
Started Jul 06 06:22:11 PM PDT 24
Finished Jul 06 06:22:14 PM PDT 24
Peak memory 233488 kb
Host smart-2ac26003-b404-4754-ab43-7222b3991221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830110789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2830110789
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1207477366
Short name T746
Test name
Test status
Simulation time 421156660 ps
CPU time 3.04 seconds
Started Jul 06 06:22:11 PM PDT 24
Finished Jul 06 06:22:14 PM PDT 24
Peak memory 233836 kb
Host smart-377df85b-025c-40c6-b760-d0f9dc37e7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207477366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1207477366
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2358676496
Short name T741
Test name
Test status
Simulation time 147200334 ps
CPU time 1.05 seconds
Started Jul 06 06:22:16 PM PDT 24
Finished Jul 06 06:22:18 PM PDT 24
Peak memory 217648 kb
Host smart-d5b93b28-303e-4891-a3bb-0bf7fe4e87c7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358676496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2358676496
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2775404453
Short name T805
Test name
Test status
Simulation time 965854012 ps
CPU time 5.24 seconds
Started Jul 06 06:22:10 PM PDT 24
Finished Jul 06 06:22:16 PM PDT 24
Peak memory 233788 kb
Host smart-9c58da5f-c931-4e59-9b52-1ada4557bc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775404453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2775404453
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4159937635
Short name T5
Test name
Test status
Simulation time 8230887158 ps
CPU time 26.68 seconds
Started Jul 06 06:22:13 PM PDT 24
Finished Jul 06 06:22:40 PM PDT 24
Peak memory 250268 kb
Host smart-50b3e7c1-5144-47bf-b8ee-abbde50d4f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159937635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4159937635
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1766955781
Short name T633
Test name
Test status
Simulation time 1329326739 ps
CPU time 9.71 seconds
Started Jul 06 06:22:14 PM PDT 24
Finished Jul 06 06:22:24 PM PDT 24
Peak memory 224168 kb
Host smart-12d8f93f-d6a8-4640-b923-7a0dd0e49ac6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1766955781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1766955781
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.111588461
Short name T313
Test name
Test status
Simulation time 4197284981 ps
CPU time 89.65 seconds
Started Jul 06 06:22:14 PM PDT 24
Finished Jul 06 06:23:44 PM PDT 24
Peak memory 266192 kb
Host smart-45281ae4-83f8-4a86-8803-4cf27e3c44c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111588461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.111588461
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2001492007
Short name T548
Test name
Test status
Simulation time 34131954 ps
CPU time 0.72 seconds
Started Jul 06 06:22:13 PM PDT 24
Finished Jul 06 06:22:14 PM PDT 24
Peak memory 206676 kb
Host smart-3cfec2de-f735-466e-b108-f130963682ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001492007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2001492007
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.505753432
Short name T888
Test name
Test status
Simulation time 34746197816 ps
CPU time 6.82 seconds
Started Jul 06 06:22:08 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 217552 kb
Host smart-b7a8e6ea-09c4-43f7-9e74-62cc919cd70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505753432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.505753432
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3499129003
Short name T546
Test name
Test status
Simulation time 150672608 ps
CPU time 0.75 seconds
Started Jul 06 06:22:11 PM PDT 24
Finished Jul 06 06:22:12 PM PDT 24
Peak memory 207016 kb
Host smart-8b7b0b45-3f75-4363-b437-d151da6c60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499129003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3499129003
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.670662014
Short name T436
Test name
Test status
Simulation time 233627294 ps
CPU time 0.9 seconds
Started Jul 06 06:22:08 PM PDT 24
Finished Jul 06 06:22:09 PM PDT 24
Peak memory 207404 kb
Host smart-cfcf30a9-e80b-44a0-8c1e-eac89c522293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670662014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.670662014
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.654785995
Short name T528
Test name
Test status
Simulation time 206834515 ps
CPU time 3.49 seconds
Started Jul 06 06:22:11 PM PDT 24
Finished Jul 06 06:22:15 PM PDT 24
Peak memory 225484 kb
Host smart-2a26a328-f9bd-41ed-a585-1ee08ca363c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654785995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.654785995
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%